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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id c17sm504720wmk.23.2021.10.27.11.08.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Oct 2021 11:08:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eRYjL84Pww6H/F8lZrKTTO88TzDQiTncI1tEGCPZPQM=; b=JfSdA/iDAKtL67Lh+AbzavPBgndB8MzLDKxRksthSpNJwLLe9vQ28DrLuMo3yMC3/8 0PsxHXIHbogmSicH5t4k0257xS55B94zYyycRMj5I3vUoj1Egub0I7qMwCRIzHNCh1j8 AZx1+JSsgyUzRSsAZyNCTxDAFMAh3FjuAPaaZTA3FCwcinFuaAfKpKDNw4IcocooO/tB JMt+ejCeyo8s6y3wZ3JNwetZ3bcwa92BGp3cGBKP86HZ0121vJCNrrjDNKejq39XLlC7 ICXieYRGtEiHr3HUQaQ1GRV9Gk9n5ifAjsOvFO1/wbL41RAWcUL29SiDfRsZlMfhtHWp fYrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=eRYjL84Pww6H/F8lZrKTTO88TzDQiTncI1tEGCPZPQM=; b=BxWorMEP16UROFwQLVCD6wryKAyN1vR2TANlyHL60l8LQkR6d+p5XyIAnuNN8pk1rk KpsUIfF3ac1tuhRe16zLEPOWyaxDAhFCM1MG2daraibFapEOEIDFZ12SjVc4Zv3YkTHn iyJaFuMMRzpG/4lIo1NhjuiKHy4NqYu2Oh8yRaEriYBRZfsd43rjkvPvA/93s/YUuf4J WI1y6r55tM0amoyXxRi0didc9EFvRIWvs/xn5HV2rCxciez0QsE0iRJwanyVRTEHfg1L LTQsH1KSOQfjFUFM3PicTpO5AvAdKlKHXznJNHUarhxyIgVtdybdd1dz/HJEGSOPXelq 2iHw== X-Gm-Message-State: AOAM5305UkAEJZM98p1bPNemsfswdcQL26+DQDCz9jH8mfAyHPoEyMJ8 eTVi8TiZAmkPQJpiqPpl2KM= X-Google-Smtp-Source: ABdhPJycmcRAscplLlxFOczUvu8PCegHXdBpHBGt+Urtyk7UQ3zTosTY6G4TIrc4ygVIxLZHTbthoQ== X-Received: by 2002:a05:600c:198d:: with SMTP id t13mr7218333wmq.21.1635358108775; Wed, 27 Oct 2021 11:08:28 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang Subject: [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format to decodetree Date: Wed, 27 Oct 2021 20:07:10 +0200 Message-Id: <20211027180730.1551932-13-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211027180730.1551932-1-f4bug@amsat.org> References: <20211027180730.1551932-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635358112718100001 Convert instructions with an 8-bit immediate value and either implicit data format or data format df to decodetree. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- v2: TCG timm is constant --- target/mips/tcg/msa.decode | 8 ++++ target/mips/tcg/msa_translate.c | 73 ++++++++------------------------- 2 files changed, 24 insertions(+), 57 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 7a4d7549258..af374f08969 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -28,6 +28,7 @@ @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5 @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5 @i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i8 +@i8 ...... .. sa:s8 ws:5 wd:5 ...... &msa_i8 df=3D0 @ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi @bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=3D= %dfm_df m=3D%dfm_m =20 @@ -40,6 +41,13 @@ BZ 010001 110 .. ..... ................= @bz BNZ 010001 111 .. ..... ................ @bz =20 { + ANDI 011110 00 ........ ..... ..... 000000 @i8 + ORI 011110 01 ........ ..... ..... 000000 @i8 + NORI 011110 10 ........ ..... ..... 000000 @i8 + XORI 011110 11 ........ ..... ..... 000000 @i8 + BMNZI 011110 00 ........ ..... ..... 000001 @i8 + BMZI 011110 01 ........ ..... ..... 000001 @i8 + BSELI 011110 10 ........ ..... ..... 000001 @i8 SHF 011110 .. ........ ..... ..... 000010 @i8_df =20 ADDVI 011110 000 .. ..... ..... ..... 000110 @u5 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 76c40dc7126..d0b990a49f6 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -27,9 +27,6 @@ static int msa_bit_df(DisasContext *ctx, int x); =20 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) enum { - OPC_MSA_I8_00 =3D 0x00 | OPC_MSA, - OPC_MSA_I8_01 =3D 0x01 | OPC_MSA, - OPC_MSA_I8_02 =3D 0x02 | OPC_MSA, OPC_MSA_3R_0D =3D 0x0D | OPC_MSA, OPC_MSA_3R_0E =3D 0x0E | OPC_MSA, OPC_MSA_3R_0F =3D 0x0F | OPC_MSA, @@ -57,15 +54,6 @@ enum { }; =20 enum { - /* I8 instruction */ - OPC_ANDI_B =3D (0x0 << 24) | OPC_MSA_I8_00, - OPC_BMNZI_B =3D (0x0 << 24) | OPC_MSA_I8_01, - OPC_ORI_B =3D (0x1 << 24) | OPC_MSA_I8_00, - OPC_BMZI_B =3D (0x1 << 24) | OPC_MSA_I8_01, - OPC_NORI_B =3D (0x2 << 24) | OPC_MSA_I8_00, - OPC_BSELI_B =3D (0x2 << 24) | OPC_MSA_I8_01, - OPC_XORI_B =3D (0x3 << 24) | OPC_MSA_I8_00, - /* VEC/2R/2RF instruction */ OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, @@ -334,6 +322,7 @@ static inline bool check_msa_enabled(DisasContext *ctx) return true; } =20 +typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv= _i32); =20 /* @@ -441,50 +430,25 @@ static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *= a) return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true); } =20 -static void gen_msa_i8(DisasContext *ctx) +static bool trans_msa_i8(DisasContext *ctx, arg_msa_i8 *a, + gen_helper_piii *gen_msa_i8) { -#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) - uint8_t i8 =3D (ctx->opcode >> 16) & 0xff; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + gen_msa_i8(cpu_env, + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->sa)); =20 - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 ti8 =3D tcg_const_i32(i8); - - switch (MASK_MSA_I8(ctx->opcode)) { - case OPC_ANDI_B: - gen_helper_msa_andi_b(cpu_env, twd, tws, ti8); - break; - case OPC_ORI_B: - gen_helper_msa_ori_b(cpu_env, twd, tws, ti8); - break; - case OPC_NORI_B: - gen_helper_msa_nori_b(cpu_env, twd, tws, ti8); - break; - case OPC_XORI_B: - gen_helper_msa_xori_b(cpu_env, twd, tws, ti8); - break; - case OPC_BMNZI_B: - gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8); - break; - case OPC_BMZI_B: - gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8); - break; - case OPC_BSELI_B: - gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(ti8); + return true; } =20 +TRANS_MSA(ANDI, trans_msa_i8, gen_helper_msa_andi_b); +TRANS_MSA(ORI, trans_msa_i8, gen_helper_msa_ori_b); +TRANS_MSA(NORI, trans_msa_i8, gen_helper_msa_nori_b); +TRANS_MSA(XORI, trans_msa_i8, gen_helper_msa_xori_b); +TRANS_MSA(BMNZI, trans_msa_i8, gen_helper_msa_bmnzi_b); +TRANS_MSA(BMZI, trans_msa_i8, gen_helper_msa_bmzi_b); +TRANS_MSA(BSELI, trans_msa_i8, gen_helper_msa_bseli_b); + static bool trans_SHF(DisasContext *ctx, arg_msa_i8 *a) { if (a->df =3D=3D DF_DOUBLE) { @@ -2111,11 +2075,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) } =20 switch (MASK_MSA_MINOR(opcode)) { - case OPC_MSA_I8_00: - case OPC_MSA_I8_01: - case OPC_MSA_I8_02: - gen_msa_i8(ctx); - break; case OPC_MSA_3R_0D: case OPC_MSA_3R_0E: case OPC_MSA_3R_0F: --=20 2.31.1