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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id m35sm5812583wms.2.2021.10.27.11.08.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Oct 2021 11:08:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1v7uzqdYtUNSUQ86iF16IiRd4CiUgCPYBCiS+YToBmY=; b=WOgBnm9ZdwUk34fl+WPyB6XGJCWBVcXZrUWZv1yoYRq8JmfEp7+YiDPlR47b4lB8qk YPq80RVMNC13NmtlogPEyWOS7ZDLEMeQ0YWpn706GavflV17n/JVPsSmdghQPy3H+smT QKYGrsQhopkTCU0TchcGgTJQZgbuwYJNG36/x4qtnqOptyg/JTpUHY4Mw6Iz2CQwZ2FL YSRovHSYH5SmqmLV5VKGpYzR8+cO8i479komUPC7tPF0qyELVd5nEvuB1JKyho4CLpMy PpBKZJGtKDU89BwtEPzo+oZl3Cu6XCv6azAiCeGy7JUchTqqPvUckVVqGy0hPx3/z5MB Lx8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=1v7uzqdYtUNSUQ86iF16IiRd4CiUgCPYBCiS+YToBmY=; b=SUGAeLER6jfK3XHeaptBcupHZoF41+cMLSXI8/7kt9ssdEjECf3IueaPczG0LP4C29 rdmru32EDeYbNNqugT9jE74GaFlSO81hvrduKMQJdOS7A1vH+RmFV6SoGaByTvIdk8Wf zfyMrV9ABxd46A5qojyR0CnDmiq/AYMDDzYguScKMreM/NqS3hbSL9ChVoYnCjpStY3v EuKhpF3ICp7iCsstXA/1puQ4fbhfvdwmxtuNrzVOnokVULraE1fCjedldfs+mgn8U0Lg 1VDZEJXuW91Sypf7mjLGbYb0w+Toh0Qd82pfN/UduJ+fN7oC1Iwi8JfnB2YREe6F7ud2 kW7A== X-Gm-Message-State: AOAM533+8l1zEUf2GbVTBG8jKfh77Uw95wGXPesenGFRMBK26qG1+Cy+ ksTPDxbcbMD75BTPpcwbERA= X-Google-Smtp-Source: ABdhPJw/jTp8DQ5cmGz7j0OmrLarCEOp17FIkmdYtJ6FJVkrtZ6EWk8+WpqPTO7Ii8xIUScOgWh0iw== X-Received: by 2002:a7b:c255:: with SMTP id b21mr7213273wmj.40.1635358099758; Wed, 27 Oct 2021 11:08:19 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang Subject: [PATCH v2 10/32] target/mips: Convert MSA BIT instruction format to decodetree Date: Wed, 27 Oct 2021 20:07:08 +0200 Message-Id: <20211027180730.1551932-11-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211027180730.1551932-1-f4bug@amsat.org> References: <20211027180730.1551932-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635358103578100001 Convert instructions with an immediate bit index and data format df/m to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: - dfm field in decodetree format - index array by CPUMIPSMSADataFormat to avoid dup - TCG tm is constant --- target/mips/tcg/msa.decode | 19 ++++ target/mips/tcg/msa_translate.c | 177 ++++++++++++++------------------ 2 files changed, 98 insertions(+), 98 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 115e90b4fce..c4699b9d4b7 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -16,6 +16,10 @@ &msa_bz df wt sa &msa_ldi df wd sa &msa_i5 df wd ws sa +&msa_bit df wd ws m + +%dfm_df 16:7 !function=3Dmsa_bit_df +%dfm_m 16:7 !function=3Dmsa_bit_m =20 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @@ -23,6 +27,7 @@ @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5 @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5 @ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi +@bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=3D= %dfm_df m=3D%dfm_m =20 LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa @@ -48,5 +53,19 @@ BNZ 010001 111 .. ..... ................= @bz =20 LDI 011110 110 .. .......... ..... 000111 @ldi =20 + SLLI 011110 000 ....... ..... ..... 001001 @bit + SRAI 011110 001 ....... ..... ..... 001001 @bit + SRLI 011110 010 ....... ..... ..... 001001 @bit + BCLRI 011110 011 ....... ..... ..... 001001 @bit + BSETI 011110 100 ....... ..... ..... 001001 @bit + BNEGI 011110 101 ....... ..... ..... 001001 @bit + BINSLI 011110 110 ....... ..... ..... 001001 @bit + BINSRI 011110 111 ....... ..... ..... 001001 @bit + + SAT_S 011110 000 ....... ..... ..... 001010 @bit + SAT_U 011110 001 ....... ..... ..... 001010 @bit + SRARI 011110 010 ....... ..... ..... 001010 @bit + SRLRI 011110 011 ....... ..... ..... 001010 @bit + MSA 011110 -------------------------- } diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index ca70c38c866..175254c1e47 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -17,6 +17,9 @@ #include "fpu_helper.h" #include "internal.h" =20 +static int msa_bit_m(DisasContext *ctx, int x); +static int msa_bit_df(DisasContext *ctx, int x); + /* Include the auto-generated decoder. */ #include "decode-msa.c.inc" =20 @@ -27,8 +30,6 @@ enum { OPC_MSA_I8_00 =3D 0x00 | OPC_MSA, OPC_MSA_I8_01 =3D 0x01 | OPC_MSA, OPC_MSA_I8_02 =3D 0x02 | OPC_MSA, - OPC_MSA_BIT_09 =3D 0x09 | OPC_MSA, - OPC_MSA_BIT_0A =3D 0x0A | OPC_MSA, OPC_MSA_3R_0D =3D 0x0D | OPC_MSA, OPC_MSA_3R_0E =3D 0x0E | OPC_MSA, OPC_MSA_3R_0F =3D 0x0F | OPC_MSA, @@ -222,20 +223,6 @@ enum { OPC_MSUBR_Q_df =3D (0xE << 22) | OPC_MSA_3RF_1C, OPC_FSULE_df =3D (0xF << 22) | OPC_MSA_3RF_1A, OPC_FMAX_A_df =3D (0xF << 22) | OPC_MSA_3RF_1B, - - /* BIT instruction df(bits 22..16) =3D _B _H _W _D */ - OPC_SLLI_df =3D (0x0 << 23) | OPC_MSA_BIT_09, - OPC_SAT_S_df =3D (0x0 << 23) | OPC_MSA_BIT_0A, - OPC_SRAI_df =3D (0x1 << 23) | OPC_MSA_BIT_09, - OPC_SAT_U_df =3D (0x1 << 23) | OPC_MSA_BIT_0A, - OPC_SRLI_df =3D (0x2 << 23) | OPC_MSA_BIT_09, - OPC_SRARI_df =3D (0x2 << 23) | OPC_MSA_BIT_0A, - OPC_BCLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_09, - OPC_SRLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_0A, - OPC_BSETI_df =3D (0x4 << 23) | OPC_MSA_BIT_09, - OPC_BNEGI_df =3D (0x5 << 23) | OPC_MSA_BIT_09, - OPC_BINSLI_df =3D (0x6 << 23) | OPC_MSA_BIT_09, - OPC_BINSRI_df =3D (0x7 << 23) | OPC_MSA_BIT_09, }; =20 static const char msaregnames[][6] =3D { @@ -257,6 +244,59 @@ static const char msaregnames[][6] =3D { "w30.d0", "w30.d1", "w31.d0", "w31.d1", }; =20 +/* Encoding of Operation Field (must be indexed by CPUMIPSMSADataFormat) */ +struct dfe { + int start; + int length; + uint32_t mask; +}; + +/* + * Extract immediate from df/{m,n} format (used by ELM & BIT instructions). + * Returns the immediate value, or -1 if the format does not match. + */ +static int msa_df_extract_val(DisasContext *ctx, int x, const struct dfe *= s) +{ + for (unsigned i =3D 0; i < 4; i++) { + if (extract32(x, s->start, s->length) =3D=3D s->mask) { + return extract32(x, 0, s->start); + } + } + return -1; +} + +/* + * Extract DataField from df/{m,n} format (used by ELM & BIT instructions). + * Returns the DataField, or -1 if the format does not match. + */ +static int msa_df_extract_df(DisasContext *ctx, int x, const struct dfe *s) +{ + for (unsigned i =3D 0; i < 4; i++) { + if (extract32(x, s->start, s->length) =3D=3D s->mask) { + return i; + } + } + return -1; +} + +static const struct dfe df_bit[] =3D { + /* Table 3.28 BIT Instruction Format */ + [DF_BYTE] =3D {3, 4, 0b1110}, + [DF_HALF] =3D {4, 3, 0b110}, + [DF_WORD] =3D {5, 2, 0b10}, + [DF_DOUBLE] =3D {6, 1, 0b0} +}; + +static int msa_bit_m(DisasContext *ctx, int x) +{ + return msa_df_extract_val(ctx, x, df_bit); +} + +static int msa_bit_df(DisasContext *ctx, int x) +{ + return msa_df_extract_df(ctx, x, df_bit); +} + static TCGv_i64 msa_wr_d[64]; =20 void msa_translate_init(void) @@ -500,90 +540,35 @@ static bool trans_LDI(DisasContext *ctx, arg_msa_ldi = *a) return true; } =20 -static void gen_msa_bit(DisasContext *ctx) +static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a, + gen_helper_piiii *gen_msa_bit) { -#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t dfm =3D (ctx->opcode >> 16) & 0x7f; - uint32_t df =3D 0, m =3D 0; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf; - TCGv_i32 tm; - TCGv_i32 twd; - TCGv_i32 tws; - - if ((dfm & 0x40) =3D=3D 0x00) { - m =3D dfm & 0x3f; - df =3D DF_DOUBLE; - } else if ((dfm & 0x60) =3D=3D 0x40) { - m =3D dfm & 0x1f; - df =3D DF_WORD; - } else if ((dfm & 0x70) =3D=3D 0x60) { - m =3D dfm & 0x0f; - df =3D DF_HALF; - } else if ((dfm & 0x78) =3D=3D 0x70) { - m =3D dfm & 0x7; - df =3D DF_BYTE; - } else { - gen_reserved_instruction(ctx); - return; + if (a->df < 0) { + return false; } =20 - tdf =3D tcg_const_i32(df); - tm =3D tcg_const_i32(m); - twd =3D tcg_const_i32(wd); - tws =3D tcg_const_i32(ws); + gen_msa_bit(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->m)); =20 - switch (MASK_MSA_BIT(ctx->opcode)) { - case OPC_SLLI_df: - gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRAI_df: - gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRLI_df: - gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BCLRI_df: - gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BSETI_df: - gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BNEGI_df: - gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BINSLI_df: - gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BINSRI_df: - gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SAT_S_df: - gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SAT_U_df: - gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRARI_df: - gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRLRI_df: - gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(tdf); - tcg_temp_free_i32(tm); - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); + return true; } =20 +TRANS_MSA(SLLI, trans_msa_bit, gen_helper_msa_slli_df); +TRANS_MSA(SRAI, trans_msa_bit, gen_helper_msa_srai_df); +TRANS_MSA(SRLI, trans_msa_bit, gen_helper_msa_srli_df); +TRANS_MSA(BCLRI, trans_msa_bit, gen_helper_msa_bclri_df); +TRANS_MSA(BSETI, trans_msa_bit, gen_helper_msa_bseti_df); +TRANS_MSA(BNEGI, trans_msa_bit, gen_helper_msa_bnegi_df); +TRANS_MSA(BINSLI, trans_msa_bit, gen_helper_msa_binsli_df); +TRANS_MSA(BINSRI, trans_msa_bit, gen_helper_msa_binsri_df); +TRANS_MSA(SAT_S, trans_msa_bit, gen_helper_msa_sat_u_df); +TRANS_MSA(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df); +TRANS_MSA(SRARI, trans_msa_bit, gen_helper_msa_srari_df); +TRANS_MSA(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); + static void gen_msa_3r(DisasContext *ctx) { #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) @@ -2128,10 +2113,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_I8_02: gen_msa_i8(ctx); break; - case OPC_MSA_BIT_09: - case OPC_MSA_BIT_0A: - gen_msa_bit(ctx); - break; case OPC_MSA_3R_0D: case OPC_MSA_3R_0E: case OPC_MSA_3R_0F: --=20 2.31.1