From nobody Tue Feb 10 11:17:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635194565611295.8743727920504; Mon, 25 Oct 2021 13:42:45 -0700 (PDT) Received: from localhost ([::1]:51210 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mf6ns-0004bl-AG for importer@patchew.org; Mon, 25 Oct 2021 16:42:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mf65C-0002cQ-S7; Mon, 25 Oct 2021 15:56:34 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:65115) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mf65A-0005Su-1q; Mon, 25 Oct 2021 15:56:34 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 26 Oct 2021 03:56:24 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2021 12:31:55 -0700 Received: from unknown (HELO hulk.wdc.com) ([10.225.167.27]) by uls-op-cesaip01.wdc.com with ESMTP; 25 Oct 2021 12:56:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1635191791; x=1666727791; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4MSgAQCCUTWZ998c11OUnaR/bBWtlmWowns0VQRFNOw=; b=PitwRE7t8I6TulBB5AyhJbbD6ApmfupV04c9EVWa+W8eDWYY+bX1zWnu pJg6AHHgNBVSsR6LkLx11lTRq44804PZw9YIJpTZMxbsWIP4shr6zRNKx d01TVIb7Zz+LxKPHBeJgTzGXgptdoAutZpkxiVTdF3COHJljZif21yKai 7Lhq4fsD7Omj00tF/GTmVp7ANloNricLMtXEgV4OC8WN0aRiprxeOdjIp 9jJmtvrN7ali+c7nxtDyjfPqYrtg5Z4aNPiQOA9kOtgQH2Ltec50tgCk0 0eUNSYxikPq2S9U1SUogMK8I4xW8yBMLyVlazZQAs5VSAvTJfthwvpFL4 w==; X-IronPort-AV: E=Sophos;i="5.87,181,1631548800"; d="scan'208";a="287683003" IronPort-SDR: XgWDMw15Ml0WUoqf+XEsNwvEatR0zUNq5rmSH5woC05NYNr+042pEaZH+vt/VM8RQNTsyreHcf juSQhd72thrKH5eKEHdDvQuh5U14mSoo4sF75iR/IymH43NCydEo83ArLdjG1ka15ZvjcGRQa2 xPw/aMSpOcGxoLGBghdn9sfMvfmP4EdSjwqZEbKnOHBJGNSKLsO7shHzi1DhRwsgSg+YGP2E93 idNGPiXal2plc0eRg7qlzrUAJTuj0I9I6J2comIZ28/T6QuQ5mSSPMBIQKJs7jLAHOD+RuVlWB SE/4hWcGUBOIx/6O2L+mxiPZ IronPort-SDR: vUKcETonMuAhjDyKWR1Q6Gj1IPfnyjflsGjj1q7LGg8o7BZKhQo/5zK+u+ffK4mc40NN1iXJl4 S7/yjQgm1l/dIw+QGyC8jQMLGiOCeRy7cv0kbTrWi24XO3Gzf7GLh2f7ogpBFgVlWsPE29g8tY mFn2T/sGPYrNMmhg9MOro1nMuG2MQQzl+zIoFDRd+uh5EIOcSnH8LPoc04rksWsq3sxEQYB+o5 BVNqd9aZaJ+88cAbqhaPESVbyrzxGjR+Yt0iR/YNc3zlTn2/5OEcMNCr7wGBXxgrr/jb+jWJR1 CZ8= WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable Date: Mon, 25 Oct 2021 12:55:55 -0700 Message-Id: <20211025195601.245631-5-atish.patra@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211025195601.245631-1-atish.patra@wdc.com> References: <20211025195601.245631-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=925953cd0=atish.patra@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Bin Meng , Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635194567062100001 Content-Type: text/plain; charset="utf-8" The RISC-V privilege specification provides flexibility to implement any number of counters from 29 programmable counters. However, the QEMU implements all the counters. Make it configurable through pmu config parameter which now will indicate how many programmable counters should be implemented by the cpu. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 96 ++++++++++++++++++++++++++++++---------------- 3 files changed, 65 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3b55f5ed0036..aec94101a4c0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -598,7 +598,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true), + DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ebc1a8754032..d0a722e7cbe1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -294,10 +294,10 @@ struct RISCVCPU { bool ext_zbb; bool ext_zbc; bool ext_zbs; - bool ext_pmu; bool ext_ifencei; bool ext_icsr; =20 + uint8_t pmu_num; char *priv_spec; char *user_spec; char *bext_spec; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c486eeaffeb8..a7249eaf917f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -57,15 +57,45 @@ static RISCVException vs(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } =20 +static RISCVException mctr(CPURISCVState *env, int csrno) +{ +#if !defined(CONFIG_USER_ONLY) + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + int ctr_index; + int base_csrno =3D CSR_MHPMCOUNTER3; + + if (riscv_cpu_is_32bit(env) && csrno >=3D CSR_MCYCLEH) { + /* Offset for RV32 mhpmcounternh counters */ + base_csrno +=3D 0x80; + } + ctr_index =3D csrno - base_csrno; + if (!cpu->cfg.pmu_num || ctr_index >=3D cpu->cfg.pmu_num) { + /* The PMU is not enabled or counter is out of range*/ + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +#endif +} + static RISCVException ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); int ctr_index; + int base_csrno =3D CSR_CYCLE; + bool brv32 =3D riscv_cpu_is_32bit(env); + + if (brv32 && csrno >=3D CSR_CYCLEH) { + /* Offset for RV32 hpmcounternh counters */ + base_csrno +=3D 0x80; + } + ctr_index =3D csrno - base_csrno; =20 - if (!cpu->cfg.ext_pmu) { - /* The Counters extensions is not enabled */ + if (!cpu->cfg.pmu_num || ctr_index >=3D (cpu->cfg.pmu_num + 3)) { + /* The PMU is not enabled or counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -93,7 +123,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; } - if (riscv_cpu_is_32bit(env)) { + if (brv32) { switch (csrno) { case CSR_CYCLEH: if (!get_field(env->mcounteren, COUNTEREN_CY)) { @@ -148,7 +178,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; } - if (riscv_cpu_is_32bit(env)) { + if (brv32) { switch (csrno) { case CSR_CYCLEH: if (!get_field(env->hcounteren, COUNTEREN_CY) && @@ -1720,35 +1750,35 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HPMCOUNTER30] =3D { "hpmcounter30", ctr, read_zero }, [CSR_HPMCOUNTER31] =3D { "hpmcounter31", ctr, read_zero }, =20 - [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", any, read_zero }, - [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", any, read_zero }, - [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", any, read_zero }, - [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", any, read_zero }, - [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", any, read_zero }, - [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", any, read_zero }, - [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", any, read_zero }, - [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", any, read_zero }, - [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", any, read_zero }, - [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", any, read_zero }, - [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", any, read_zero }, - [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", any, read_zero }, - [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", any, read_zero }, - [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", any, read_zero }, - [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", any, read_zero }, - [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", any, read_zero }, - [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", any, read_zero }, - [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", any, read_zero }, - [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", any, read_zero }, - [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", any, read_zero }, - [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", any, read_zero }, - [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", any, read_zero }, - [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", any, read_zero }, - [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", any, read_zero }, - [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", any, read_zero }, - [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", any, read_zero }, - [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", any, read_zero }, - [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", any, read_zero }, - [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", any, read_zero }, + [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", mctr, read_zero }, + [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", mctr, read_zero }, + [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", mctr, read_zero }, + [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", mctr, read_zero }, + [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", mctr, read_zero }, + [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", mctr, read_zero }, + [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", mctr, read_zero }, + [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", mctr, read_zero }, + [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", mctr, read_zero }, + [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", mctr, read_zero }, + [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", mctr, read_zero }, + [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", mctr, read_zero }, + [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", mctr, read_zero }, + [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", mctr, read_zero }, + [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", mctr, read_zero }, + [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", mctr, read_zero }, + [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", mctr, read_zero }, + [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", mctr, read_zero }, + [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", mctr, read_zero }, + [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", mctr, read_zero }, + [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", mctr, read_zero }, + [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", mctr, read_zero }, + [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", mctr, read_zero }, + [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", mctr, read_zero }, + [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", mctr, read_zero }, + [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", mctr, read_zero }, + [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", mctr, read_zero }, + [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", mctr, read_zero }, + [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", mctr, read_zero }, =20 [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_zero }, [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_zero }, --=20 2.31.1