From nobody Tue Feb 10 17:13:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635165481564679.3865178323357; Mon, 25 Oct 2021 05:38:01 -0700 (PDT) Received: from localhost ([::1]:34324 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mezEm-0007hR-CJ for importer@patchew.org; Mon, 25 Oct 2021 08:38:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mez5n-0005re-Jb; Mon, 25 Oct 2021 08:28:43 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:43062) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mez5l-00083W-Cs; Mon, 25 Oct 2021 08:28:43 -0400 Received: from mailhost.u-ga.fr (mailhost1.u-ga.fr [152.77.1.10]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id 1BAEE41965; Mon, 25 Oct 2021 14:28:33 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id EE2DA60070; Mon, 25 Oct 2021 14:28:32 +0200 (CEST) Received: from palmier.tima.u-ga.fr (35.201.90.79.rev.sfr.net [79.90.201.35]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id BBD4A14005D; Mon, 25 Oct 2021 14:28:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=univ-grenoble-alpes.fr; s=2020; t=1635164913; bh=CrGAg0XluHvjypIQoChkRG8OCZ7bzXGXawDAStTZlxg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=coNik2FD19DztaLtpbXiVwyVfxkAAALUMI7dc1HiqPJlgnV6lL1kHH3SBN1uzGI8o Zl0chhs2S0yPpoLatA6JPZsN4xzZm6rOrWrKiChTHob2tYD7bhQbvk4WdJJL/Wi0nF cvPrjeN8ral84QUI9snKpedvqrHN7Jrkg62DIQEpHosEG9L53acmIoCpT6vt3+HhnL cJsV6XFZ0UNeZqhRRIL1NfHURf91RhNxQ24IlO3CVzqjM7/KlwOuSDAEVgY9Jzi24M 5vDSFItq6O6HaL4Ly8yr0LKujgyJaqweVhCXYtx2lsfPIqMeyMGgO7II5lBNwA4Ob8 PFhuRZx6x/O/Q== From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers Date: Mon, 25 Oct 2021 14:28:06 +0200 Message-Id: <20211025122818.168890-6-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211025122818.168890-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211025122818.168890-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1635165482641100001 The upper 64-bit of the 128-bit registers have now a place inside the cpu state structure, and are created as globals for future use. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 9 +++++++++ target/riscv/machine.c | 20 ++++++++++++++++++++ target/riscv/translate.c | 5 ++++- 4 files changed, 35 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a33dc30be8..f6d7a1793d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -109,6 +109,7 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 struct CPURISCVState { target_ulong gpr[32]; + target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ uint64_t fpr[32]; /* assume both F and D extensions */ =20 /* vector coprocessor state. */ @@ -326,6 +327,7 @@ static inline bool riscv_feature(CPURISCVState *env, in= t feature) #include "cpu_user.h" =20 extern const char * const riscv_int_regnames[]; +extern const char * const riscv_int_regnamesh[]; extern const char * const riscv_fpr_regnames[]; =20 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 788fa0b11c..8c1cda35b4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -42,6 +42,15 @@ const char * const riscv_int_regnames[] =3D { "x28/t3", "x29/t4", "x30/t5", "x31/t6" }; =20 +const char * const riscv_int_regnamesh[] =3D { + "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", + "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h= ", + "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h= ", + "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h= ", + "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h= ", + "x30h/t5h", "x31h/t6h" +}; + const char * const riscv_fpr_regnames[] =3D { "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", diff --git a/target/riscv/machine.c b/target/riscv/machine.c index f64b2a96c1..78636ec96d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -84,6 +84,14 @@ static bool vector_needed(void *opaque) return riscv_has_ext(env, RVV); } =20 +static bool rv128_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + + return env->misa_mxl_max =3D=3D MXL_RV128; +} + static const VMStateDescription vmstate_vector =3D { .name =3D "cpu/vector", .version_id =3D 1, @@ -138,6 +146,17 @@ static const VMStateDescription vmstate_hyper =3D { } }; =20 +static const VMStateDescription vmstate_rv128 =3D { + .name =3D "cpu/rv128", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D rv128_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 3, @@ -191,6 +210,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_pmp, &vmstate_hyper, &vmstate_vector, + &vmstate_rv128, NULL } }; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5c7971b189..63a52bb707 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -32,7 +32,7 @@ #include "instmap.h" =20 /* global register indices */ -static TCGv cpu_gpr[32], cpu_pc, cpu_vl; +static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; @@ -749,10 +749,13 @@ void riscv_translate_init(void) * unless you specifically block reads/writes to reg 0. */ cpu_gpr[0] =3D NULL; + cpu_gprh[0] =3D NULL; =20 for (i =3D 1; i < 32; i++) { cpu_gpr[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); + cpu_gprh[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); } =20 for (i =3D 0; i < 32; i++) { --=20 2.33.0