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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id w14sm2381838wmi.37.2021.10.23.14.49.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Oct 2021 14:49:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sPvSWraAlK7Nph4ty/Vbsk19Tc0DzeKGebIhAV3dvYU=; b=EirtFh+ic9zODrrAjfdgoFlsvaXSvFoALvFg/Hh9R5Qhm0EHSrmKEjmDQN11Bi6w2Q 8XtDc5Wu8YxZjzLGddLGlg/b6egLHNl5IiNcq1GOg5/lqsMafEwrFZYYUrOEzNEyepQb l6dKGgx7qKGOZL8X/9T+j1x/edFbTWS96AIcTYmYxjrdGpq2+N5enKShAo96MkMZcRs4 HEPwJg4ZYrRfiNgKkzcW2rX1XEH9p7UdBvOPv+5HDzbcam/BLBpObFLiSZbtCAuL575p XA7mXesTMF3p3TZ1x29HBYO4xD9P7SOfHkRQlGw8XdVnctNyPU80V52QtQp9FtalEf0O Fe7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sPvSWraAlK7Nph4ty/Vbsk19Tc0DzeKGebIhAV3dvYU=; b=mKiK1aKQO3KyWogGyaZo19HB9/PFpqEiDo+1JmDMM7n/RsDnNJnKD6GUTDTNIQNSCX vnbbNBRhC3NrF9Yf2qrclHyAQpw4pDt12Tak1ez33ad/BFPUQ/H9fZygaerH1IFbVoXc KsV7qQhjwJHS3foY19s5tLFVm/ajX/WMZRNYSnmdgUAu3gd1T3WyQ2/k5kj2U0hDFElY Q7sQlRzV/c6DHv5djKGWuE1datt5BCu1GGmCSacumHoji0UaSWWj2KbUHqV6dp18VcOq iSby1MhzYY3lgOspxmALcR2Pi7zJ5yCa2WT0kp0L6UacxlrAXPNRVI8HS5QHeo6XU8N0 B4EA== X-Gm-Message-State: AOAM532/k4QVrBnJdhq+dmPOOSV09mrHRQvnvXmy4cWA7rm5KtBABfKq vhF7q/Rj7zd9K4mfA+JhHZo= X-Google-Smtp-Source: ABdhPJwbgrvGfwIHcZOZp109liCaJrw9YaBgOf4XJA09GOGM32tLWxdZtCi3S4uiUaovdFwuWDmn/g== X-Received: by 2002:a5d:64cd:: with SMTP id f13mr10997199wri.92.1635025797098; Sat, 23 Oct 2021 14:49:57 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Luis Pires Subject: [PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Date: Sat, 23 Oct 2021 23:47:53 +0200 Message-Id: <20211023214803.522078-24-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211023214803.522078-1-f4bug@amsat.org> References: <20211023214803.522078-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635025800240100003 Convert 3-register operations to decodetree. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/msa.decode | 11 ++ target/mips/tcg/msa_translate.c | 213 +++++++++----------------------- 2 files changed, 66 insertions(+), 158 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index ca0fd568560..4a9cf85fa7a 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -80,10 +80,21 @@ BNZ 010001 111 .. ..... ...............= . @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + DOTP_S 011110 000.. ..... ..... ..... 010011 @3r + DOTP_U 011110 001.. ..... ..... ..... 010011 @3r + DPADD_S 011110 010.. ..... ..... ..... 010011 @3r + DPADD_U 011110 011.. ..... ..... ..... 010011 @3r + DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r + DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r + SLD 011110 000 .. ..... ..... ..... 010100 @3r SPLAT 011110 001 .. ..... ..... ..... 010100 @3r =20 VSHF 011110 000 .. ..... ..... ..... 010101 @3r + HADD_S 011110 100.. ..... ..... ..... 010101 @3r + HADD_U 011110 101.. ..... ..... ..... 010101 @3r + HSUB_S 011110 110.. ..... ..... ..... 010101 @3r + HSUB_U 011110 111.. ..... ..... ..... 010101 @3r =20 FCAF 011110 0000 . ..... ..... ..... 011010 @3rf FCUN 011110 0001 . ..... ..... ..... 011010 @3rf diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 0c7055c68bd..e1da532e5c9 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -44,13 +44,11 @@ enum { OPC_ADD_A_df =3D (0x0 << 23) | OPC_MSA_3R_10, OPC_SUBS_S_df =3D (0x0 << 23) | OPC_MSA_3R_11, OPC_MULV_df =3D (0x0 << 23) | OPC_MSA_3R_12, - OPC_DOTP_S_df =3D (0x0 << 23) | OPC_MSA_3R_13, OPC_SRA_df =3D (0x1 << 23) | OPC_MSA_3R_0D, OPC_SUBV_df =3D (0x1 << 23) | OPC_MSA_3R_0E, OPC_ADDS_A_df =3D (0x1 << 23) | OPC_MSA_3R_10, OPC_SUBS_U_df =3D (0x1 << 23) | OPC_MSA_3R_11, OPC_MADDV_df =3D (0x1 << 23) | OPC_MSA_3R_12, - OPC_DOTP_U_df =3D (0x1 << 23) | OPC_MSA_3R_13, OPC_SRAR_df =3D (0x1 << 23) | OPC_MSA_3R_15, OPC_SRL_df =3D (0x2 << 23) | OPC_MSA_3R_0D, OPC_MAX_S_df =3D (0x2 << 23) | OPC_MSA_3R_0E, @@ -58,7 +56,6 @@ enum { OPC_ADDS_S_df =3D (0x2 << 23) | OPC_MSA_3R_10, OPC_SUBSUS_U_df =3D (0x2 << 23) | OPC_MSA_3R_11, OPC_MSUBV_df =3D (0x2 << 23) | OPC_MSA_3R_12, - OPC_DPADD_S_df =3D (0x2 << 23) | OPC_MSA_3R_13, OPC_PCKEV_df =3D (0x2 << 23) | OPC_MSA_3R_14, OPC_SRLR_df =3D (0x2 << 23) | OPC_MSA_3R_15, OPC_BCLR_df =3D (0x3 << 23) | OPC_MSA_3R_0D, @@ -66,7 +63,6 @@ enum { OPC_CLT_U_df =3D (0x3 << 23) | OPC_MSA_3R_0F, OPC_ADDS_U_df =3D (0x3 << 23) | OPC_MSA_3R_10, OPC_SUBSUU_S_df =3D (0x3 << 23) | OPC_MSA_3R_11, - OPC_DPADD_U_df =3D (0x3 << 23) | OPC_MSA_3R_13, OPC_PCKOD_df =3D (0x3 << 23) | OPC_MSA_3R_14, OPC_BSET_df =3D (0x4 << 23) | OPC_MSA_3R_0D, OPC_MIN_S_df =3D (0x4 << 23) | OPC_MSA_3R_0E, @@ -74,30 +70,24 @@ enum { OPC_AVE_S_df =3D (0x4 << 23) | OPC_MSA_3R_10, OPC_ASUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_11, OPC_DIV_S_df =3D (0x4 << 23) | OPC_MSA_3R_12, - OPC_DPSUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_13, OPC_ILVL_df =3D (0x4 << 23) | OPC_MSA_3R_14, - OPC_HADD_S_df =3D (0x4 << 23) | OPC_MSA_3R_15, OPC_BNEG_df =3D (0x5 << 23) | OPC_MSA_3R_0D, OPC_MIN_U_df =3D (0x5 << 23) | OPC_MSA_3R_0E, OPC_CLE_U_df =3D (0x5 << 23) | OPC_MSA_3R_0F, OPC_AVE_U_df =3D (0x5 << 23) | OPC_MSA_3R_10, OPC_ASUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_11, OPC_DIV_U_df =3D (0x5 << 23) | OPC_MSA_3R_12, - OPC_DPSUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_13, OPC_ILVR_df =3D (0x5 << 23) | OPC_MSA_3R_14, - OPC_HADD_U_df =3D (0x5 << 23) | OPC_MSA_3R_15, OPC_BINSL_df =3D (0x6 << 23) | OPC_MSA_3R_0D, OPC_MAX_A_df =3D (0x6 << 23) | OPC_MSA_3R_0E, OPC_AVER_S_df =3D (0x6 << 23) | OPC_MSA_3R_10, OPC_MOD_S_df =3D (0x6 << 23) | OPC_MSA_3R_12, OPC_ILVEV_df =3D (0x6 << 23) | OPC_MSA_3R_14, - OPC_HSUB_S_df =3D (0x6 << 23) | OPC_MSA_3R_15, OPC_BINSR_df =3D (0x7 << 23) | OPC_MSA_3R_0D, OPC_MIN_A_df =3D (0x7 << 23) | OPC_MSA_3R_0E, OPC_AVER_U_df =3D (0x7 << 23) | OPC_MSA_3R_10, OPC_MOD_U_df =3D (0x7 << 23) | OPC_MSA_3R_12, OPC_ILVOD_df =3D (0x7 << 23) | OPC_MSA_3R_14, - OPC_HSUB_U_df =3D (0x7 << 23) | OPC_MSA_3R_15, =20 /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ OPC_SLDI_df =3D (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, @@ -209,6 +199,10 @@ static inline bool check_msa_access(DisasContext *ctx) TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \ gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d) =20 +#define TRANS_DF_B(NAME, trans_func, gen_func) \ + TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \ + NULL, gen_func##_h, gen_func##_w, gen_func##_d) + static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, TCGCond cond) { @@ -484,10 +478,61 @@ static bool trans_msa_3r_df(DisasContext *ctx, arg_ms= a_r *a, return true; } =20 +static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, + void (*gen_msa_3r_b)(TCGv_ptr, TCGv_i32, + TCGv_i32, TCGv_i32), + void (*gen_msa_3r_h)(TCGv_ptr, TCGv_i32, + TCGv_i32, TCGv_i32), + void (*gen_msa_3r_w)(TCGv_ptr, TCGv_i32, + TCGv_i32, TCGv_i32), + void (*gen_msa_3r_d)(TCGv_ptr, TCGv_i32, + TCGv_i32, TCGv_i32)) +{ + TCGv_i32 twd =3D tcg_const_i32(a->wd); + TCGv_i32 tws =3D tcg_const_i32(a->ws); + TCGv_i32 twt =3D tcg_const_i32(a->wt); + + switch (a->df) { + case DF_BYTE: + if (gen_msa_3r_b =3D=3D NULL) { + gen_reserved_instruction(ctx); + } else { + gen_msa_3r_b(cpu_env, twd, tws, twt); + } + break; + case DF_HALF: + gen_msa_3r_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_msa_3r_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_msa_3r_d(cpu_env, twd, tws, twt); + break; + } + + tcg_temp_free_i32(twt); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twd); + + return true; +} + +TRANS_DF_B(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); +TRANS_DF_B(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); +TRANS_DF_B(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); +TRANS_DF_B(DPADD_U, trans_msa_3r, gen_helper_msa_dpadd_u); +TRANS_DF_B(DPSUB_S, trans_msa_3r, gen_helper_msa_dpsub_s); +TRANS_DF_B(DPSUB_U, trans_msa_3r, gen_helper_msa_dpsub_u); + TRANS_MSA(SLD, trans_msa_3r_df, gen_helper_msa_sld_df); TRANS_MSA(SPLAT, trans_msa_3r_df, gen_helper_msa_splat_df); =20 TRANS_MSA(VSHF, trans_msa_3r_df, gen_helper_msa_vshf_df); +TRANS_DF_B(HADD_S, trans_msa_3r, gen_helper_msa_hadd_s); +TRANS_DF_B(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u); +TRANS_DF_B(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s); +TRANS_DF_B(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u); =20 static void gen_msa_3r(DisasContext *ctx) { @@ -1303,154 +1348,6 @@ static void gen_msa_3r(DisasContext *ctx) break; } break; - - case OPC_DOTP_S_df: - case OPC_DOTP_U_df: - case OPC_DPADD_S_df: - case OPC_DPADD_U_df: - case OPC_DPSUB_S_df: - case OPC_HADD_S_df: - case OPC_DPSUB_U_df: - case OPC_HADD_U_df: - case OPC_HSUB_S_df: - case OPC_HSUB_U_df: - if (df =3D=3D DF_BYTE) { - gen_reserved_instruction(ctx); - break; - } - switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_HADD_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HADD_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HSUB_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HSUB_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DOTP_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DOTP_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPADD_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPADD_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPSUB_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPSUB_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - } - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); --=20 2.31.1