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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id u6sm6838413wmc.29.2021.10.23.14.49.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Oct 2021 14:49:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V2YNKMYkRLSbMPSCXijWN2U7P7p3cWA9eRMds81+W0U=; b=R0LB1uqQ4MWMkYp6R71QWzcRyJEWnt2arHEZpPEpHPe9sL7rVaZqdS/RxLPnPWoq8Y Q0nTyY1PW1tS8aPF0hVsfJTfIhD7AZ5MFUspJEUxCYd5nGGLqMmXurf+L/WYeCmLVJVe c9UhjKqZPwmbs3IZpn6eF1ohP3Bs5BD7A/5yqV5f5ggDlyBYeQvgp66DmyTnMtNH9wNk NI3iUiKdFwOvfLzRraauXeL/mTupNXe+CrSVDvyVK6XOa749MsDRZ3TsEgIqoflpEkBj Vgv3FS/DNykvJAyuctSZvy2BKNhmdBGhVfyMgxtALQ+NCZe3cYuxZK8f8BLBgZSUJE0U KTjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=V2YNKMYkRLSbMPSCXijWN2U7P7p3cWA9eRMds81+W0U=; b=Z9fqCCA/GIOi/oGL/4I8xLzkyb/vlOgyBK2ZQFxA2LL8qV6qZarM0L9RL3P1jwtjsD 2DHhcJarKXi/s8vaBIzrUNWn+SH0p6j1MbBr3fkvfdc/5qU+pY9CQ0rKMo5sjo0bfCar A+6LFVZM3Jq0e8gTybhIzH458XZwK8wCAEbIte6Al/UoSgqdC7CPzd5Iv1DEWAS5v1gA AueOO0wL3WMOFG4fwhnC96d3uUKFBNyIpHh3+APmigsrqk5H/9M8B1XAuOsXVRTxHqZt oco1/DZCggzDXU/N8L7ufrIeLl0UjoGK1DElFpPOk35F0l3GyN6SVk1XvnpfiPFZZJga LAsA== X-Gm-Message-State: AOAM530WpTm/JbiNV7zoY0CVhrF8KP6QXJPp6QvjaMfl3y6SM+P/gxWr H7O4wTE/thuOEiIA6DZZdlU= X-Google-Smtp-Source: ABdhPJz5dRGwPZc7LkHZtG2qC48I5pTexe744dEl1UPOqSWkKYvoYb4+CX9xlnttuY5ppSUwjd2Sgg== X-Received: by 2002:a05:600c:210a:: with SMTP id u10mr19890632wml.139.1635025777611; Sat, 23 Oct 2021 14:49:37 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Luis Pires Subject: [PATCH 19/33] target/mips: Convert MSA VEC instruction format to decodetree Date: Sat, 23 Oct 2021 23:47:49 +0200 Message-Id: <20211023214803.522078-20-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211023214803.522078-1-f4bug@amsat.org> References: <20211023214803.522078-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635025779877100001 Convert 3-register instructions with implicit data formats to decodetree. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/msa.decode | 8 ++++ target/mips/tcg/msa_translate.c | 82 +++++++-------------------------- 2 files changed, 24 insertions(+), 66 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 88757f547eb..72447041fef 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -21,6 +21,7 @@ @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_ldst @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=3D0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=3D0 @2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=3D0 @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_ldst @@ -77,6 +78,13 @@ BNZ 010001 111 .. ..... ................= @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit =20 + AND_V 011110 00000 ..... ..... ..... 011110 @vec + OR_V 011110 00001 ..... ..... ..... 011110 @vec + NOR_V 011110 00010 ..... ..... ..... 011110 @vec + XOR_V 011110 00011 ..... ..... ..... 011110 @vec + BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec + BMZ_V 011110 00101 ..... ..... ..... 011110 @vec + BSEL_V 011110 00110 ..... ..... ..... 011110 @vec FILL 011110 11000000 .. ..... ..... 011110 @2r PCNT 011110 11000001 .. ..... ..... 011110 @2r NLOC 011110 11000010 .. ..... ..... 011110 @2r diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index f54e9d173ac..461a427c9df 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -37,19 +37,9 @@ enum { OPC_MSA_3RF_1A =3D 0x1A | OPC_MSA, OPC_MSA_3RF_1B =3D 0x1B | OPC_MSA, OPC_MSA_3RF_1C =3D 0x1C | OPC_MSA, - OPC_MSA_VEC =3D 0x1E | OPC_MSA, }; =20 enum { - /* VEC/2R instruction */ - OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, - OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, - OPC_NOR_V =3D (0x02 << 21) | OPC_MSA_VEC, - OPC_XOR_V =3D (0x03 << 21) | OPC_MSA_VEC, - OPC_BMNZ_V =3D (0x04 << 21) | OPC_MSA_VEC, - OPC_BMZ_V =3D (0x05 << 21) | OPC_MSA_VEC, - OPC_BSEL_V =3D (0x06 << 21) | OPC_MSA_VEC, - /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, @@ -1925,67 +1915,30 @@ TRANS_MSA(FTINT_U, trans_msa_2rf, gen_helper_msa_f= tint_u_df); TRANS_MSA(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); TRANS_MSA(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); =20 -static void gen_msa_vec_v(DisasContext *ctx) +static bool trans_msa_vec(DisasContext *ctx, arg_msa_r *a, + void (*gen_msa_vec)(TCGv_ptr, TCGv_i32, + TCGv_i32, TCGv_i32)) { -#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); + TCGv_i32 twd =3D tcg_const_i32(a->wd); + TCGv_i32 tws =3D tcg_const_i32(a->ws); + TCGv_i32 twt =3D tcg_const_i32(a->wt); =20 - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - gen_helper_msa_and_v(cpu_env, twd, tws, twt); - break; - case OPC_OR_V: - gen_helper_msa_or_v(cpu_env, twd, tws, twt); - break; - case OPC_NOR_V: - gen_helper_msa_nor_v(cpu_env, twd, tws, twt); - break; - case OPC_XOR_V: - gen_helper_msa_xor_v(cpu_env, twd, tws, twt); - break; - case OPC_BMNZ_V: - gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt); - break; - case OPC_BMZ_V: - gen_helper_msa_bmz_v(cpu_env, twd, tws, twt); - break; - case OPC_BSEL_V: - gen_helper_msa_bsel_v(cpu_env, twd, tws, twt); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } + gen_msa_vec(cpu_env, twd, tws, twt); =20 tcg_temp_free_i32(twd); tcg_temp_free_i32(tws); tcg_temp_free_i32(twt); + + return true; } =20 -static void gen_msa_vec(DisasContext *ctx) -{ - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - case OPC_OR_V: - case OPC_NOR_V: - case OPC_XOR_V: - case OPC_BMNZ_V: - case OPC_BMZ_V: - case OPC_BSEL_V: - gen_msa_vec_v(ctx); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } -} +TRANS_MSA(AND_V, trans_msa_vec, gen_helper_msa_and_v); +TRANS_MSA(OR_V, trans_msa_vec, gen_helper_msa_or_v); +TRANS_MSA(NOR_V, trans_msa_vec, gen_helper_msa_nor_v); +TRANS_MSA(XOR_V, trans_msa_vec, gen_helper_msa_xor_v); +TRANS_MSA(BMNZ_V, trans_msa_vec, gen_helper_msa_bmnz_v); +TRANS_MSA(BMZ_V, trans_msa_vec, gen_helper_msa_bmz_v); +TRANS_MSA(BSEL_V, trans_msa_vec, gen_helper_msa_bsel_v); =20 static bool trans_MSA(DisasContext *ctx, arg_MSA *a) { @@ -2015,9 +1968,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_3RF_1C: gen_msa_3rf(ctx); break; - case OPC_MSA_VEC: - gen_msa_vec(ctx); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); --=20 2.31.1