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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id i24sm12150286wml.26.2021.10.23.14.48.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Oct 2021 14:48:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7Twe1tKnuWtesTnk71X2V6F+BbjJ4TQgKol2D+Vvz98=; b=Hex5MOIbTKi1Zje7/On3X7aAcBD4ucfx4PfSBAbK9aBW4bIEskzrmfAIIufvT/2oey hUAKU37Xu2WAjIQKWKu4z3SPMqOsqlgUaYcJk3AY7nDbIV9d1IK3G/1+rzo9tkSeTXNQ bHOsC6A9nbmp8703Q6DwCCMYBFvDOc4E8UTN2YvqZMYIUNL7Ry8J1DmkWiYHJF2bPWzI jTq5MFl9rYrhLemRIOxCKCNEUghX+DqGpZOQJFSBbOCfMEsVy/12oHHwU4oOk5N1ra6P mOlpxpv2jT8c/LDtSxiPO0v1AdmxhFeC0oR6+V6OaCOnF0UhT3Ji0PTr/sThTF/8HF6u rDbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=7Twe1tKnuWtesTnk71X2V6F+BbjJ4TQgKol2D+Vvz98=; b=XLHgeIhN9g5/Lj3IO4t4WRiZ50XMSxxjIcMnrvt8dMwDLHlTqxNbI16xxYiZdN+wcN S9Zpsak4EJXmbsWNOhaJMNuqkkhhIlJjBrTcSLwSgoOdYXDEbV5PxPsXUuH0tI8gAA2B BGRWAaHW3lYxWlPaaw5RApzSdxQAk1Cs4do5QCGMonWCqcU0ZGT9KJbZeb3hWgz+Aa7C EqQWREw0FyrUJ7rkVOWLb4kFESKNAnFMhT4jzQZr4NRZvv07ZYD3Ia0q4Rsx+EifuObY tYaKgUtjKAnmFze67Sve4xWeOel6GRPRkMWAbmxv/Xl/gx+U72VxrY2h5QOZFEPDJuW6 BVmw== X-Gm-Message-State: AOAM531p5UZ2kXBMLsdw9yn8nA0P3UEv25xzJu53tMaw4ONoarPum8rV mflmhbBtJtJO6QKrNmWaLeQ= X-Google-Smtp-Source: ABdhPJzoSAq9XsjF3ihflLJxgI9lHbsMLHMQbcqWRJnpTiP2iegX/umLs+p4DkI1OQlmQfHkOt1R0Q== X-Received: by 2002:a5d:4a4d:: with SMTP id v13mr10441801wrs.353.1635025738685; Sat, 23 Oct 2021 14:48:58 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Luis Pires Subject: [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree Date: Sat, 23 Oct 2021 23:47:41 +0200 Message-Id: <20211023214803.522078-12-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211023214803.522078-1-f4bug@amsat.org> References: <20211023214803.522078-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1635025740732100001 Convert instructions with a 5-bit immediate value to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/msa.decode | 15 +++++ target/mips/tcg/msa_translate.c | 99 +++++++++------------------------ 2 files changed, 40 insertions(+), 74 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 86aa66f05b9..5aaa85456da 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -19,6 +19,8 @@ @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3D3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_ldst +@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_ldst @ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldst ws= =3D0 =20 LSA 000000 ..... ..... ..... 000 .. 000101 @lsa @@ -30,6 +32,19 @@ BZ 010001 110 .. ..... ................= @bz BNZ 010001 111 .. ..... ................ @bz =20 { + ADDVI 011110 000 .. ..... ..... ..... 000110 @u5 + SUBVI 011110 001 .. ..... ..... ..... 000110 @u5 + MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5 + MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5 + MINI_S 011110 100 .. ..... ..... ..... 000110 @s5 + MINI_U 011110 101 .. ..... ..... ..... 000110 @u5 + + CEQI 011110 000 .. ..... ..... ..... 000111 @s5 + CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5 + CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5 + CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5 + CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5 + LDI 011110 110 .. .......... ..... 000111 @ldi =20 MSA 011110 -------------------------- diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 7c1bbfaec61..962aef601cb 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -27,8 +27,6 @@ enum { OPC_MSA_I8_00 =3D 0x00 | OPC_MSA, OPC_MSA_I8_01 =3D 0x01 | OPC_MSA, OPC_MSA_I8_02 =3D 0x02 | OPC_MSA, - OPC_MSA_I5_06 =3D 0x06 | OPC_MSA, - OPC_MSA_I5_07 =3D 0x07 | OPC_MSA, OPC_MSA_BIT_09 =3D 0x09 | OPC_MSA, OPC_MSA_BIT_0A =3D 0x0A | OPC_MSA, OPC_MSA_3R_0D =3D 0x0D | OPC_MSA, @@ -58,19 +56,6 @@ enum { }; =20 enum { - /* I5 instruction df(bits 22..21) =3D _b, _h, _w, _d */ - OPC_ADDVI_df =3D (0x0 << 23) | OPC_MSA_I5_06, - OPC_CEQI_df =3D (0x0 << 23) | OPC_MSA_I5_07, - OPC_SUBVI_df =3D (0x1 << 23) | OPC_MSA_I5_06, - OPC_MAXI_S_df =3D (0x2 << 23) | OPC_MSA_I5_06, - OPC_CLTI_S_df =3D (0x2 << 23) | OPC_MSA_I5_07, - OPC_MAXI_U_df =3D (0x3 << 23) | OPC_MSA_I5_06, - OPC_CLTI_U_df =3D (0x3 << 23) | OPC_MSA_I5_07, - OPC_MINI_S_df =3D (0x4 << 23) | OPC_MSA_I5_06, - OPC_CLEI_S_df =3D (0x4 << 23) | OPC_MSA_I5_07, - OPC_MINI_U_df =3D (0x5 << 23) | OPC_MSA_I5_06, - OPC_CLEI_U_df =3D (0x5 << 23) | OPC_MSA_I5_07, - /* I8 instruction */ OPC_ANDI_B =3D (0x0 << 24) | OPC_MSA_I8_00, OPC_BMNZI_B =3D (0x0 << 24) | OPC_MSA_I8_01, @@ -341,6 +326,9 @@ static inline bool check_msa_access(DisasContext *ctx) return true; } =20 +#define TRANS_MSA(NAME, trans_func, gen_func) \ + TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, gen_func) + static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, TCGCond cond) { @@ -507,69 +495,36 @@ static void gen_msa_i8(DisasContext *ctx) tcg_temp_free_i32(ti8); } =20 -static void gen_msa_i5(DisasContext *ctx) +static bool trans_msa_i5(DisasContext *ctx, arg_msa_ldst *a, + void (*gen_msa_i5)(TCGv_ptr, TCGv_i32, TCGv_i32, + TCGv_i32, TCGv_i32)) { -#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - int8_t s5 =3D (int8_t) sextract32(ctx->opcode, 16, 5); - uint8_t u5 =3D extract32(ctx->opcode, 16, 5); + TCGv_i32 tdf =3D tcg_constant_i32(a->df); + TCGv_i32 twd =3D tcg_const_i32(a->wd); + TCGv_i32 tws =3D tcg_const_i32(a->ws); + TCGv_i32 timm =3D tcg_const_i32(a->sa); =20 - TCGv_i32 tdf =3D tcg_const_i32(extract32(ctx->opcode, 21, 2)); - TCGv_i32 twd =3D tcg_const_i32(extract32(ctx->opcode, 11, 5)); - TCGv_i32 tws =3D tcg_const_i32(extract32(ctx->opcode, 6, 5)); - TCGv_i32 timm =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(timm, u5); + gen_msa_i5(cpu_env, tdf, twd, tws, timm); =20 - switch (MASK_MSA_I5(ctx->opcode)) { - case OPC_ADDVI_df: - gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_SUBVI_df: - gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MAXI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MAXI_U_df: - gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MINI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MINI_U_df: - gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CEQI_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLTI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLTI_U_df: - gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLEI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLEI_U_df: - gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(tdf); tcg_temp_free_i32(twd); tcg_temp_free_i32(tws); tcg_temp_free_i32(timm); + + return true; } =20 +TRANS_MSA(ADDVI, trans_msa_i5, gen_helper_msa_addvi_df); +TRANS_MSA(SUBVI, trans_msa_i5, gen_helper_msa_subvi_df); +TRANS_MSA(MAXI_S, trans_msa_i5, gen_helper_msa_maxi_s_df); +TRANS_MSA(MAXI_U, trans_msa_i5, gen_helper_msa_maxi_u_df); +TRANS_MSA(MINI_S, trans_msa_i5, gen_helper_msa_mini_s_df); +TRANS_MSA(MINI_U, trans_msa_i5, gen_helper_msa_mini_u_df); +TRANS_MSA(CLTI_S, trans_msa_i5, gen_helper_msa_clti_s_df); +TRANS_MSA(CLTI_U, trans_msa_i5, gen_helper_msa_clti_u_df); +TRANS_MSA(CLEI_S, trans_msa_i5, gen_helper_msa_clei_s_df); +TRANS_MSA(CLEI_U, trans_msa_i5, gen_helper_msa_clei_u_df); +TRANS_MSA(CEQI, trans_msa_i5, gen_helper_msa_ceqi_df); + static bool trans_LDI(DisasContext *ctx, arg_msa_ldst *a) { TCGv_i32 tdf; @@ -2196,10 +2151,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_I8_02: gen_msa_i8(ctx); break; - case OPC_MSA_I5_06: - case OPC_MSA_I5_07: - gen_msa_i5(ctx); - break; case OPC_MSA_BIT_09: case OPC_MSA_BIT_0A: gen_msa_bit(ctx); --=20 2.31.1