[PATCH 0/3] target/mips: MSA opcode fixes

Philippe Mathieu-Daudé posted 3 patches 2 years, 5 months ago
Test checkpatch passed
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20211022174550.36937-1-f4bug@amsat.org
Maintainers: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>
target/mips/tcg/msa_helper.c | 64 ++++++++++++++++++------------------
target/mips/cpu-defs.c.inc   |  1 +
2 files changed, 33 insertions(+), 32 deletions(-)
[PATCH 0/3] target/mips: MSA opcode fixes
Posted by Philippe Mathieu-Daudé 2 years, 5 months ago
Fix a pair of MSA opcodes, and update the MSA_IR config register
in the Loongson-3A4000 model.

Philippe Mathieu-Daudé (3):
  target/mips: Fix MSA MADDV.B opcode
  target/mips: Fix MSA MSUBV.B opcode
  target/mips: Fix Loongson-3A4000 MSAIR config register

 target/mips/tcg/msa_helper.c | 64 ++++++++++++++++++------------------
 target/mips/cpu-defs.c.inc   |  1 +
 2 files changed, 33 insertions(+), 32 deletions(-)

-- 
2.31.1

Re: [PATCH 0/3] target/mips: MSA opcode fixes
Posted by Philippe Mathieu-Daudé 2 years, 5 months ago
On 10/22/21 19:45, Philippe Mathieu-Daudé wrote:
> Fix a pair of MSA opcodes, and update the MSA_IR config register
> in the Loongson-3A4000 model.
> 
> Philippe Mathieu-Daudé (3):
>   target/mips: Fix MSA MADDV.B opcode
>   target/mips: Fix MSA MSUBV.B opcode

Patches 1 & 2 applied to mips-next.