From nobody Mon Feb 9 15:28:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634829720202686.034617646656; Thu, 21 Oct 2021 08:22:00 -0700 (PDT) Received: from localhost ([::1]:50712 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdZtH-0007fA-0P for importer@patchew.org; Thu, 21 Oct 2021 11:21:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53964) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdZln-0007wN-A5; Thu, 21 Oct 2021 11:14:16 -0400 Received: from atcsqr.andestech.com ([60.248.187.195]:24329) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdZli-0007Ch-A1; Thu, 21 Oct 2021 11:14:14 -0400 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 19LFDCAM088677; Thu, 21 Oct 2021 23:13:12 +0800 (GMT-8) (envelope-from ruinland@andestech.com) Received: from APC301.andestech.com (10.0.12.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 21 Oct 2021 23:13:15 +0800 From: Ruinland Chuan-Tzu Tsai To: , , Subject: [RFC PATCH v5 1/3] riscv: Adding Andes A25 and AX25 cpu models Date: Thu, 21 Oct 2021 23:09:19 +0800 Message-ID: <20211021150921.721630-2-ruinland@andestech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021150921.721630-1-ruinland@andestech.com> References: <20211021150921.721630-1-ruinland@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.12.120] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 19LFDCAM088677 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.187.195; envelope-from=ruinland@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ycliang@andestech.com, alankao@andestech.com, dylan@andestech.com, qemu-devel@nongnu.org, Ruinland Chuan-Tzu Tsai , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634829721644100003 Content-Type: text/plain; charset="utf-8" Introduce A25 and AX25 CPU model designed by Andes Technology. Signed-off-by: Ruinland Chuan-Tzu Tsai Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 16 ++++++++++++++++ target/riscv/cpu.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7c626d89cd..0c93b7edd7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -168,6 +168,13 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, RV64); } =20 +static void ax25_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); +} + static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -222,6 +229,13 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } + +static void a25_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); +} #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -789,8 +803,10 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init= ), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_A25, a25_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_AX25, ax25_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5896aca346..3bef0d1265 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -37,6 +37,8 @@ #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") +#define TYPE_RISCV_CPU_A25 RISCV_CPU_TYPE_NAME("andes-a25") +#define TYPE_RISCV_CPU_AX25 RISCV_CPU_TYPE_NAME("andes-ax25") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") --=20 2.25.1 From nobody Mon Feb 9 15:28:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634829452996467.32996817469586; Thu, 21 Oct 2021 08:17:32 -0700 (PDT) Received: from localhost ([::1]:44438 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdZox-0003MZ-EE for importer@patchew.org; Thu, 21 Oct 2021 11:17:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53942) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdZll-0007tu-AQ; Thu, 21 Oct 2021 11:14:13 -0400 Received: from atcsqr.andestech.com ([60.248.187.195]:24330) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdZli-0007Ci-87; Thu, 21 Oct 2021 11:14:13 -0400 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 19LFDMSV088710; Thu, 21 Oct 2021 23:13:22 +0800 (GMT-8) (envelope-from ruinland@andestech.com) Received: from APC301.andestech.com (10.0.12.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 21 Oct 2021 23:13:22 +0800 From: Ruinland Chuan-Tzu Tsai To: , , Subject: [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw() Date: Thu, 21 Oct 2021 23:09:20 +0800 Message-ID: <20211021150921.721630-3-ruinland@andestech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021150921.721630-1-ruinland@andestech.com> References: <20211021150921.721630-1-ruinland@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.12.120] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 19LFDMSV088710 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.187.195; envelope-from=ruinland@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ycliang@andestech.com, alankao@andestech.com, dylan@andestech.com, qemu-devel@nongnu.org, Ruinland Chuan-Tzu Tsai , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634829454327100001 Content-Type: text/plain; charset="utf-8" riscv_csrrw() will be called by CSR handling helpers, which is the most suitable place for checking wheter a custom CSR is being accessed. If we're touching a custom CSR, invoke the registered handlers. Signed-off-by: Ruinland Chuan-Tzu Tsai --- target/riscv/cpu.c | 19 +++++++++++++++++ target/riscv/cpu.h | 13 +++++++++++- target/riscv/csr.c | 38 +++++++++++++++++++++++++++------- target/riscv/custom_csr_defs.h | 7 +++++++ 4 files changed, 68 insertions(+), 9 deletions(-) create mode 100644 target/riscv/custom_csr_defs.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0c93b7edd7..a72fd32f01 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -34,6 +34,9 @@ =20 static const char riscv_exts[26] =3D "IEMAFDQCLBJTPVNSUHKORWXYZG"; =20 +GHashTable *custom_csr_map =3D NULL; +#include "custom_csr_defs.h" + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -149,6 +152,22 @@ static void set_resetvec(CPURISCVState *env, target_ul= ong resetvec) #endif } =20 +static void setup_custom_csr(CPURISCVState *env, + riscv_custom_csr_operations csr_map_struct[]) +{ + int i; + env->custom_csr_map =3D g_hash_table_new(g_direct_hash, g_direct_equal= ); + for (i =3D 0; i < MAX_CUSTOM_CSR_NUM; i++) { + if (csr_map_struct[i].csrno !=3D 0) { + g_hash_table_insert(env->custom_csr_map, + GINT_TO_POINTER(csr_map_struct[i].csrno), + &csr_map_struct[i].csr_opset); + } else { + break; + } + } +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3bef0d1265..012be10d0a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -245,6 +245,11 @@ struct CPURISCVState { =20 /* Fields from here on are preserved across CPU reset. */ QEMUTimer *timer; /* Internal timer */ + + /* Custom CSR opset table per hart */ + GHashTable *custom_csr_map; =20 + /* Custom CSR value holder per hart */ = =20 + void *custom_csr_val; =20 }; =20 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, @@ -496,9 +501,15 @@ typedef struct { riscv_csr_op_fn op; } riscv_csr_operations; =20 +typedef struct { + int csrno; + riscv_csr_operations csr_opset; +} riscv_custom_csr_operations; + /* CSR function table constants */ enum { - CSR_TABLE_SIZE =3D 0x1000 + CSR_TABLE_SIZE =3D 0x1000, + MAX_CUSTOM_CSR_NUM =3D 100 }; =20 /* CSR function table */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 23fbbd3216..1048ee3b44 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1403,6 +1403,14 @@ static RISCVException write_pmpaddr(CPURISCVState *e= nv, int csrno, =20 #endif =20 +/* Custom CSR related routines */ +static gpointer find_custom_csr(CPURISCVState *env, int csrno) +{ + gpointer ret; + ret =3D g_hash_table_lookup(env->custom_csr_map, GINT_TO_POINTER(csrno= )); + return ret; +} + /* * riscv_csrrw - read and/or update control and status register * @@ -1419,6 +1427,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int cs= rno, RISCVException ret; target_ulong old_value; RISCVCPU *cpu =3D env_archcpu(env); + riscv_csr_operations *csr_op; int read_only =3D get_field(csrno, 0xC00) =3D=3D 3; =20 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails = */ @@ -1449,26 +1458,39 @@ RISCVException riscv_csrrw(CPURISCVState *env, int = csrno, return RISCV_EXCP_ILLEGAL_INST; } =20 + /* try to handle_custom_csr */ + if (unlikely(env->custom_csr_map !=3D NULL)) { + riscv_csr_operations *custom_csr_opset =3D (riscv_csr_operations *) + find_custom_csr(env, csrno); + if (custom_csr_opset !=3D NULL) { + csr_op =3D custom_csr_opset; + } else { + csr_op =3D &csr_ops[csrno]; + } + } else { + csr_op =3D &csr_ops[csrno]; + } + /* check predicate */ - if (!csr_ops[csrno].predicate) { + if (!csr_op->predicate) { return RISCV_EXCP_ILLEGAL_INST; } - ret =3D csr_ops[csrno].predicate(env, csrno); + ret =3D csr_op->predicate(env, csrno); if (ret !=3D RISCV_EXCP_NONE) { return ret; } =20 /* execute combined read/write operation if it exists */ - if (csr_ops[csrno].op) { - return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_m= ask); + if (csr_op->op) { + return csr_op->op(env, csrno, ret_value, new_value, write_mask); } =20 /* if no accessor exists then return failure */ - if (!csr_ops[csrno].read) { + if (!csr_op->read) { return RISCV_EXCP_ILLEGAL_INST; } /* read old value */ - ret =3D csr_ops[csrno].read(env, csrno, &old_value); + ret =3D csr_op->read(env, csrno, &old_value); if (ret !=3D RISCV_EXCP_NONE) { return ret; } @@ -1476,8 +1498,8 @@ RISCVException riscv_csrrw(CPURISCVState *env, int cs= rno, /* write value if writable and write mask set, otherwise drop writes */ if (write_mask) { new_value =3D (old_value & ~write_mask) | (new_value & write_mask); - if (csr_ops[csrno].write) { - ret =3D csr_ops[csrno].write(env, csrno, new_value); + if (csr_op->write) { + ret =3D csr_op->write(env, csrno, new_value); if (ret !=3D RISCV_EXCP_NONE) { return ret; } diff --git a/target/riscv/custom_csr_defs.h b/target/riscv/custom_csr_defs.h new file mode 100644 index 0000000000..4dbf8cf1fd --- /dev/null +++ b/target/riscv/custom_csr_defs.h @@ -0,0 +1,7 @@ +/*=20 + * Copyright (c) 2021 Andes Technology Corp. + * SPDX-License-Identifier: GPL-2.0+ + * Custom CSR variables provided by _csr.c + */ + +/* Left blank purposely in this commit. */ --=20 2.25.1 From nobody Mon Feb 9 15:28:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634829629206221.82052254569555; Thu, 21 Oct 2021 08:20:29 -0700 (PDT) Received: from localhost ([::1]:47832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdZrn-0005hp-Ul for importer@patchew.org; Thu, 21 Oct 2021 11:20:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53974) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdZln-0007wQ-VP; Thu, 21 Oct 2021 11:14:16 -0400 Received: from atcsqr.andestech.com ([60.248.187.195]:24331) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdZli-0007Cf-6K; Thu, 21 Oct 2021 11:14:15 -0400 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 19LFDRj6088733; Thu, 21 Oct 2021 23:13:27 +0800 (GMT-8) (envelope-from ruinland@andestech.com) Received: from APC301.andestech.com (10.0.12.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 21 Oct 2021 23:13:29 +0800 From: Ruinland Chuan-Tzu Tsai To: , , Subject: [RFC PATCH v5 3/3] riscv: Enable custom CSR support for Andes AX25 and A25 CPUs Date: Thu, 21 Oct 2021 23:09:21 +0800 Message-ID: <20211021150921.721630-4-ruinland@andestech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021150921.721630-1-ruinland@andestech.com> References: <20211021150921.721630-1-ruinland@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.12.120] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 19LFDRj6088733 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.187.195; envelope-from=ruinland@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ycliang@andestech.com, alankao@andestech.com, dylan@andestech.com, qemu-devel@nongnu.org, Ruinland Chuan-Tzu Tsai , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634829630137100001 Content-Type: text/plain; charset="utf-8" Add CSR bits definitions, CSR table and handler functions for Andes AX25 and A25 CPUs. Also, enable the logic in a(x)25_cpu_init(). Signed-off-by: Ruinland Chuan-Tzu Tsai --- target/riscv/andes_cpu_bits.h | 129 +++++++++++++++++++++++ target/riscv/cpu.c | 4 + target/riscv/csr_andes.c | 183 +++++++++++++++++++++++++++++++++ target/riscv/custom_csr_defs.h | 3 +- target/riscv/meson.build | 1 + 5 files changed, 319 insertions(+), 1 deletion(-) create mode 100644 target/riscv/andes_cpu_bits.h create mode 100644 target/riscv/csr_andes.c diff --git a/target/riscv/andes_cpu_bits.h b/target/riscv/andes_cpu_bits.h new file mode 100644 index 0000000000..84b0900423 --- /dev/null +++ b/target/riscv/andes_cpu_bits.h @@ -0,0 +1,129 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + * + * Andes custom CSRs bit definitions + * + */ + +/* + * =3D=3D=3D=3D=3D=3D=3D=3D=3D Missing drafted/standard CSR definitions = =3D=3D=3D=3D=3D=3D=3D=3D=3D + * TINFO is in official debug sepc, it's not in cpu_bits.h yet. + */ +#define CSR_TINFO 0x7a4 + +#if !defined(CONFIG_USER_ONLY) +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D AndeStar V5 machine mode CSRs =3D=3D=3D=3D= =3D=3D=3D=3D=3D */ +/* Configuration Registers */ +#define CSR_MICM_CFG 0xfc0 +#define CSR_MDCM_CFG 0xfc1 +#define CSR_MMSC_CFG 0xfc2 +#define CSR_MMSC_CFG2 0xfc3 +#define CSR_MVEC_CFG 0xfc7 + +/* Crash Debug CSRs */ +#define CSR_MCRASH_STATESAVE 0xfc8 +#define CSR_MSTATUS_CRASHSAVE 0xfc9 + +/* Memory CSRs */ +#define CSR_MILMB 0x7c0 +#define CSR_MDLMB 0x7c1 +#define CSR_MECC_CODE 0x7C2 +#define CSR_MNVEC 0x7c3 +#define CSR_MCACHE_CTL 0x7ca +#define CSR_MCCTLBEGINADDR 0x7cb +#define CSR_MCCTLCOMMAND 0x7cc +#define CSR_MCCTLDATA 0x7cd +#define CSR_MPPIB 0x7f0 +#define CSR_MFIOB 0x7f1 + +/* Hardware Stack Protection & Recording */ +#define CSR_MHSP_CTL 0x7c6 +#define CSR_MSP_BOUND 0x7c7 +#define CSR_MSP_BASE 0x7c8 +#define CSR_MXSTATUS 0x7c4 +#define CSR_MDCAUSE 0x7c9 +#define CSR_MSLIDELEG 0x7d5 +#define CSR_MSAVESTATUS 0x7d6 +#define CSR_MSAVEEPC1 0x7d7 +#define CSR_MSAVECAUSE1 0x7d8 +#define CSR_MSAVEEPC2 0x7d9 +#define CSR_MSAVECAUSE2 0x7da +#define CSR_MSAVEDCAUSE1 0x7db +#define CSR_MSAVEDCAUSE2 0x7dc + +/* Control CSRs */ +#define CSR_MPFT_CTL 0x7c5 +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MCLK_CTL 0x7df + +/* Counter related CSRs */ +#define CSR_MCOUNTERWEN 0x7ce +#define CSR_MCOUNTERINTEN 0x7cf +#define CSR_MCOUNTERMASK_M 0x7d1 +#define CSR_MCOUNTERMASK_S 0x7d2 +#define CSR_MCOUNTERMASK_U 0x7d3 +#define CSR_MCOUNTEROVF 0x7d4 + +/* Enhanced CLIC CSRs */ +#define CSR_MIRQ_ENTRY 0x7ec +#define CSR_MINTSEL_JAL 0x7ed +#define CSR_PUSHMCAUSE 0x7ee +#define CSR_PUSHMEPC 0x7ef +#define CSR_PUSHMXSTATUS 0x7eb + +/* Andes Physical Memory Attribute(PMA) CSRs */ +#define CSR_PMACFG0 0xbc0 +#define CSR_PMACFG1 0xbc1 +#define CSR_PMACFG2 0xbc2 +#define CSR_PMACFG3 0xbc3 +#define CSR_PMAADDR0 0xbd0 +#define CSR_PMAADDR1 0xbd1 +#define CSR_PMAADDR2 0xbd2 +#define CSR_PMAADDR3 0xbd2 +#define CSR_PMAADDR4 0xbd4 +#define CSR_PMAADDR5 0xbd5 +#define CSR_PMAADDR6 0xbd6 +#define CSR_PMAADDR7 0xbd7 +#define CSR_PMAADDR8 0xbd8 +#define CSR_PMAADDR9 0xbd9 +#define CSR_PMAADDR10 0xbda +#define CSR_PMAADDR11 0xbdb +#define CSR_PMAADDR12 0xbdc +#define CSR_PMAADDR13 0xbdd +#define CSR_PMAADDR14 0xbde +#define CSR_PMAADDR15 0xbdf + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D AndeStar V5 supervisor mode CSRs =3D=3D=3D= =3D=3D=3D=3D=3D=3D */ +/* Supervisor trap registers */ +#define CSR_SLIE 0x9c4 +#define CSR_SLIP 0x9c5 +#define CSR_SDCAUSE 0x9c9 + +/* Supervisor counter registers */ +#define CSR_SCOUNTERINTEN 0x9cf +#define CSR_SCOUNTERMASK_M 0x9d1 +#define CSR_SCOUNTERMASK_S 0x9d2 +#define CSR_SCOUNTERMASK_U 0x9d3 +#define CSR_SCOUNTEROVF 0x9d4 +#define CSR_SCOUNTINHIBIT 0x9e0 +#define CSR_SHPMEVENT3 0x9e3 +#define CSR_SHPMEVENT4 0x9e4 +#define CSR_SHPMEVENT5 0x9e5 +#define CSR_SHPMEVENT6 0x9e6 + +/* Supervisor control registers */ +#define CSR_SCCTLDATA 0x9cd +#define CSR_SMISC_CTL 0x9d0 + +#endif /* !defined(CONFIG_USER_ONLY) */ + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D AndeStar V5 user mode CSRs =3D=3D=3D=3D=3D= =3D=3D=3D=3D */ +/* User mode control registers */ +#define CSR_UITB 0x800 +#define CSR_UCODE 0x801 +#define CSR_UDCAUSE 0x809 +#define CSR_UCCTLBEGINADDR 0x80b +#define CSR_UCCTLCOMMAND 0x80c +#define CSR_WFE 0x810 +#define CSR_SLEEPVALUE 0x811 +#define CSR_TXEVT 0x812 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a72fd32f01..fe63e68b8e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -192,6 +192,8 @@ static void ax25_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + setup_custom_csr(env, andes_custom_csr_table); + env->custom_csr_val =3D g_malloc(andes_custom_csr_size); } =20 static void rv64_sifive_u_cpu_init(Object *obj) @@ -254,6 +256,8 @@ static void a25_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + setup_custom_csr(env, andes_custom_csr_table); + env->custom_csr_val =3D g_malloc(andes_custom_csr_size); } #endif =20 diff --git a/target/riscv/csr_andes.c b/target/riscv/csr_andes.c new file mode 100644 index 0000000000..8617f40483 --- /dev/null +++ b/target/riscv/csr_andes.c @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2021 Andes Technology Corp. + * SPDX-License-Identifier: GPL-2.0+ + * Andes custom CSR table and handling functions + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "cpu.h" +#include "qemu/main-loop.h" +#include "exec/exec-all.h" +#include "andes_cpu_bits.h" + +struct andes_csr_val { + target_long uitb; +}; + +#if !defined(CONFIG_USER_ONLY) +static RISCVException read_mmsc_cfg(CPURISCVState *env, int csrno, target_= ulong *val) +{ + /* enable pma probe */ + *val =3D 0x40000000; + return RISCV_EXCP_NONE; +} +#endif + +static RISCVException write_uitb(CPURISCVState *env, int csrno, target_ulo= ng val) +{ + struct andes_csr_val *andes_csr =3D env->custom_csr_val; + andes_csr->uitb =3D val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_uitb(CPURISCVState *env, int csrno, target_ulon= g *val) +{ + struct andes_csr_val *andes_csr =3D env->custom_csr_val; + *val =3D andes_csr->uitb; + return RISCV_EXCP_NONE; +} + + +static RISCVException any(CPURISCVState *env, int csrno) +{ + return RISCV_EXCP_NONE; +} + +static RISCVException read_zero(CPURISCVState *env, int csrno, target_ulon= g *val) +{ + *val =3D 0; + return RISCV_EXCP_NONE; +} + +static RISCVException write_stub(CPURISCVState *env, int csrno, target_ulo= ng val) +{ + return RISCV_EXCP_NONE; +} + +int andes_custom_csr_size =3D sizeof(struct andes_csr_val); +riscv_custom_csr_operations andes_custom_csr_table[MAX_CUSTOM_CSR_NUM] =3D= { + /* =3D=3D=3D=3D=3D=3D=3D=3D=3D AndeStar V5 machine mode CSRs =3D=3D=3D= =3D=3D=3D=3D=3D=3D */ + #if !defined(CONFIG_USER_ONLY) + /* Configuration Registers */ + {CSR_MICM_CFG, { "micm_cfg", any, read_zero, write_st= ub} }, + {CSR_MDCM_CFG, { "mdcm_cfg", any, read_zero, write_st= ub} }, + {CSR_MMSC_CFG, { "mmsc_cfg", any, read_mmsc_cfg, writ= e_stub} }, + {CSR_MMSC_CFG2, { "mmsc_cfg2", any, read_zero, write_st= ub} }, + {CSR_MVEC_CFG, { "mvec_cfg", any, read_zero, write_st= ub} }, + + /* Crash Debug CSRs */ + {CSR_MCRASH_STATESAVE, { "mcrash_statesave", any, read_zero, write_s= tub} }, + {CSR_MSTATUS_CRASHSAVE, { "mstatus_crashsave", any, read_zero, write_s= tub} }, + + /* Memory CSRs */ + {CSR_MILMB, { "milmb", any, read_zero, write_st= ub} }, + {CSR_MDLMB, { "mdlmb", any, read_zero, write_st= ub} }, + {CSR_MECC_CODE, { "mecc_code", any, read_zero, write_st= ub} }, + {CSR_MNVEC, { "mnvec", any, read_zero, write_st= ub} }, + {CSR_MCACHE_CTL, { "mcache_ctl", any, read_zero, write_st= ub} }, + {CSR_MCCTLBEGINADDR, { "mcctlbeginaddr", any, read_zero, write_st= ub} }, + {CSR_MCCTLCOMMAND, { "mcctlcommand", any, read_zero, write_st= ub} }, + {CSR_MCCTLDATA, { "mcctldata", any, read_zero, write_st= ub} }, + {CSR_MPPIB, { "mppib", any, read_zero, write_st= ub} }, + {CSR_MFIOB, { "mfiob", any, read_zero, write_st= ub} }, + + /* Hardware Stack Protection & Recording */ + {CSR_MHSP_CTL, { "mhsp_ctl", any, read_zero, write_st= ub} }, + {CSR_MSP_BOUND, { "msp_bound", any, read_zero, write_st= ub} }, + {CSR_MSP_BASE, { "msp_base", any, read_zero, write_st= ub} }, + {CSR_MXSTATUS, { "mxstatus", any, read_zero, write_st= ub} }, + {CSR_MDCAUSE, { "mdcause", any, read_zero, write_st= ub} }, + {CSR_MSLIDELEG, { "mslideleg", any, read_zero, write_st= ub} }, + {CSR_MSAVESTATUS, { "msavestatus", any, read_zero, write_st= ub} }, + {CSR_MSAVEEPC1, { "msaveepc1", any, read_zero, write_st= ub} }, + {CSR_MSAVECAUSE1, { "msavecause1", any, read_zero, write_st= ub} }, + {CSR_MSAVEEPC2, { "msaveepc2", any, read_zero, write_st= ub} }, + {CSR_MSAVECAUSE2, { "msavecause2", any, read_zero, write_st= ub} }, + {CSR_MSAVEDCAUSE1, { "msavedcause1", any, read_zero, write_st= ub} }, + {CSR_MSAVEDCAUSE2, { "msavedcause2", any, read_zero, write_st= ub} }, + + /* Control CSRs */ + {CSR_MPFT_CTL, { "mpft_ctl", any, read_zero, write_st= ub} }, + {CSR_MMISC_CTL, { "mmisc_ctl", any, read_zero, write_st= ub} }, + {CSR_MCLK_CTL, { "mclk_ctl", any, read_zero, write_st= ub} }, + + /* Counter related CSRs */ + {CSR_MCOUNTERWEN, { "mcounterwen", any, read_zero, write_st= ub} }, + {CSR_MCOUNTERINTEN, { "mcounterinten", any, read_zero, write_st= ub} }, + {CSR_MCOUNTERMASK_M, { "mcountermask_m", any, read_zero, write_st= ub} }, + {CSR_MCOUNTERMASK_S, { "mcountermask_s", any, read_zero, write_st= ub} }, + {CSR_MCOUNTERMASK_U, { "mcountermask_u", any, read_zero, write_st= ub} }, + {CSR_MCOUNTEROVF, { "mcounterovf", any, read_zero, write_st= ub} }, + + /* Enhanced CLIC CSRs */ + {CSR_MIRQ_ENTRY, { "mirq_entry", any, read_zero, write_st= ub} }, + {CSR_MINTSEL_JAL, { "mintsel_jal", any, read_zero, write_st= ub} }, + {CSR_PUSHMCAUSE, { "pushmcause", any, read_zero, write_st= ub} }, + {CSR_PUSHMEPC, { "pushmepc", any, read_zero, write_st= ub} }, + {CSR_PUSHMXSTATUS, { "pushmxstatus", any, read_zero, write_st= ub} }, + + /* Andes Physical Memory Attribute(PMA) CSRs */ + {CSR_PMACFG0, { "pmacfg0", any, read_zero, write_st= ub} }, + {CSR_PMACFG1, { "pmacfg1", any, read_zero, write_st= ub} }, + {CSR_PMACFG2, { "pmacfg2", any, read_zero, write_st= ub} }, + {CSR_PMACFG3, { "pmacfg3", any, read_zero, write_st= ub} }, + {CSR_PMAADDR0, { "pmaaddr0", any, read_zero, write_st= ub} }, + {CSR_PMAADDR1, { "pmaaddr1", any, read_zero, write_st= ub} }, + {CSR_PMAADDR2, { "pmaaddr2", any, read_zero, write_st= ub} }, + {CSR_PMAADDR3, { "pmaaddr3", any, read_zero, write_st= ub} }, + {CSR_PMAADDR4, { "pmaaddr4", any, read_zero, write_st= ub} }, + {CSR_PMAADDR5, { "pmaaddr5", any, read_zero, write_st= ub} }, + {CSR_PMAADDR6, { "pmaaddr6", any, read_zero, write_st= ub} }, + {CSR_PMAADDR7, { "pmaaddr7", any, read_zero, write_st= ub} }, + {CSR_PMAADDR8, { "pmaaddr8", any, read_zero, write_st= ub} }, + {CSR_PMAADDR9, { "pmaaddr9", any, read_zero, write_st= ub} }, + {CSR_PMAADDR10, { "pmaaddr10", any, read_zero, write_st= ub} }, + {CSR_PMAADDR11, { "pmaaddr11", any, read_zero, write_st= ub} }, + {CSR_PMAADDR12, { "pmaaddr12", any, read_zero, write_st= ub} }, + {CSR_PMAADDR13, { "pmaaddr13", any, read_zero, write_st= ub} }, + {CSR_PMAADDR14, { "pmaaddr14", any, read_zero, write_st= ub} }, + {CSR_PMAADDR15, { "pmaaddr15", any, read_zero, write_st= ub} }, + + /* Debug/Trace Registers (shared with Debug Mode) */ + {CSR_TSELECT, { "tselect", any, read_zero, write_st= ub} }, + {CSR_TDATA1, { "tdata1", any, read_zero, write_st= ub} }, + {CSR_TDATA2, { "tdata2", any, read_zero, write_st= ub} }, + {CSR_TDATA3, { "tdata3", any, read_zero, write_st= ub} }, + {CSR_TINFO, { "tinfo", any, read_zero, write_st= ub} }, + + /* =3D=3D=3D=3D=3D=3D=3D=3D=3D AndeStar V5 supervisor mode CSRs =3D=3D= =3D=3D=3D=3D=3D=3D=3D */ + /* Supervisor trap registers */ + {CSR_SLIE, { "slie", any, read_zero, write_st= ub} }, + {CSR_SLIP, { "slip", any, read_zero, write_st= ub} }, + {CSR_SDCAUSE, { "sdcause", any, read_zero, write_st= ub} }, + + /* Supervisor counter registers */ + {CSR_SCOUNTERINTEN, { "scounterinten", any, read_zero, write_st= ub} }, + {CSR_SCOUNTERMASK_M, { "scountermask_m", any, read_zero, write_st= ub} }, + {CSR_SCOUNTERMASK_S, { "scountermask_s", any, read_zero, write_st= ub} }, + {CSR_SCOUNTERMASK_U, { "scountermask_u", any, read_zero, write_st= ub} }, + {CSR_SCOUNTEROVF, { "scounterovf", any, read_zero, write_st= ub} }, + {CSR_SCOUNTINHIBIT, { "scountinhibit", any, read_zero, write_st= ub} }, + {CSR_SHPMEVENT3, { "shpmevent3", any, read_zero, write_st= ub} }, + {CSR_SHPMEVENT4, { "shpmevent4", any, read_zero, write_st= ub} }, + {CSR_SHPMEVENT5, { "shpmevent5", any, read_zero, write_st= ub} }, + {CSR_SHPMEVENT6, { "shpmevent6", any, read_zero, write_st= ub} }, + + /* Supervisor control registers */ + {CSR_SCCTLDATA, { "scctldata", any, read_zero, write_st= ub} }, + {CSR_SMISC_CTL, { "smisc_ctl", any, read_zero, write_st= ub} }, + #endif + + /* =3D=3D=3D=3D=3D=3D=3D=3D=3D AndeStar V5 user mode CSRs =3D=3D=3D=3D= =3D=3D=3D=3D=3D */ + /* User mode control registers */ + {CSR_UITB, { "uitb", any, read_uitb, write_ui= tb} }, + {CSR_UCODE, { "ucode", any, read_zero, write_st= ub} }, + {CSR_UDCAUSE, { "udcause", any, read_zero, write_st= ub} }, + {CSR_UCCTLBEGINADDR, { "ucctlbeginaddr", any, read_zero, write_st= ub} }, + {CSR_UCCTLCOMMAND, { "ucctlcommand", any, read_zero, write_st= ub} }, + {CSR_WFE, { "wfe", any, read_zero, write_st= ub} }, + {CSR_SLEEPVALUE, { "sleepvalue", any, read_zero, write_st= ub} }, + {CSR_TXEVT, { "csr_txevt", any, read_zero, write_st= ub} }, + {0, { "", NULL, NULL, NULL } }, + }; diff --git a/target/riscv/custom_csr_defs.h b/target/riscv/custom_csr_defs.h index 4dbf8cf1fd..b09083585b 100644 --- a/target/riscv/custom_csr_defs.h +++ b/target/riscv/custom_csr_defs.h @@ -4,4 +4,5 @@ * Custom CSR variables provided by _csr.c */ =20 -/* Left blank purposely in this commit. */ +extern riscv_custom_csr_operations andes_custom_csr_table[MAX_CUSTOM_CSR_N= UM]; +extern int andes_custom_csr_size; diff --git a/target/riscv/meson.build b/target/riscv/meson.build index d5e0bc93ea..5c87672ff9 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -9,6 +9,7 @@ gen =3D [ riscv_ss =3D ss.source_set() riscv_ss.add(gen) riscv_ss.add(files( + 'csr_andes.c', 'cpu.c', 'cpu_helper.c', 'csr.c', --=20 2.25.1