From nobody Sat May 4 15:43:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634738008006343.2961714582799; Wed, 20 Oct 2021 06:53:28 -0700 (PDT) Received: from localhost ([::1]:58846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdC22-0003az-Of for importer@patchew.org; Wed, 20 Oct 2021 09:53:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38202) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdBtf-000127-Dl; Wed, 20 Oct 2021 09:44:47 -0400 Received: from [201.28.113.2] (port=17190 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdBtd-0004Hp-FY; Wed, 20 Oct 2021 09:44:47 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Wed, 20 Oct 2021 09:57:32 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id 164F980045D; Wed, 20 Oct 2021 09:57:32 -0300 (-03) From: "Lucas Mateus Castro (alqotel)" To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 1/2] target/ppc: Fixed call to deferred exception Date: Wed, 20 Oct 2021 09:57:23 -0300 Message-Id: <20211020125724.78028-2-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211020125724.78028-1-lucas.araujo@eldorado.org.br> References: <20211020125724.78028-1-lucas.araujo@eldorado.org.br> X-OriginalArrivalTime: 20 Oct 2021 12:57:32.0321 (UTC) FILETIME=[0BC7C110:01D7C5B2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Lucas Mateus Castro \(alqotel\)" , richard.henderson@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634738009193100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Lucas Mateus Castro (alqotel)" mtfsf, mtfsfi and mtfsb1 instructions call helper_float_check_status after updating the value of FPSCR, but helper_float_check_status checks fp_status and fp_status isn't updated based on FPSCR and since the value of fp_status is reset earlier in the instruction, it's always 0. Because of this helper_float_check_status would change the FI bit to 0 as this bit checks if the last operation was inexact and float_flag_inexact is always 0. These instructions also don't throw exceptions correctly since helper_float_check_status throw exceptions based on fp_status. This commit created a new helper, helper_fpscr_check_status that checks FPSCR value instead of fp_status and checks for a larger variety of exceptions than do_float_check_status. The hardware used to compare QEMU's behavior to, was a Power9. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/266 Signed-off-by: Lucas Mateus Castro (alqotel) --- target/ppc/fpu_helper.c | 41 ++++++++++++++++++++++++++++++ target/ppc/helper.h | 1 + target/ppc/translate/fp-impl.c.inc | 6 ++--- 3 files changed, 45 insertions(+), 3 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c4896cecc8..f086cb503f 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -414,6 +414,47 @@ void helper_store_fpscr(CPUPPCState *env, uint64_t val= , uint32_t nibbles) ppc_store_fpscr(env, val); } =20 +void helper_fpscr_check_status(CPUPPCState *env) +{ + CPUState *cs =3D env_cpu(env); + target_ulong fpscr =3D env->fpscr; + int error =3D 0; + + if ((fpscr & FP_VXSOFT) && (fpscr_ve !=3D 0)) { + error =3D POWERPC_EXCP_FP_VXSOFT; + } else if ((fpscr & FP_OX) && (fpscr & FP_OE)) { + error =3D POWERPC_EXCP_FP_OX; + } else if ((fpscr & FP_UX) && (fpscr & FP_UE)) { + error =3D POWERPC_EXCP_FP_UX; + } else if ((fpscr & FP_XX) && (fpscr & FP_XE)) { + error =3D POWERPC_EXCP_FP_XX; + } else if ((fpscr & FP_ZX) && (fpscr & FP_ZE)) { + error =3D POWERPC_EXCP_FP_ZX; + } else if ((fpscr & FP_VXSNAN) && (fpscr_ve !=3D 0)) { + error =3D POWERPC_EXCP_FP_VXSNAN; + } else if ((fpscr & FP_VXISI) && (fpscr_ve !=3D 0)) { + error =3D POWERPC_EXCP_FP_VXISI; + } else if ((fpscr & FP_VXIDI) && (fpscr_ve !=3D 0)) { + error =3D POWERPC_EXCP_FP_VXIDI; + } else if ((fpscr & FP_VXZDZ) && (fpscr_ve !=3D 0)) { + error =3D POWERPC_EXCP_FP_VXZDZ; + } else if ((fpscr & FP_VXIMZ) && (fpscr_ve !=3D 0)) { + error =3D POWERPC_EXCP_FP_VXIMZ; + } else if ((fpscr & FP_VXVC) && (fpscr_ve !=3D 0)) { + error =3D POWERPC_EXCP_FP_VXVC; + } + + if (error) { + cs->exception_index =3D POWERPC_EXCP_PROGRAM; + env->error_code =3D error | POWERPC_EXCP_FP; + /* Deferred floating-point exception after target FPSCR update */ + if (fp_exceptions_enabled(env)) { + raise_exception_err_ra(env, cs->exception_index, + env->error_code, GETPC()); + } + } +} + static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) { CPUState *cs =3D env_cpu(env); diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 4076aa281e..baa3715e73 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -61,6 +61,7 @@ DEF_HELPER_FLAGS_1(cntlzw32, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_2(brinc, TCG_CALL_NO_RWG_SE, tl, tl, tl) =20 DEF_HELPER_1(float_check_status, void, env) +DEF_HELPER_1(fpscr_check_status, void, env) DEF_HELPER_1(reset_fpstatus, void, env) DEF_HELPER_2(compute_fprf_float64, void, env, i64) DEF_HELPER_3(store_fpscr, void, env, i64, i32) diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-i= mpl.c.inc index 9f7868ee28..0a9b1ecc60 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -782,7 +782,7 @@ static void gen_mtfsb1(DisasContext *ctx) tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a deferred exception */ - gen_helper_float_check_status(cpu_env); + gen_helper_fpscr_check_status(cpu_env); } =20 /* mtfsf */ @@ -818,7 +818,7 @@ static void gen_mtfsf(DisasContext *ctx) tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a deferred exception */ - gen_helper_float_check_status(cpu_env); + gen_helper_fpscr_check_status(cpu_env); tcg_temp_free_i64(t1); } =20 @@ -851,7 +851,7 @@ static void gen_mtfsfi(DisasContext *ctx) tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a deferred exception */ - gen_helper_float_check_status(cpu_env); + gen_helper_fpscr_check_status(cpu_env); } =20 /*** Floating-point load = ***/ --=20 2.31.1 From nobody Sat May 4 15:43:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634738081665458.3062615882924; Wed, 20 Oct 2021 06:54:41 -0700 (PDT) Received: from localhost ([::1]:32854 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdC3E-00057G-HH for importer@patchew.org; Wed, 20 Oct 2021 09:54:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38188) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdBtc-0000pK-Ey; Wed, 20 Oct 2021 09:44:44 -0400 Received: from [201.28.113.2] (port=17190 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdBta-0004Hp-Fj; Wed, 20 Oct 2021 09:44:43 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Wed, 20 Oct 2021 09:57:33 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id 24FAB80045D; Wed, 20 Oct 2021 09:57:33 -0300 (-03) From: "Lucas Mateus Castro (alqotel)" To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 2/2] target/ppc: ppc_store_fpscr doesn't update bit 52 Date: Wed, 20 Oct 2021 09:57:24 -0300 Message-Id: <20211020125724.78028-3-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211020125724.78028-1-lucas.araujo@eldorado.org.br> References: <20211020125724.78028-1-lucas.araujo@eldorado.org.br> X-OriginalArrivalTime: 20 Oct 2021 12:57:33.0384 (UTC) FILETIME=[0C69F480:01D7C5B2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Lucas Mateus Castro \(alqotel\)" , richard.henderson@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634738082357100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Lucas Mateus Castro (alqotel)" This commit fixes the difference reported in the bug in the reserved bit 52, it does this by adding this bit to the mask of bits to not be directly altered in the ppc_store_fpscr function (the hardware used to compare to QEMU was a Power9). Although this is a difference reported in the bug, since it's a reserved bit it may be a "don't care" case, as put in the bug report. Looking at the ISA it doesn't explicitly mentions this bit can't be set, like it does for FEX and VX, so I'm unsure if this is necessary. Signed-off-by: Lucas Mateus Castro (alqotel) --- target/ppc/cpu.c | 2 +- target/ppc/cpu.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index 7ad9bd6044..5c411b32ff 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -112,7 +112,7 @@ static inline void fpscr_set_rounding_mode(CPUPPCState = *env) =20 void ppc_store_fpscr(CPUPPCState *env, target_ulong val) { - val &=3D ~(FP_VX | FP_FEX); + val &=3D FPSCR_MTFS_MASK; if (val & FPSCR_IX) { val |=3D FP_VX; } diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index baa4e7c34d..4b42b281ed 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -736,6 +736,9 @@ enum { FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \ FP_VXSQRT | FP_VXCVI) =20 +/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */ +#define FPSCR_MTFS_MASK ~((1ull << 11) | FP_VX | FP_FEX) + /*************************************************************************= ****/ /* Vector status and control register */ #define VSCR_NJ 16 /* Vector non-java */ --=20 2.31.1