From nobody Tue Feb 10 15:03:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637412309915.5205919560492; Tue, 19 Oct 2021 02:56:52 -0700 (PDT) Received: from localhost ([::1]:34252 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mclrX-0008Rk-4J for importer@patchew.org; Tue, 19 Oct 2021 05:56:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58780) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljp-0000ke-Bi; Tue, 19 Oct 2021 05:48:53 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:54802) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljm-0006WS-Lu; Tue, 19 Oct 2021 05:48:53 -0400 Received: from mailhost.u-ga.fr (mailhost1.u-ga.fr [152.77.1.10]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id 7E25942015; Tue, 19 Oct 2021 11:48:28 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id 668B4601D5; Tue, 19 Oct 2021 11:48:28 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id 43A6114005D; Tue, 19 Oct 2021 11:48:28 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 10/21] target/riscv: support for 128-bit loads and store Date: Tue, 19 Oct 2021 11:48:01 +0200 Message-Id: <20211019094812.614056-11-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637412960100001 The 128-bit ISA adds ldu, lq and sq. We provide here support for these instructions. Note that although we compute a 128-bit address, we only use the lower 64-bit to actually address memory, cowardly utilizing the existing address translation mechanism of QEMU. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- target/riscv/insn16.decode | 32 +++++- target/riscv/insn32.decode | 4 + target/riscv/translate.c | 7 -- target/riscv/insn_trans/trans_rvi.c.inc | 146 ++++++++++++++++++++++-- 4 files changed, 171 insertions(+), 18 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 2e9212663c..151fc6e567 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -39,6 +39,10 @@ %imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=3Dex_shift_4 %imm_lui 12:s1 2:5 !function=3Dex_shift_12 =20 +# Added for 128 bit support +%uimm_cl_q 5:2 10:3 !function=3Dex_shift_3 +%uimm_6bit_lq 2:3 12:1 5:2 !function=3Dex_shift_3 +%uimm_6bit_sq 7:3 10:3 !function=3Dex_shift_3 =20 # Argument sets imported from insn32.decode: &empty !extern @@ -54,16 +58,20 @@ # Formats 16: @cr .... ..... ..... .. &r rs2=3D%rs2_5 rs1=3D%rd = %rd @ci ... . ..... ..... .. &i imm=3D%imm_ci rs1=3D%rd = %rd +@cl_q ... . ..... ..... .. &i imm=3D%uimm_6bit_lq rs1=3D2 %rd @cl_d ... ... ... .. ... .. &i imm=3D%uimm_cl_d rs1=3D%rs1_3 = rd=3D%rs2_3 @cl_w ... ... ... .. ... .. &i imm=3D%uimm_cl_w rs1=3D%rs1_3 = rd=3D%rs2_3 @cs_2 ... ... ... .. ... .. &r rs2=3D%rs2_3 rs1=3D%rs1_3 = rd=3D%rs1_3 +@cs_q ... ... ... .. ... .. &s imm=3D%uimm_cl_q rs1=3D%rs1_3 = rs2=3D%rs2_3 @cs_d ... ... ... .. ... .. &s imm=3D%uimm_cl_d rs1=3D%rs1_3 = rs2=3D%rs2_3 @cs_w ... ... ... .. ... .. &s imm=3D%uimm_cl_w rs1=3D%rs1_3 = rs2=3D%rs2_3 @cj ... ........... .. &j imm=3D%imm_cj @cb_z ... ... ... .. ... .. &b imm=3D%imm_cb rs1=3D%rs1_3 = rs2=3D0 =20 +@c_lqsp ... . ..... ..... .. &i imm=3D%uimm_6bit_lq rs1=3D2 %rd @c_ldsp ... . ..... ..... .. &i imm=3D%uimm_6bit_ld rs1=3D2 %rd @c_lwsp ... . ..... ..... .. &i imm=3D%uimm_6bit_lw rs1=3D2 %rd +@c_sqsp ... . ..... ..... .. &s imm=3D%uimm_6bit_sq rs1=3D2 rs2= =3D%rs2_5 @c_sdsp ... . ..... ..... .. &s imm=3D%uimm_6bit_sd rs1=3D2 rs2= =3D%rs2_5 @c_swsp ... . ..... ..... .. &s imm=3D%uimm_6bit_sw rs1=3D2 rs2= =3D%rs2_5 @c_li ... . ..... ..... .. &i imm=3D%imm_ci rs1=3D0 %rd @@ -87,9 +95,17 @@ illegal 000 000 000 00 --- 00 addi 000 ... ... .. ... 00 @c_addi4spn } -fld 001 ... ... .. ... 00 @cl_d +{ + fld 001 ... ... .. ... 00 @cl_d + # *** RV128C specific Standard Extension (Quadrant 0) *** + lq 001 ... ... .. ... 00 @cl_q +} lw 010 ... ... .. ... 00 @cl_w -fsd 101 ... ... .. ... 00 @cs_d +{ + fsd 101 ... ... .. ... 00 @cs_d + # *** RV128C specific Standard Extension (Quadrant 0) *** + sq 101 ... ... .. ... 00 @cs_q +} sw 110 ... ... .. ... 00 @cs_w =20 # *** RV32C and RV64C specific Standard Extension (Quadrant 0) *** @@ -132,7 +148,11 @@ addw 100 1 11 ... 01 ... 01 @cs_2 =20 # *** RV32/64C Standard Extension (Quadrant 2) *** slli 000 . ..... ..... 10 @c_shift2 -fld 001 . ..... ..... 10 @c_ldsp +{ + fld 001 . ..... ..... 10 @c_ldsp + # *** RV128C specific Standard Extension (Quadrant 2) *** + lq 001 ... ... .. ... 10 @c_lqsp +} { illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=3D0 lw 010 . ..... ..... 10 @c_lwsp @@ -147,7 +167,11 @@ fld 001 . ..... ..... 10 @c_ldsp jalr 100 1 ..... 00000 10 @c_jalr rd=3D1 # C.JALR add 100 1 ..... ..... 10 @cr } -fsd 101 ...... ..... 10 @c_sdsp +{ + fsd 101 ...... ..... 10 @c_sdsp + # *** RV128C specific Standard Extension (Quadrant 2) *** + sq 101 ... ... .. ... 10 @c_sqsp +} sw 110 . ..... ..... 10 @c_swsp =20 # *** RV32C and RV64C specific Standard Extension (Quadrant 2) *** diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 2f251dac1b..1e7ddecc22 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -163,6 +163,10 @@ sllw 0000000 ..... ..... 001 ..... 0111011 @r srlw 0000000 ..... ..... 101 ..... 0111011 @r sraw 0100000 ..... ..... 101 ..... 0111011 @r =20 +# *** RV128I Base Instruction Set (in addition to RV64I) *** +ldu ............ ..... 111 ..... 0000011 @i +lq ............ ..... 010 ..... 0001111 @i +sq ............ ..... 100 ..... 0100011 @s # *** RV32M Standard Extension *** mul 0000001 ..... ..... 000 ..... 0110011 @r mulh 0000001 ..... ..... 001 ..... 0110011 @r diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b6ddcf7a10..e8f08f921e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -429,13 +429,6 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i = *a, DisasExtend ext, =20 gen_set_gpr(ctx, a->rd, dest); =20 - /* devilish temporary code so that the patch compiles */ - if (get_xl_max(ctx) =3D=3D MXL_RV128) { - (void)get_gprh(ctx, 6); - (void)dest_gprh(ctx, 6); - gen_set_gprh(ctx, 6, NULL); - } - return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 5c2a117a70..92f41f3a86 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -134,7 +134,15 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) return gen_branch(ctx, a, TCG_COND_GEU); } =20 -static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) +static void gen_addi2_i128(TCGv retl, TCGv reth, + TCGv srcl, TCGv srch, target_long imm) +{ + TCGv imml =3D tcg_constant_tl(imm), + immh =3D tcg_constant_tl(-(imm < 0)); + tcg_gen_add2_tl(retl, reth, srcl, srch, imml, immh); +} + +static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop) { TCGv dest =3D dest_gpr(ctx, a->rd); TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); @@ -150,6 +158,63 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, Mem= Op memop) return true; } =20 +/* + * TODO: we should assert that src1h =3D=3D 0, as we do not change the + * address translation mechanism + */ +static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop) +{ + TCGv src1l =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src1h =3D get_gprh(ctx, a->rs1); + TCGv destl =3D dest_gpr(ctx, a->rd); + TCGv desth =3D dest_gprh(ctx, a->rd); + TCGv addrl =3D tcg_temp_new(); + TCGv addrh =3D tcg_temp_new(); + TCGv imml =3D tcg_temp_new(); + TCGv immh =3D tcg_constant_tl(-(a->imm < 0)); + + /* Build a 128-bit address */ + if (a->imm !=3D 0) { + tcg_gen_movi_tl(imml, a->imm); + tcg_gen_add2_tl(addrl, addrh, src1l, src1h, imml, immh); + } else { + tcg_gen_mov_tl(addrl, src1l); + tcg_gen_mov_tl(addrh, src1h); + } + + if (memop !=3D (MemOp)MO_TEO) { + tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_tl(desth, destl, 63); + } else { + tcg_gen_movi_tl(desth, 0); + } + } else { + tcg_gen_qemu_ld_tl(memop & MO_BSWAP ? desth : destl, addrl, + ctx->mem_idx, MO_TEQ); + gen_addi2_i128(addrl, addrh, addrl, addrh, 8); + tcg_gen_qemu_ld_tl(memop & MO_BSWAP ? destl : desth, addrl, + ctx->mem_idx, MO_TEQ); + } + + gen_set_gpr(ctx, a->rd, destl); + gen_set_gprh(ctx, a->rd, desth); + + tcg_temp_free(addrl); + tcg_temp_free(addrh); + tcg_temp_free(imml); + return true; +} + +static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) +{ + if (get_xl(ctx) =3D=3D MXL_RV128) { + return gen_load_i128(ctx, a, memop); + } else { + return gen_load_tl(ctx, a, memop); + } +} + static bool trans_lb(DisasContext *ctx, arg_lb *a) { return gen_load(ctx, a, MO_SB); @@ -165,6 +230,18 @@ static bool trans_lw(DisasContext *ctx, arg_lw *a) return gen_load(ctx, a, MO_TESL); } =20 +static bool trans_ld(DisasContext *ctx, arg_ld *a) +{ + REQUIRE_64_OR_128BIT(ctx); + return gen_load(ctx, a, MO_TESQ); +} + +static bool trans_lq(DisasContext *ctx, arg_lq *a) +{ + REQUIRE_128BIT(ctx); + return gen_load(ctx, a, MO_TEO); +} + static bool trans_lbu(DisasContext *ctx, arg_lbu *a) { return gen_load(ctx, a, MO_UB); @@ -177,17 +254,17 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) =20 static bool trans_lwu(DisasContext *ctx, arg_lwu *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); return gen_load(ctx, a, MO_TEUL); } =20 -static bool trans_ld(DisasContext *ctx, arg_ld *a) +static bool trans_ldu(DisasContext *ctx, arg_ldu *a) { - REQUIRE_64BIT(ctx); - return gen_load(ctx, a, MO_TEQ); + REQUIRE_128BIT(ctx); + return gen_load(ctx, a, MO_TEUQ); } =20 -static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) +static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop) { TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); @@ -202,6 +279,55 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, Me= mOp memop) return true; } =20 +/* + * TODO: we should assert that src1h =3D=3D 0, as we do not change the + * address translation mechanism + */ +static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop) +{ + TCGv src1l =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src1h =3D get_gprh(ctx, a->rs1); + TCGv src2l =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv src2h =3D get_gprh(ctx, a->rs2); + TCGv addrl =3D tcg_temp_new(); + TCGv addrh =3D tcg_temp_new(); + TCGv imml =3D tcg_temp_new(); + TCGv immh =3D tcg_constant_tl(-(a->imm < 0)); + + /* Build a 128-bit address */ + if (a->imm !=3D 0) { + tcg_gen_movi_tl(imml, a->imm); + tcg_gen_add2_tl(addrl, addrh, src1l, src1h, imml, immh); + } else { + tcg_gen_mov_tl(addrl, src1l); + tcg_gen_mov_tl(addrh, src1h); + } + + if (memop !=3D (MemOp)MO_TEO) { + tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop); + } else { + tcg_gen_qemu_st_tl(memop & MO_BSWAP ? src2h : src2l, addrl, + ctx->mem_idx, MO_TEQ); + gen_addi2_i128(addrl, addrh, addrl, addrh, 8); + tcg_gen_qemu_st_tl(memop & MO_BSWAP ? src2l : src2h, addrl, + ctx->mem_idx, MO_TEQ); + } + + tcg_temp_free(addrl); + tcg_temp_free(addrh); + tcg_temp_free(imml); + return true; +} + +static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) +{ + if (get_xl(ctx) =3D=3D MXL_RV128) { + return gen_store_i128(ctx, a, memop); + } else { + return gen_store_tl(ctx, a, memop); + } +} + static bool trans_sb(DisasContext *ctx, arg_sb *a) { return gen_store(ctx, a, MO_SB); @@ -219,10 +345,16 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a) =20 static bool trans_sd(DisasContext *ctx, arg_sd *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); return gen_store(ctx, a, MO_TEQ); } =20 +static bool trans_sq(DisasContext *ctx, arg_sq *a) +{ + REQUIRE_128BIT(ctx); + return gen_store(ctx, a, MO_TEO); +} + static bool trans_addi(DisasContext *ctx, arg_addi *a) { return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl); --=20 2.33.0