From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637519822870.8042481127703; Tue, 19 Oct 2021 02:58:39 -0700 (PDT) Received: from localhost ([::1]:41280 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcltG-0004mW-Ml for importer@patchew.org; Tue, 19 Oct 2021 05:58:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58618) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljV-0000S6-UH; Tue, 19 Oct 2021 05:48:35 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:54584) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljO-0006Pe-6O; Tue, 19 Oct 2021 05:48:32 -0400 Received: from mailhost.u-ga.fr (mailhost1.u-ga.fr [152.77.1.10]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id 32EA541F91; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id 19C03601D5; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id E910614005D; Tue, 19 Oct 2021 11:48:21 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 01/21] memory: change define name for consistency Date: Tue, 19 Oct 2021 11:47:52 +0200 Message-Id: <20211019094812.614056-2-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637520442100001 Changed MO_Q into MO_UQ so as to avoid confusion, as suggested by Philippe Mathieu-Daud=C3=A9. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/memop.h | 8 ++++---- target/arm/translate-a32.h | 4 ++-- target/arm/translate-a64.c | 8 ++++---- target/arm/translate-neon.c | 6 +++--- target/arm/translate-sve.c | 2 +- target/arm/translate-vfp.c | 8 ++++---- target/arm/translate.c | 2 +- target/ppc/translate.c | 24 +++++++++++----------- target/sparc/translate.c | 4 ++-- target/ppc/translate/fixedpoint-impl.c.inc | 20 +++++++++--------- target/ppc/translate/fp-impl.c.inc | 4 ++-- target/ppc/translate/vsx-impl.c.inc | 4 ++-- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 10 ++++----- tcg/i386/tcg-target.c.inc | 4 ++-- tcg/mips/tcg-target.c.inc | 4 ++-- tcg/ppc/tcg-target.c.inc | 8 ++++---- tcg/riscv/tcg-target.c.inc | 6 +++--- tcg/s390x/tcg-target.c.inc | 10 ++++----- 19 files changed, 69 insertions(+), 69 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index 04264ffd6b..c554bb0ee8 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -88,26 +88,26 @@ typedef enum MemOp { MO_SB =3D MO_SIGN | MO_8, MO_SW =3D MO_SIGN | MO_16, MO_SL =3D MO_SIGN | MO_32, - MO_Q =3D MO_64, + MO_UQ =3D MO_64, =20 MO_LEUW =3D MO_LE | MO_UW, MO_LEUL =3D MO_LE | MO_UL, MO_LESW =3D MO_LE | MO_SW, MO_LESL =3D MO_LE | MO_SL, - MO_LEQ =3D MO_LE | MO_Q, + MO_LEQ =3D MO_LE | MO_UQ, =20 MO_BEUW =3D MO_BE | MO_UW, MO_BEUL =3D MO_BE | MO_UL, MO_BESW =3D MO_BE | MO_SW, MO_BESL =3D MO_BE | MO_SL, - MO_BEQ =3D MO_BE | MO_Q, + MO_BEQ =3D MO_BE | MO_UQ, =20 #ifdef NEED_CPU_H MO_TEUW =3D MO_TE | MO_UW, MO_TEUL =3D MO_TE | MO_UL, MO_TESW =3D MO_TE | MO_SW, MO_TESL =3D MO_TE | MO_SL, - MO_TEQ =3D MO_TE | MO_Q, + MO_TEQ =3D MO_TE | MO_UQ, #endif =20 MO_SSIZE =3D MO_SIZE | MO_SIGN, diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 88f15df60e..ec0330ea0f 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -114,13 +114,13 @@ void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, T= CGv_i32 a32, static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index) { - gen_aa32_ld_i64(s, val, a32, index, MO_Q); + gen_aa32_ld_i64(s, val, a32, index, MO_UQ); } =20 static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index) { - gen_aa32_st_i64(s, val, a32, index, MO_Q); + gen_aa32_st_i64(s, val, a32, index, MO_UQ); } =20 DO_GEN_LD(8u, MO_UB) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cec672f229..1411fdfb6f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -973,7 +973,7 @@ static void do_fp_st(DisasContext *s, int srcidx, TCGv_= i64 tcg_addr, int size) =20 tcg_gen_ld_i64(tmphi, cpu_env, fp_reg_hi_offset(s, srcidx)); =20 - mop =3D s->be_data | MO_Q; + mop =3D s->be_data | MO_UQ; tcg_gen_qemu_st_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s), mop | (s->align_mem ? MO_ALIGN_16 : 0)); tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); @@ -1007,7 +1007,7 @@ static void do_fp_ld(DisasContext *s, int destidx, TC= Gv_i64 tcg_addr, int size) tmphi =3D tcg_temp_new_i64(); tcg_hiaddr =3D tcg_temp_new_i64(); =20 - mop =3D s->be_data | MO_Q; + mop =3D s->be_data | MO_UQ; tcg_gen_qemu_ld_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s), mop | (s->align_mem ? MO_ALIGN_16 : 0)); tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); @@ -4099,10 +4099,10 @@ static void disas_ldst_tag(DisasContext *s, uint32_= t insn) int i, n =3D (1 + is_pair) << LOG2_TAG_GRANULE; =20 tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, - MO_Q | MO_ALIGN_16); + MO_UQ | MO_ALIGN_16); for (i =3D 8; i < n; i +=3D 8) { tcg_gen_addi_i64(clean_addr, clean_addr, 8); - tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q); + tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_UQ); } tcg_temp_free_i64(tcg_zero); } diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index dd43de558e..3854dd3516 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -73,7 +73,7 @@ static void neon_load_element64(TCGv_i64 var, int reg, in= t ele, MemOp mop) case MO_UL: tcg_gen_ld32u_i64(var, cpu_env, offset); break; - case MO_Q: + case MO_UQ: tcg_gen_ld_i64(var, cpu_env, offset); break; default: @@ -1830,7 +1830,7 @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff= *a, return false; } =20 - if ((a->vd & 1) || (src1_mop =3D=3D MO_Q && (a->vn & 1))) { + if ((a->vd & 1) || (src1_mop =3D=3D MO_UQ && (a->vn & 1))) { return false; } =20 @@ -1910,7 +1910,7 @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff= *a, }; \ int narrow_mop =3D a->size =3D=3D MO_32 ? MO_32 | SIGN : -1; = \ return do_prewiden_3d(s, a, widenfn[a->size], addfn[a->size], \ - SRC1WIDE ? MO_Q : narrow_mop, \ + SRC1WIDE ? MO_UQ : narrow_mop, \ narrow_mop); \ } =20 diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index bc91a64171..86104b857e 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5284,7 +5284,7 @@ static const MemOp dtype_mop[16] =3D { MO_UB, MO_UB, MO_UB, MO_UB, MO_SL, MO_UW, MO_UW, MO_UW, MO_SW, MO_SW, MO_UL, MO_UL, - MO_SB, MO_SB, MO_SB, MO_Q + MO_SB, MO_SB, MO_SB, MO_UQ }; =20 #define dtype_msz(x) (dtype_mop[x] & MO_SIZE) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 59bcaec5be..17f796e32a 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -1170,11 +1170,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg= _VLDR_VSTR_dp *a) addr =3D add_reg_for_lit(s, a->rn, offset); tmp =3D tcg_temp_new_i64(); if (a->l) { - gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); + gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_UQ | MO_ALIGN_4= ); vfp_store_reg64(tmp, a->vd); } else { vfp_load_reg64(tmp, a->vd); - gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); + gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_UQ | MO_ALIGN_4= ); } tcg_temp_free_i64(tmp); tcg_temp_free_i32(addr); @@ -1322,12 +1322,12 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg= _VLDM_VSTM_dp *a) for (i =3D 0; i < n; i++) { if (a->l) { /* load */ - gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIG= N_4); + gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_UQ | MO_ALI= GN_4); vfp_store_reg64(tmp, a->vd + i); } else { /* store */ vfp_load_reg64(tmp, a->vd + i); - gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIG= N_4); + gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_UQ | MO_ALI= GN_4); } tcg_gen_addi_i32(addr, addr, offset); } diff --git a/target/arm/translate.c b/target/arm/translate.c index d6af5b1b03..0390e9d48e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1220,7 +1220,7 @@ void read_neon_element64(TCGv_i64 dest, int reg, int = ele, MemOp memop) case MO_UL: tcg_gen_ld32u_i64(dest, cpu_env, off); break; - case MO_Q: + case MO_UQ: tcg_gen_ld_i64(dest, cpu_env, off); break; default: diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c3c6cb9589..8133f7dea0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3228,10 +3228,10 @@ GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) -GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) +GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) =20 #if defined(TARGET_PPC64) -GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) +GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) #endif =20 #define GEN_QEMU_STORE_TL(stop, op) \ @@ -3262,10 +3262,10 @@ static void glue(gen_qemu_, glue(stop, _i64))(Disas= Context *ctx, \ GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) -GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) +GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) =20 #if defined(TARGET_PPC64) -GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) +GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) #endif =20 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) = \ @@ -3302,7 +3302,7 @@ GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) #if defined(TARGET_PPC64) -GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) +GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) #endif =20 #if defined(TARGET_PPC64) @@ -3411,7 +3411,7 @@ GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) #if defined(TARGET_PPC64) -GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) +GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) #endif =20 #if defined(TARGET_PPC64) @@ -3905,7 +3905,7 @@ static void gen_lwat(DisasContext *ctx) #ifdef TARGET_PPC64 static void gen_ldat(DisasContext *ctx) { - gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); + gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); } #endif =20 @@ -3988,7 +3988,7 @@ static void gen_stwat(DisasContext *ctx) #ifdef TARGET_PPC64 static void gen_stdat(DisasContext *ctx) { - gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); + gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); } #endif =20 @@ -4040,9 +4040,9 @@ STCX(stwcx_, DEF_MEMOP(MO_UL)) =20 #if defined(TARGET_PPC64) /* ldarx */ -LARX(ldarx, DEF_MEMOP(MO_Q)) +LARX(ldarx, DEF_MEMOP(MO_UQ)) /* stdcx. */ -STCX(stdcx_, DEF_MEMOP(MO_Q)) +STCX(stdcx_, DEF_MEMOP(MO_UQ)) =20 /* lqarx */ static void gen_lqarx(DisasContext *ctx) @@ -8050,7 +8050,7 @@ GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) #if defined(TARGET_PPC64) -GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) +GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) #endif =20 #undef GEN_STX_E @@ -8076,7 +8076,7 @@ GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) #if defined(TARGET_PPC64) -GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) +GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) #endif =20 #undef GEN_CRLOGIC diff --git a/target/sparc/translate.c b/target/sparc/translate.c index fdb8bbe5dc..7dfb33f867 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2830,7 +2830,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) default: { TCGv_i32 r_asi =3D tcg_const_i32(da.asi); - TCGv_i32 r_mop =3D tcg_const_i32(MO_Q); + TCGv_i32 r_mop =3D tcg_const_i32(MO_UQ); =20 save_state(dc); gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); @@ -2886,7 +2886,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T= CGv addr, default: { TCGv_i32 r_asi =3D tcg_const_i32(da.asi); - TCGv_i32 r_mop =3D tcg_const_i32(MO_Q); + TCGv_i32 r_mop =3D tcg_const_i32(MO_UQ); =20 save_state(dc); gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop); diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 2e2518ee15..33ce041d0b 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -131,11 +131,11 @@ TRANS64(LWAUX, do_ldst_X, true, false, MO_SL) TRANS64(PLWA, do_ldst_PLS_D, false, false, MO_SL) =20 /* Load Doubleword */ -TRANS64(LD, do_ldst_D, false, false, MO_Q) -TRANS64(LDX, do_ldst_X, false, false, MO_Q) -TRANS64(LDU, do_ldst_D, true, false, MO_Q) -TRANS64(LDUX, do_ldst_X, true, false, MO_Q) -TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q) +TRANS64(LD, do_ldst_D, false, false, MO_UQ) +TRANS64(LDX, do_ldst_X, false, false, MO_UQ) +TRANS64(LDU, do_ldst_D, true, false, MO_UQ) +TRANS64(LDUX, do_ldst_X, true, false, MO_UQ) +TRANS64(PLD, do_ldst_PLS_D, false, false, MO_UQ) =20 /* Store Byte */ TRANS(STB, do_ldst_D, false, true, MO_UB) @@ -159,11 +159,11 @@ TRANS(STWUX, do_ldst_X, true, true, MO_UL) TRANS(PSTW, do_ldst_PLS_D, false, true, MO_UL) =20 /* Store Doubleword */ -TRANS64(STD, do_ldst_D, false, true, MO_Q) -TRANS64(STDX, do_ldst_X, false, true, MO_Q) -TRANS64(STDU, do_ldst_D, true, true, MO_Q) -TRANS64(STDUX, do_ldst_X, true, true, MO_Q) -TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q) +TRANS64(STD, do_ldst_D, false, true, MO_UQ) +TRANS64(STDX, do_ldst_X, false, true, MO_UQ) +TRANS64(STDU, do_ldst_D, true, true, MO_UQ) +TRANS64(STDUX, do_ldst_X, true, true, MO_UQ) +TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_UQ) =20 /* * Fixed-Point Compare Instructions diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-i= mpl.c.inc index 9f7868ee28..01b5c53bf4 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -974,7 +974,7 @@ static void gen_lfdepx(DisasContext *ctx) EA =3D tcg_temp_new(); t0 =3D tcg_temp_new_i64(); gen_addr_reg_index(ctx, EA); - tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_Q)); + tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UQ)); set_fpr(rD(ctx->opcode), t0); tcg_temp_free(EA); tcg_temp_free_i64(t0); @@ -1210,7 +1210,7 @@ static void gen_stfdepx(DisasContext *ctx) t0 =3D tcg_temp_new_i64(); gen_addr_reg_index(ctx, EA); get_fpr(t0, rD(ctx->opcode)); - tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_Q)); + tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_UQ)); tcg_temp_free(EA); tcg_temp_free_i64(t0); } diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index 57a7f73bba..c1b1dde01c 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -162,8 +162,8 @@ static void gen_lxvdsx(DisasContext *ctx) gen_addr_reg_index(ctx, EA); =20 data =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); - tcg_gen_gvec_dup_i64(MO_Q, vsr_full_offset(xT(ctx->opcode)), 16, 16, d= ata); + tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, DEF_MEMOP(MO_UQ)); + tcg_gen_gvec_dup_i64(MO_UQ, vsr_full_offset(xT(ctx->opcode)), 16, 16, = data); =20 tcg_temp_free(EA); tcg_temp_free_i64(data); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 5edca8d44d..a8db553287 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1744,7 +1744,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, Mem= Op memop, TCGType ext, case MO_SL: tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); break; - case MO_Q: + case MO_UQ: tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r); break; default: diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 633b8a37ba..e31f454695 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1443,13 +1443,13 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] = =3D { #ifdef HOST_WORDS_BIGENDIAN [MO_UW] =3D helper_be_lduw_mmu, [MO_UL] =3D helper_be_ldul_mmu, - [MO_Q] =3D helper_be_ldq_mmu, + [MO_UQ] =3D helper_be_ldq_mmu, [MO_SW] =3D helper_be_ldsw_mmu, [MO_SL] =3D helper_be_ldul_mmu, #else [MO_UW] =3D helper_le_lduw_mmu, [MO_UL] =3D helper_le_ldul_mmu, - [MO_Q] =3D helper_le_ldq_mmu, + [MO_UQ] =3D helper_le_ldq_mmu, [MO_SW] =3D helper_le_ldsw_mmu, [MO_SL] =3D helper_le_ldul_mmu, #endif @@ -1694,7 +1694,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) default: tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); break; - case MO_Q: + case MO_UQ: if (datalo !=3D TCG_REG_R1) { tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); @@ -1781,7 +1781,7 @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemO= p opc, case MO_UL: tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend); break; - case MO_Q: + case MO_UQ: /* Avoid ldrd for user-only emulation, to handle unaligned. */ if (USING_SOFTMMU && use_armv6_instructions && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { @@ -1824,7 +1824,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, Mem= Op opc, TCGReg datalo, case MO_UL: tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); break; - case MO_Q: + case MO_UQ: /* Avoid ldrd for user-only emulation, to handle unaligned. */ if (USING_SOFTMMU && use_armv6_instructions && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 84b109bb84..0b5d385ad6 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1827,7 +1827,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) case MO_UL: tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); break; - case MO_Q: + case MO_UQ: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX); } else if (data_reg =3D=3D TCG_REG_EDX) { @@ -2019,7 +2019,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, } break; #endif - case MO_Q: + case MO_UQ: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, base, index, 0, ofs); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index d8f6914f03..15704c84fa 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1384,7 +1384,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, case MO_SL: tcg_out_opc_imm(s, OPC_LW, lo, base, 0); break; - case MO_Q | MO_BSWAP: + case MO_UQ | MO_BSWAP: if (TCG_TARGET_REG_BITS =3D=3D 64) { if (use_mips32r2_instructions) { tcg_out_opc_imm(s, OPC_LD, lo, base, 0); @@ -1413,7 +1413,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); } break; - case MO_Q: + case MO_UQ: /* Prefer to load from offset 0 first, but allow for overlap. */ if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_opc_imm(s, OPC_LD, lo, base, 0); diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 3e4ca2be88..6802cb06a3 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1935,24 +1935,24 @@ static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_B= SWAP) + 1] =3D { [MO_UB] =3D LBZX, [MO_UW] =3D LHZX, [MO_UL] =3D LWZX, - [MO_Q] =3D LDX, + [MO_UQ] =3D LDX, [MO_SW] =3D LHAX, [MO_SL] =3D LWAX, [MO_BSWAP | MO_UB] =3D LBZX, [MO_BSWAP | MO_UW] =3D LHBRX, [MO_BSWAP | MO_UL] =3D LWBRX, - [MO_BSWAP | MO_Q] =3D LDBRX, + [MO_BSWAP | MO_UQ] =3D LDBRX, }; =20 static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] =3D { [MO_UB] =3D STBX, [MO_UW] =3D STHX, [MO_UL] =3D STWX, - [MO_Q] =3D STDX, + [MO_UQ] =3D STDX, [MO_BSWAP | MO_UB] =3D STBX, [MO_BSWAP | MO_UW] =3D STHBRX, [MO_BSWAP | MO_UL] =3D STWBRX, - [MO_BSWAP | MO_Q] =3D STDBRX, + [MO_BSWAP | MO_UQ] =3D STDBRX, }; =20 static const uint32_t qemu_exts_opc[4] =3D { diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 9b13a46fb4..b621694321 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -862,7 +862,7 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { #if TCG_TARGET_REG_BITS =3D=3D 64 [MO_SL] =3D helper_be_ldsl_mmu, #endif - [MO_Q] =3D helper_be_ldq_mmu, + [MO_UQ] =3D helper_be_ldq_mmu, #else [MO_UW] =3D helper_le_lduw_mmu, [MO_SW] =3D helper_le_ldsw_mmu, @@ -870,7 +870,7 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { #if TCG_TARGET_REG_BITS =3D=3D 64 [MO_SL] =3D helper_le_ldsl_mmu, #endif - [MO_Q] =3D helper_le_ldq_mmu, + [MO_UQ] =3D helper_le_ldq_mmu, #endif }; =20 @@ -1083,7 +1083,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, case MO_SL: tcg_out_opc_imm(s, OPC_LW, lo, base, 0); break; - case MO_Q: + case MO_UQ: /* Prefer to load from offset 0 first, but allow for overlap. */ if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_opc_imm(s, OPC_LD, lo, base, 0); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 8938c446c8..61d6694268 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1745,10 +1745,10 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, M= emOp opc, TCGReg data, tcg_out_insn(s, RXY, LGF, data, base, index, disp); break; =20 - case MO_Q | MO_BSWAP: + case MO_UQ | MO_BSWAP: tcg_out_insn(s, RXY, LRVG, data, base, index, disp); break; - case MO_Q: + case MO_UQ: tcg_out_insn(s, RXY, LG, data, base, index, disp); break; =20 @@ -1791,10 +1791,10 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp opc, TCGReg data, } break; =20 - case MO_Q | MO_BSWAP: + case MO_UQ | MO_BSWAP: tcg_out_insn(s, RXY, STRVG, data, base, index, disp); break; - case MO_Q: + case MO_UQ: tcg_out_insn(s, RXY, STG, data, base, index, disp); break; =20 @@ -1928,7 +1928,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) case MO_UL: tgen_ext32u(s, TCG_REG_R4, data_reg); break; - case MO_Q: + case MO_UQ: tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); break; default: --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637050795901.7900603139818; Tue, 19 Oct 2021 02:50:50 -0700 (PDT) Received: from localhost ([::1]:43342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcllh-0003Ew-ET for importer@patchew.org; Tue, 19 Oct 2021 05:50:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljP-0000Fr-L5; Tue, 19 Oct 2021 05:48:27 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:54608) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljN-0006Q3-Lp; Tue, 19 Oct 2021 05:48:27 -0400 Received: from mailhost.u-ga.fr (mailhost2.u-ga.fr [129.88.177.242]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id 5289D41BB2; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id 39E5D601E3; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id 1BD8514005A; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 02/21] memory: add a few defines for octo (128-bit) values Date: Tue, 19 Oct 2021 11:47:53 +0200 Message-Id: <20211019094812.614056-3-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637053069100001 Introducing unsigned quad, signed quad, and octo accesses types to handle load and store by 128-bit processors. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot --- include/exec/memop.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index c554bb0ee8..476ea6cdae 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -85,10 +85,13 @@ typedef enum MemOp { MO_UB =3D MO_8, MO_UW =3D MO_16, MO_UL =3D MO_32, + MO_UQ =3D MO_64, MO_SB =3D MO_SIGN | MO_8, MO_SW =3D MO_SIGN | MO_16, MO_SL =3D MO_SIGN | MO_32, - MO_UQ =3D MO_64, + MO_SQ =3D MO_SIGN | MO_64, + MO_Q =3D MO_64, + MO_O =3D MO_128, =20 MO_LEUW =3D MO_LE | MO_UW, MO_LEUL =3D MO_LE | MO_UL, @@ -105,9 +108,12 @@ typedef enum MemOp { #ifdef NEED_CPU_H MO_TEUW =3D MO_TE | MO_UW, MO_TEUL =3D MO_TE | MO_UL, + MO_TEUQ =3D MO_TE | MO_UQ, MO_TESW =3D MO_TE | MO_SW, MO_TESL =3D MO_TE | MO_SL, MO_TEQ =3D MO_TE | MO_UQ, + MO_TESQ =3D MO_TE | MO_SQ, + MO_TEO =3D MO_TE | MO_O, #endif =20 MO_SSIZE =3D MO_SIZE | MO_SIGN, --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637207609297.2502870273497; Tue, 19 Oct 2021 02:53:27 -0700 (PDT) Received: from localhost ([::1]:52518 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcloE-0001XT-AQ for importer@patchew.org; Tue, 19 Oct 2021 05:53:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljS-0000JV-7e; Tue, 19 Oct 2021 05:48:30 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:54630) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljO-0006QF-8D; Tue, 19 Oct 2021 05:48:29 -0400 Received: from mailhost.u-ga.fr (mailhost2.u-ga.fr [129.88.177.242]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id 7DDDB41FA5; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id 6148D601E2; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id 3A98E14005D; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations Date: Tue, 19 Oct 2021 11:47:54 +0200 Message-Id: <20211019094812.614056-4-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637209785100003 Addition of not, xor, div and rem on 128-bit integers, used in particular within div/rem and csr helpers for computations on 128-bit registers. These will be used by the 128-bit riscv version. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- include/qemu/int128.h | 264 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 264 insertions(+) diff --git a/include/qemu/int128.h b/include/qemu/int128.h index 2ac0746426..b3236d85ad 100644 --- a/include/qemu/int128.h +++ b/include/qemu/int128.h @@ -58,6 +58,11 @@ static inline Int128 int128_exts64(int64_t a) return a; } =20 +static inline Int128 int128_not(Int128 a) +{ + return ~a; +} + static inline Int128 int128_and(Int128 a, Int128 b) { return a & b; @@ -68,6 +73,11 @@ static inline Int128 int128_or(Int128 a, Int128 b) return a | b; } =20 +static inline Int128 int128_xor(Int128 a, Int128 b) +{ + return a ^ b; +} + static inline Int128 int128_rshift(Int128 a, int n) { return a >> n; @@ -162,6 +172,26 @@ static inline Int128 bswap128(Int128 a) #endif } =20 +static inline Int128 int128_divu(Int128 a, Int128 b) +{ + return (__uint128_t)a / (__uint128_t)b; +} + +static inline Int128 int128_remu(Int128 a, Int128 b) +{ + return (__uint128_t)a % (__uint128_t)b; +} + +static inline Int128 int128_divs(Int128 a, Int128 b) +{ + return a / b; +} + +static inline Int128 int128_rems(Int128 a, Int128 b) +{ + return a % b; +} + #else /* !CONFIG_INT128 */ =20 typedef struct Int128 Int128; @@ -235,6 +265,11 @@ static inline Int128 int128_exts64(int64_t a) return int128_make128(a, (a < 0) ? -1 : 0); } =20 +static inline Int128 int128_not(Int128 a) +{ + return int128_make128(~a.lo, ~a.hi); +} + static inline Int128 int128_and(Int128 a, Int128 b) { return int128_make128(a.lo & b.lo, a.hi & b.hi); @@ -245,6 +280,11 @@ static inline Int128 int128_or(Int128 a, Int128 b) return int128_make128(a.lo | b.lo, a.hi | b.hi); } =20 +static inline Int128 int128_xor(Int128 a, Int128 b) +{ + return int128_make128(a.lo ^ b.lo, a.hi ^ b.hi); +} + static inline Int128 int128_rshift(Int128 a, int n) { int64_t h; @@ -359,6 +399,228 @@ static inline Int128 bswap128(Int128 a) return int128_make128(bswap64(a.hi), bswap64(a.lo)); } =20 +#include "qemu/host-utils.h" +/* + * Division and remainder algorithms for 128-bit. + * Na=C3=AFve implementation of Knuth Algorithm D, can be optimized quite = a bit if + * it becomes a bootleneck. + * Precondition: function never called with v equals to 0, has to be dealt + * with beforehand. + */ +static inline void divrem128(uint64_t ul, uint64_t uh, + uint64_t vl, uint64_t vh, + uint64_t *ql, uint64_t *qh, + uint64_t *rl, uint64_t *rh) +{ + const uint64_t b =3D ((uint64_t) 1) << 32; + const int m =3D 4; + uint64_t qhat, rhat, p; + int n, s, i; + int64_t j, t, k; + + /* Build arrays of 32-bit words for u and v */ + uint32_t u[4] =3D {ul & 0xffffffff, (ul >> 32) & 0xffffffff, + uh & 0xffffffff, (uh >> 32) & 0xffffffff}; + uint32_t v[4] =3D {vl & 0xffffffff, (vl >> 32) & 0xffffffff, + vh & 0xffffffff, (vh >> 32) & 0xffffffff}; + + uint32_t q[4] =3D {0}, r[4] =3D {0}, un[5] =3D {0}, vn[4] =3D {0}; + + if (v[3]) { + n =3D 4; + } else if (v[2]) { + n =3D 3; + } else if (v[1]) { + n =3D 2; + } else if (v[0]) { + n =3D 1; + } else { + /* never happens, but makes gcc shy */ + n =3D 0; + } + + if (n =3D=3D 1) { + /* Take care of the case of a single-digit divisor here */ + k =3D 0; + for (j =3D m - 1; j >=3D 0; j--) { + q[j] =3D (k * b + u[j]) / v[0]; + k =3D (k * b + u[j]) - q[j] * v[0]; + } + if (r !=3D NULL) { + r[0] =3D k; + } + } else { + s =3D clz32(v[n - 1]); /* 0 <=3D s <=3D 32 */ + if (s !=3D 0) { + for (i =3D n - 1; i > 0; i--) { + vn[i] =3D ((v[i] << s) | (v[i - 1] >> (32 - s))); + } + vn[0] =3D v[0] << s; + + un[m] =3D u[m - 1] >> (32 - s); + for (i =3D m - 1; i > 0; i--) { + un[i] =3D (u[i] << s) | (u[i - 1] >> (32 - s)); + } + un[0] =3D u[0] << s; + } else { + for (i =3D 0; i < n; i++) { + vn[i] =3D v[i]; + } + + for (i =3D 0; i < m; i++) { + un[i] =3D u[i]; + } + un[m] =3D 0; + } + + /* Step D2 : loop on j */ + for (j =3D m - n; j >=3D 0; j--) { /* Main loop */ + /* Step D3 : Compute estimate qhat of q[j] */ + qhat =3D (un[j + n] * b + un[j + n - 1]) / vn[n - 1]; + /* Optimized mod vn[n -1 ] */ + rhat =3D (un[j + n] * b + un[j + n - 1]) - qhat * vn[n - 1]; + + while (true) { + if (qhat =3D=3D b + || qhat * vn[n - 2] > b * rhat + un[j + n - 2]) { + qhat =3D qhat - 1; + rhat =3D rhat + vn[n - 1]; + if (rhat < b) { + continue; + } + } + break; + } + + /* Step D4 : Multiply and subtract */ + k =3D 0; + for (i =3D 0; i < n; i++) { + p =3D qhat * vn[i]; + t =3D un[i + j] - k - (p & 0xffffffff); + un[i + j] =3D t; + k =3D (p >> 32) - (t >> 32); + } + t =3D un[j + n] - k; + un[j + n] =3D t; + + /* Step D5 */ + q[j] =3D qhat; /* Store quotient digit */ + /* Step D6 */ + if (t < 0) { /* If we subtracted too much, add back */ + q[j] =3D q[j] - 1; + k =3D 0; + for (i =3D 0; i < n; i++) { + t =3D un[i + j] + vn[i] + k; + un[i + j] =3D t; + k =3D t >> 32; + } + un[j + n] =3D un[j + n] + k; + } + } /* D7 Loop */ + + /* Step D8 : Unnormalize */ + if (rl && rh) { + if (s !=3D 0) { + for (i =3D 0; i < n; i++) { + r[i] =3D (un[i] >> s) | (un[i + 1] << (32 - s)); + } + } else { + for (i =3D 0; i < n; i++) { + r[i] =3D un[i]; + } + } + } + } + + if (ql && qh) { + *ql =3D q[0] | ((uint64_t)q[1] << 32); + *qh =3D q[2] | ((uint64_t)q[3] << 32); + } + + if (rl && rh) { + *rl =3D r[0] | ((uint64_t)r[1] << 32); + *rh =3D r[2] | ((uint64_t)r[3] << 32); + } +} + +static inline Int128 int128_divu(Int128 a, Int128 b) +{ + uint64_t qh, ql; + + divrem128(int128_getlo(a), int128_gethi(a), + int128_getlo(b), int128_gethi(b), + &ql, &qh, + NULL, NULL); + + return int128_make128(ql, qh); +} + +static inline Int128 int128_remu(Int128 a, Int128 b) +{ + uint64_t rh, rl; + + divrem128(int128_getlo(a), int128_gethi(a), + int128_getlo(b), int128_gethi(b), + NULL, NULL, + &rl, &rh); + + return int128_make128(rl, rh); +} + +static inline Int128 int128_divs(Int128 a, Int128 b) +{ + uint64_t qh, ql; + bool sgna =3D !int128_nonneg(a), + sgnb =3D !int128_nonneg(b); + + if (sgna) { + a =3D int128_neg(a); + } + + if (sgnb) { + b =3D int128_neg(b); + } + + divrem128(int128_getlo(a), int128_gethi(a), + int128_getlo(b), int128_gethi(b), + &ql, &qh, + NULL, NULL); + Int128 q =3D int128_make128(ql, qh); + + if (sgna !=3D sgnb) { + q =3D int128_neg(q); + } + + return q; +} + +static inline Int128 int128_rems(Int128 a, Int128 b) +{ + uint64_t rh, rl; + bool sgna =3D !int128_nonneg(a), + sgnb =3D !int128_nonneg(b); + + if (sgna) { + a =3D int128_neg(a); + } + + if (sgnb) { + b =3D int128_neg(b); + } + + divrem128(int128_getlo(a), int128_gethi(a), + int128_getlo(b), int128_gethi(b), + NULL, NULL, + &rl, &rh); + Int128 r =3D int128_make128(rl, rh); + + if (sgna) { + r =3D int128_neg(r); + } + + return r; +} + #endif /* CONFIG_INT128 */ =20 static inline void bswap128s(Int128 *s) @@ -366,4 +628,6 @@ static inline void bswap128s(Int128 *s) *s =3D bswap128(*s); } =20 +#define UINT128_MAX int128_make128(~0LL, ~0LL) + #endif /* INT128_H */ --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163463705062324.18890920711476; Tue, 19 Oct 2021 02:50:50 -0700 (PDT) Received: from localhost ([::1]:43334 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcllh-0003EW-78 for importer@patchew.org; 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Tue, 19 Oct 2021 11:48:22 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 04/21] target/riscv: additional macros to check instruction support Date: Tue, 19 Oct 2021 11:47:55 +0200 Message-Id: <20211019094812.614056-5-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637053100100002 Given that the 128-bit version of the riscv spec adds new instructions, and that some instructions that were previously only available in 64-bit mode are now available for both 64-bit and 128-bit, we added new macros to check for the processor mode during translation. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- target/riscv/translate.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 35245aafa7..121fcd71fe 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -350,6 +350,24 @@ EX_SH(12) } \ } while (0) =20 +#define REQUIRE_128BIT(ctx) do { \ + if (get_xl(ctx) < MXL_RV128) { \ + return false; \ + } \ +} while (0) + +#define REQUIRE_32_OR_64BIT(ctx) do { \ + if (get_xl(ctx) =3D=3D MXL_RV128) { \ + return false; \ + } \ +} while (0) + +#define REQUIRE_64_OR_128BIT(ctx) do { \ + if (get_xl(ctx) =3D=3D MXL_RV32) { \ + return false; \ + } \ +} while (0) + static int ex_rvc_register(DisasContext *ctx, int reg) { return 8 + reg; --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637371686761.9525628877843; Tue, 19 Oct 2021 02:56:11 -0700 (PDT) Received: from localhost ([::1]:59782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mclqs-0006WJ-Ie for importer@patchew.org; Tue, 19 Oct 2021 05:56:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljU-0000Rq-MZ; Tue, 19 Oct 2021 05:48:34 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:54734) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljR-0006VK-1L; Tue, 19 Oct 2021 05:48:32 -0400 Received: from mailhost.u-ga.fr (mailhost2.u-ga.fr [129.88.177.242]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id BC24941FF1; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id A2FDA601E2; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id 865E014005D; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers Date: Tue, 19 Oct 2021 11:47:56 +0200 Message-Id: <20211019094812.614056-6-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637374012100001 Introduction of a gen_logic function for bitwise logic to implement instructions in which not propagation of information occurs between bits and use of this function on the bitwise instructions. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson --- target/riscv/translate.c | 27 +++++++++++++++++++++++++ target/riscv/insn_trans/trans_rvb.c.inc | 6 +++--- target/riscv/insn_trans/trans_rvi.c.inc | 12 +++++------ 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 121fcd71fe..3c2e9fb790 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -382,6 +382,33 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) /* Include the auto-generated decoder for 32 bit insn */ #include "decode-insn32.c.inc" =20 +static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, + void (*func)(TCGv, TCGv, target_long)) +{ + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, ext); + + func(dest, src1, a->imm); + + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + +static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext, + void (*func)(TCGv, TCGv, TCGv)) +{ + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, ext); + TCGv src2 =3D get_gpr(ctx, a->rs2, ext); + + func(dest, src1, src2); + + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, void (*func)(TCGv, TCGv, target_long)) { diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index cc39e6033b..28f911f95d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -86,19 +86,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a) static bool trans_andn(DisasContext *ctx, arg_andn *a) { REQUIRE_ZBB(ctx); - return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl); + return gen_logic(ctx, a, EXT_NONE, tcg_gen_andc_tl); } =20 static bool trans_orn(DisasContext *ctx, arg_orn *a) { REQUIRE_ZBB(ctx); - return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl); + return gen_logic(ctx, a, EXT_NONE, tcg_gen_orc_tl); } =20 static bool trans_xnor(DisasContext *ctx, arg_xnor *a) { REQUIRE_ZBB(ctx); - return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl); + return gen_logic(ctx, a, EXT_NONE, tcg_gen_eqv_tl); } =20 static bool trans_min(DisasContext *ctx, arg_min *a) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 91dc438a3a..ed138f748e 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -250,17 +250,17 @@ static bool trans_sltiu(DisasContext *ctx, arg_sltiu = *a) =20 static bool trans_xori(DisasContext *ctx, arg_xori *a) { - return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl); + return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl); } =20 static bool trans_ori(DisasContext *ctx, arg_ori *a) { - return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl); + return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl); } =20 static bool trans_andi(DisasContext *ctx, arg_andi *a) { - return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl); + return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl); } =20 static bool trans_slli(DisasContext *ctx, arg_slli *a) @@ -317,7 +317,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a) =20 static bool trans_xor(DisasContext *ctx, arg_xor *a) { - return gen_arith(ctx, a, EXT_NONE, tcg_gen_xor_tl); + return gen_logic(ctx, a, EXT_NONE, tcg_gen_xor_tl); } =20 static bool trans_srl(DisasContext *ctx, arg_srl *a) @@ -332,12 +332,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a) =20 static bool trans_or(DisasContext *ctx, arg_or *a) { - return gen_arith(ctx, a, EXT_NONE, tcg_gen_or_tl); + return gen_logic(ctx, a, EXT_NONE, tcg_gen_or_tl); } =20 static bool trans_and(DisasContext *ctx, arg_and *a) { - return gen_arith(ctx, a, EXT_NONE, tcg_gen_and_tl); + return gen_logic(ctx, a, EXT_NONE, tcg_gen_and_tl); } =20 static bool trans_addiw(DisasContext *ctx, arg_addiw *a) --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637191851884.0452934217544; Tue, 19 Oct 2021 02:53:11 -0700 (PDT) Received: from localhost ([::1]:51734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mclny-00010J-Oz for importer@patchew.org; Tue, 19 Oct 2021 05:53:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58570) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljT-0000Or-Ed; Tue, 19 Oct 2021 05:48:31 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:54736) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljR-0006VJ-2I; Tue, 19 Oct 2021 05:48:31 -0400 Received: from mailhost.u-ga.fr (mailhost2.u-ga.fr [129.88.177.242]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id D7E3B42012; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id C201A601E2; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id A6FC114005A; Tue, 19 Oct 2021 11:48:22 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers Date: Tue, 19 Oct 2021 11:47:57 +0200 Message-Id: <20211019094812.614056-7-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637192938100001 The upper 64-bit of the 128-bit registers have now a place inside the cpu state structure, and are created as globals for future use. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 1 + target/riscv/translate.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c24bc9a039..c8b98f1b70 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -109,6 +109,7 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 struct CPURISCVState { target_ulong gpr[32]; + target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ uint64_t fpr[32]; /* assume both F and D extensions */ =20 /* vector coprocessor state. */ diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3c2e9fb790..b64fe8470d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -32,7 +32,7 @@ #include "instmap.h" =20 /* global register indices */ -static TCGv cpu_gpr[32], cpu_pc, cpu_vl; +static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; @@ -755,10 +755,13 @@ void riscv_translate_init(void) * unless you specifically block reads/writes to reg 0. */ cpu_gpr[0] =3D NULL; + cpu_gprh[0] =3D NULL; =20 for (i =3D 1; i < 32; i++) { cpu_gpr[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); + cpu_gprh[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]); } =20 for (i =3D 0; i < 32; i++) { --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637301070888.7154925034898; Tue, 19 Oct 2021 02:55:01 -0700 (PDT) Received: from localhost ([::1]:56904 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mclpk-0004Yw-0M for importer@patchew.org; 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Tue, 19 Oct 2021 11:48:22 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles Date: Tue, 19 Oct 2021 11:47:58 +0200 Message-Id: <20211019094812.614056-8-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637301872100001 This patch is kind of a mess because several files have to be slightly modified to allow for a new target. Most of these modifications have to deal with changing what was a binary choice into a ternary one. Although we did our best to avoid testing for TARGET_RISCV128 (which we did), it is implicitly there in '#else' statements. Most added infrastructure files are no far from being copies of the 64-bit version. Once this patch applied, adding risc128-sofmmu to --target-list produces a (no so useful yet) executable. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- configs/devices/riscv128-softmmu/default.mak | 17 +++++++ configs/targets/riscv128-softmmu.mak | 6 +++ include/disas/dis-asm.h | 1 + include/hw/riscv/sifive_cpu.h | 3 ++ target/riscv/cpu-param.h | 5 ++ target/riscv/cpu.h | 3 ++ disas/riscv.c | 5 ++ target/riscv/cpu.c | 23 +++++++++- target/riscv/gdbstub.c | 3 ++ target/riscv/insn_trans/trans_rvd.c.inc | 12 ++--- target/riscv/insn_trans/trans_rvf.c.inc | 6 +-- gdb-xml/riscv-128bit-cpu.xml | 48 ++++++++++++++++++++ gdb-xml/riscv-128bit-virtual.xml | 12 +++++ target/riscv/Kconfig | 3 ++ 14 files changed, 137 insertions(+), 10 deletions(-) create mode 100644 configs/devices/riscv128-softmmu/default.mak create mode 100644 configs/targets/riscv128-softmmu.mak create mode 100644 gdb-xml/riscv-128bit-cpu.xml create mode 100644 gdb-xml/riscv-128bit-virtual.xml diff --git a/configs/devices/riscv128-softmmu/default.mak b/configs/devices= /riscv128-softmmu/default.mak new file mode 100644 index 0000000000..e838f35785 --- /dev/null +++ b/configs/devices/riscv128-softmmu/default.mak @@ -0,0 +1,17 @@ +# Default configuration for riscv128-softmmu + +# Uncomment the following lines to disable these optional devices: +# +#CONFIG_PCI_DEVICES=3Dn +# No does not seem to be an option for these two parameters +CONFIG_SEMIHOSTING=3Dy +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy + +# Boards: +# +CONFIG_SPIKE=3Dn +CONFIG_SIFIVE_E=3Dn +CONFIG_SIFIVE_U=3Dn +CONFIG_RISCV_VIRT=3Dy +CONFIG_MICROCHIP_PFSOC=3Dn +CONFIG_SHAKTI_C=3Dn diff --git a/configs/targets/riscv128-softmmu.mak b/configs/targets/riscv12= 8-softmmu.mak new file mode 100644 index 0000000000..7e5976bbf3 --- /dev/null +++ b/configs/targets/riscv128-softmmu.mak @@ -0,0 +1,6 @@ +#For now a raw copy of the riscv64 version as changing TARGET_ARCH to risc= v64 might trigger to much stuff for now +TARGET_ARCH=3Driscv128 +TARGET_BASE_ARCH=3Driscv +TARGET_SUPPORTS_MTTCG=3Dy +TARGET_XML_FILES=3Dgdb-xml/riscv-128bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-128bit-virtual.xml +TARGET_NEED_FDT=3Dy diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index 524f29196d..d9c725adae 100644 --- a/include/disas/dis-asm.h +++ b/include/disas/dis-asm.h @@ -460,6 +460,7 @@ int print_insn_little_nios2 (bfd_vma, disassemble_i= nfo*); int print_insn_xtensa (bfd_vma, disassemble_info*); int print_insn_riscv32 (bfd_vma, disassemble_info*); int print_insn_riscv64 (bfd_vma, disassemble_info*); +int print_insn_riscv128 (bfd_vma, disassemble_info*); int print_insn_rx(bfd_vma, disassemble_info *); int print_insn_hexagon(bfd_vma, disassemble_info *); =20 diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h index 136799633a..64078feba8 100644 --- a/include/hw/riscv/sifive_cpu.h +++ b/include/hw/riscv/sifive_cpu.h @@ -26,6 +26,9 @@ #elif defined(TARGET_RISCV64) #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 +#else +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 #endif =20 #endif /* HW_SIFIVE_CPU_H */ diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index 80eb615f93..c10459b56f 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -16,6 +16,11 @@ # define TARGET_LONG_BITS 32 # define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ +#else +/* 64-bit target, since QEMU isn't built to have TARGET_LONG_BITS over 64 = */ +# define TARGET_LONG_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ +# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ /* diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c8b98f1b70..5d21128865 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -38,6 +38,7 @@ #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") +#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("rv128") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") @@ -50,6 +51,8 @@ # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 #elif defined(TARGET_RISCV64) # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#else +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE128 #endif =20 #define RV(x) ((target_ulong)1 << (x - 'A')) diff --git a/disas/riscv.c b/disas/riscv.c index 793ad14c27..03c8dc9961 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -3090,3 +3090,8 @@ int print_insn_riscv64(bfd_vma memaddr, struct disass= emble_info *info) { return print_insn_riscv(memaddr, info, rv64); } + +int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info) +{ + return print_insn_riscv(memaddr, info, rv128); +} diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b81b880900..d5a87f57e9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -143,6 +143,8 @@ static void riscv_any_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#else + set_misa(env, MXL_RV128, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_11_0); } @@ -169,7 +171,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } -#else +#elif defined(TARGET_RISCV32) static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -209,6 +211,13 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } +#else +static void rv128_base_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + /* We set this in the realise function */ + set_misa(env, MXL_RV128, 0); +} #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -395,6 +404,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disas= semble_info *info) case MXL_RV64: info->print_insn =3D print_insn_riscv64; break; + case MXL_RV128: + info->print_insn =3D print_insn_riscv128; + break; default: g_assert_not_reached(); } @@ -457,6 +469,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) #ifdef TARGET_RISCV64 case MXL_RV64: break; +#elif !defined(TARGET_RISCV32) + case MXL_RV128: + break; #endif case MXL_RV32: break; @@ -657,6 +672,8 @@ static gchar *riscv_gdb_arch_name(CPUState *cs) return g_strdup("riscv:rv32"); case MXL_RV64: return g_strdup("riscv:rv64"); + case MXL_RV128: + return g_strdup("riscv:rv128"); default: g_assert_not_reached(); } @@ -721,6 +738,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; #elif defined(TARGET_RISCV64) cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; +#else + cc->gdb_core_xml_file =3D "riscv-128bit-cpu.xml"; #endif cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; @@ -808,6 +827,8 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), +#else + DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; =20 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 23429179e2..f840a309e2 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -204,6 +204,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) #elif defined(TARGET_RISCV64) gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, 1, "riscv-64bit-virtual.xml", 0); +#else + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, + 1, "riscv-128bit-virtual.xml", 0); #endif =20 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index db9ae15755..41da696ec4 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -393,11 +393,11 @@ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_= x_d *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 -#ifdef TARGET_RISCV64 +#ifdef TARGET_RISCV32 + qemu_build_not_reached(); +#else gen_set_gpr(ctx, a->rd, cpu_fpr[a->rs1]); return true; -#else - qemu_build_not_reached(); #endif } =20 @@ -437,11 +437,11 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_= d_x *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 -#ifdef TARGET_RISCV64 +#ifdef TARGET_RISCV32 + qemu_build_not_reached(); +#else tcg_gen_mov_tl(cpu_fpr[a->rd], get_gpr(ctx, a->rs1, EXT_NONE)); mark_fs_dirty(ctx); return true; -#else - qemu_build_not_reached(); #endif } diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index bddbd418d9..90cc51e5d6 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -311,10 +311,10 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_= x_w *a) =20 TCGv dest =3D dest_gpr(ctx, a->rd); =20 -#if defined(TARGET_RISCV64) - tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]); -#else +#if defined(TARGET_RISCV32) tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]); +#else + tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]); #endif =20 gen_set_gpr(ctx, a->rd, dest); diff --git a/gdb-xml/riscv-128bit-cpu.xml b/gdb-xml/riscv-128bit-cpu.xml new file mode 100644 index 0000000000..c98168148f --- /dev/null +++ b/gdb-xml/riscv-128bit-cpu.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-128bit-virtual.xml b/gdb-xml/riscv-128bit-virtua= l.xml new file mode 100644 index 0000000000..db9a0ff677 --- /dev/null +++ b/gdb-xml/riscv-128bit-virtual.xml @@ -0,0 +1,12 @@ + + + + + + + + diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig index b9e5932f13..f9ea52a59a 100644 --- a/target/riscv/Kconfig +++ b/target/riscv/Kconfig @@ -3,3 +3,6 @@ config RISCV32 =20 config RISCV64 bool + +config RISCV128 + bool --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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The access to the gprh field can not be protected at compile time to make sure it is accessed only in the 128-bit version of the processor because we have no way to indicate that the misa_mxl_max field is const. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- target/riscv/translate.c | 45 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b64fe8470d..b6ddcf7a10 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -55,6 +55,7 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; target_ulong priv_ver; + RISCVMXL misa_mxl_max; RISCVMXL xl; uint32_t misa_ext; uint32_t opcode; @@ -116,6 +117,13 @@ static inline int get_olen(DisasContext *ctx) return 16 << get_ol(ctx); } =20 +/* The maximum register length */ +#ifdef TARGET_RISCV32 +#define get_xl_max(ctx) MXL_RV32 +#else +#define get_xl_max(ctx) ((ctx)->misa_mxl_max) +#endif + /* * RISC-V requires NaN-boxing of narrower width floating point values. * This applies when a 32-bit value is assigned to a 64-bit FP register. @@ -220,6 +228,7 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, Dis= asExtend ext) } break; case MXL_RV64: + case MXL_RV128: break; default: g_assert_not_reached(); @@ -227,6 +236,14 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, Di= sasExtend ext) return cpu_gpr[reg_num]; } =20 +static TCGv get_gprh(DisasContext *ctx, int reg_num) +{ + if (reg_num =3D=3D 0 || get_ol(ctx) < MXL_RV128) { + return ctx->zero; + } + return cpu_gprh[reg_num]; +} + static TCGv dest_gpr(DisasContext *ctx, int reg_num) { if (reg_num =3D=3D 0 || get_olen(ctx) < TARGET_LONG_BITS) { @@ -235,6 +252,14 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num) return cpu_gpr[reg_num]; } =20 +static TCGv dest_gprh(DisasContext *ctx, int reg_num) +{ + if (reg_num =3D=3D 0 || get_ol(ctx) < MXL_RV128) { + return temp_new(ctx); + } + return cpu_gprh[reg_num]; +} + static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) { if (reg_num !=3D 0) { @@ -243,6 +268,7 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num,= TCGv t) tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); break; case MXL_RV64: + case MXL_RV128: tcg_gen_mov_tl(cpu_gpr[reg_num], t); break; default: @@ -251,6 +277,17 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num= , TCGv t) } } =20 +static void gen_set_gprh(DisasContext *ctx, int reg_num, TCGv t) +{ + if (reg_num !=3D 0) { + if (get_ol(ctx) < MXL_RV128) { + tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); + } else { + tcg_gen_mov_tl(cpu_gprh[reg_num], t); + } + } +} + static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) { target_ulong next_pc; @@ -392,6 +429,13 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i = *a, DisasExtend ext, =20 gen_set_gpr(ctx, a->rd, dest); =20 + /* devilish temporary code so that the patch compiles */ + if (get_xl_max(ctx) =3D=3D MXL_RV128) { + (void)get_gprh(ctx, 6); + (void)dest_gprh(ctx, 6); + gen_set_gprh(ctx, 6, NULL); + } + return true; } =20 @@ -655,6 +699,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen =3D 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->misa_mxl_max =3D env->misa_mxl_max; ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs =3D cs; ctx->ntemp =3D 0; --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637397700119.0219359232002; Tue, 19 Oct 2021 02:56:37 -0700 (PDT) Received: from localhost ([::1]:33012 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mclrI-0007ce-La for importer@patchew.org; Tue, 19 Oct 2021 05:56:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58640) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljW-0000SU-K9; Tue, 19 Oct 2021 05:48:36 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:54784) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljT-0006W3-R1; Tue, 19 Oct 2021 05:48:33 -0400 Received: from mailhost.u-ga.fr (mailhost2.u-ga.fr [129.88.177.242]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id 56CA041F73; Tue, 19 Oct 2021 11:48:28 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id 3EC2B601E2; Tue, 19 Oct 2021 11:48:28 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id 2373D14005A; Tue, 19 Oct 2021 11:48:28 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 09/21] target/riscv: moving some insns close to similar insns Date: Tue, 19 Oct 2021 11:48:00 +0200 Message-Id: <20211019094812.614056-10-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637397970100001 lwu and ld are functionally close to the other loads, but were after the stores in the source file. Similarly, xor was away from or and and by two arithmetic functions, while the immediate versions were nicely put together. This patch moves the aforementioned loads after lhu, and xor above or, where they more logically belong. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++++++++------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index ed138f748e..5c2a117a70 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -175,6 +175,18 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) return gen_load(ctx, a, MO_TEUW); } =20 +static bool trans_lwu(DisasContext *ctx, arg_lwu *a) +{ + REQUIRE_64BIT(ctx); + return gen_load(ctx, a, MO_TEUL); +} + +static bool trans_ld(DisasContext *ctx, arg_ld *a) +{ + REQUIRE_64BIT(ctx); + return gen_load(ctx, a, MO_TEQ); +} + static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); @@ -205,18 +217,6 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a) return gen_store(ctx, a, MO_TESL); } =20 -static bool trans_lwu(DisasContext *ctx, arg_lwu *a) -{ - REQUIRE_64BIT(ctx); - return gen_load(ctx, a, MO_TEUL); -} - -static bool trans_ld(DisasContext *ctx, arg_ld *a) -{ - REQUIRE_64BIT(ctx); - return gen_load(ctx, a, MO_TEQ); -} - static bool trans_sd(DisasContext *ctx, arg_sd *a) { REQUIRE_64BIT(ctx); @@ -315,11 +315,6 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a) return gen_arith(ctx, a, EXT_SIGN, gen_sltu); } =20 -static bool trans_xor(DisasContext *ctx, arg_xor *a) -{ - return gen_logic(ctx, a, EXT_NONE, tcg_gen_xor_tl); -} - static bool trans_srl(DisasContext *ctx, arg_srl *a) { return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl); @@ -330,6 +325,11 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a) return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl); } =20 +static bool trans_xor(DisasContext *ctx, arg_xor *a) +{ + return gen_logic(ctx, a, EXT_NONE, tcg_gen_xor_tl); +} + static bool trans_or(DisasContext *ctx, arg_or *a) { return gen_logic(ctx, a, EXT_NONE, tcg_gen_or_tl); --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637412309915.5205919560492; Tue, 19 Oct 2021 02:56:52 -0700 (PDT) Received: from localhost ([::1]:34252 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mclrX-0008Rk-4J for importer@patchew.org; Tue, 19 Oct 2021 05:56:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58780) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljp-0000ke-Bi; Tue, 19 Oct 2021 05:48:53 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:54802) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljm-0006WS-Lu; Tue, 19 Oct 2021 05:48:53 -0400 Received: from mailhost.u-ga.fr (mailhost1.u-ga.fr [152.77.1.10]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id 7E25942015; Tue, 19 Oct 2021 11:48:28 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id 668B4601D5; Tue, 19 Oct 2021 11:48:28 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id 43A6114005D; Tue, 19 Oct 2021 11:48:28 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 10/21] target/riscv: support for 128-bit loads and store Date: Tue, 19 Oct 2021 11:48:01 +0200 Message-Id: <20211019094812.614056-11-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637412960100001 The 128-bit ISA adds ldu, lq and sq. We provide here support for these instructions. Note that although we compute a 128-bit address, we only use the lower 64-bit to actually address memory, cowardly utilizing the existing address translation mechanism of QEMU. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- target/riscv/insn16.decode | 32 +++++- target/riscv/insn32.decode | 4 + target/riscv/translate.c | 7 -- target/riscv/insn_trans/trans_rvi.c.inc | 146 ++++++++++++++++++++++-- 4 files changed, 171 insertions(+), 18 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 2e9212663c..151fc6e567 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -39,6 +39,10 @@ %imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=3Dex_shift_4 %imm_lui 12:s1 2:5 !function=3Dex_shift_12 =20 +# Added for 128 bit support +%uimm_cl_q 5:2 10:3 !function=3Dex_shift_3 +%uimm_6bit_lq 2:3 12:1 5:2 !function=3Dex_shift_3 +%uimm_6bit_sq 7:3 10:3 !function=3Dex_shift_3 =20 # Argument sets imported from insn32.decode: &empty !extern @@ -54,16 +58,20 @@ # Formats 16: @cr .... ..... ..... .. &r rs2=3D%rs2_5 rs1=3D%rd = %rd @ci ... . ..... ..... .. &i imm=3D%imm_ci rs1=3D%rd = %rd +@cl_q ... . ..... ..... .. &i imm=3D%uimm_6bit_lq rs1=3D2 %rd @cl_d ... ... ... .. ... .. &i imm=3D%uimm_cl_d rs1=3D%rs1_3 = rd=3D%rs2_3 @cl_w ... ... ... .. ... .. &i imm=3D%uimm_cl_w rs1=3D%rs1_3 = rd=3D%rs2_3 @cs_2 ... ... ... .. ... .. &r rs2=3D%rs2_3 rs1=3D%rs1_3 = rd=3D%rs1_3 +@cs_q ... ... ... .. ... .. &s imm=3D%uimm_cl_q rs1=3D%rs1_3 = rs2=3D%rs2_3 @cs_d ... ... ... .. ... .. &s imm=3D%uimm_cl_d rs1=3D%rs1_3 = rs2=3D%rs2_3 @cs_w ... ... ... .. ... .. &s imm=3D%uimm_cl_w rs1=3D%rs1_3 = rs2=3D%rs2_3 @cj ... ........... .. &j imm=3D%imm_cj @cb_z ... ... ... .. ... .. &b imm=3D%imm_cb rs1=3D%rs1_3 = rs2=3D0 =20 +@c_lqsp ... . ..... ..... .. &i imm=3D%uimm_6bit_lq rs1=3D2 %rd @c_ldsp ... . ..... ..... .. &i imm=3D%uimm_6bit_ld rs1=3D2 %rd @c_lwsp ... . ..... ..... .. &i imm=3D%uimm_6bit_lw rs1=3D2 %rd +@c_sqsp ... . ..... ..... .. &s imm=3D%uimm_6bit_sq rs1=3D2 rs2= =3D%rs2_5 @c_sdsp ... . ..... ..... .. &s imm=3D%uimm_6bit_sd rs1=3D2 rs2= =3D%rs2_5 @c_swsp ... . ..... ..... .. &s imm=3D%uimm_6bit_sw rs1=3D2 rs2= =3D%rs2_5 @c_li ... . ..... ..... .. &i imm=3D%imm_ci rs1=3D0 %rd @@ -87,9 +95,17 @@ illegal 000 000 000 00 --- 00 addi 000 ... ... .. ... 00 @c_addi4spn } -fld 001 ... ... .. ... 00 @cl_d +{ + fld 001 ... ... .. ... 00 @cl_d + # *** RV128C specific Standard Extension (Quadrant 0) *** + lq 001 ... ... .. ... 00 @cl_q +} lw 010 ... ... .. ... 00 @cl_w -fsd 101 ... ... .. ... 00 @cs_d +{ + fsd 101 ... ... .. ... 00 @cs_d + # *** RV128C specific Standard Extension (Quadrant 0) *** + sq 101 ... ... .. ... 00 @cs_q +} sw 110 ... ... .. ... 00 @cs_w =20 # *** RV32C and RV64C specific Standard Extension (Quadrant 0) *** @@ -132,7 +148,11 @@ addw 100 1 11 ... 01 ... 01 @cs_2 =20 # *** RV32/64C Standard Extension (Quadrant 2) *** slli 000 . ..... ..... 10 @c_shift2 -fld 001 . ..... ..... 10 @c_ldsp +{ + fld 001 . ..... ..... 10 @c_ldsp + # *** RV128C specific Standard Extension (Quadrant 2) *** + lq 001 ... ... .. ... 10 @c_lqsp +} { illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=3D0 lw 010 . ..... ..... 10 @c_lwsp @@ -147,7 +167,11 @@ fld 001 . ..... ..... 10 @c_ldsp jalr 100 1 ..... 00000 10 @c_jalr rd=3D1 # C.JALR add 100 1 ..... ..... 10 @cr } -fsd 101 ...... ..... 10 @c_sdsp +{ + fsd 101 ...... ..... 10 @c_sdsp + # *** RV128C specific Standard Extension (Quadrant 2) *** + sq 101 ... ... .. ... 10 @c_sqsp +} sw 110 . ..... ..... 10 @c_swsp =20 # *** RV32C and RV64C specific Standard Extension (Quadrant 2) *** diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 2f251dac1b..1e7ddecc22 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -163,6 +163,10 @@ sllw 0000000 ..... ..... 001 ..... 0111011 @r srlw 0000000 ..... ..... 101 ..... 0111011 @r sraw 0100000 ..... ..... 101 ..... 0111011 @r =20 +# *** RV128I Base Instruction Set (in addition to RV64I) *** +ldu ............ ..... 111 ..... 0000011 @i +lq ............ ..... 010 ..... 0001111 @i +sq ............ ..... 100 ..... 0100011 @s # *** RV32M Standard Extension *** mul 0000001 ..... ..... 000 ..... 0110011 @r mulh 0000001 ..... ..... 001 ..... 0110011 @r diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b6ddcf7a10..e8f08f921e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -429,13 +429,6 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i = *a, DisasExtend ext, =20 gen_set_gpr(ctx, a->rd, dest); =20 - /* devilish temporary code so that the patch compiles */ - if (get_xl_max(ctx) =3D=3D MXL_RV128) { - (void)get_gprh(ctx, 6); - (void)dest_gprh(ctx, 6); - gen_set_gprh(ctx, 6, NULL); - } - return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 5c2a117a70..92f41f3a86 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -134,7 +134,15 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) return gen_branch(ctx, a, TCG_COND_GEU); } =20 -static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) +static void gen_addi2_i128(TCGv retl, TCGv reth, + TCGv srcl, TCGv srch, target_long imm) +{ + TCGv imml =3D tcg_constant_tl(imm), + immh =3D tcg_constant_tl(-(imm < 0)); + tcg_gen_add2_tl(retl, reth, srcl, srch, imml, immh); +} + +static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop) { TCGv dest =3D dest_gpr(ctx, a->rd); TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); @@ -150,6 +158,63 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, Mem= Op memop) return true; } =20 +/* + * TODO: we should assert that src1h =3D=3D 0, as we do not change the + * address translation mechanism + */ +static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop) +{ + TCGv src1l =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src1h =3D get_gprh(ctx, a->rs1); + TCGv destl =3D dest_gpr(ctx, a->rd); + TCGv desth =3D dest_gprh(ctx, a->rd); + TCGv addrl =3D tcg_temp_new(); + TCGv addrh =3D tcg_temp_new(); + TCGv imml =3D tcg_temp_new(); + TCGv immh =3D tcg_constant_tl(-(a->imm < 0)); + + /* Build a 128-bit address */ + if (a->imm !=3D 0) { + tcg_gen_movi_tl(imml, a->imm); + tcg_gen_add2_tl(addrl, addrh, src1l, src1h, imml, immh); + } else { + tcg_gen_mov_tl(addrl, src1l); + tcg_gen_mov_tl(addrh, src1h); + } + + if (memop !=3D (MemOp)MO_TEO) { + tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_tl(desth, destl, 63); + } else { + tcg_gen_movi_tl(desth, 0); + } + } else { + tcg_gen_qemu_ld_tl(memop & MO_BSWAP ? desth : destl, addrl, + ctx->mem_idx, MO_TEQ); + gen_addi2_i128(addrl, addrh, addrl, addrh, 8); + tcg_gen_qemu_ld_tl(memop & MO_BSWAP ? destl : desth, addrl, + ctx->mem_idx, MO_TEQ); + } + + gen_set_gpr(ctx, a->rd, destl); + gen_set_gprh(ctx, a->rd, desth); + + tcg_temp_free(addrl); + tcg_temp_free(addrh); + tcg_temp_free(imml); + return true; +} + +static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) +{ + if (get_xl(ctx) =3D=3D MXL_RV128) { + return gen_load_i128(ctx, a, memop); + } else { + return gen_load_tl(ctx, a, memop); + } +} + static bool trans_lb(DisasContext *ctx, arg_lb *a) { return gen_load(ctx, a, MO_SB); @@ -165,6 +230,18 @@ static bool trans_lw(DisasContext *ctx, arg_lw *a) return gen_load(ctx, a, MO_TESL); } =20 +static bool trans_ld(DisasContext *ctx, arg_ld *a) +{ + REQUIRE_64_OR_128BIT(ctx); + return gen_load(ctx, a, MO_TESQ); +} + +static bool trans_lq(DisasContext *ctx, arg_lq *a) +{ + REQUIRE_128BIT(ctx); + return gen_load(ctx, a, MO_TEO); +} + static bool trans_lbu(DisasContext *ctx, arg_lbu *a) { return gen_load(ctx, a, MO_UB); @@ -177,17 +254,17 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) =20 static bool trans_lwu(DisasContext *ctx, arg_lwu *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); return gen_load(ctx, a, MO_TEUL); } =20 -static bool trans_ld(DisasContext *ctx, arg_ld *a) +static bool trans_ldu(DisasContext *ctx, arg_ldu *a) { - REQUIRE_64BIT(ctx); - return gen_load(ctx, a, MO_TEQ); + REQUIRE_128BIT(ctx); + return gen_load(ctx, a, MO_TEUQ); } =20 -static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) +static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop) { TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); @@ -202,6 +279,55 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, Me= mOp memop) return true; } =20 +/* + * TODO: we should assert that src1h =3D=3D 0, as we do not change the + * address translation mechanism + */ +static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop) +{ + TCGv src1l =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src1h =3D get_gprh(ctx, a->rs1); + TCGv src2l =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv src2h =3D get_gprh(ctx, a->rs2); + TCGv addrl =3D tcg_temp_new(); + TCGv addrh =3D tcg_temp_new(); + TCGv imml =3D tcg_temp_new(); + TCGv immh =3D tcg_constant_tl(-(a->imm < 0)); + + /* Build a 128-bit address */ + if (a->imm !=3D 0) { + tcg_gen_movi_tl(imml, a->imm); + tcg_gen_add2_tl(addrl, addrh, src1l, src1h, imml, immh); + } else { + tcg_gen_mov_tl(addrl, src1l); + tcg_gen_mov_tl(addrh, src1h); + } + + if (memop !=3D (MemOp)MO_TEO) { + tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop); + } else { + tcg_gen_qemu_st_tl(memop & MO_BSWAP ? src2h : src2l, addrl, + ctx->mem_idx, MO_TEQ); + gen_addi2_i128(addrl, addrh, addrl, addrh, 8); + tcg_gen_qemu_st_tl(memop & MO_BSWAP ? src2l : src2h, addrl, + ctx->mem_idx, MO_TEQ); + } + + tcg_temp_free(addrl); + tcg_temp_free(addrh); + tcg_temp_free(imml); + return true; +} + +static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) +{ + if (get_xl(ctx) =3D=3D MXL_RV128) { + return gen_store_i128(ctx, a, memop); + } else { + return gen_store_tl(ctx, a, memop); + } +} + static bool trans_sb(DisasContext *ctx, arg_sb *a) { return gen_store(ctx, a, MO_SB); @@ -219,10 +345,16 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a) =20 static bool trans_sd(DisasContext *ctx, arg_sd *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); return gen_store(ctx, a, MO_TEQ); } =20 +static bool trans_sq(DisasContext *ctx, arg_sq *a) +{ + REQUIRE_128BIT(ctx); + return gen_store(ctx, a, MO_TEO); +} + static bool trans_addi(DisasContext *ctx, arg_addi *a) { return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl); --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16346374782767.239276537126557; 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Tue, 19 Oct 2021 11:48:28 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions Date: Tue, 19 Oct 2021 11:48:02 +0200 Message-Id: <20211019094812.614056-12-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637479650100003 The 128-bit bitwise instructions do not need any function prototype change as the functions can be applied independently on the lower and upper part of the registers. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- target/riscv/translate.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e8f08f921e..71982f6284 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -429,6 +429,17 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i = *a, DisasExtend ext, =20 gen_set_gpr(ctx, a->rd, dest); =20 + if (get_xl_max(ctx) =3D=3D MXL_RV128) { + if (get_ol(ctx) =3D=3D MXL_RV128) { + uint64_t immh =3D -(a->imm < 0); + src1 =3D get_gprh(ctx, a->rs1); + dest =3D dest_gprh(ctx, a->rd); + + func(dest, src1, immh); + } + gen_set_gprh(ctx, a->rd, dest); + } + return true; } =20 @@ -443,6 +454,17 @@ static bool gen_logic(DisasContext *ctx, arg_r *a, Dis= asExtend ext, =20 gen_set_gpr(ctx, a->rd, dest); =20 + if (get_xl_max(ctx) =3D=3D MXL_RV128) { + if (get_ol(ctx) =3D=3D MXL_RV128) { + dest =3D dest_gprh(ctx, a->rd); + src1 =3D get_gprh(ctx, a->rs1); + src2 =3D get_gprh(ctx, a->rs2); + + func(dest, src1, src2); + } + gen_set_gprh(ctx, a->rd, dest); + } + return true; } =20 --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637877167634.2694008674923; Tue, 19 Oct 2021 03:04:37 -0700 (PDT) Received: from localhost ([::1]:55922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mclz2-0006IM-7U for importer@patchew.org; Tue, 19 Oct 2021 06:04:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljq-0000rA-RI; Tue, 19 Oct 2021 05:48:54 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:54848) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljo-0006YD-9J; Tue, 19 Oct 2021 05:48:54 -0400 Received: from mailhost.u-ga.fr (mailhost1.u-ga.fr [152.77.1.10]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id CEF0E4202A; Tue, 19 Oct 2021 11:48:28 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id B48A0601D5; Tue, 19 Oct 2021 11:48:28 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id 8F03D14005D; Tue, 19 Oct 2021 11:48:28 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions Date: Tue, 19 Oct 2021 11:48:03 +0200 Message-Id: <20211019094812.614056-13-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637878350100003 Adding the 128-bit version of lui and auipc. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- target/riscv/insn_trans/trans_rvi.c.inc | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 92f41f3a86..b5e292a2aa 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -26,14 +26,17 @@ static bool trans_illegal(DisasContext *ctx, arg_empty = *a) =20 static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a) { - REQUIRE_64BIT(ctx); - return trans_illegal(ctx, a); + REQUIRE_64_OR_128BIT(ctx); + return trans_illegal(ctx, a); } =20 static bool trans_lui(DisasContext *ctx, arg_lui *a) { if (a->rd !=3D 0) { tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm); + if (get_xl_max(ctx) =3D=3D MXL_RV128) { + tcg_gen_movi_tl(cpu_gprh[a->rd], -(a->imm < 0)); + } } return true; } @@ -41,7 +44,19 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a) static bool trans_auipc(DisasContext *ctx, arg_auipc *a) { if (a->rd !=3D 0) { + if (get_xl_max(ctx) =3D=3D MXL_RV128) { + /* TODO : when pc is 128 bits, use all its bits */ + TCGv pc =3D tcg_constant_tl(ctx->base.pc_next), + imml =3D tcg_constant_tl(a->imm), + immh =3D tcg_constant_tl(-(a->imm < 0)), + zero =3D tcg_constant_tl(0); + tcg_gen_add2_tl(cpu_gpr[a->rd], cpu_gprh[a->rd], + pc, zero, + imml, immh); + return true; + } tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next); + return true; } return true; } --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637512860381.60378895437145; Tue, 19 Oct 2021 02:58:32 -0700 (PDT) Received: from localhost ([::1]:40556 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mclt9-0004Ic-N3 for importer@patchew.org; Tue, 19 Oct 2021 05:58:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58848) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljw-0001EP-23; Tue, 19 Oct 2021 05:49:00 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:54896) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljr-0006cQ-MQ; Tue, 19 Oct 2021 05:48:59 -0400 Received: from mailhost.u-ga.fr (mailhost1.u-ga.fr [152.77.1.10]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id 0569E41F91; Tue, 19 Oct 2021 11:48:34 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id E2034601D5; Tue, 19 Oct 2021 11:48:33 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id B9B8914005A; Tue, 19 Oct 2021 11:48:28 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions Date: Tue, 19 Oct 2021 11:48:04 +0200 Message-Id: <20211019094812.614056-14-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637514064100001 Handling shifts for 32, 64 and 128 operation length for RV128, following the general framework for handling various olens proposed by Richard. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- target/riscv/insn32.decode | 10 + target/riscv/translate.c | 96 ++++++++-- target/riscv/insn_trans/trans_rvb.c.inc | 22 +-- target/riscv/insn_trans/trans_rvi.c.inc | 238 ++++++++++++++++++++++-- 4 files changed, 321 insertions(+), 45 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 1e7ddecc22..c642f6d09d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -22,6 +22,7 @@ %rs1 15:5 %rd 7:5 %sh5 20:5 +%sh6 20:6 =20 %sh7 20:7 %csr 20:12 @@ -92,6 +93,9 @@ # Formats 64: @sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5 = %rs1 %rd =20 +# Formats 128: +@sh6 ...... ...... ..... ... ..... ....... &shift shamt=3D%sh6 %rs1 = %rd + # *** Privileged Instructions *** ecall 000000000000 00000 000 00000 1110011 ebreak 000000000001 00000 000 00000 1110011 @@ -167,6 +171,12 @@ sraw 0100000 ..... ..... 101 ..... 0111011 @r ldu ............ ..... 111 ..... 0000011 @i lq ............ ..... 010 ..... 0001111 @i sq ............ ..... 100 ..... 0100011 @s +sllid 000000 ...... ..... 001 ..... 1011011 @sh6 +srlid 000000 ...... ..... 101 ..... 1011011 @sh6 +sraid 010000 ...... ..... 101 ..... 1011011 @sh6 +slld 0000000 ..... ..... 001 ..... 1111011 @r +srld 0000000 ..... ..... 101 ..... 1111011 @r +srad 0100000 ..... ..... 101 ..... 1111011 @r # *** RV32M Standard Extension *** mul 0000001 ..... ..... 000 ..... 0110011 @r mulh 0000001 ..... ..... 001 ..... 0110011 @r diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 71982f6284..67a82a0855 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -419,6 +419,22 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) /* Include the auto-generated decoder for 32 bit insn */ #include "decode-insn32.c.inc" =20 +/* + * xlm xl ol tl func remark + * ----+----+----+----+------+------------------- + * 32 32 32 32 f_tl + * 64 64 64 64 f_tl + * 64 64 32 64 f_32 sign extends to 64 + * 64 32 32 64 f_32 sign extends to 64 + * 128 128 128 64 f_128 + * 128 128 64 64 f_tl sign extends to 128 + * 128 128 32 64 f_32 sign extends to 128 + * 128 64 64 64 f_tl sign extends to 128 + * 128 64 32 64 f_32 sign extends to 128 + * 128 32 32 64 f_32 sign extends to 128 + * ----+----+----+----+------+------------------- + */ + static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, void (*func)(TCGv, TCGv, target_long)) { @@ -523,7 +539,8 @@ static bool gen_arith_per_ol(DisasContext *ctx, arg_r *= a, DisasExtend ext, } =20 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend = ext, - void (*func)(TCGv, TCGv, target_long)) + void (*func)(TCGv, TCGv, target_long), + void (*f128)(TCGv, TCGv, TCGv, TCGv, target_l= ong)) { TCGv dest, src1; int max_len =3D get_olen(ctx); @@ -532,29 +549,52 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_s= hift *a, DisasExtend ext, return false; } =20 - dest =3D dest_gpr(ctx, a->rd); - src1 =3D get_gpr(ctx, a->rs1, ext); + if (get_xl_max(ctx) < MXL_RV128) { + dest =3D dest_gpr(ctx, a->rd); + src1 =3D get_gpr(ctx, a->rs1, ext); =20 - func(dest, src1, a->shamt); + func(dest, src1, a->shamt); =20 - gen_set_gpr(ctx, a->rd, dest); + gen_set_gpr(ctx, a->rd, dest); + } else { + TCGv src1l =3D get_gpr(ctx, a->rs1, ext), + src1h =3D get_gprh(ctx, a->rs1), + destl =3D tcg_temp_new(), + desth =3D tcg_temp_new(); + + if (max_len < 128) { + func(destl, src1l, a->shamt); + gen_set_gpr(ctx, a->rd, destl); + gen_set_gprh(ctx, a->rd, desth); + } else { + assert(f128 !=3D NULL); + f128(destl, desth, src1l, src1h, a->shamt); + gen_set_gpr(ctx, a->rd, destl); + gen_set_gprh(ctx, a->rd, desth); + } + + tcg_temp_free(destl); + tcg_temp_free(desth); + } return true; } =20 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*f_tl)(TCGv, TCGv, target_long), - void (*f_32)(TCGv, TCGv, target_long)) + void (*f_32)(TCGv, TCGv, target_long), + void (*f_128)(TCGv, TCGv, TCGv, TCGv, + target_long)) { int olen =3D get_olen(ctx); if (olen !=3D TARGET_LONG_BITS) { if (olen =3D=3D 32) { f_tl =3D f_32; - } else { + } else if (olen !=3D 128) { g_assert_not_reached(); } } - return gen_shift_imm_fn(ctx, a, ext, f_tl); + return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); } =20 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend = ext, @@ -578,34 +618,58 @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_s= hift *a, DisasExtend ext, } =20 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, - void (*func)(TCGv, TCGv, TCGv)) + void (*func)(TCGv, TCGv, TCGv), + void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) { - TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv src1 =3D get_gpr(ctx, a->rs1, ext); TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); TCGv ext2 =3D tcg_temp_new(); =20 tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1); - func(dest, src1, ext2); =20 - gen_set_gpr(ctx, a->rd, dest); + if (get_xl_max(ctx) < MXL_RV128) { + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, ext); + func(dest, src1, ext2); + + gen_set_gpr(ctx, a->rd, dest); + } else { + TCGv src1l =3D get_gpr(ctx, a->rs1, ext), + src1h =3D get_gprh(ctx, a->rs1), + destl =3D tcg_temp_new(), + desth =3D tcg_temp_new(); + + if (get_olen(ctx) < 128) { + func(destl, src1l, ext2); + gen_set_gpr(ctx, a->rd, destl); + gen_set_gprh(ctx, a->rd, desth); + } else { + assert(f128 !=3D NULL); + f128(destl, desth, src1l, src1h, ext2); + gen_set_gpr(ctx, a->rd, destl); + gen_set_gprh(ctx, a->rd, desth); + } + + tcg_temp_free(destl); + tcg_temp_free(desth); + } tcg_temp_free(ext2); return true; } =20 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, void (*f_tl)(TCGv, TCGv, TCGv), - void (*f_32)(TCGv, TCGv, TCGv)) + void (*f_32)(TCGv, TCGv, TCGv), + void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) { int olen =3D get_olen(ctx); if (olen !=3D TARGET_LONG_BITS) { if (olen =3D=3D 32) { f_tl =3D f_32; - } else { + } else if (olen !=3D 128) { g_assert_not_reached(); } } - return gen_shift(ctx, a, ext, f_tl); + return gen_shift(ctx, a, ext, f_tl, f_128); } =20 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 28f911f95d..cae97ed842 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -156,7 +156,7 @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt) static bool trans_bset(DisasContext *ctx, arg_bset *a) { REQUIRE_ZBS(ctx); - return gen_shift(ctx, a, EXT_NONE, gen_bset); + return gen_shift(ctx, a, EXT_NONE, gen_bset, NULL); } =20 static bool trans_bseti(DisasContext *ctx, arg_bseti *a) @@ -178,7 +178,7 @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt) static bool trans_bclr(DisasContext *ctx, arg_bclr *a) { REQUIRE_ZBS(ctx); - return gen_shift(ctx, a, EXT_NONE, gen_bclr); + return gen_shift(ctx, a, EXT_NONE, gen_bclr, NULL); } =20 static bool trans_bclri(DisasContext *ctx, arg_bclri *a) @@ -200,7 +200,7 @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt) static bool trans_binv(DisasContext *ctx, arg_binv *a) { REQUIRE_ZBS(ctx); - return gen_shift(ctx, a, EXT_NONE, gen_binv); + return gen_shift(ctx, a, EXT_NONE, gen_binv, NULL); } =20 static bool trans_binvi(DisasContext *ctx, arg_binvi *a) @@ -218,7 +218,7 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) static bool trans_bext(DisasContext *ctx, arg_bext *a) { REQUIRE_ZBS(ctx); - return gen_shift(ctx, a, EXT_NONE, gen_bext); + return gen_shift(ctx, a, EXT_NONE, gen_bext, NULL); } =20 static bool trans_bexti(DisasContext *ctx, arg_bexti *a) @@ -248,7 +248,7 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_ZBB(ctx); - return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw); + return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, N= ULL); } =20 static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt) @@ -266,7 +266,7 @@ static bool trans_rori(DisasContext *ctx, arg_rori *a) { REQUIRE_ZBB(ctx); return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, - tcg_gen_rotri_tl, gen_roriw); + tcg_gen_rotri_tl, gen_roriw, NULL); } =20 static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) @@ -290,7 +290,7 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) static bool trans_rol(DisasContext *ctx, arg_rol *a) { REQUIRE_ZBB(ctx); - return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw); + return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, N= ULL); } =20 static void gen_rev8_32(TCGv ret, TCGv src1) @@ -402,7 +402,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a) REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); ctx->ol =3D MXL_RV32; - return gen_shift(ctx, a, EXT_NONE, gen_rorw); + return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL); } =20 static bool trans_roriw(DisasContext *ctx, arg_roriw *a) @@ -410,7 +410,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a) REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); ctx->ol =3D MXL_RV32; - return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw); + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL); } =20 static bool trans_rolw(DisasContext *ctx, arg_rolw *a) @@ -418,7 +418,7 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a) REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); ctx->ol =3D MXL_RV32; - return gen_shift(ctx, a, EXT_NONE, gen_rolw); + return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL); } =20 #define GEN_SHADD_UW(SHAMT) \ @@ -475,7 +475,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_u= w *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBA(ctx); - return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw); + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw, NULL); } =20 static bool trans_clmul(DisasContext *ctx, arg_clmul *a) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index b5e292a2aa..6e2c89cd5e 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -410,9 +410,22 @@ static bool trans_andi(DisasContext *ctx, arg_andi *a) return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl); } =20 +static void gen_slli_i128(TCGv retl, TCGv reth, + TCGv src1l, TCGv src1h, + target_long shamt) +{ + if (shamt >=3D 64) { + tcg_gen_shli_tl(reth, src1l, shamt - 64); + tcg_gen_movi_tl(retl, 0); + } else { + tcg_gen_extract2_tl(reth, src1l, src1h, 64 - shamt); + tcg_gen_shli_tl(retl, src1l, shamt); + } +} + static bool trans_slli(DisasContext *ctx, arg_slli *a) { - return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); + return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, gen_slli_i1= 28); } =20 static void gen_srliw(TCGv dst, TCGv src, target_long shamt) @@ -420,10 +433,23 @@ static void gen_srliw(TCGv dst, TCGv src, target_long= shamt) tcg_gen_extract_tl(dst, src, shamt, 32 - shamt); } =20 +static void gen_srli_i128(TCGv retl, TCGv reth, + TCGv src1l, TCGv src1h, + target_long shamt) +{ + if (shamt >=3D 64) { + tcg_gen_shri_tl(retl, src1h, shamt - 64); + tcg_gen_movi_tl(reth, 0); + } else { + tcg_gen_extract2_tl(retl, src1l, src1h, shamt); + tcg_gen_shri_tl(reth, src1h, shamt); + } +} + static bool trans_srli(DisasContext *ctx, arg_srli *a) { return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, - tcg_gen_shri_tl, gen_srliw); + tcg_gen_shri_tl, gen_srliw, gen_srli_i1= 28); } =20 static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) @@ -431,10 +457,23 @@ static void gen_sraiw(TCGv dst, TCGv src, target_long= shamt) tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt); } =20 +static void gen_srai_i128(TCGv retl, TCGv reth, + TCGv src1l, TCGv src1h, + target_long shamt) +{ + if (shamt >=3D 64) { + tcg_gen_sari_tl(retl, src1h, shamt - 64); + tcg_gen_sari_tl(reth, src1h, 63); + } else { + tcg_gen_extract2_tl(retl, src1l, src1h, shamt); + tcg_gen_sari_tl(reth, src1h, shamt); + } +} + static bool trans_srai(DisasContext *ctx, arg_srai *a) { return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, - tcg_gen_sari_tl, gen_sraiw); + tcg_gen_sari_tl, gen_sraiw, gen_srai_i1= 28); } =20 static bool trans_add(DisasContext *ctx, arg_add *a) @@ -447,9 +486,75 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a) return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl); } =20 +enum M128_DIR { + M128_LEFT, + M128_RIGHT, + M128_RIGHT_ARITH +}; +/* 127 <=3D arg2 <=3D 0 */ +static void gen_shift_mod128(TCGv ret, TCGv arg1, TCGv arg2, enum M128_DIR= dir) +{ + TCGv tmp1 =3D tcg_temp_new(), + tmp2 =3D tcg_temp_new(), + sgn =3D tcg_temp_new(), + cnst_zero =3D tcg_constant_tl(0); + + tcg_gen_setcondi_tl(TCG_COND_GEU, tmp1, arg2, 64); + + tcg_gen_andi_tl(tmp2, arg2, 0x3f); + switch (dir) { + case M128_LEFT: + tcg_gen_shl_tl(tmp2, arg1, tmp2); + break; + case M128_RIGHT: + tcg_gen_shr_tl(tmp2, arg1, tmp2); + break; + case M128_RIGHT_ARITH: + tcg_gen_sar_tl(tmp2, arg1, tmp2); + break; + } + + if (dir =3D=3D M128_RIGHT_ARITH) { + tcg_gen_sari_tl(sgn, arg1, 63); + tcg_gen_movcond_tl(TCG_COND_NE, ret, tmp1, cnst_zero, sgn, tmp2); + } else { + tcg_gen_movcond_tl(TCG_COND_NE, ret, tmp1, cnst_zero, cnst_zero, t= mp2); + } + + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); + tcg_temp_free(sgn); + return; +} + +static void gen_sll_i128(TCGv destl, TCGv desth, + TCGv src1l, TCGv src1h, TCGv shamt) +{ + TCGv tmp =3D tcg_temp_new(); + /* + * From Hacker's Delight 2.17: + * y1 =3D x1 << n | x0 u>> (64 - n) | x0 << (n - 64) + */ + gen_shift_mod128(desth, src1h, shamt, M128_LEFT); + + tcg_gen_movi_tl(tmp, 64); + tcg_gen_sub_tl(tmp, tmp, shamt); + gen_shift_mod128(tmp, src1l, tmp, M128_RIGHT); + tcg_gen_or_tl(desth, desth, tmp); + + tcg_gen_subi_tl(tmp, shamt, 64); + gen_shift_mod128(tmp, src1l, tmp, M128_LEFT); + tcg_gen_or_tl(desth, desth, tmp); + + /* From Hacker's Delight 2.17: y0 =3D x0 << n */ + gen_shift_mod128(destl, src1l, shamt, M128_LEFT); + + tcg_temp_free(tmp); +} + static bool trans_sll(DisasContext *ctx, arg_sll *a) { - return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl); + return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, gen_sll_i128); } =20 static bool trans_slt(DisasContext *ctx, arg_slt *a) @@ -462,14 +567,67 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a) return gen_arith(ctx, a, EXT_SIGN, gen_sltu); } =20 +static void gen_srl_i128(TCGv destl, TCGv desth, + TCGv src1l, TCGv src1h, TCGv shamt) +{ + TCGv tmp =3D tcg_temp_new(); + /* + * From Hacker's Delight 2.17: + * y0 =3D x0 u>> n | x1 << (64 - n) | x1 u>> (n - 64) + */ + gen_shift_mod128(destl, src1l, shamt, M128_RIGHT); + + tcg_gen_movi_tl(tmp, 64); + tcg_gen_sub_tl(tmp, tmp, shamt); + gen_shift_mod128(tmp, src1h, tmp, M128_LEFT); + tcg_gen_or_tl(destl, destl, tmp); + + tcg_gen_subi_tl(tmp, shamt, 64); + gen_shift_mod128(tmp, src1h, tmp, M128_RIGHT); + tcg_gen_or_tl(destl, destl, tmp); + + /* From Hacker's Delight 2.17 : y1 =3D x1 u>> n */ + gen_shift_mod128(desth, src1h, shamt, M128_RIGHT); + + tcg_temp_free(tmp); +} + static bool trans_srl(DisasContext *ctx, arg_srl *a) { - return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl); + return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, gen_srl_i128); +} + +static void gen_sra_i128(TCGv destl, TCGv desth, + TCGv src1l, TCGv src1h, TCGv shamt) +{ + TCGv tmp1 =3D tcg_temp_new(), + tmp2 =3D tcg_temp_new(), + const64 =3D tcg_constant_tl(64); + + /* Compute y0 value if n < 64: x0 u>> n | x1 << (64 - n) */ + gen_shift_mod128(tmp1, src1l, shamt, M128_RIGHT); + tcg_gen_movi_tl(tmp2, 64); + tcg_gen_sub_tl(tmp2, tmp2, shamt); + gen_shift_mod128(tmp2, src1h, tmp2, M128_LEFT); + tcg_gen_or_tl(tmp1, tmp1, tmp2); + + /* Compute y0 value if n >=3D 64: x1 s>> (n - 64) */ + tcg_gen_subi_tl(tmp2, shamt, 64); + gen_shift_mod128(tmp2, src1h, tmp2, M128_RIGHT_ARITH); + + /* Conditionally move one value or the other */ + tcg_gen_movcond_tl(TCG_COND_LT, destl, shamt, const64, tmp1, tmp2); + + /* y1 =3D x1 s>> n */ + gen_shift_mod128(desth, src1h, shamt, M128_RIGHT_ARITH); + + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); } =20 static bool trans_sra(DisasContext *ctx, arg_sra *a) { - return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl); + return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, gen_sra_i128); } =20 static bool trans_xor(DisasContext *ctx, arg_xor *a) @@ -496,25 +654,47 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw = *a) =20 static bool trans_slliw(DisasContext *ctx, arg_slliw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); ctx->ol =3D MXL_RV32; - return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); + return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, NULL); } =20 static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); ctx->ol =3D MXL_RV32; - return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw); + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw, NULL); } =20 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); ctx->ol =3D MXL_RV32; - return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw); + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw, NULL); } =20 +static bool trans_sllid(DisasContext *ctx, arg_sllid *a) +{ + REQUIRE_128BIT(ctx); + ctx->ol =3D MXL_RV64; + return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, NULL); +} + +static bool trans_srlid(DisasContext *ctx, arg_srlid *a) +{ + REQUIRE_128BIT(ctx); + ctx->ol =3D MXL_RV64; + return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shri_tl, NULL); +} + +static bool trans_sraid(DisasContext *ctx, arg_sraid *a) +{ + REQUIRE_128BIT(ctx); + ctx->ol =3D MXL_RV64; + return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_sari_tl, NULL); +} + + static bool trans_addw(DisasContext *ctx, arg_addw *a) { REQUIRE_64BIT(ctx); @@ -531,25 +711,47 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a) =20 static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); ctx->ol =3D MXL_RV32; - return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl); + return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, NULL); } =20 static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); ctx->ol =3D MXL_RV32; - return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl); + return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, NULL); } =20 static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); ctx->ol =3D MXL_RV32; - return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl); + return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL); } =20 +static bool trans_slld(DisasContext *ctx, arg_slld *a) +{ + REQUIRE_128BIT(ctx); + ctx->ol =3D MXL_RV64; + return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, NULL); +} + +static bool trans_srld(DisasContext *ctx, arg_srld *a) +{ + REQUIRE_128BIT(ctx); + ctx->ol =3D MXL_RV64; + return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, NULL); +} + +static bool trans_srad(DisasContext *ctx, arg_srad *a) +{ + REQUIRE_128BIT(ctx); + ctx->ol =3D MXL_RV64; + return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL); +} + + static bool trans_fence(DisasContext *ctx, arg_fence *a) { /* FENCE is a full memory barrier. */ --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634638043992467.681927224276; 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Tue, 19 Oct 2021 11:48:33 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions Date: Tue, 19 Oct 2021 11:48:05 +0200 Message-Id: <20211019094812.614056-15-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634638045908100001 Addition of 128-bit adds and subs in their various sizes. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- target/riscv/insn32.decode | 3 + target/riscv/translate.c | 105 ++++++++++++--- target/riscv/insn_trans/trans_rvb.c.inc | 20 +-- target/riscv/insn_trans/trans_rvi.c.inc | 169 ++++++++++++++++++++++-- target/riscv/insn_trans/trans_rvm.c.inc | 26 ++-- 5 files changed, 266 insertions(+), 57 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c642f6d09d..3556bf49cc 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -171,9 +171,12 @@ sraw 0100000 ..... ..... 101 ..... 0111011 @r ldu ............ ..... 111 ..... 0000011 @i lq ............ ..... 010 ..... 0001111 @i sq ............ ..... 100 ..... 0100011 @s +addid ............ ..... 000 ..... 1011011 @i sllid 000000 ...... ..... 001 ..... 1011011 @sh6 srlid 000000 ...... ..... 101 ..... 1011011 @sh6 sraid 010000 ...... ..... 101 ..... 1011011 @sh6 +addd 0000000 ..... ..... 000 ..... 1111011 @r +subd 0100000 ..... ..... 000 ..... 1111011 @r slld 0000000 ..... ..... 001 ..... 1111011 @r srld 0000000 ..... ..... 101 ..... 1111011 @r srad 0100000 ..... ..... 101 ..... 1111011 @r diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 67a82a0855..332a5d0384 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -485,57 +485,122 @@ static bool gen_logic(DisasContext *ctx, arg_r *a, D= isasExtend ext, } =20 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, - void (*func)(TCGv, TCGv, target_long)) + void (*func)(TCGv, TCGv, target_long), + void (*f128)(TCGv, TCGv, TCGv, TCGv, target_l= ong)) { - TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv src1 =3D get_gpr(ctx, a->rs1, ext); + if (get_xl_max(ctx) < MXL_RV128) { + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, ext); =20 - func(dest, src1, a->imm); + func(dest, src1, a->imm); =20 - gen_set_gpr(ctx, a->rd, dest); + gen_set_gpr(ctx, a->rd, dest); + } else { + TCGv src1l =3D get_gpr(ctx, a->rs1, ext), + src1h =3D get_gprh(ctx, a->rs1), + destl =3D tcg_temp_new(), + desth =3D tcg_temp_new(); + + if (get_ol(ctx) < MXL_RV128) { + func(destl, src1l, a->imm); + gen_set_gpr(ctx, a->rd, destl); + gen_set_gprh(ctx, a->rd, desth); + } else { + assert(f128 !=3D NULL); + f128(destl, desth, src1l, src1h, a->imm); + gen_set_gpr(ctx, a->rd, destl); + gen_set_gprh(ctx, a->rd, desth); + } + + tcg_temp_free(destl); + tcg_temp_free(desth); + } return true; } =20 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, - void (*func)(TCGv, TCGv, TCGv)) + void (*func)(TCGv, TCGv, TCGv), + void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TC= Gv)) { - TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv src1 =3D get_gpr(ctx, a->rs1, ext); - TCGv src2 =3D tcg_constant_tl(a->imm); =20 - func(dest, src1, src2); + if (get_xl_max(ctx) < MXL_RV128) { + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, ext); + TCGv src2 =3D tcg_constant_tl(a->imm); =20 - gen_set_gpr(ctx, a->rd, dest); + func(dest, src1, src2); + + gen_set_gpr(ctx, a->rd, dest); + } else { + TCGv src1l =3D get_gpr(ctx, a->rs1, ext), + src1h =3D get_gprh(ctx, a->rs1), + src2l =3D tcg_constant_tl(a->imm), + src2h =3D tcg_constant_tl(-(a->imm < 0)), + destl =3D tcg_temp_new(), + desth =3D tcg_temp_new(); + + assert(f128 !=3D NULL); + f128(destl, desth, src1l, src1h, src2l, src2h); + gen_set_gpr(ctx, a->rd, destl); + gen_set_gprh(ctx, a->rd, desth); + tcg_temp_free(destl); + tcg_temp_free(desth); + } return true; } =20 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, - void (*func)(TCGv, TCGv, TCGv)) + void (*func)(TCGv, TCGv, TCGv), + void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) { - TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv src1 =3D get_gpr(ctx, a->rs1, ext); - TCGv src2 =3D get_gpr(ctx, a->rs2, ext); + if (get_xl_max(ctx) < MXL_RV128) { + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, ext); + TCGv src2 =3D get_gpr(ctx, a->rs2, ext); =20 - func(dest, src1, src2); + func(dest, src1, src2); =20 - gen_set_gpr(ctx, a->rd, dest); + gen_set_gpr(ctx, a->rd, dest); + } else { + TCGv src1l =3D get_gpr(ctx, a->rs1, ext), + src1h =3D get_gprh(ctx, a->rs1), + src2l =3D get_gpr(ctx, a->rs2, ext), + src2h =3D get_gprh(ctx, a->rs2), + destl =3D tcg_temp_new(), + desth =3D tcg_temp_new(); + + if (get_ol(ctx) < MXL_RV128) { + func(destl, src1l, src2l); + gen_set_gpr(ctx, a->rd, destl); + gen_set_gprh(ctx, a->rd, desth); + } else { + assert(f128 !=3D NULL); + f128(destl, desth, src1l, src1h, src2l, src2h); + gen_set_gpr(ctx, a->rd, destl); + gen_set_gprh(ctx, a->rd, desth); + } + + tcg_temp_free(destl); + tcg_temp_free(desth); + } return true; } =20 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, void (*f_tl)(TCGv, TCGv, TCGv), - void (*f_32)(TCGv, TCGv, TCGv)) + void (*f_32)(TCGv, TCGv, TCGv), + void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, T= CGv)) { int olen =3D get_olen(ctx); =20 if (olen !=3D TARGET_LONG_BITS) { if (olen =3D=3D 32) { f_tl =3D f_32; - } else { + } else if (olen !=3D 128) { g_assert_not_reached(); } } - return gen_arith(ctx, a, ext, f_tl); + return gen_arith(ctx, a, ext, f_tl, f_128); } =20 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend = ext, diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index cae97ed842..764c0b7122 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -104,25 +104,25 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a) static bool trans_min(DisasContext *ctx, arg_min *a) { REQUIRE_ZBB(ctx); - return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl); + return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl, NULL); } =20 static bool trans_max(DisasContext *ctx, arg_max *a) { REQUIRE_ZBB(ctx); - return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl); + return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl, NULL); } =20 static bool trans_minu(DisasContext *ctx, arg_minu *a) { REQUIRE_ZBB(ctx); - return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl); + return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl, NULL); } =20 static bool trans_maxu(DisasContext *ctx, arg_maxu *a) { REQUIRE_ZBB(ctx); - return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl); + return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl, NULL); } =20 static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a) @@ -354,7 +354,7 @@ GEN_SHADD(3) static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a)= \ { = \ REQUIRE_ZBA(ctx); = \ - return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add); = \ + return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add, NULL); = \ } =20 GEN_TRANS_SHADD(1) @@ -444,7 +444,7 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, = \ { \ REQUIRE_64BIT(ctx); \ REQUIRE_ZBA(ctx); \ - return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw); \ + return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw, NULL); \ } =20 GEN_TRANS_SHADD_UW(1) @@ -463,7 +463,7 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw = *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBA(ctx); - return gen_arith(ctx, a, EXT_NONE, gen_add_uw); + return gen_arith(ctx, a, EXT_NONE, gen_add_uw, NULL); } =20 static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt) @@ -481,7 +481,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_u= w *a) static bool trans_clmul(DisasContext *ctx, arg_clmul *a) { REQUIRE_ZBC(ctx); - return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul); + return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL); } =20 static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2) @@ -493,11 +493,11 @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2) static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a) { REQUIRE_ZBC(ctx); - return gen_arith(ctx, a, EXT_NONE, gen_clmulh); + return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL); } =20 static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a) { REQUIRE_ZBC(ctx); - return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr); + return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL); } diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 6e2c89cd5e..6497338842 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -97,13 +97,121 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) return true; } =20 +/* + * Comparison predicates using bitwise logic taken from Hacker's Delight, = 2.12 + * We are just interested in the sign bit, so rl is not used but for subtr= acting + */ +static bool gen_setcond_i128(TCGv rl, TCGv rh, + TCGv al, TCGv ah, + TCGv bl, TCGv bh, + TCGCond cond) +{ + switch (cond) { + case TCG_COND_EQ: + tcg_gen_setcond_tl(TCG_COND_EQ, rl, al, bl); + tcg_gen_setcond_tl(TCG_COND_EQ, rh, ah, bh); + tcg_gen_and_tl(rl, rl, rh); + break; + + case TCG_COND_NE: + tcg_gen_setcond_tl(TCG_COND_NE, rl, al, bl); + tcg_gen_setcond_tl(TCG_COND_NE, rh, ah, bh); + tcg_gen_or_tl(rl, rl, rh); + break; + + case TCG_COND_LT: + { + TCGv tmp1 =3D tcg_temp_new(), + tmp2 =3D tcg_temp_new(); + + tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh); + tcg_gen_xor_tl(tmp1, rh, ah); + tcg_gen_xor_tl(tmp2, ah, bh); + tcg_gen_and_tl(tmp1, tmp1, tmp2); + tcg_gen_xor_tl(tmp1, rh, tmp1); + tcg_gen_shri_tl(rl, tmp1, 63); + + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); + break; + } + + case TCG_COND_GE: + /* Invert result of TCG_COND_LT */ + gen_setcond_i128(rl, rh, al, ah, bl, bh, TCG_COND_LT); + tcg_gen_xori_tl(rl, rl, 1); + break; + + case TCG_COND_LTU: + { + TCGv tmp1 =3D tcg_temp_new(), + tmp2 =3D tcg_temp_new(); + + tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh); + tcg_gen_eqv_tl(tmp1, ah, bh); + tcg_gen_and_tl(tmp1, tmp1, rh); + tcg_gen_andc_tl(tmp2, bh, ah); + tcg_gen_or_tl(tmp1, tmp1, tmp2); + tcg_gen_shri_tl(rl, tmp1, 63); + + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); + break; + } + + case TCG_COND_GEU: + /* Invert result of TCG_COND_LTU */ + gen_setcond_i128(rl, rh, al, ah, bl, bh, TCG_COND_LTU); + tcg_gen_xori_tl(rl, rl, 1); + break; + + default: + return false; + } + tcg_gen_movi_tl(rh, 0); + return true; +} + static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) { TCGLabel *l =3D gen_new_label(); TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_SIGN); TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_SIGN); =20 - tcg_gen_brcond_tl(cond, src1, src2, l); + if (get_xl(ctx) =3D=3D MXL_RV128) { + TCGv src1h =3D get_gprh(ctx, a->rs1), + src2h =3D get_gprh(ctx, a->rs2), + tmpl =3D tcg_temp_new(), + tmph =3D tcg_temp_new(); + + /* + * Do not use gen_setcond_i128 for EQ and NE as these conditions a= re + * often met and can be more efficiently implemented. + */ + if (cond =3D=3D TCG_COND_EQ || cond =3D=3D TCG_COND_NE) { + /* + * bnez and beqz being used quite often too, lets optimize the= m, + * although QEMU's tcg optimizer handles these cases nicely + */ + if (a->rs2 =3D=3D 0) { + tcg_gen_or_tl(tmpl, src1, src1h); + tcg_gen_brcondi_tl(cond, tmpl, 0, l); + } else { + tcg_gen_xor_tl(tmpl, src1, src2); + tcg_gen_xor_tl(tmph, src1h, src2h); + tcg_gen_or_tl(tmpl, tmpl, tmph); + tcg_gen_brcondi_tl(cond, tmpl, 0, l); + } + } else { + gen_setcond_i128(tmpl, tmph, src1, src1h, src2, src2h, cond); + tcg_gen_brcondi_tl(TCG_COND_NE, tmpl, 0, l); + } + + tcg_temp_free(tmph); + tcg_temp_free(tmpl); + } else { + tcg_gen_brcond_tl(cond, src1, src2, l); + } gen_goto_tb(ctx, 1, ctx->pc_succ_insn); =20 gen_set_label(l); /* branch taken */ @@ -370,9 +478,30 @@ static bool trans_sq(DisasContext *ctx, arg_sq *a) return gen_store(ctx, a, MO_TEO); } =20 +static bool trans_addd(DisasContext *ctx, arg_addd *a) +{ + REQUIRE_128BIT(ctx); + ctx->ol =3D MXL_RV64; + return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, NULL); +} + +static bool trans_addid(DisasContext *ctx, arg_addid *a) +{ + REQUIRE_128BIT(ctx); + ctx->ol =3D MXL_RV64; + return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, NULL); +} + +static bool trans_subd(DisasContext *ctx, arg_subd *a) +{ + REQUIRE_128BIT(ctx); + ctx->ol =3D MXL_RV64; + return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, NULL); +} + static bool trans_addi(DisasContext *ctx, arg_addi *a) { - return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl); + return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, gen_addi2_i= 128); } =20 static void gen_slt(TCGv ret, TCGv s1, TCGv s2) @@ -380,19 +509,31 @@ static void gen_slt(TCGv ret, TCGv s1, TCGv s2) tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2); } =20 +static void gen_slt_i128(TCGv retl, TCGv reth, + TCGv s1l, TCGv s1h, TCGv s2l, TCGv s2h) +{ + gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LT); +} + static void gen_sltu(TCGv ret, TCGv s1, TCGv s2) { tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2); } =20 +static void gen_sltu_i128(TCGv retl, TCGv reth, + TCGv s1l, TCGv s1h, TCGv s2l, TCGv s2h) +{ + gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LTU); +} + static bool trans_slti(DisasContext *ctx, arg_slti *a) { - return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt); + return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt, gen_slt_i128); } =20 static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a) { - return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu); + return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu, gen_sltu_i128); } =20 static bool trans_xori(DisasContext *ctx, arg_xori *a) @@ -478,12 +619,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a) =20 static bool trans_add(DisasContext *ctx, arg_add *a) { - return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, tcg_gen_add2_tl); } =20 static bool trans_sub(DisasContext *ctx, arg_sub *a) { - return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, tcg_gen_sub2_tl); } =20 enum M128_DIR { @@ -559,12 +700,12 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a) =20 static bool trans_slt(DisasContext *ctx, arg_slt *a) { - return gen_arith(ctx, a, EXT_SIGN, gen_slt); + return gen_arith(ctx, a, EXT_SIGN, gen_slt, gen_slt_i128); } =20 static bool trans_sltu(DisasContext *ctx, arg_sltu *a) { - return gen_arith(ctx, a, EXT_SIGN, gen_sltu); + return gen_arith(ctx, a, EXT_SIGN, gen_sltu, gen_sltu_i128); } =20 static void gen_srl_i128(TCGv destl, TCGv desth, @@ -647,9 +788,9 @@ static bool trans_and(DisasContext *ctx, arg_and *a) =20 static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); ctx->ol =3D MXL_RV32; - return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl); + return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, NULL); } =20 static bool trans_slliw(DisasContext *ctx, arg_slliw *a) @@ -697,16 +838,16 @@ static bool trans_sraid(DisasContext *ctx, arg_sraid = *a) =20 static bool trans_addw(DisasContext *ctx, arg_addw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); ctx->ol =3D MXL_RV32; - return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, NULL); } =20 static bool trans_subw(DisasContext *ctx, arg_subw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); ctx->ol =3D MXL_RV32; - return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, NULL); } =20 static bool trans_sllw(DisasContext *ctx, arg_sllw *a) diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index 2af0e5c139..efe25dfc11 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -22,7 +22,7 @@ static bool trans_mul(DisasContext *ctx, arg_mul *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL); } =20 static void gen_mulh(TCGv ret, TCGv s1, TCGv s2) @@ -42,7 +42,7 @@ static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2) static bool trans_mulh(DisasContext *ctx, arg_mulh *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w); + return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w, NULL); } =20 static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) @@ -76,7 +76,7 @@ static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2) static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w); + return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w, NU= LL); } =20 static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2) @@ -91,7 +91,7 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) { REQUIRE_EXT(ctx, RVM); /* gen_mulh_w works for either sign as input. */ - return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w); + return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w, NULL); } =20 static void gen_div(TCGv ret, TCGv source1, TCGv source2) @@ -130,7 +130,7 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source= 2) static bool trans_div(DisasContext *ctx, arg_div *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_SIGN, gen_div); + return gen_arith(ctx, a, EXT_SIGN, gen_div, NULL); } =20 static void gen_divu(TCGv ret, TCGv source1, TCGv source2) @@ -158,7 +158,7 @@ static void gen_divu(TCGv ret, TCGv source1, TCGv sourc= e2) static bool trans_divu(DisasContext *ctx, arg_divu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_ZERO, gen_divu); + return gen_arith(ctx, a, EXT_ZERO, gen_divu, NULL); } =20 static void gen_rem(TCGv ret, TCGv source1, TCGv source2) @@ -199,7 +199,7 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source= 2) static bool trans_rem(DisasContext *ctx, arg_rem *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_SIGN, gen_rem); + return gen_arith(ctx, a, EXT_SIGN, gen_rem, NULL); } =20 static void gen_remu(TCGv ret, TCGv source1, TCGv source2) @@ -227,7 +227,7 @@ static void gen_remu(TCGv ret, TCGv source1, TCGv sourc= e2) static bool trans_remu(DisasContext *ctx, arg_remu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_ZERO, gen_remu); + return gen_arith(ctx, a, EXT_ZERO, gen_remu, NULL); } =20 static bool trans_mulw(DisasContext *ctx, arg_mulw *a) @@ -235,7 +235,7 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a) REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); ctx->ol =3D MXL_RV32; - return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL); } =20 static bool trans_divw(DisasContext *ctx, arg_divw *a) @@ -243,7 +243,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a) REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); ctx->ol =3D MXL_RV32; - return gen_arith(ctx, a, EXT_SIGN, gen_div); + return gen_arith(ctx, a, EXT_SIGN, gen_div, NULL); } =20 static bool trans_divuw(DisasContext *ctx, arg_divuw *a) @@ -251,7 +251,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a) REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); ctx->ol =3D MXL_RV32; - return gen_arith(ctx, a, EXT_ZERO, gen_divu); + return gen_arith(ctx, a, EXT_ZERO, gen_divu, NULL); } =20 static bool trans_remw(DisasContext *ctx, arg_remw *a) @@ -259,7 +259,7 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a) REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); ctx->ol =3D MXL_RV32; - return gen_arith(ctx, a, EXT_SIGN, gen_rem); + return gen_arith(ctx, a, EXT_SIGN, gen_rem, NULL); } =20 static bool trans_remuw(DisasContext *ctx, arg_remuw *a) @@ -267,5 +267,5 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a) REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); ctx->ol =3D MXL_RV32; - return gen_arith(ctx, a, EXT_ZERO, gen_remu); + return gen_arith(ctx, a, EXT_ZERO, gen_remu, NULL); } --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637553784280.2896158986598; Tue, 19 Oct 2021 02:59:13 -0700 (PDT) Received: from localhost ([::1]:43836 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mclto-0006WC-Hk for importer@patchew.org; Tue, 19 Oct 2021 05:59:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljx-0001KU-QD; Tue, 19 Oct 2021 05:49:01 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:54936) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljs-0006cw-0B; Tue, 19 Oct 2021 05:49:01 -0400 Received: from mailhost.u-ga.fr (mailhost1.u-ga.fr [152.77.1.10]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id 61FB041F73; Tue, 19 Oct 2021 11:48:34 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id 48B2C601D5; Tue, 19 Oct 2021 11:48:34 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id 160D814005A; Tue, 19 Oct 2021 11:48:34 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 15/21] target/riscv: support for 128-bit M extension Date: Tue, 19 Oct 2021 11:48:06 +0200 Message-Id: <20211019094812.614056-16-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637554933100001 Given the complexity of the implementation of these instructions, we call helpers to produce their behavior. From an implementation standpoint, we ended up by adding two more tcg globals to return the 128-bit result in a wrapper that itself is called by gen_arith. The sub 128-bit insns are now handled through the existing generation functions. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 1 + target/riscv/helper.h | 6 + target/riscv/insn32.decode | 7 + target/riscv/m128_helper.c | 109 ++++++++++ target/riscv/translate.c | 7 +- target/riscv/insn_trans/trans_rvm.c.inc | 263 ++++++++++++++++++++++-- target/riscv/meson.build | 1 + 7 files changed, 380 insertions(+), 14 deletions(-) create mode 100644 target/riscv/m128_helper.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5d21128865..8b96ccb37a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -113,6 +113,7 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) struct CPURISCVState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ + target_ulong hlpr[2]; /* scratch registers for 128-bit div/rem helper= s */ uint64_t fpr[32]; /* assume both F and D extensions */ =20 /* vector coprocessor state. */ diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c7a5376227..67f5d23692 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1147,3 +1147,9 @@ DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr= , env, i32) DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32) + +/* 128-bit integer multiplication and division */ +DEF_HELPER_5(divu_i128, void, env, i64, i64, i64, i64) +DEF_HELPER_5(divs_i128, void, env, i64, i64, i64, i64) +DEF_HELPER_5(remu_i128, void, env, i64, i64, i64, i64) +DEF_HELPER_5(rems_i128, void, env, i64, i64, i64, i64) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3556bf49cc..876e5f7f5b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -197,6 +197,13 @@ divuw 0000001 ..... ..... 101 ..... 0111011 @r remw 0000001 ..... ..... 110 ..... 0111011 @r remuw 0000001 ..... ..... 111 ..... 0111011 @r =20 +# *** RV128M Standard Extension (in addition to RV64M) *** +muld 0000001 ..... ..... 000 ..... 1111011 @r +divd 0000001 ..... ..... 100 ..... 1111011 @r +divud 0000001 ..... ..... 101 ..... 1111011 @r +remd 0000001 ..... ..... 110 ..... 1111011 @r +remud 0000001 ..... ..... 111 ..... 1111011 @r + # *** RV32A Standard Extension *** lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st diff --git a/target/riscv/m128_helper.c b/target/riscv/m128_helper.c new file mode 100644 index 0000000000..694ca5da9b --- /dev/null +++ b/target/riscv/m128_helper.c @@ -0,0 +1,109 @@ +/* + * RISC-V Emulation Helpers for QEMU. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "qemu/main-loop.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" + +void HELPER(divu_i128)(CPURISCVState *env, + uint64_t ul, uint64_t uh, + uint64_t vl, uint64_t vh) +{ + uint64_t ql, qh; + Int128 q; + + if (vl =3D=3D 0 && vh =3D=3D 0) { /* Handle special behavior on div by= zero */ + ql =3D ~0x0; + qh =3D ~0x0; + } else { + q =3D int128_divu(int128_make128(ul, uh), int128_make128(vl, vh)); + ql =3D int128_getlo(q); + qh =3D int128_gethi(q); + } + + env->hlpr[0] =3D ql; + env->hlpr[1] =3D qh; +} + +void HELPER(remu_i128)(CPURISCVState *env, + uint64_t ul, uint64_t uh, + uint64_t vl, uint64_t vh) +{ + uint64_t rl, rh; + Int128 r; + + if (vl =3D=3D 0 && vh =3D=3D 0) { + rl =3D ul; + rh =3D uh; + } else { + r =3D int128_remu(int128_make128(ul, uh), int128_make128(vl, vh)); + rl =3D int128_getlo(r); + rh =3D int128_gethi(r); + } + + env->hlpr[0] =3D rl; + env->hlpr[1] =3D rh; +} + +void HELPER(divs_i128)(CPURISCVState *env, + uint64_t ul, uint64_t uh, + uint64_t vl, uint64_t vh) +{ + uint64_t qh, ql; + Int128 q; + + if (vl =3D=3D 0 && vh =3D=3D 0) { /* Div by zero check */ + ql =3D ~0x0; + qh =3D ~0x0; + } else if (uh =3D=3D 0x8000000000000000 && ul =3D=3D 0 && + vh =3D=3D ~0x0 && vl =3D=3D ~0x0) { + /* Signed div overflow check (-2**127 / -1) */ + ql =3D ul; + qh =3D uh; + } else { + q =3D int128_divs(int128_make128(ul, uh), int128_make128(vl, vh)); + ql =3D int128_getlo(q); + qh =3D int128_gethi(q); + } + + env->hlpr[0] =3D ql; + env->hlpr[1] =3D qh; +} + +void HELPER(rems_i128)(CPURISCVState *env, + uint64_t ul, uint64_t uh, + uint64_t vl, uint64_t vh) +{ + uint64_t rh, rl; + Int128 r; + + if (vl =3D=3D 0 && vh =3D=3D 0) { + rl =3D ul; + rh =3D uh; + } else { + r =3D int128_rems(int128_make128(ul, uh), int128_make128(vl, vh)); + rl =3D int128_getlo(r); + rh =3D int128_gethi(r); + } + + env->hlpr[0] =3D rl; + env->hlpr[1] =3D rh; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 332a5d0384..2d76832d56 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -32,7 +32,7 @@ #include "instmap.h" =20 /* global register indices */ -static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl; +static TCGv cpu_gpr[32], cpu_gprh[32], cpu_hlpr[2], cpu_pc, cpu_vl; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; @@ -953,6 +953,11 @@ void riscv_translate_init(void) offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]); } =20 + cpu_hlpr[0] =3D tcg_global_mem_new(cpu_env, + offsetof(CPURISCVState, hlpr[0]), "helper_reg0"); + cpu_hlpr[1] =3D tcg_global_mem_new(cpu_env, + offsetof(CPURISCVState, hlpr[1]), "helper_reg1"); + for (i =3D 0; i < 32; i++) { cpu_fpr[i] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index efe25dfc11..ea355ce333 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -18,11 +18,106 @@ * this program. If not, see . */ =20 +static void gen_mulu2_i128(TCGv rll, TCGv rlh, TCGv rhl, TCGv rhh, + TCGv al, TCGv ah, TCGv bl, TCGv bh) +{ + TCGv tmpl =3D tcg_temp_new(), + tmph =3D tcg_temp_new(), + cnst_zero =3D tcg_constant_tl(0); + + tcg_gen_mulu2_tl(rll, rlh, al, bl); + + tcg_gen_mulu2_tl(tmpl, tmph, al, bh); + tcg_gen_add2_tl(rlh, rhl, rlh, cnst_zero, tmpl, tmph); + tcg_gen_mulu2_tl(tmpl, tmph, ah, bl); + tcg_gen_add2_tl(rlh, tmph, rlh, rhl, tmpl, tmph); + /* Overflow detection into rhh */ + tcg_gen_setcond_tl(TCG_COND_LTU, rhh, tmph, rhl); + + tcg_gen_mov_tl(rhl, tmph); + + tcg_gen_mulu2_tl(tmpl, tmph, ah, bh); + tcg_gen_add2_tl(rhl, rhh, rhl, rhh, tmpl, tmph); + + tcg_temp_free(tmpl); + tcg_temp_free(tmph); +} + +static void gen_mul_i128(TCGv rll, TCGv rlh, + TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) +{ + TCGv rhl =3D tcg_temp_new(), + rhh =3D tcg_temp_new(); + + gen_mulu2_i128(rll, rlh, rhl, rhh, rs1l, rs1h, rs2l, rs2h); + + tcg_temp_free(rhl); + tcg_temp_free(rhh); +} + =20 static bool trans_mul(DisasContext *ctx, arg_mul *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, gen_mul_i128); +} + +static void gen_mulh_i128(TCGv rhl, TCGv rhh, + TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) +{ + TCGv rll =3D tcg_temp_new(), + rlh =3D tcg_temp_new(), + rlln =3D tcg_temp_new(), + rlhn =3D tcg_temp_new(), + rhln =3D tcg_temp_new(), + rhhn =3D tcg_temp_new(), + sgnres =3D tcg_temp_new(), + tmp =3D tcg_temp_new(), + cnst_one =3D tcg_constant_tl(1), + cnst_zero =3D tcg_constant_tl(0); + + /* Extract sign of result (=3D> sgn(a) xor sgn(b)) */ + tcg_gen_setcondi_tl(TCG_COND_LT, sgnres, rs1h, 0); + tcg_gen_setcondi_tl(TCG_COND_LT, tmp, rs2h, 0); + tcg_gen_xor_tl(sgnres, sgnres, tmp); + + /* Take absolute value of operands */ + tcg_gen_sari_tl(rhl, rs1h, 63); + tcg_gen_add2_tl(rlln, rlhn, rs1l, rs1h, rhl, rhl); + tcg_gen_xor_tl(rlln, rlln, rhl); + tcg_gen_xor_tl(rlhn, rlhn, rhl); + + tcg_gen_sari_tl(rhl, rs2h, 63); + tcg_gen_add2_tl(rhln, rhhn, rs2l, rs2h, rhl, rhl); + tcg_gen_xor_tl(rhln, rhln, rhl); + tcg_gen_xor_tl(rhhn, rhhn, rhl); + + /* Unsigned multiplication */ + gen_mulu2_i128(rll, rlh, rhl, rhh, rlln, rlhn, rhln, rhhn); + + /* Negation of result (two's complement : ~res + 1) */ + tcg_gen_not_tl(rlln, rll); + tcg_gen_not_tl(rlhn, rlh); + tcg_gen_not_tl(rhln, rhl); + tcg_gen_not_tl(rhhn, rhh); + + tcg_gen_add2_tl(rlln, tmp, rlln, cnst_zero, cnst_one, cnst_zero); + tcg_gen_add2_tl(rlhn, tmp, rlhn, cnst_zero, tmp, cnst_zero); + tcg_gen_add2_tl(rhln, tmp, rhln, cnst_zero, tmp, cnst_zero); + tcg_gen_add2_tl(rhhn, tmp, rhhn, cnst_zero, tmp, cnst_zero); + + /* Move conditionally result or -result depending on result sign */ + tcg_gen_movcond_tl(TCG_COND_NE, rhl, sgnres, cnst_zero, rhln, rhl); + tcg_gen_movcond_tl(TCG_COND_NE, rhh, sgnres, cnst_zero, rhhn, rhh); + + tcg_temp_free(rll); + tcg_temp_free(rlh); + tcg_temp_free(rlln); + tcg_temp_free(rlhn); + tcg_temp_free(rhln); + tcg_temp_free(rhhn); + tcg_temp_free(sgnres); + tcg_temp_free(tmp); } =20 static void gen_mulh(TCGv ret, TCGv s1, TCGv s2) @@ -42,7 +137,59 @@ static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2) static bool trans_mulh(DisasContext *ctx, arg_mulh *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w, NULL); + return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w, + gen_mulh_i128); +} + +static void gen_mulhsu_i128(TCGv rhl, TCGv rhh, + TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) +{ + TCGv rll =3D tcg_temp_new(), + rlh =3D tcg_temp_new(), + rlln =3D tcg_temp_new(), + rlhn =3D tcg_temp_new(), + rhln =3D tcg_temp_new(), + rhhn =3D tcg_temp_new(), + sgnres =3D tcg_temp_new(), + tmp =3D tcg_temp_new(), + cnst_one =3D tcg_constant_tl(1), + cnst_zero =3D tcg_constant_tl(0); + + /* Extract sign of result (=3D> sgn(a)) */ + tcg_gen_setcondi_tl(TCG_COND_LT, sgnres, rs1h, 0); + + /* Take absolute value of rs1 */ + tcg_gen_sari_tl(rhl, rs1h, 63); + tcg_gen_add2_tl(rlln, rlhn, rs1l, rs1h, rhl, rhl); + tcg_gen_xor_tl(rlln, rlln, rhl); + tcg_gen_xor_tl(rlhn, rlhn, rhl); + + /* Unsigned multiplication */ + gen_mulu2_i128(rll, rlh, rhl, rhh, rlln, rlhn, rs2l, rs2h); + + /* Negation of result (two's complement : ~res + 1) */ + tcg_gen_not_tl(rlln, rll); + tcg_gen_not_tl(rlhn, rlh); + tcg_gen_not_tl(rhln, rhl); + tcg_gen_not_tl(rhhn, rhh); + + tcg_gen_add2_tl(rlln, tmp, rlln, cnst_zero, cnst_one, cnst_zero); + tcg_gen_add2_tl(rlhn, tmp, rlhn, cnst_zero, tmp, cnst_zero); + tcg_gen_add2_tl(rhln, tmp, rhln, cnst_zero, tmp, cnst_zero); + tcg_gen_add2_tl(rhhn, tmp, rhhn, cnst_zero, tmp, cnst_zero); + + /* Move conditionally result or -result depending on result sign */ + tcg_gen_movcond_tl(TCG_COND_NE, rhl, sgnres, cnst_zero, rhln, rhl); + tcg_gen_movcond_tl(TCG_COND_NE, rhh, sgnres, cnst_zero, rhhn, rhh); + + tcg_temp_free(rll); + tcg_temp_free(rlh); + tcg_temp_free(rlln); + tcg_temp_free(rlhn); + tcg_temp_free(rhln); + tcg_temp_free(rhhn); + tcg_temp_free(sgnres); + tcg_temp_free(tmp); } =20 static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) @@ -76,7 +223,20 @@ static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2) static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w, NU= LL); + return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w, + gen_mulhsu_i128); +} + +static void gen_mulhu_i128(TCGv rhl, TCGv rhh, + TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) +{ + TCGv rll =3D tcg_temp_new(), + rlh =3D tcg_temp_new(); + + gen_mulu2_i128(rll, rlh, rhl, rhh, rs1l, rs1h, rs2l, rs2h); + + tcg_temp_free(rll); + tcg_temp_free(rlh); } =20 static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2) @@ -91,7 +251,17 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) { REQUIRE_EXT(ctx, RVM); /* gen_mulh_w works for either sign as input. */ - return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w, NULL); + return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w, + gen_mulhu_i128); +} + +static void gen_div_i128(TCGv rdl, TCGv rdh, + TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) +{ + gen_helper_divs_i128(cpu_env, (TCGv_i64)rs1l, (TCGv_i64)rs1h, + (TCGv_i64)rs2l, (TCGv_i64)rs2h); + tcg_gen_mov_tl(rdl, cpu_hlpr[0]); + tcg_gen_mov_tl(rdh, cpu_hlpr[1]); } =20 static void gen_div(TCGv ret, TCGv source1, TCGv source2) @@ -130,7 +300,16 @@ static void gen_div(TCGv ret, TCGv source1, TCGv sourc= e2) static bool trans_div(DisasContext *ctx, arg_div *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_SIGN, gen_div, NULL); + return gen_arith(ctx, a, EXT_SIGN, gen_div, gen_div_i128); +} + +static void gen_divu_i128(TCGv rdl, TCGv rdh, + TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) +{ + gen_helper_divu_i128(cpu_env, (TCGv_i64)rs1l, (TCGv_i64)rs1h, + (TCGv_i64)rs2l, (TCGv_i64)rs2h); + tcg_gen_mov_tl(rdl, cpu_hlpr[0]); + tcg_gen_mov_tl(rdh, cpu_hlpr[1]); } =20 static void gen_divu(TCGv ret, TCGv source1, TCGv source2) @@ -158,7 +337,16 @@ static void gen_divu(TCGv ret, TCGv source1, TCGv sour= ce2) static bool trans_divu(DisasContext *ctx, arg_divu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_ZERO, gen_divu, NULL); + return gen_arith(ctx, a, EXT_ZERO, gen_divu, gen_divu_i128); +} + +static void gen_rem_i128(TCGv rdl, TCGv rdh, + TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) +{ + gen_helper_rems_i128(cpu_env, (TCGv_i64)rs1l, (TCGv_i64)rs1h, + (TCGv_i64)rs2l, (TCGv_i64)rs2h); + tcg_gen_mov_tl(rdl, cpu_hlpr[0]); + tcg_gen_mov_tl(rdh, cpu_hlpr[1]); } =20 static void gen_rem(TCGv ret, TCGv source1, TCGv source2) @@ -199,7 +387,16 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv sourc= e2) static bool trans_rem(DisasContext *ctx, arg_rem *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_SIGN, gen_rem, NULL); + return gen_arith(ctx, a, EXT_SIGN, gen_rem, gen_rem_i128); +} + +static void gen_remu_i128(TCGv rdl, TCGv rdh, + TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) +{ + gen_helper_remu_i128(cpu_env, (TCGv_i64)rs1l, (TCGv_i64)rs1h, + (TCGv_i64)rs2l, (TCGv_i64)rs2h); + tcg_gen_mov_tl(rdl, cpu_hlpr[0]); + tcg_gen_mov_tl(rdh, cpu_hlpr[1]); } =20 static void gen_remu(TCGv ret, TCGv source1, TCGv source2) @@ -227,12 +424,12 @@ static void gen_remu(TCGv ret, TCGv source1, TCGv sou= rce2) static bool trans_remu(DisasContext *ctx, arg_remu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_ZERO, gen_remu, NULL); + return gen_arith(ctx, a, EXT_ZERO, gen_remu, gen_remu_i128); } =20 static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); REQUIRE_EXT(ctx, RVM); ctx->ol =3D MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL); @@ -240,7 +437,7 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a) =20 static bool trans_divw(DisasContext *ctx, arg_divw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); REQUIRE_EXT(ctx, RVM); ctx->ol =3D MXL_RV32; return gen_arith(ctx, a, EXT_SIGN, gen_div, NULL); @@ -248,7 +445,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a) =20 static bool trans_divuw(DisasContext *ctx, arg_divuw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); REQUIRE_EXT(ctx, RVM); ctx->ol =3D MXL_RV32; return gen_arith(ctx, a, EXT_ZERO, gen_divu, NULL); @@ -256,7 +453,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a) =20 static bool trans_remw(DisasContext *ctx, arg_remw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); REQUIRE_EXT(ctx, RVM); ctx->ol =3D MXL_RV32; return gen_arith(ctx, a, EXT_SIGN, gen_rem, NULL); @@ -264,8 +461,48 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a) =20 static bool trans_remuw(DisasContext *ctx, arg_remuw *a) { - REQUIRE_64BIT(ctx); + REQUIRE_64_OR_128BIT(ctx); REQUIRE_EXT(ctx, RVM); ctx->ol =3D MXL_RV32; return gen_arith(ctx, a, EXT_ZERO, gen_remu, NULL); } + +static bool trans_muld(DisasContext *ctx, arg_muld *a) +{ + REQUIRE_128BIT(ctx); + REQUIRE_EXT(ctx, RVM); + ctx->ol =3D MXL_RV64; + return gen_arith(ctx, a, EXT_SIGN, tcg_gen_mul_tl, NULL); +} + +static bool trans_divd(DisasContext *ctx, arg_divd *a) +{ + REQUIRE_128BIT(ctx); + REQUIRE_EXT(ctx, RVM); + ctx->ol =3D MXL_RV64; + return gen_arith(ctx, a, EXT_SIGN, gen_div, NULL); +} + +static bool trans_divud(DisasContext *ctx, arg_divud *a) +{ + REQUIRE_128BIT(ctx); + REQUIRE_EXT(ctx, RVM); + ctx->ol =3D MXL_RV64; + return gen_arith(ctx, a, EXT_ZERO, gen_divu, NULL); +} + +static bool trans_remd(DisasContext *ctx, arg_remd *a) +{ + REQUIRE_128BIT(ctx); + REQUIRE_EXT(ctx, RVM); + ctx->ol =3D MXL_RV64; + return gen_arith(ctx, a, EXT_SIGN, gen_rem, NULL); +} + +static bool trans_remud(DisasContext *ctx, arg_remud *a) +{ + REQUIRE_128BIT(ctx); + REQUIRE_EXT(ctx, RVM); + ctx->ol =3D MXL_RV64; + return gen_arith(ctx, a, EXT_ZERO, gen_remu, NULL); +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index d5e0bc93ea..a32158da93 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -18,6 +18,7 @@ riscv_ss.add(files( 'vector_helper.c', 'bitmanip_helper.c', 'translate.c', + 'm128_helper.c' )) =20 riscv_softmmu_ss =3D ss.source_set() --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637833895230.55623172490402; Tue, 19 Oct 2021 03:03:53 -0700 (PDT) Received: from localhost ([::1]:54348 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mclyK-0005EI-TN for importer@patchew.org; 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Tue, 19 Oct 2021 11:48:34 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 16/21] target/riscv: adding high part of some csrs Date: Tue, 19 Oct 2021 11:48:07 +0200 Message-Id: <20211019094812.614056-17-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637834812100001 Adding the high part of a minimal set of csr. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8b96ccb37a..27ec4fec63 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -192,6 +192,13 @@ struct CPURISCVState { target_ulong hgatp; uint64_t htimedelta; =20 + /* Upper 64-bits of 128-bit CSRs */ + uint64_t mtvech; + uint64_t mscratchh; + uint64_t mepch; + uint64_t satph; + uint64_t mstatush; + /* Virtual CSRs */ /* * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637744500257.54480041825695; Tue, 19 Oct 2021 03:02:24 -0700 (PDT) Received: from localhost ([::1]:48884 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mclwt-0001eG-9T for importer@patchew.org; Tue, 19 Oct 2021 06:02:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58882) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljx-0001Jz-NB; Tue, 19 Oct 2021 05:49:01 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:54980) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljs-0006d5-8G; Tue, 19 Oct 2021 05:49:01 -0400 Received: from mailhost.u-ga.fr (mailhost1.u-ga.fr [152.77.1.10]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id ACD9942088; Tue, 19 Oct 2021 11:48:34 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id 936D8601D5; Tue, 19 Oct 2021 11:48:34 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id 6ACC314005A; Tue, 19 Oct 2021 11:48:34 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns Date: Tue, 19 Oct 2021 11:48:08 +0200 Message-Id: <20211019094812.614056-18-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637750103100001 Given the side effects they have, the csr instructions are realized as helpers. We extend this existing infrastructure for 128-bit sized csr. We have a slight issue with returning 128-bit values: we use the globals we added to support div/rem insns to that end. Theses helpers all call a unique function that is currently a stub. The trans_csrxx functions supporting 128-bit are yet to be implemented. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 4 ++++ target/riscv/helper.h | 3 +++ target/riscv/csr.c | 7 +++++++ target/riscv/op_helper.c | 44 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 27ec4fec63..eb4f63fcbf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -470,6 +470,10 @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVStat= e *env, int csrno, target_ulong new_value, target_ulong write_mask); =20 +RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, + Int128 *ret_value, + Int128 new_value, Int128 write_mask); + typedef struct { const char *name; riscv_csr_predicate_fn predicate; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 67f5d23692..e27bdb9075 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -66,6 +66,9 @@ DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_2(csrr, tl, env, int) DEF_HELPER_3(csrw, void, env, int, tl) DEF_HELPER_4(csrrw, tl, env, int, tl, tl) +DEF_HELPER_2(csrr_i128, void, env, int) +DEF_HELPER_4(csrw_i128, void, env, int, tl, tl) +DEF_HELPER_6(csrrw_i128, void, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_2(sret, tl, env, tl) DEF_HELPER_2(mret, tl, env, tl) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 69e4d65fcd..b802ee0dbc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1516,6 +1516,13 @@ RISCVException riscv_csrrw(CPURISCVState *env, int c= srno, return RISCV_EXCP_NONE; } =20 +RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, + Int128 *ret_value, + Int128 new_value, Int128 write_mask) +{ + return RISCV_EXCP_ILLEGAL_INST; +} + /* * Debugger support. If not in user mode, set env->debugger before the * riscv_csrrw call and clear it after the call. diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index ee7c24efe7..753eb35000 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -69,6 +69,50 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, return val; } =20 +void helper_csrr_i128(CPURISCVState *env, int csr) +{ + Int128 rv =3D int128_zero(); + RISCVException ret =3D riscv_csrrw_i128(env, csr, &rv, + int128_zero(), + int128_zero()); + + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); + } + + env->hlpr[0] =3D int128_getlo(rv); + env->hlpr[1] =3D int128_gethi(rv); +} + +void helper_csrw_i128(CPURISCVState *env, int csr, + target_ulong srcl, target_ulong srch) +{ + RISCVException ret =3D riscv_csrrw_i128(env, csr, NULL, + int128_make128(srcl, srch), + UINT128_MAX); + + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); + } +} + +void helper_csrrw_i128(CPURISCVState *env, int csr, + target_ulong srcl, target_ulong srch, + target_ulong maskl, target_ulong maskh) +{ + Int128 rv =3D int128_zero(); + RISCVException ret =3D riscv_csrrw_i128(env, csr, &rv, + int128_make128(srcl, srch), + int128_make128(maskl, maskh)); + + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); + } + + env->hlpr[0] =3D int128_getlo(rv); + env->hlpr[1] =3D int128_gethi(rv); +} + #ifndef CONFIG_USER_ONLY =20 target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163463813917796.31958530486725; Tue, 19 Oct 2021 03:08:59 -0700 (PDT) Received: from localhost ([::1]:38788 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcm3G-0005K5-2I for importer@patchew.org; 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Tue, 19 Oct 2021 11:48:34 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support Date: Tue, 19 Oct 2021 11:48:09 +0200 Message-Id: <20211019094812.614056-19-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634638140863100001 As opposed to the gen_arith and gen_shift generation helpers, the csr insns do not have a common prototype, so the choice to generate 32/64 or 128-bit helper calls is done in the trans_csrxx functions. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 201 ++++++++++++++++++------ 1 file changed, 156 insertions(+), 45 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 6497338842..e08fa482c4 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -962,20 +962,74 @@ static bool do_csrrw(DisasContext *ctx, int rd, int r= c, TCGv src, TCGv mask) return do_csr_post(ctx); } =20 +static bool do_csrr_i128(DisasContext *ctx, int rd, int rc) +{ + TCGv_i32 csr =3D tcg_constant_i32(rc); + + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_csrr_i128(cpu_env, csr); + gen_set_gpr(ctx, rd, cpu_hlpr[0]); + gen_set_gprh(ctx, rd, cpu_hlpr[1]); + return do_csr_post(ctx); +} + +static bool do_csrw_i128(DisasContext *ctx, int rc, TCGv srcl, TCGv srch) +{ + TCGv_i32 csr =3D tcg_constant_i32(rc); + + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_csrw_i128(cpu_env, csr, srcl, srch); + return do_csr_post(ctx); +} + +static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc, + TCGv srcl, TCGv srch, TCGv maskl, TCGv maskh) +{ + TCGv_i32 csr =3D tcg_constant_i32(rc); + + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_csrrw_i128(cpu_env, csr, srcl, srch, maskl, maskh); + gen_set_gpr(ctx, rd, cpu_hlpr[0]); + gen_set_gprh(ctx, rd, cpu_hlpr[1]); + return do_csr_post(ctx); +} + static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a) { - TCGv src =3D get_gpr(ctx, a->rs1, EXT_NONE); - - /* - * If rd =3D=3D 0, the insn shall not read the csr, nor cause any of t= he - * side effects that might occur on a csr read. - */ - if (a->rd =3D=3D 0) { - return do_csrw(ctx, a->csr, src); + if (get_xl(ctx) < MXL_RV128) { + TCGv src =3D get_gpr(ctx, a->rs1, EXT_NONE); + + /* + * If rd =3D=3D 0, the insn shall not read the csr, nor cause any = of the + * side effects that might occur on a csr read. + */ + if (a->rd =3D=3D 0) { + return do_csrw(ctx, a->csr, src); + } + + TCGv mask =3D tcg_constant_tl(-1); + return do_csrrw(ctx, a->rd, a->csr, src, mask); + } else { + TCGv srcl =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv srch =3D get_gprh(ctx, a->rs1); + + /* + * If rd =3D=3D 0, the insn shall not read the csr, nor cause any = of the + * side effects that might occur on a csr read. + */ + if (a->rd =3D=3D 0) { + return do_csrw_i128(ctx, a->csr, srcl, srch); + } + + TCGv mask =3D tcg_constant_tl(-1); + return do_csrrw_i128(ctx, a->rd, a->csr, srcl, srch, mask, mask); } - - TCGv mask =3D tcg_constant_tl(-1); - return do_csrrw(ctx, a->rd, a->csr, src, mask); } =20 static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a) @@ -987,13 +1041,24 @@ static bool trans_csrrs(DisasContext *ctx, arg_csrrs= *a) * a zero value, the instruction will still attempt to write the * unmodified value back to the csr and will cause side effects. */ - if (a->rs1 =3D=3D 0) { - return do_csrr(ctx, a->rd, a->csr); + if (get_xl(ctx) < MXL_RV128) { + if (a->rs1 =3D=3D 0) { + return do_csrr(ctx, a->rd, a->csr); + } + + TCGv ones =3D tcg_constant_tl(-1); + TCGv mask =3D get_gpr(ctx, a->rs1, EXT_ZERO); + return do_csrrw(ctx, a->rd, a->csr, ones, mask); + } else { + if (a->rs1 =3D=3D 0) { + return do_csrr_i128(ctx, a->rd, a->csr); + } + + TCGv ones =3D tcg_constant_tl(-1); + TCGv maskl =3D get_gpr(ctx, a->rs1, EXT_ZERO); + TCGv maskh =3D get_gprh(ctx, a->rs1); + return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, maskl, maskh); } - - TCGv ones =3D tcg_constant_tl(-1); - TCGv mask =3D get_gpr(ctx, a->rs1, EXT_ZERO); - return do_csrrw(ctx, a->rd, a->csr, ones, mask); } =20 static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a) @@ -1005,28 +1070,54 @@ static bool trans_csrrc(DisasContext *ctx, arg_csrr= c *a) * a zero value, the instruction will still attempt to write the * unmodified value back to the csr and will cause side effects. */ - if (a->rs1 =3D=3D 0) { - return do_csrr(ctx, a->rd, a->csr); + if (get_xl(ctx) < MXL_RV128) { + if (a->rs1 =3D=3D 0) { + return do_csrr(ctx, a->rd, a->csr); + } + + TCGv mask =3D get_gpr(ctx, a->rs1, EXT_ZERO); + return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask); + } else { + if (a->rs1 =3D=3D 0) { + return do_csrr_i128(ctx, a->rd, a->csr); + } + + TCGv maskl =3D get_gpr(ctx, a->rs1, EXT_ZERO); + TCGv maskh =3D get_gprh(ctx, a->rs1); + return do_csrrw_i128(ctx, a->rd, a->csr, + ctx->zero, ctx->zero, maskl, maskh); } - - TCGv mask =3D get_gpr(ctx, a->rs1, EXT_ZERO); - return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask); } =20 static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a) { - TCGv src =3D tcg_constant_tl(a->rs1); - - /* - * If rd =3D=3D 0, the insn shall not read the csr, nor cause any of t= he - * side effects that might occur on a csr read. - */ - if (a->rd =3D=3D 0) { - return do_csrw(ctx, a->csr, src); + if (get_xl(ctx) < MXL_RV128) { + TCGv src =3D tcg_constant_tl(a->rs1); + + /* + * If rd =3D=3D 0, the insn shall not read the csr, nor cause any = of the + * side effects that might occur on a csr read. + */ + if (a->rd =3D=3D 0) { + return do_csrw(ctx, a->csr, src); + } + + TCGv mask =3D tcg_constant_tl(-1); + return do_csrrw(ctx, a->rd, a->csr, src, mask); + } else { + TCGv src =3D tcg_constant_tl(a->rs1); + + /* + * If rd =3D=3D 0, the insn shall not read the csr, nor cause any = of the + * side effects that might occur on a csr read. + */ + if (a->rd =3D=3D 0) { + return do_csrw_i128(ctx, a->csr, src, ctx->zero); + } + + TCGv mask =3D tcg_constant_tl(-1); + return do_csrrw_i128(ctx, a->rd, a->csr, src, ctx->zero, mask, mas= k); } - - TCGv mask =3D tcg_constant_tl(-1); - return do_csrrw(ctx, a->rd, a->csr, src, mask); } =20 static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a) @@ -1038,16 +1129,26 @@ static bool trans_csrrsi(DisasContext *ctx, arg_csr= rsi *a) * a zero value, the instruction will still attempt to write the * unmodified value back to the csr and will cause side effects. */ - if (a->rs1 =3D=3D 0) { - return do_csrr(ctx, a->rd, a->csr); + if (get_xl(ctx) < MXL_RV128) { + if (a->rs1 =3D=3D 0) { + return do_csrr(ctx, a->rd, a->csr); + } + + TCGv ones =3D tcg_constant_tl(-1); + TCGv mask =3D tcg_constant_tl(a->rs1); + return do_csrrw(ctx, a->rd, a->csr, ones, mask); + } else { + if (a->rs1 =3D=3D 0) { + return do_csrr_i128(ctx, a->rd, a->csr); + } + + TCGv ones =3D tcg_constant_tl(-1); + TCGv mask =3D tcg_constant_tl(a->rs1); + return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, mask, ctx->ze= ro); } - - TCGv ones =3D tcg_constant_tl(-1); - TCGv mask =3D tcg_constant_tl(a->rs1); - return do_csrrw(ctx, a->rd, a->csr, ones, mask); } =20 -static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a) +static bool trans_csrrci(DisasContext *ctx, arg_csrrci * a) { /* * If rs1 =3D=3D 0, the insn shall not write to the csr at all, nor @@ -1056,10 +1157,20 @@ static bool trans_csrrci(DisasContext *ctx, arg_csr= rci *a) * a zero value, the instruction will still attempt to write the * unmodified value back to the csr and will cause side effects. */ - if (a->rs1 =3D=3D 0) { - return do_csrr(ctx, a->rd, a->csr); + if (get_xl(ctx) < MXL_RV128) { + if (a->rs1 =3D=3D 0) { + return do_csrr(ctx, a->rd, a->csr); + } + + TCGv mask =3D tcg_constant_tl(a->rs1); + return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask); + } else { + if (a->rs1 =3D=3D 0) { + return do_csrr_i128(ctx, a->rd, a->csr); + } + + TCGv mask =3D tcg_constant_tl(a->rs1); + return do_csrrw_i128(ctx, a->rd, a->csr, + ctx->zero, ctx->zero, mask, ctx->zero); } - - TCGv mask =3D tcg_constant_tl(a->rs1); - return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask); } --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634638264158910.9578894779366; Tue, 19 Oct 2021 03:11:04 -0700 (PDT) Received: from localhost ([::1]:42648 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcm5H-0007sP-3g for importer@patchew.org; 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Tue, 19 Oct 2021 11:48:34 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 19/21] target/riscv: actual functions to realize crs 128-bit insns Date: Tue, 19 Oct 2021 11:48:10 +0200 Message-Id: <20211019094812.614056-20-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634638265060100001 The csrs are accessed through function pointers: we set-up the table for the 128-bit accesses, make the stub a function that does what it should, and implement basic accesses on read-only csrs. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 16 +++++ target/riscv/csr.c | 152 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 165 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eb4f63fcbf..253e87cd92 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,6 +474,15 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, in= t csrno, Int128 *ret_value, Int128 new_value, Int128 write_mask); =20 +typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csr= no, + Int128 *ret_value); +typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int cs= rno, + Int128 new_value); +typedef RISCVException (*riscv_csr_op128_fn)(CPURISCVState *env, int csrno, + Int128 *ret_value, + Int128 new_value, + Int128 write_mask); + typedef struct { const char *name; riscv_csr_predicate_fn predicate; @@ -482,6 +491,12 @@ typedef struct { riscv_csr_op_fn op; } riscv_csr_operations; =20 +typedef struct { + riscv_csr_read128_fn read128; + riscv_csr_write128_fn write128; + riscv_csr_op128_fn op128; +} riscv_csr_operations128; + /* CSR function table constants */ enum { CSR_TABLE_SIZE =3D 0x1000 @@ -489,6 +504,7 @@ enum { =20 /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; +extern riscv_csr_operations128 csr_ops_128[CSR_TABLE_SIZE]; =20 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b802ee0dbc..3aac19e277 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -462,6 +462,13 @@ static const char valid_vm_1_10_64[16] =3D { }; =20 /* Machine Information Registers */ +static RISCVException read_zero_i128(CPURISCVState *env, int csrno, + Int128 *val) +{ + *val =3D int128_zero(); + return RISCV_EXCP_NONE; +} + static RISCVException read_zero(CPURISCVState *env, int csrno, target_ulong *val) { @@ -469,6 +476,13 @@ static RISCVException read_zero(CPURISCVState *env, in= t csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_mhartid_i128(CPURISCVState *env, int csrno, + Int128 *val) +{ + *val =3D int128_make64(env->mhartid); + return RISCV_EXCP_NONE; +} + static RISCVException read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) { @@ -569,6 +583,13 @@ static RISCVException write_mstatush(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_misa_i128(CPURISCVState *env, int csrno, + Int128 *val) +{ + *val =3D int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); + return RISCV_EXCP_NONE; +} + static RISCVException read_misa(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1516,11 +1537,118 @@ RISCVException riscv_csrrw(CPURISCVState *env, int= csrno, return RISCV_EXCP_NONE; } =20 +static inline RISCVException riscv_csrrw_check_i128(CPURISCVState *env, + int csrno, + Int128 write_mask, + RISCVCPU *cpu) +{ + /* check privileges and return -1 if check fails */ +#if !defined(CONFIG_USER_ONLY) + int effective_priv =3D env->priv; + int read_only =3D get_field(csrno, 0xc00) =3D=3D 3; + + if (riscv_has_ext(env, RVH) && + env->priv =3D=3D PRV_S && + !riscv_cpu_virt_enabled(env)) { + /* + * We are in S mode without virtualisation, therefore we are in HS= Mode. + * Add 1 to the effective privledge level to allow us to access the + * Hypervisor CSRs. + */ + effective_priv++; + } + + if ((int128_nz(write_mask) && read_only) || + (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { + return RISCV_EXCP_ILLEGAL_INST; + } +#endif + + /* ensure the CSR extension is enabled. */ + if (!cpu->cfg.ext_icsr) { + return RISCV_EXCP_ILLEGAL_INST; + } + + /* check predicate */ + if (!csr_ops[csrno].predicate) { + return RISCV_EXCP_ILLEGAL_INST; + } + RISCVException ret =3D csr_ops[csrno].predicate(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + return RISCV_EXCP_NONE; +} + RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, - Int128 *ret_value, - Int128 new_value, Int128 write_mask) + Int128 *ret_value, + Int128 new_value, Int128 write_mask) { - return RISCV_EXCP_ILLEGAL_INST; + RISCVException ret; + Int128 old_value; + + RISCVCPU *cpu =3D env_archcpu(env); + + if (!csr_ops_128[csrno].read128 && !csr_ops_128[csrno].op128) { + /* + * FIXME: Fall back to 64-bit version for now, if the 128-bit + * alternative isn't defined. + * Note, some CSRs don't extend to MXLEN, for those, + * this fallback is correctly handling the read/write. + */ + target_ulong ret_64; + ret =3D riscv_csrrw(env, csrno, &ret_64, + int128_getlo(new_value), + int128_getlo(write_mask)); + + if (ret_value) { + *ret_value =3D int128_make64(ret_64); + } + + return ret; + } + + RISCVException check_status =3D + riscv_csrrw_check_i128(env, csrno, write_mask, cpu); + if (check_status !=3D RISCV_EXCP_NONE) { + return check_status; + } + + /* execute combined read/write operation if it exists */ + if (csr_ops_128[csrno].op128) { + return csr_ops_128[csrno].op128(env, csrno, ret_value, + new_value, write_mask); + } + + /* if no accessor exists then return failure */ + if (!csr_ops_128[csrno].read128) { + return RISCV_EXCP_ILLEGAL_INST; + } + /* read old value */ + ret =3D csr_ops_128[csrno].read128(env, csrno, &old_value); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + /* write value if writable and write mask set, otherwise drop writes */ + if (int128_nz(write_mask)) { + new_value =3D int128_or(int128_and(old_value, int128_not(write_mas= k)), + int128_and(new_value, write_mask)); + if (csr_ops_128[csrno].write128) { + ret =3D csr_ops_128[csrno].write128(env, csrno, new_value); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + } + } + + /* return old value */ + if (ret_value) { + *ret_value =3D old_value; + } + + return RISCV_EXCP_NONE; } =20 /* @@ -1544,6 +1672,24 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env,= int csrno, } =20 /* Control and Status Register function table */ +riscv_csr_operations128 csr_ops_128[CSR_TABLE_SIZE] =3D { +#if !defined(CONFIG_USER_ONLY) + [CSR_MVENDORID] =3D { read_zero_i128 }, + [CSR_MARCHID] =3D { read_zero_i128 }, + [CSR_MIMPID] =3D { read_zero_i128 }, + [CSR_MHARTID] =3D { read_mhartid_i128 }, + + [CSR_MSTATUS] =3D { read_zero_i128 }, + [CSR_MISA] =3D { read_misa_i128 }, + [CSR_MTVEC] =3D { read_zero_i128 }, + + [CSR_MSCRATCH] =3D { read_zero_i128 }, + [CSR_MEPC] =3D { read_zero_i128 }, + + [CSR_SATP] =3D { read_zero_i128 }, +#endif +}; + riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* User Floating-Point CSRs */ [CSR_FFLAGS] =3D { "fflags", fs, read_fflags, write_fflags }, --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634637990570380.4630705729594; Tue, 19 Oct 2021 03:06:30 -0700 (PDT) Received: from localhost ([::1]:58686 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcm0r-00089g-Gv for importer@patchew.org; Tue, 19 Oct 2021 06:06:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58954) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mclk0-0001VQ-HQ; Tue, 19 Oct 2021 05:49:04 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:55076) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljx-0006jE-Pq; Tue, 19 Oct 2021 05:49:04 -0400 Received: from mailhost.u-ga.fr (mailhost1.u-ga.fr [152.77.1.10]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id 3B0A841F6E; Tue, 19 Oct 2021 11:48:40 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id 1B0A0601D6; Tue, 19 Oct 2021 11:48:40 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id EC6F814005A; Tue, 19 Oct 2021 11:48:34 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 20/21] target/riscv: adding 128-bit access functions for some csrs Date: Tue, 19 Oct 2021 11:48:11 +0200 Message-Id: <20211019094812.614056-21-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634637992616100001 Access to mstatus, mtvec, mscratch and mepc is implemented. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 111 ++++++++++++++++++++++++++++++++++++++-- 2 files changed, 108 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index e248c6bf6d..e4750afc78 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -360,6 +360,7 @@ =20 #define MSTATUS32_SD 0x80000000 #define MSTATUS64_SD 0x8000000000000000ULL +#define MSTATUSH128_SD 0x8000000000000000ULL =20 #define MISA32_MXL 0xC0000000 #define MISA64_MXL 0xC000000000000000ULL diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3aac19e277..877cd2d63a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -509,6 +509,61 @@ static uint64_t add_status_sd(RISCVMXL xl, uint64_t st= atus) return status; } =20 +static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, + Int128 *val) +{ + *val =3D int128_make128(env->mstatus, env->mstatush); + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstatus_i128(CPURISCVState *env, int csrno, + Int128 val) +{ + Int128 mstatus =3D int128_make128(env->mstatus, env->mstatush); + Int128 mask =3D int128_zero(); + int dirty; + + /* flush tlb on mstatus fields that affect VM */ + if (int128_getlo(int128_xor(mstatus, val)) + & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | + MSTATUS_MPRV | MSTATUS_SUM)) { + tlb_flush(env_cpu(env)); + } + mask =3D int128_make64(MSTATUS_SIE | MSTATUS_SPIE | + MSTATUS_MIE | MSTATUS_MPIE | + MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS= _SUM | + MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS= _TSR | + MSTATUS_TW); + + if (!riscv_cpu_is_32bit(env)) { + /* + * RV32: MPV and GVA are not in mstatus. The current plan is to + * add them to mstatush. For now, we just don't support it. + */ + mask =3D int128_or(mask, int128_make64(MSTATUS_MPV | MSTATUS_GVA)); + } + + mstatus =3D int128_or(int128_and(mstatus, int128_not(mask)), + int128_and(val, mask)); + + dirty =3D ((int128_getlo(mstatus) & MSTATUS_FS) =3D=3D MSTATUS_FS) | + ((int128_getlo(mstatus) & MSTATUS_XS) =3D=3D MSTATUS_XS); + if (dirty) { + if (riscv_cpu_is_32bit(env)) { + mstatus =3D int128_make64(int128_getlo(mstatus) | MSTATUS32_SD= ); + } else if (riscv_cpu_is_64bit(env)) { + mstatus =3D int128_make64(int128_getlo(mstatus) | MSTATUS64_SD= ); + } else { + mstatus =3D int128_or(mstatus, int128_make128(0, MSTATUSH128_S= D)); + } + } + + env->mstatus =3D int128_getlo(mstatus); + env->mstatush =3D int128_gethi(mstatus); + + return RISCV_EXCP_NONE; +} + static RISCVException read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) { @@ -713,6 +768,26 @@ static RISCVException write_mie(CPURISCVState *env, in= t csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_mtvec_i128(CPURISCVState *env, int csrno, + Int128 *val) +{ + *val =3D int128_make128(env->mtvec, env->mtvech); + return RISCV_EXCP_NONE; +} + +static RISCVException write_mtvec_i128(CPURISCVState *env, int csrno, + Int128 val) +{ + /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D reserv= ed */ + if ((int128_getlo(val) & 3) < 2) { + env->mtvec =3D int128_getlo(val); + env->mtvech =3D int128_gethi(val); + } else { + qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n= "); + } + return RISCV_EXCP_NONE; +} + static RISCVException read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) { @@ -747,6 +822,19 @@ static RISCVException write_mcounteren(CPURISCVState *= env, int csrno, } =20 /* Machine Trap Handling */ +static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno, + Int128 *val) { + *val =3D int128_make128(env->mscratch, env->mscratchh); + return RISCV_EXCP_NONE; +} + +static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno, + Int128 val) { + env->mscratch =3D int128_getlo(val); + env->mscratchh =3D int128_gethi(val); + return RISCV_EXCP_NONE; +} + static RISCVException read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) { @@ -761,6 +849,21 @@ static RISCVException write_mscratch(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_mepc_i128(CPURISCVState *env, int csrno, + Int128 *val) +{ + *val =3D int128_make128(env->mepc, env->mepch); + return RISCV_EXCP_NONE; +} + +static RISCVException write_mepc_i128(CPURISCVState *env, int csrno, + Int128 val) +{ + env->mepc =3D int128_getlo(val); + env->mepch =3D int128_gethi(val); + return RISCV_EXCP_NONE; +} + static RISCVException read_mepc(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1679,12 +1782,12 @@ riscv_csr_operations128 csr_ops_128[CSR_TABLE_SIZE]= =3D { [CSR_MIMPID] =3D { read_zero_i128 }, [CSR_MHARTID] =3D { read_mhartid_i128 }, =20 - [CSR_MSTATUS] =3D { read_zero_i128 }, + [CSR_MSTATUS] =3D { read_mstatus_i128, write_mstatus_i128 }, [CSR_MISA] =3D { read_misa_i128 }, - [CSR_MTVEC] =3D { read_zero_i128 }, + [CSR_MTVEC] =3D { read_mtvec_i128, write_mtvec_i128 }, =20 - [CSR_MSCRATCH] =3D { read_zero_i128 }, - [CSR_MEPC] =3D { read_zero_i128 }, + [CSR_MSCRATCH] =3D { read_mscratch_i128, write_mscratch_i128 }, + [CSR_MEPC] =3D { read_mepc_i128, write_mepc_i128 }, =20 [CSR_SATP] =3D { read_zero_i128 }, #endif --=20 2.33.0 From nobody Wed May 22 02:42:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=univ-grenoble-alpes.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163463809115078.91709341818023; Tue, 19 Oct 2021 03:08:11 -0700 (PDT) Received: from localhost ([::1]:36082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcm2U-0003Wl-0E for importer@patchew.org; Tue, 19 Oct 2021 06:08:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mclk0-0001Wz-Um; Tue, 19 Oct 2021 05:49:04 -0400 Received: from zm-mta-out-3.u-ga.fr ([152.77.200.56]:55098) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcljx-0006jI-Sp; Tue, 19 Oct 2021 05:49:04 -0400 Received: from mailhost.u-ga.fr (mailhost1.u-ga.fr [152.77.1.10]) by zm-mta-out-3.u-ga.fr (Postfix) with ESMTP id 5DBCA420B5; Tue, 19 Oct 2021 11:48:40 +0200 (CEST) Received: from smtps.univ-grenoble-alpes.fr (smtps2.u-ga.fr [152.77.18.2]) by mailhost.u-ga.fr (Postfix) with ESMTP id 4455D601D6; Tue, 19 Oct 2021 11:48:40 +0200 (CEST) Received: from palmier.u-ga.fr (palmier.tima.u-ga.fr [147.171.132.208]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: petrotf@univ-grenoble-alpes.fr) by smtps.univ-grenoble-alpes.fr (Postfix) with ESMTPSA id 1DF9A14005D; Tue, 19 Oct 2021 11:48:40 +0200 (CEST) From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 21/21] target/riscv: support for 128-bit satp Date: Tue, 19 Oct 2021 11:48:12 +0200 Message-Id: <20211019094812.614056-22-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Greylist: Whitelist-UGA SMTP Authentifie (petrotf@univ-grenoble-alpes.fr) via submission-587 ACL (41) X-Greylist: Whitelist-UGA MAILHOST (SMTP non authentifie) depuis 152.77.18.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.77.200.56; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=zm-mta-out-3.u-ga.fr X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634638091592100003 Support for a 128-bit satp. This is a bit more involved than necessary because we took the opportunity to increase the page size to 16kB, and change the page table geometry, which makes the page walk a bit more parametrizable (variables instead of defines). Note that is anyway a necessary step for the merging of the 32-bit and 64-bit riscv versions in a single executable. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Co-authored-by: Fabien Portas --- target/riscv/cpu-param.h | 9 +++- target/riscv/cpu_bits.h | 10 ++++ target/riscv/cpu_helper.c | 54 ++++++++++++++------ target/riscv/csr.c | 105 ++++++++++++++++++++++++++++++++------ 4 files changed, 144 insertions(+), 34 deletions(-) diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index c10459b56f..78f0916403 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -19,10 +19,15 @@ #else /* 64-bit target, since QEMU isn't built to have TARGET_LONG_BITS over 64 = */ # define TARGET_LONG_BITS 64 -# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ -# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ +# define TARGET_PHYS_ADDR_SPACE_BITS 64 /* 54-bit PPN */ +# define TARGET_VIRT_ADDR_SPACE_BITS 44 /* sv44 */ #endif + +#if defined(TARGET_RISCV32) || defined(TARGET_RISCV64) #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ +#else +#define TARGET_PAGE_BITS 14 /* 16 KiB pages for RV128 */ +#endif /* * The current MMU Modes are: * - U mode 0b000 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index e4750afc78..b04b103e31 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -430,6 +430,11 @@ typedef enum { #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL =20 +/* RV128 satp CSR field masks (H/L for high/low dword) */ +#define SATP128_HMODE 0xFF00000000000000ULL +#define SATP128_HASID 0x00FFFFFFFF000000ULL +#define SATP128_LPPN 0x0003FFFFFFFFFFFFULL + /* VM modes (mstatus.vm) privileged ISA 1.9.1 */ #define VM_1_09_MBARE 0 #define VM_1_09_MBB 1 @@ -445,6 +450,9 @@ typedef enum { #define VM_1_10_SV48 9 #define VM_1_10_SV57 10 #define VM_1_10_SV64 11 +#define VM_1_10_SV44 12 +#define VM_1_10_SV54 13 + =20 /* Page table entry (PTE) fields */ #define PTE_V 0x001 /* Valid */ @@ -462,6 +470,8 @@ typedef enum { =20 /* Leaf page shift amount */ #define PGSHIFT 12 +/* For now, pages in RV128 are 16 KiB. */ +#define PGSHIFT128 14 =20 /* Default Reset Vector adress */ #define DEFAULT_RSTVEC 0x1000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0d1132f39d..d4b1e328ae 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -469,7 +469,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, *prot =3D 0; =20 hwaddr base; - int levels, ptidxbits, ptesize, vm, sum, mxr, widened; + int levels, ptidxbits, ptesize, vm, sum, mxr, widened, pgshift; =20 if (first_stage =3D=3D true) { mxr =3D get_field(env->mstatus, MSTATUS_MXR); @@ -482,17 +482,25 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { base =3D (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSH= IFT; vm =3D get_field(env->vsatp, SATP32_MODE); - } else { + } else if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { base =3D (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSH= IFT; vm =3D get_field(env->vsatp, SATP64_MODE); + } else { + /* TODO : Hypervisor extension not supported yet in RV128.= */ + g_assert_not_reached(); } } else { if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHI= FT; vm =3D get_field(env->satp, SATP32_MODE); - } else { + } else if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { base =3D (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHI= FT; vm =3D get_field(env->satp, SATP64_MODE); + } else if (riscv_cpu_mxl(env) =3D=3D MXL_RV128) { + base =3D (hwaddr)get_field(env->satp, SATP128_LPPN) << PGS= HIFT128; + vm =3D get_field(env->satph, SATP128_HMODE); + } else { + g_assert_not_reached(); } } widened =3D 0; @@ -500,9 +508,15 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { base =3D (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; vm =3D get_field(env->hgatp, SATP32_MODE); - } else { + } else if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { base =3D (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; vm =3D get_field(env->hgatp, SATP64_MODE); + } else { + /* + * TODO : Hypervisor extension not supported yet in RV128, + * so there shouldn't be any two-stage address lookups. + */ + g_assert_not_reached(); } widened =3D 2; } @@ -510,13 +524,17 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, sum =3D get_field(env->mstatus, MSTATUS_SUM) || use_background || is_d= ebug; switch (vm) { case VM_1_10_SV32: - levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; + levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; pgshift =3D 12; break; case VM_1_10_SV39: - levels =3D 3; ptidxbits =3D 9; ptesize =3D 8; break; + levels =3D 3; ptidxbits =3D 9; ptesize =3D 8; pgshift =3D 12; break; case VM_1_10_SV48: - levels =3D 4; ptidxbits =3D 9; ptesize =3D 8; break; + levels =3D 4; ptidxbits =3D 9; ptesize =3D 8; pgshift =3D 12; break; case VM_1_10_SV57: - levels =3D 5; ptidxbits =3D 9; ptesize =3D 8; break; + levels =3D 5; ptidxbits =3D 9; ptesize =3D 8; pgshift =3D 12; break; + case VM_1_10_SV44: + levels =3D 3; ptidxbits =3D 10; ptesize =3D 16; pgshift =3D 14; brea= k; + case VM_1_10_SV54: + levels =3D 4; ptidxbits =3D 10; ptesize =3D 16; pgshift =3D 14; bre= ak; case VM_1_10_MBARE: *physical =3D addr; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -526,7 +544,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } =20 CPUState *cs =3D env_cpu(env); - int va_bits =3D PGSHIFT + levels * ptidxbits + widened; + int va_bits =3D pgshift + levels * ptidxbits + widened; target_ulong mask, masked_msbs; =20 if (TARGET_LONG_BITS > (va_bits - 1)) { @@ -541,6 +559,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } =20 int ptshift =3D (levels - 1) * ptidxbits; + uint64_t pgoff_mask =3D (1ULL << pgshift) - 1; int i; =20 #if !TCG_OVERSIZED_GUEST @@ -549,10 +568,10 @@ restart: for (i =3D 0; i < levels; i++, ptshift -=3D ptidxbits) { target_ulong idx; if (i =3D=3D 0) { - idx =3D (addr >> (PGSHIFT + ptshift)) & + idx =3D (addr >> (pgshift + ptshift)) & ((1 << (ptidxbits + widened)) - 1); } else { - idx =3D (addr >> (PGSHIFT + ptshift)) & + idx =3D (addr >> (pgshift + ptshift)) & ((1 << ptidxbits) - 1); } =20 @@ -560,6 +579,7 @@ restart: hwaddr pte_addr; =20 if (two_stage && first_stage) { + /* TODO : Two-stage translation for RV128 */ int vbase_prot; hwaddr vbase; =20 @@ -593,6 +613,10 @@ restart: if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { pte =3D address_space_ldl(cs->as, pte_addr, attrs, &res); } else { + /* + * For RV128, load only lower 64 bits as only those + * are used for now + */ pte =3D address_space_ldq(cs->as, pte_addr, attrs, &res); } =20 @@ -607,7 +631,7 @@ restart: return TRANSLATE_FAIL; } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { /* Inner PTE, continue walking */ - base =3D ppn << PGSHIFT; + base =3D ppn << pgshift; } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { /* Reserved leaf PTE flags: PTE_W */ return TRANSLATE_FAIL; @@ -679,9 +703,9 @@ restart: =20 /* for superpage mappings, make a fake leaf PTE for the TLB's benefit. */ - target_ulong vpn =3D addr >> PGSHIFT; - *physical =3D ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIF= T) | - (addr & ~TARGET_PAGE_MASK); + target_ulong vpn =3D addr >> pgshift; + *physical =3D ((ppn | (vpn & ((1L << ptshift) - 1))) << pgshif= t) | + (addr & pgoff_mask); =20 /* set permissions on the TLB entry */ if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 877cd2d63a..028adab6a8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -461,6 +461,12 @@ static const char valid_vm_1_10_64[16] =3D { [VM_1_10_SV57] =3D 1 }; =20 +static const bool valid_vm_1_10_128[16] =3D { + [VM_1_10_MBARE] =3D 1, + [VM_1_10_SV44] =3D 1, + [VM_1_10_SV54] =3D 1 +}; + /* Machine Information Registers */ static RISCVException read_zero_i128(CPURISCVState *env, int csrno, Int128 *val) @@ -535,29 +541,27 @@ static RISCVException write_mstatus_i128(CPURISCVStat= e *env, int csrno, MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS= _TSR | MSTATUS_TW); =20 - if (!riscv_cpu_is_32bit(env)) { - /* - * RV32: MPV and GVA are not in mstatus. The current plan is to - * add them to mstatush. For now, we just don't support it. - */ - mask =3D int128_or(mask, int128_make64(MSTATUS_MPV | MSTATUS_GVA)); - } + mask =3D int128_or(mask, int128_make64(MSTATUS_MPV | MSTATUS_GVA)); =20 mstatus =3D int128_or(int128_and(mstatus, int128_not(mask)), int128_and(val, mask)); =20 dirty =3D ((int128_getlo(mstatus) & MSTATUS_FS) =3D=3D MSTATUS_FS) | ((int128_getlo(mstatus) & MSTATUS_XS) =3D=3D MSTATUS_XS); + + /* Cannot use add_status_sd here, let's do it the old way */ if (dirty) { - if (riscv_cpu_is_32bit(env)) { - mstatus =3D int128_make64(int128_getlo(mstatus) | MSTATUS32_SD= ); - } else if (riscv_cpu_is_64bit(env)) { - mstatus =3D int128_make64(int128_getlo(mstatus) | MSTATUS64_SD= ); - } else { - mstatus =3D int128_or(mstatus, int128_make128(0, MSTATUSH128_S= D)); - } + mstatus =3D int128_or(mstatus, int128_make128(0, MSTATUSH128_SD)); } =20 + /* SXL and UXL fields are for now read only, at xl_max */ + mstatus =3D int128_make128( + set_field(int128_getlo(mstatus), MSTATUS64_SXL, MXL_R= V128), + int128_gethi(mstatus)); + mstatus =3D int128_make128( + set_field(int128_getlo(mstatus), MSTATUS64_UXL, MXL_R= V128), + int128_gethi(mstatus)); + env->mstatus =3D int128_getlo(mstatus); env->mstatush =3D int128_gethi(mstatus); =20 @@ -575,8 +579,12 @@ static int validate_vm(CPURISCVState *env, target_ulon= g vm) { if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; - } else { + } else if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { return valid_vm_1_10_64[vm & 0xf]; + } else if (riscv_cpu_mxl(env) =3D=3D MXL_RV128) { + return valid_vm_1_10_128[vm & 0xf]; + } else { + return 0; } } =20 @@ -1114,6 +1122,69 @@ static RISCVException rmw_sip(CPURISCVState *env, in= t csrno, } =20 /* Supervisor Protection and Translation */ +static RISCVException read_satp_i128(CPURISCVState *env, int csrno, + Int128 *val) +{ + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + *val =3D int128_zero(); + return RISCV_EXCP_NONE; + } + + if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { + return RISCV_EXCP_ILLEGAL_INST; + } else { + *val =3D int128_make128(env->satp, env->satph); + } + + return RISCV_EXCP_NONE; +} + +static RISCVException write_satp_i128(CPURISCVState *env, int csrno, + Int128 val) +{ + uint32_t asid; + bool vm_ok; + Int128 mask; + + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + return RISCV_EXCP_NONE; + } + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + vm_ok =3D validate_vm(env, get_field(int128_getlo(val), SATP32_MOD= E)); + mask =3D int128_make64((int128_getlo(val) ^ env->satp) + & (SATP32_MODE | SATP32_ASID | SATP32_PPN)); + asid =3D (int128_getlo(val) ^ env->satp) & SATP32_ASID; + } else if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { + vm_ok =3D validate_vm(env, get_field(int128_getlo(val), SATP64_MOD= E)); + mask =3D int128_make64((int128_getlo(val) ^ env->satp) + & (SATP64_MODE | SATP64_ASID | SATP64_PPN)); + asid =3D (int128_getlo(val) ^ env->satp) & SATP64_ASID; + } else if (riscv_cpu_mxl(env) =3D=3D MXL_RV128) { + vm_ok =3D validate_vm(env, get_field(int128_gethi(val), SATP128_HM= ODE)); + mask =3D int128_and( + int128_xor(val, int128_make128(env->satp, env->satph)), + int128_make128(SATP128_LPPN, SATP128_HMODE | SATP128_HA= SID)); + asid =3D (int128_gethi(val) ^ env->satph) & SATP128_HASID; + } else { + g_assert_not_reached(); + } + + + if (vm_ok && int128_nz(mask)) { + if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { + return RISCV_EXCP_ILLEGAL_INST; + } else { + if (asid) { + tlb_flush(env_cpu(env)); + } + env->satp =3D int128_getlo(val); + env->satph =3D int128_gethi(val); + } + } + return RISCV_EXCP_NONE; +} + static RISCVException read_satp(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1648,7 +1719,7 @@ static inline RISCVException riscv_csrrw_check_i128(C= PURISCVState *env, /* check privileges and return -1 if check fails */ #if !defined(CONFIG_USER_ONLY) int effective_priv =3D env->priv; - int read_only =3D get_field(csrno, 0xc00) =3D=3D 3; + int read_only =3D get_field(csrno, 0xC00) =3D=3D 3; =20 if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_S && @@ -1789,7 +1860,7 @@ riscv_csr_operations128 csr_ops_128[CSR_TABLE_SIZE] = =3D { [CSR_MSCRATCH] =3D { read_mscratch_i128, write_mscratch_i128 }, [CSR_MEPC] =3D { read_mepc_i128, write_mepc_i128 }, =20 - [CSR_SATP] =3D { read_zero_i128 }, + [CSR_SATP] =3D { read_satp_i128, write_satp_i128 }, #endif }; =20 --=20 2.33.0