From nobody Tue Feb 10 12:59:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163460258465576.76832715071248; Mon, 18 Oct 2021 17:16:24 -0700 (PDT) Received: from localhost ([::1]:57116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccnn-0005k9-Gc for importer@patchew.org; Mon, 18 Oct 2021 20:16:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZU-00053E-Vz for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:41 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:38622) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZI-0001nj-4O for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:36 -0400 Received: by mail-pf1-x431.google.com with SMTP id k26so16054030pfi.5 for ; Mon, 18 Oct 2021 17:01:23 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RT2VpKAEfApm7ELgrgjYw2HluCj4mChRvtgjB+9QAL8=; b=mOa5XS+CnoMwE7kXn80tS1WwIXH2ThuYKDDNaWe/fjMKBUJ1MeeURqmvqUNSCrAVEB xSkp9wf6mXBJNhuaa4TOPC1H6MmMKJbBNSkWd7mnIL3Irx8PmaBjjaigvHE9BRTTH2z+ ajajCCOJq8EM53r6SnSGiQz2AauSZWeNTqZVmLen4CYMdk+X//UrPR5f1ddSdqLAbcbd M7SMcC0+IQ5Wqg/a6IudtHov/WhL9IrBcQ02Y1PHWZe/BAdTlJ66rlw0MFUHvjaOu3lK 2lLMJnRTJCYmmkBsa/nDDdm8rGOEC5R2MNLs314NJc5uLmmqqcK3vW6QHWMf6Xuec95u nFVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RT2VpKAEfApm7ELgrgjYw2HluCj4mChRvtgjB+9QAL8=; b=gCa0+0JBAGjEi5R9KirnoEZlSjbfT0KYNWgZXevtzCPpFGDSTCu/Gw+x+M1zTWFNNN 40MysqUSmWLwaKK7ohwvJBow3SQqUpSqAHhVItnLnXH/YjVYTZfOSq5tcQHegKwhpioF chOyKf3+sqLGiLw1AqQE3aXx/NZhX3VsNO6k7VZIQA9RiLb1Z8ifjxc8DwXFkO3NPRLA ms2/5d40I+gJAiBqD0fqYBffw73x50ep0v9/qvpQmS9IOqzOQN0dRB6LbVYxka+QOSay Oizkc+3EWN9OK9gO4p1j60gCO8923MtM3GBylMTECMUAAcz2hPuBPG2zgIB0fKxh/6bB +5qQ== X-Gm-Message-State: AOAM532vwDrmXiVWYEpSse3f/OXxRoTNQcUYShD3rxZsoq5zvEAFL3Qe afG3oovPFE2EXOqNatBHpHjHPmv+yE+eDg== X-Google-Smtp-Source: ABdhPJxkK6LqrPJ4F2Ki4aiYyeiqUsQhwpmh0qvF9TzjunE0t4FgnSBmq72jNQ67yZ2XkXBOMvs4iQ== X-Received: by 2002:a63:f62:: with SMTP id 34mr25909411pgp.159.1634601681515; Mon, 18 Oct 2021 17:01:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 16/16] target/riscv: Compute mstatus.sd on demand Date: Mon, 18 Oct 2021 17:01:08 -0700 Message-Id: <20211019000108.3678724-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634602586025100001 Content-Type: text/plain; charset="utf-8" The position of this read-only field is dependent on the current cpu width. Rather than having to compute that difference in many places, compute it only on read. Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 3 +-- target/riscv/csr.c | 37 ++++++++++++++++++++++--------------- target/riscv/translate.c | 5 ++--- 3 files changed, 25 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 429afd1f48..0d1132f39d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -185,10 +185,9 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) =20 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - uint64_t sd =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? MSTATUS32_SD : MS= TATUS64_SD; uint64_t mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | - MSTATUS64_UXL | sd; + MSTATUS64_UXL; bool current_virt =3D riscv_cpu_virt_enabled(env); =20 g_assert(riscv_has_ext(env, RVH)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c4a479ddd2..69e4d65fcd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -477,10 +477,28 @@ static RISCVException read_mhartid(CPURISCVState *env= , int csrno, } =20 /* Machine Trap Setup */ + +/* We do not store SD explicitly, only compute it on demand. */ +static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) +{ + if ((status & MSTATUS_FS) =3D=3D MSTATUS_FS || + (status & MSTATUS_XS) =3D=3D MSTATUS_XS) { + switch (xl) { + case MXL_RV32: + return status | MSTATUS32_SD; + case MXL_RV64: + return status | MSTATUS64_SD; + default: + g_assert_not_reached(); + } + } + return status; +} + static RISCVException read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mstatus; + *val =3D add_status_sd(riscv_cpu_mxl(env), env->mstatus); return RISCV_EXCP_NONE; } =20 @@ -498,7 +516,6 @@ static RISCVException write_mstatus(CPURISCVState *env,= int csrno, { uint64_t mstatus =3D env->mstatus; uint64_t mask =3D 0; - int dirty; =20 /* flush tlb on mstatus fields that affect VM */ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | @@ -520,12 +537,7 @@ static RISCVException write_mstatus(CPURISCVState *env= , int csrno, =20 mstatus =3D (mstatus & ~mask) | (val & mask); =20 - dirty =3D ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS) | - ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - mstatus =3D set_field(mstatus, MSTATUS32_SD, dirty); - } else { - mstatus =3D set_field(mstatus, MSTATUS64_SD, dirty); + if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { /* SXL and UXL fields are for now read only */ mstatus =3D set_field(mstatus, MSTATUS64_SXL, MXL_RV64); mstatus =3D set_field(mstatus, MSTATUS64_UXL, MXL_RV64); @@ -798,13 +810,8 @@ static RISCVException read_sstatus(CPURISCVState *env,= int csrno, { target_ulong mask =3D (sstatus_v1_10_mask); =20 - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - mask |=3D SSTATUS32_SD; - } else { - mask |=3D SSTATUS64_SD; - } - - *val =3D env->mstatus & mask; + /* TODO: Use SXL not MXL. */ + *val =3D add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index de013fbf9b..35245aafa7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -280,7 +280,6 @@ static void gen_jal(DisasContext *ctx, int rd, target_u= long imm) static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; - target_ulong sd =3D get_xl(ctx) =3D=3D MXL_RV32 ? MSTATUS32_SD : MSTAT= US64_SD; =20 if (ctx->mstatus_fs !=3D MSTATUS_FS) { /* Remember the state change for the rest of the TB. */ @@ -288,7 +287,7 @@ static void mark_fs_dirty(DisasContext *ctx) =20 tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_temp_free(tmp); } @@ -299,7 +298,7 @@ static void mark_fs_dirty(DisasContext *ctx) =20 tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); tcg_temp_free(tmp); } --=20 2.25.1