From nobody Tue May 21 18:59:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634563732571668.0632477809133; Mon, 18 Oct 2021 06:28:52 -0700 (PDT) Received: from localhost ([::1]:38790 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcSh9-00065p-GH for importer@patchew.org; Mon, 18 Oct 2021 09:28:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47310) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcSee-0002tQ-CH for qemu-devel@nongnu.org; Mon, 18 Oct 2021 09:26:16 -0400 Received: from smtpout4.mo529.mail-out.ovh.net ([217.182.185.173]:60877) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcSec-0006BH-DH for qemu-devel@nongnu.org; Mon, 18 Oct 2021 09:26:16 -0400 Received: from mxplan5.mail.ovh.net (unknown [10.109.138.252]) by mo529.mail-out.ovh.net (Postfix) with ESMTPS id E0C04C5612FE; Mon, 18 Oct 2021 15:26:11 +0200 (CEST) Received: from kaod.org (37.59.142.96) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Mon, 18 Oct 2021 15:26:11 +0200 Authentication-Results: garm.ovh; auth=pass (GARM-96R0015b787b96-90c0-4ec1-8534-99accbe18c51, F07B6F3C357710E32BAB16EB0BBFA04B60198819) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Subject: [PATCH v2 1/5] aspeed/wdt: Introduce a container for the MMIO region Date: Mon, 18 Oct 2021 15:26:05 +0200 Message-ID: <20211018132609.160008-2-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211018132609.160008-1-clg@kaod.org> References: <20211018132609.160008-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [37.59.142.96] X-ClientProxiedBy: DAG1EX1.mxp5.local (172.16.2.1) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: 15e880a6-2af7-45d6-975d-588fc0415e69 X-Ovh-Tracer-Id: 8499136925812099945 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvtddrvddvtddgiedvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrdelieenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehmgihplhgrnhehrdhmrghilhdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtoheptghlgheskhgrohgurdhorhhg Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=217.182.185.173; envelope-from=clg@kaod.org; helo=smtpout4.mo529.mail-out.ovh.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Joel Stanley Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634563733817100003 On the AST2600, the 2nd watchdog timer can be controlled through the FMC controller to disable the alternate boot function. Next changes will map the WDT2 registers in the AST2600 FMC memory region. Add a container on top of the register region for this purpose. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Francisco Iglesias Reviewed-by: Peter Delevoryas Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/watchdog/wdt_aspeed.h | 1 + hw/watchdog/wdt_aspeed.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_asp= eed.h index f945cd6c5833..14e91acb1284 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -28,6 +28,7 @@ struct AspeedWDTState { QEMUTimer *timer; =20 /*< public >*/ + MemoryRegion iomem_container; MemoryRegion iomem; uint32_t regs[ASPEED_WDT_REGS_MAX]; =20 diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index 146ffcd71301..803e861a9c61 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -275,9 +275,13 @@ static void aspeed_wdt_realize(DeviceState *dev, Error= **errp) */ s->pclk_freq =3D PCLK_HZ; =20 + memory_region_init(&s->iomem_container, OBJECT(s), + TYPE_ASPEED_WDT ".container", ASPEED_WDT_REGS_MAX *= 4); + sysbus_init_mmio(sbd, &s->iomem_container); + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s, TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4); - sysbus_init_mmio(sbd, &s->iomem); + memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); } =20 static Property aspeed_wdt_properties[] =3D { --=20 2.31.1 From nobody Tue May 21 18:59:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163456393290587.2902244796436; Mon, 18 Oct 2021 06:32:12 -0700 (PDT) Received: from localhost ([::1]:46630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcSkN-00038D-HT for importer@patchew.org; Mon, 18 Oct 2021 09:32:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47398) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcSeh-0002ul-1H for qemu-devel@nongnu.org; Mon, 18 Oct 2021 09:26:19 -0400 Received: from 10.mo548.mail-out.ovh.net ([46.105.77.235]:54537) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcSee-0006DL-Bn for qemu-devel@nongnu.org; Mon, 18 Oct 2021 09:26:18 -0400 Received: from mxplan5.mail.ovh.net (unknown [10.109.143.2]) by mo548.mail-out.ovh.net (Postfix) with ESMTPS id B52D1204C4; Mon, 18 Oct 2021 13:26:12 +0000 (UTC) Received: from kaod.org (37.59.142.96) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Mon, 18 Oct 2021 15:26:11 +0200 Authentication-Results: garm.ovh; auth=pass (GARM-96R0019c4d4946-db25-46d9-8d6d-fbd749b81368, F07B6F3C357710E32BAB16EB0BBFA04B60198819) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Subject: [PATCH v2 2/5] aspeed: Initialize the watchdog device models before the FMC models Date: Mon, 18 Oct 2021 15:26:06 +0200 Message-ID: <20211018132609.160008-3-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211018132609.160008-1-clg@kaod.org> References: <20211018132609.160008-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [37.59.142.96] X-ClientProxiedBy: DAG1EX1.mxp5.local (172.16.2.1) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: 8c6912f3-dfdb-4361-834d-e8e8145ecdf7 X-Ovh-Tracer-Id: 8499418400517884777 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvtddrvddvtddgiedvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrdelieenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehmgihplhgrnhehrdhmrghilhdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtoheptghlgheskhgrohgurdhorhhg Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=46.105.77.235; envelope-from=clg@kaod.org; helo=10.mo548.mail-out.ovh.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Joel Stanley Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634563933968100003 Next changes will map the WDT2 registers in the AST2600 FMC memory region. Make sure the MemoryRegion pointers are correctly initialized before setting the object links. Do the same in the Aspeed AST2400 and AST2500 SoC models for consistency. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Francisco Iglesias Reviewed-by: Peter Delevoryas Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/aspeed_ast2600.c | 36 ++++++++++++++++++------------------ hw/arm/aspeed_soc.c | 36 ++++++++++++++++++------------------ 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 0384357a9510..3a7aa910b157 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -148,6 +148,11 @@ static void aspeed_soc_ast2600_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); =20 + for (i =3D 0; i < sc->wdts_num; i++) { + snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); + object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); + } + snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); object_initialize_child(obj, "adc", &s->adc, typename); =20 @@ -175,11 +180,6 @@ static void aspeed_soc_ast2600_init(Object *obj) object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), "max-ram-size"); =20 - for (i =3D 0; i < sc->wdts_num; i++) { - snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); - object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); - } - for (i =3D 0; i < sc->macs_num; i++) { object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], TYPE_FTGMAC100); @@ -325,6 +325,19 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); } =20 + /* Watch dog */ + for (i =3D 0; i < sc->wdts_num; i++) { + AspeedWDTClass *awc =3D ASPEED_WDT_GET_CLASS(&s->wdt[i]); + + object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu= ), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, + sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); + } + /* ADC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { return; @@ -395,19 +408,6 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDM= C]); =20 - /* Watch dog */ - for (i =3D 0; i < sc->wdts_num; i++) { - AspeedWDTClass *awc =3D ASPEED_WDT_GET_CLASS(&s->wdt[i]); - - object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu= ), - &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { - return; - } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, - sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); - } - /* Net */ for (i =3D 0; i < sc->macs_num; i++) { object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 7d53cf2f5133..2eb30d14cf94 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -162,6 +162,11 @@ static void aspeed_soc_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); =20 + for (i =3D 0; i < sc->wdts_num; i++) { + snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); + object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); + } + snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); object_initialize_child(obj, "adc", &s->adc, typename); =20 @@ -189,11 +194,6 @@ static void aspeed_soc_init(Object *obj) object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), "max-ram-size"); =20 - for (i =3D 0; i < sc->wdts_num; i++) { - snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); - object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); - } - for (i =3D 0; i < sc->macs_num; i++) { object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], TYPE_FTGMAC100); @@ -290,6 +290,19 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); } =20 + /* Watch dog */ + for (i =3D 0; i < sc->wdts_num; i++) { + AspeedWDTClass *awc =3D ASPEED_WDT_GET_CLASS(&s->wdt[i]); + + object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu= ), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, + sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); + } + /* ADC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { return; @@ -354,19 +367,6 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDM= C]); =20 - /* Watch dog */ - for (i =3D 0; i < sc->wdts_num; i++) { - AspeedWDTClass *awc =3D ASPEED_WDT_GET_CLASS(&s->wdt[i]); - - object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu= ), - &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { - return; - } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, - sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); - } - /* Net */ for (i =3D 0; i < sc->macs_num; i++) { object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, --=20 2.31.1 From nobody Tue May 21 18:59:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634564614447145.30246857455177; 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Mon, 18 Oct 2021 15:26:12 +0200 Authentication-Results: garm.ovh; auth=pass (GARM-96R0019e9176f8-73c1-4b9d-9c8b-86203e92de54, F07B6F3C357710E32BAB16EB0BBFA04B60198819) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Subject: [PATCH v2 3/5] aspeed/smc: Improve support for the alternate boot function Date: Mon, 18 Oct 2021 15:26:07 +0200 Message-ID: <20211018132609.160008-4-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211018132609.160008-1-clg@kaod.org> References: <20211018132609.160008-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [37.59.142.96] X-ClientProxiedBy: DAG1EX1.mxp5.local (172.16.2.1) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: b8f2eb58-3e1f-4ec7-9f1a-ad2ec8240354 X-Ovh-Tracer-Id: 8499418397763472236 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvtddrvddvtddgiedvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrdelieenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehmgihplhgrnhehrdhmrghilhdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtoheptghlgheskhgrohgurdhorhhg Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=46.105.45.231; envelope-from=clg@kaod.org; helo=8.mo548.mail-out.ovh.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Delevoryas , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Joel Stanley Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634564617855100001 Map the WDT2 registers in the AST2600 FMC memory region by creating a local address space on top of WDT2 memory region. The model only implements the enable bit of the control register. The reload register uses a 0.1s unit instead of a 1us. Values are converted on the fly when doing the accesses. The restart register is the same. Cc: Peter Delevoryas Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Peter Delevoryas --- include/hw/ssi/aspeed_smc.h | 3 ++ hw/arm/aspeed_ast2600.c | 2 + hw/ssi/aspeed_smc.c | 78 ++++++++++++++++++++++++++++++++++++- hw/ssi/trace-events | 1 + 4 files changed, 82 insertions(+), 2 deletions(-) diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 75bc793bd269..ad3c80f2d809 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -76,6 +76,9 @@ struct AspeedSMCState { MemoryRegion *dram_mr; AddressSpace dram_as; =20 + AddressSpace wdt2_as; + MemoryRegion *wdt2_mr; + AspeedSMCFlash flashes[ASPEED_SMC_CS_MAX]; =20 uint8_t snoop_index; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 3a7aa910b157..4abb0bb91e92 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -366,6 +366,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) } =20 /* FMC, The number of CS is set at the board level */ + object_property_set_link(OBJECT(&s->fmc), "wdt2", OBJECT(&s->wdt[2].io= mem), + &error_abort); object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 8a988c167604..1770985230b0 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -130,6 +130,8 @@ #define FMC_WDT2_CTRL_SINGLE_BOOT_MODE BIT(5) #define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4) /* O: primary 1: alternate= */ #define FMC_WDT2_CTRL_EN BIT(0) +#define R_FMC_WDT2_RELOAD (0x68 / 4) +#define R_FMC_WDT2_RESTART (0x6C / 4) =20 /* DMA Control/Status Register */ #define R_DMA_CTRL (0x80 / 4) @@ -704,6 +706,54 @@ static void aspeed_smc_reset(DeviceState *d) s->snoop_dummies =3D 0; } =20 +#define ASPEED_WDT_RELOAD 0x04 +#define ASPEED_WDT_RESTART 0x08 +#define ASPEED_WDT_CTRL 0x0C + +static void aspeed_smc_wdt2_write(AspeedSMCState *s, uint32_t offset, + uint32_t value) +{ + MemTxResult result; + + address_space_stl_le(&s->wdt2_as, offset, value, MEMTXATTRS_UNSPECIFIE= D, + &result); + if (result !=3D MEMTX_OK) { + aspeed_smc_error("WDT2 write failed @%08x", offset); + return; + } +} + +static uint64_t aspeed_smc_wdt2_read(AspeedSMCState *s, uint32_t offset) +{ + MemTxResult result; + uint32_t value; + + value =3D address_space_ldl_le(&s->wdt2_as, offset, MEMTXATTRS_UNSPECI= FIED, + &result); + if (result !=3D MEMTX_OK) { + aspeed_smc_error("WDT2 read failed @%08x", offset); + return -1; + } + return value; +} + +static void aspeed_smc_wdt2_enable(AspeedSMCState *s, bool enable) +{ + uint32_t value; + + value =3D aspeed_smc_wdt2_read(s, ASPEED_WDT_CTRL); + if (value =3D=3D -1) { + return; + } + + value &=3D ~BIT(0); + value |=3D enable; + + aspeed_smc_wdt2_write(s, ASPEED_WDT_CTRL, value); + + trace_aspeed_smc_wdt2_enable(enable ? "en" : "dis"); +} + static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int si= ze) { AspeedSMCState *s =3D ASPEED_SMC(opaque); @@ -718,7 +768,6 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr ad= dr, unsigned int size) addr =3D=3D R_CE_CMD_CTRL || addr =3D=3D R_INTR_CTRL || addr =3D=3D R_DUMMY_DATA || - (aspeed_smc_has_wdt_control(asc) && addr =3D=3D R_FMC_WDT2_CTRL) || (aspeed_smc_has_dma(asc) && addr =3D=3D R_DMA_CTRL) || (aspeed_smc_has_dma(asc) && addr =3D=3D R_DMA_FLASH_ADDR) || (aspeed_smc_has_dma(asc) && addr =3D=3D R_DMA_DRAM_ADDR) || @@ -731,6 +780,10 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr a= ddr, unsigned int size) trace_aspeed_smc_read(addr << 2, size, s->regs[addr]); =20 return s->regs[addr]; + } else if (aspeed_smc_has_wdt_control(asc) && addr =3D=3D R_FMC_WDT2_C= TRL) { + return aspeed_smc_wdt2_read(s, ASPEED_WDT_CTRL); + } else if (aspeed_smc_has_wdt_control(asc) && addr =3D=3D R_FMC_WDT2_R= ELOAD) { + return aspeed_smc_wdt2_read(s, ASPEED_WDT_RELOAD) / 100000; } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\= n", __func__, addr); @@ -1053,7 +1106,11 @@ static void aspeed_smc_write(void *opaque, hwaddr ad= dr, uint64_t data, } else if (addr =3D=3D R_DUMMY_DATA) { s->regs[addr] =3D value & 0xff; } else if (aspeed_smc_has_wdt_control(asc) && addr =3D=3D R_FMC_WDT2_C= TRL) { - s->regs[addr] =3D value & FMC_WDT2_CTRL_EN; + aspeed_smc_wdt2_enable(s, !!(value & FMC_WDT2_CTRL_EN)); + } else if (aspeed_smc_has_wdt_control(asc) && addr =3D=3D R_FMC_WDT2_R= ELOAD) { + aspeed_smc_wdt2_write(s, ASPEED_WDT_RELOAD, value * 100000); + } else if (aspeed_smc_has_wdt_control(asc) && addr =3D=3D R_FMC_WDT2_R= ESTART) { + aspeed_smc_wdt2_write(s, ASPEED_WDT_RESTART, value); } else if (addr =3D=3D R_INTR_CTRL) { s->regs[addr] =3D value; } else if (aspeed_smc_has_dma(asc) && addr =3D=3D R_DMA_CTRL) { @@ -1108,6 +1165,16 @@ static void aspeed_smc_dma_setup(AspeedSMCState *s, = Error **errp) TYPE_ASPEED_SMC ".dma-dram"); } =20 +static void aspeed_smc_wdt_setup(AspeedSMCState *s, Error **errp) +{ + if (!s->wdt2_mr) { + error_setg(errp, TYPE_ASPEED_SMC ": 'wdt2' link not set"); + return; + } + + address_space_init(&s->wdt2_as, s->wdt2_mr, TYPE_ASPEED_SMC ".wdt2"); +} + static void aspeed_smc_realize(DeviceState *dev, Error **errp) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); @@ -1189,6 +1256,11 @@ static void aspeed_smc_realize(DeviceState *dev, Err= or **errp) if (aspeed_smc_has_dma(asc)) { aspeed_smc_dma_setup(s, errp); } + + /* WDT2 support */ + if (aspeed_smc_has_wdt_control(asc)) { + aspeed_smc_wdt_setup(s, errp); + } } =20 static const VMStateDescription vmstate_aspeed_smc =3D { @@ -1208,6 +1280,8 @@ static Property aspeed_smc_properties[] =3D { DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, fal= se), DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_LINK("wdt2", AspeedSMCState, wdt2_mr, + TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events index 612d3d6087aa..0de79bf9c6a5 100644 --- a/hw/ssi/trace-events +++ b/hw/ssi/trace-events @@ -9,6 +9,7 @@ aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%0= 8x: 0x%08x" aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint32_t dram_addr= , uint32_t size) "%s flash:@0x%08x dram:@0x%08x size:0x%08x" aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx= 64 " size %u: 0x%" PRIx64 aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect" +aspeed_smc_wdt2_enable(const char *prefix) "WDT2 is %sabled" =20 # npcm7xx_fiu.c =20 --=20 2.31.1 From nobody Tue May 21 18:59:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 18 Oct 2021 13:26:14 +0000 (UTC) Received: from kaod.org (37.59.142.96) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Mon, 18 Oct 2021 15:26:12 +0200 Authentication-Results: garm.ovh; auth=pass (GARM-96R001068ba90d-1e75-41cd-920c-601283f517b7, F07B6F3C357710E32BAB16EB0BBFA04B60198819) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Subject: [PATCH v2 4/5] aspeed/smc: Use a container for the flash mmio address space Date: Mon, 18 Oct 2021 15:26:08 +0200 Message-ID: <20211018132609.160008-5-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211018132609.160008-1-clg@kaod.org> References: <20211018132609.160008-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [37.59.142.96] X-ClientProxiedBy: DAG1EX1.mxp5.local (172.16.2.1) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: 62602c3c-167e-46a2-b393-916f0c15173c X-Ovh-Tracer-Id: 8499699873454525292 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvtddrvddvtddgiedvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrdelieenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehmgihplhgrnhehrdhmrghilhdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtoheptghlgheskhgrohgurdhorhhg Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=46.105.33.25; envelope-from=clg@kaod.org; helo=7.mo548.mail-out.ovh.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Joel Stanley Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634564141669100001 Because AddressSpaces must not be sysbus-mapped, commit e9c568dbc225 ("hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use alias") introduced an alias for the flash mmio region. Using a container is cleaner. Cc: Philippe Mathieu-Daud=C3=A9 Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Francisco Iglesias Reviewed-by: Peter Delevoryas Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/ssi/aspeed_smc.h | 2 +- hw/ssi/aspeed_smc.c | 11 +++++++---- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index ad3c80f2d809..61d23ec1f13e 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -52,8 +52,8 @@ struct AspeedSMCState { SysBusDevice parent_obj; =20 MemoryRegion mmio; + MemoryRegion mmio_flash_container; MemoryRegion mmio_flash; - MemoryRegion mmio_flash_alias; =20 qemu_irq irq; =20 diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 1770985230b0..d4f03881ddf5 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -1218,14 +1218,17 @@ static void aspeed_smc_realize(DeviceState *dev, Er= ror **errp) * window in which the flash modules are mapped. The size and * address depends on the SoC model and controller type. */ + memory_region_init(&s->mmio_flash_container, OBJECT(s), + TYPE_ASPEED_SMC ".container", + asc->flash_window_size); + sysbus_init_mmio(sbd, &s->mmio_flash_container); + memory_region_init_io(&s->mmio_flash, OBJECT(s), &aspeed_smc_flash_default_ops, s, TYPE_ASPEED_SMC ".flash", asc->flash_window_size); - memory_region_init_alias(&s->mmio_flash_alias, OBJECT(s), - TYPE_ASPEED_SMC ".flash", - &s->mmio_flash, 0, asc->flash_window_size); - sysbus_init_mmio(sbd, &s->mmio_flash_alias); + memory_region_add_subregion(&s->mmio_flash_container, 0x0, + &s->mmio_flash); =20 /* * Let's create a sub memory region for each possible peripheral. All --=20 2.31.1 From nobody Tue May 21 18:59:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634564484085489.32670862693067; Mon, 18 Oct 2021 06:41:24 -0700 (PDT) Received: from localhost ([::1]:40802 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcStG-0001kl-Nr for importer@patchew.org; Mon, 18 Oct 2021 09:41:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcSei-0002wF-01 for qemu-devel@nongnu.org; Mon, 18 Oct 2021 09:26:21 -0400 Received: from 10.mo548.mail-out.ovh.net ([46.105.77.235]:42225) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcSef-0006ED-Ln for qemu-devel@nongnu.org; Mon, 18 Oct 2021 09:26:19 -0400 Received: from mxplan5.mail.ovh.net (unknown [10.109.143.2]) by mo548.mail-out.ovh.net (Postfix) with ESMTPS id 734BD1FFFA; Mon, 18 Oct 2021 13:26:14 +0000 (UTC) Received: from kaod.org (37.59.142.96) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Mon, 18 Oct 2021 15:26:13 +0200 Authentication-Results: garm.ovh; auth=pass (GARM-96R00177649be0-59b1-4f34-957c-ba3fbdc143c2, F07B6F3C357710E32BAB16EB0BBFA04B60198819) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Subject: [PATCH v2 5/5] speed/sdhci: Add trace events Date: Mon, 18 Oct 2021 15:26:09 +0200 Message-ID: <20211018132609.160008-6-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211018132609.160008-1-clg@kaod.org> References: <20211018132609.160008-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [37.59.142.96] X-ClientProxiedBy: DAG1EX1.mxp5.local (172.16.2.1) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: 9093df4e-e7b5-419b-ad91-ec691fe96755 X-Ovh-Tracer-Id: 8499699875552791401 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvtddrvddvtddgiedvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrdelieenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehmgihplhgrnhehrdhmrghilhdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtoheptghlgheskhgrohgurdhorhhg Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=46.105.77.235; envelope-from=clg@kaod.org; helo=10.mo548.mail-out.ovh.net X-Spam_score_int: 0 X-Spam_score: -0.0 X-Spam_bar: / X-Spam_report: (-0.0 / 5.0 requ) RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Joel Stanley Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634564485550100001 Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Francisco Iglesias Reviewed-by: Peter Delevoryas Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/sd/aspeed_sdhci.c | 5 +++++ hw/sd/trace-events | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index 3299844de6dc..df1bdf1fa4ed 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sdhci.c @@ -14,6 +14,7 @@ #include "hw/irq.h" #include "migration/vmstate.h" #include "hw/qdev-properties.h" +#include "trace.h" =20 #define ASPEED_SDHCI_INFO 0x00 #define ASPEED_SDHCI_INFO_SLOT1 (1 << 17) @@ -60,6 +61,8 @@ static uint64_t aspeed_sdhci_read(void *opaque, hwaddr ad= dr, unsigned int size) } } =20 + trace_aspeed_sdhci_read(addr, size, (uint64_t) val); + return (uint64_t)val; } =20 @@ -68,6 +71,8 @@ static void aspeed_sdhci_write(void *opaque, hwaddr addr,= uint64_t val, { AspeedSDHCIState *sdhci =3D opaque; =20 + trace_aspeed_sdhci_write(addr, size, val); + switch (addr) { case ASPEED_SDHCI_INFO: /* The RESET bit automatically clears. */ diff --git a/hw/sd/trace-events b/hw/sd/trace-events index 3cc2ef89ba6b..94a00557b26f 100644 --- a/hw/sd/trace-events +++ b/hw/sd/trace-events @@ -68,3 +68,7 @@ pl181_fifo_push(uint32_t data) "FIFO push 0x%08" PRIx32 pl181_fifo_pop(uint32_t data) "FIFO pop 0x%08" PRIx32 pl181_fifo_transfer_complete(void) "FIFO transfer complete" pl181_data_engine_idle(void) "data engine idle" + +# aspeed_sdhci.c +aspeed_sdhci_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx= 64 " size %u: 0x%" PRIx64 +aspeed_sdhci_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRI= x64 " size %u: 0x%" PRIx64 --=20 2.31.1