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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/24] target/arm: Drop checks for singlestep_enabled
Date: Sat, 16 Oct 2021 11:14:56 -0700
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GDB single-stepping is now handled generically.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 10 ++--------
target/arm/translate.c | 36 ++++++------------------------------
2 files changed, 8 insertions(+), 38 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 717afd481c..cec672f229 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -404,8 +404,6 @@ static inline void gen_goto_tb(DisasContext *s, int n, =
uint64_t dest)
gen_a64_set_pc_im(dest);
if (s->ss_active) {
gen_step_complete_exception(s);
- } else if (s->base.singlestep_enabled) {
- gen_exception_internal(EXCP_DEBUG);
} else {
tcg_gen_lookup_and_goto_ptr();
s->base.is_jmp =3D DISAS_NORETURN;
@@ -14879,7 +14877,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc=
base, CPUState *cpu)
{
DisasContext *dc =3D container_of(dcbase, DisasContext, base);
=20
- if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) {
+ if (unlikely(dc->ss_active)) {
/* Note that this means single stepping WFI doesn't halt the CPU.
* For conditional branch insns this is harmless unreachable code =
as
* gen_goto_tb() has already handled emitting the debug exception
@@ -14891,11 +14889,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *d=
cbase, CPUState *cpu)
/* fall through */
case DISAS_EXIT:
case DISAS_JUMP:
- if (dc->base.singlestep_enabled) {
- gen_exception_internal(EXCP_DEBUG);
- } else {
- gen_step_complete_exception(dc);
- }
+ gen_step_complete_exception(dc);
break;
case DISAS_NORETURN:
break;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f7086c66a5..d6af5b1b03 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -341,7 +341,7 @@ static void gen_exception_internal(int excp)
tcg_temp_free_i32(tcg_excp);
}
=20
-static void gen_step_complete_exception(DisasContext *s)
+static void gen_singlestep_exception(DisasContext *s)
{
/* We just completed step of an insn. Move from Active-not-pending
* to Active-pending, and then also take the swstep exception.
@@ -357,30 +357,6 @@ static void gen_step_complete_exception(DisasContext *=
s)
s->base.is_jmp =3D DISAS_NORETURN;
}
=20
-static void gen_singlestep_exception(DisasContext *s)
-{
- /* Generate the right kind of exception for singlestep, which is
- * either the architectural singlestep or EXCP_DEBUG for QEMU's
- * gdb singlestepping.
- */
- if (s->ss_active) {
- gen_step_complete_exception(s);
- } else {
- gen_exception_internal(EXCP_DEBUG);
- }
-}
-
-static inline bool is_singlestepping(DisasContext *s)
-{
- /* Return true if we are singlestepping either because of
- * architectural singlestep or QEMU gdbstub singlestep. This does
- * not include the command line '-singlestep' mode which is rather
- * misnamed as it only means "one instruction per TB" and doesn't
- * affect the code we generate.
- */
- return s->base.singlestep_enabled || s->ss_active;
-}
-
void clear_eci_state(DisasContext *s)
{
/*
@@ -837,7 +813,7 @@ static inline void gen_bx_excret_final_code(DisasContex=
t *s)
/* Is the new PC value in the magic range indicating exception return?=
*/
tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
/* No: end the TB as we would for a DISAS_JMP */
- if (is_singlestepping(s)) {
+ if (s->ss_active) {
gen_singlestep_exception(s);
} else {
tcg_gen_exit_tb(NULL, 0);
@@ -2606,7 +2582,7 @@ static void gen_goto_tb(DisasContext *s, int n, targe=
t_ulong dest)
/* Jump, specifying which TB number to use if we gen_goto_tb() */
static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
{
- if (unlikely(is_singlestepping(s))) {
+ if (unlikely(s->ss_active)) {
/* An indirect jump so that we still trigger the debug exception. =
*/
gen_set_pc_im(s, dest);
s->base.is_jmp =3D DISAS_JUMP;
@@ -9459,7 +9435,7 @@ static void arm_tr_init_disas_context(DisasContextBas=
e *dcbase, CPUState *cs)
dc->page_start =3D dc->base.pc_first & TARGET_PAGE_MASK;
=20
/* If architectural single step active, limit to 1. */
- if (is_singlestepping(dc)) {
+ if (dc->ss_active) {
dc->base.max_insns =3D 1;
}
=20
@@ -9794,7 +9770,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, =
CPUState *cpu)
* insn codepath itself.
*/
gen_bx_excret_final_code(dc);
- } else if (unlikely(is_singlestepping(dc))) {
+ } else if (unlikely(dc->ss_active)) {
/* Unconditional and "condition passed" instruction codepath. */
switch (dc->base.is_jmp) {
case DISAS_SWI:
@@ -9889,7 +9865,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, =
CPUState *cpu)
/* "Condition failed" instruction codepath for the branch/trap ins=
n */
gen_set_label(dc->condlabel);
gen_set_condexec(dc);
- if (unlikely(is_singlestepping(dc))) {
+ if (unlikely(dc->ss_active)) {
gen_set_pc_im(dc, dc->base.pc_next);
gen_singlestep_exception(dc);
} else {
--=20
2.25.1