From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271166922303.78635409591595; Thu, 14 Oct 2021 21:12:46 -0700 (PDT) Received: from localhost ([::1]:54766 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEaL-00015b-60 for importer@patchew.org; Fri, 15 Oct 2021 00:12:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38616) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYd-0006f5-57 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:10:59 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:41947) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYb-0008WE-7c for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:10:58 -0400 Received: by mail-pj1-x102f.google.com with SMTP id na16-20020a17090b4c1000b0019f5bb661f9so6415392pjb.0 for ; Thu, 14 Oct 2021 21:10:56 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:10:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KuLneJaR8ad6zfXTHHDWg+qki3lZgiD+ST/qhhyEGtg=; b=Q8DQDDwoPV6XOzXFGiN+2e06iPsAqlzS3h9OYiPILk9999LxJ1yf765DaQ4z94o2gO CtYJnqk9Chw4CLku5tXfdWgzs6a02qm2Z/AP2G0XQoWVxyiZWe4MvLVi7rO1EvOWqWpV M12CpK74BDAKupe3kgjq/kItxoIxNzW/KMy6pv7RkKOTG6U+OPx7a2claOb2oc+UMvfg 6LnvbI2Y8YhnrVVxriOIe8H/EEd+HVUYq1wivlnDBUMjJDkFKO8uzOhAyyEtJrdh9XoU TbOJD7WGLNwILfHIo6KE9gJ+qm2WDW2rrDPvhweJQUoU7h6RIlJNuE0JjhRrXTGsWeDY HNHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KuLneJaR8ad6zfXTHHDWg+qki3lZgiD+ST/qhhyEGtg=; b=xIbouTGaPNExh3tMVkO799HB0c6mF982b0PPIzXS8ugr6D3uXJ+mdEB4V2/5wpkAKZ uFBKrlCkIFe9vT9GJKE3ETm92DudnoicbzJMCetVPs5SmU88PJcOCnxQgu9dNRXoc3Yd /cuOP7vl4dN/70A3Anz7IOil7jrdduDJa6Us5xhPM1sMXoDfYDc1q6atGX18OXMK4a8s iZ6IzPQ2fg71U7dB69YCFBc65rHAzClgFpC1YPonNOpv2xbqnWH/vnIxszzvDiCqnF2M sUyIo3uQnqhJJ/g8RBvSzoe3jZyeKfzW7a/6n2JWCmDDyV/PGnfdIQExl2tkjqO4oyzs V8Nw== X-Gm-Message-State: AOAM532icjzrVknR0F9gaTZASmdJ39SNi1CG6GYXVQAS0UlMYcrSEzFR SLSwrHO6rY+RQtQw4ApGLkrrddIlPhhY9w== X-Google-Smtp-Source: ABdhPJzphE7WbWe9VqXJhZv77Dw/itXeRthCWbCQibv+SlhYN3+z3JL1SYlkpwpApl8ssORwUNyJuQ== X-Received: by 2002:a17:90a:de84:: with SMTP id n4mr7006410pjv.226.1634271055778; Thu, 14 Oct 2021 21:10:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 01/67] accel/tcg: Split out adjust_signal_pc Date: Thu, 14 Oct 2021 21:09:47 -0700 Message-Id: <20211015041053.2769193-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271168247100001 Split out a function to adjust the raw signal pc into a value that could be passed to cpu_restore_state. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- v2: Adjust pc in place; return MMUAccessType. --- include/exec/exec-all.h | 10 ++++++++++ accel/tcg/user-exec.c | 41 +++++++++++++++++++++++++---------------- 2 files changed, 35 insertions(+), 16 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 9d5987ba04..e54f8e5d65 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -663,6 +663,16 @@ static inline tb_page_addr_t get_page_addr_code_hostp(= CPUArchState *env, return addr; } =20 +/** + * adjust_signal_pc: + * @pc: raw pc from the host signal ucontext_t. + * @is_write: host memory operation was write, or read-modify-write. + * + * Alter @pc as required for unwinding. Return the type of the + * guest memory access -- host reads may be for guest execution. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e6bb29b42d..c02d509ec6 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -57,18 +57,11 @@ static void QEMU_NORETURN cpu_exit_tb_from_sighandler(C= PUState *cpu, cpu_loop_exit_noexc(cpu); } =20 -/* 'pc' is the host PC at which the exception was raised. 'address' is - the effective address of the memory exception. 'is_write' is 1 if a - write caused the exception and otherwise 0'. 'old_set' is the - signal set which should be restored */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) +/* + * Adjust the pc to pass to cpu_restore_state; return the memop type. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write) { - CPUState *cpu =3D current_cpu; - CPUClass *cc; - unsigned long address =3D (unsigned long)info->si_addr; - MMUAccessType access_type =3D is_write ? MMU_DATA_STORE : MMU_DATA_LOA= D; - switch (helper_retaddr) { default: /* @@ -77,7 +70,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo= _t *info, * pointer into the generated code that will unwind to the * correct guest pc. */ - pc =3D helper_retaddr; + *pc =3D helper_retaddr; break; =20 case 0: @@ -97,7 +90,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo= _t *info, * Therefore, adjust to compensate for what will be done later * by cpu_restore_state_from_tb. */ - pc +=3D GETPC_ADJ; + *pc +=3D GETPC_ADJ; break; =20 case 1: @@ -113,12 +106,28 @@ static inline int handle_cpu_signal(uintptr_t pc, sig= info_t *info, * * Like tb_gen_code, release the memory lock before cpu_loop_exit. */ - pc =3D 0; - access_type =3D MMU_INST_FETCH; mmap_unlock(); - break; + *pc =3D 0; + return MMU_INST_FETCH; } =20 + return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; +} + +/* + * 'pc' is the host PC at which the exception was raised. + * 'address' is the effective address of the memory exception. + * 'is_write' is 1 if a write caused the exception and otherwise 0. + * 'old_set' is the signal set which should be restored. + */ +static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, + int is_write, sigset_t *old_set) +{ + CPUState *cpu =3D current_cpu; + CPUClass *cc; + unsigned long address =3D (unsigned long)info->si_addr; + MMUAccessType access_type =3D adjust_signal_pc(&pc, is_write); + /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running * code or during translation which can fault as we cross pages. --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271321910971.9890102124385; Thu, 14 Oct 2021 21:15:21 -0700 (PDT) Received: from localhost ([::1]:35278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEcq-0006rF-Nu for importer@patchew.org; Fri, 15 Oct 2021 00:15:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38650) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYe-0006fF-H7 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:00 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:41949) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYb-0008WM-Sy for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:00 -0400 Received: by mail-pj1-x1031.google.com with SMTP id na16-20020a17090b4c1000b0019f5bb661f9so6415410pjb.0 for ; Thu, 14 Oct 2021 21:10:57 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.10.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:10:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Xj+GBWow8u43T9kfx0pjQLSKyRLLPuU7SzICT50Nk5s=; b=jZuug+o019EfKoHhMGR63+bwuoHKY41oienXVmxxvQnShcmhYnHrK9qosb2utXVuRX Wcs2SD4/pSk2U4LDbK6L6CtwlUbyxaqFSquHQUmOVJRPswvycVVrGNTXc3MoLBwzFOz9 XXiA7CtJddmb51ZApyb7vFMSKb8DpfnXyXUsU3EmqXKM7qPsKILVEDw3/gVmGYUwOYg9 k1pdunAQT0TELpQRSnToNhuWwPm3Nlupq4QTlelRKfQwDVn/Ww6nocihIgOakzB+VuOY 2rCWIB6J+3tLBIlq2ZXtBk2fzrw6PLyJIgux/FmMKdGIiN7glUIXCjbsT6YV32BrygZ5 yJWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xj+GBWow8u43T9kfx0pjQLSKyRLLPuU7SzICT50Nk5s=; b=q0vUc7lk3cVoJaK40305BFSjzHb+8owBA82uHerijqvD1HZUdXGp2kPFlsCuSyKreX ZKHMtCVn+b8mlzkNNaXAkGBrxu4GJchYgt7hOR/TKFpUDarXN48odudapsnwes+DrwRH Q40RmhNGVSVlGwXGmW9UBT7dp5RuAQ0+2PdhtMdwC01TIzGKf3KKaSLMyONx34TVlBZU O57DItiOaOx9FhSL2kAWJ7+FdBOR2vHXXj9965ThkmxFNzspsM0xfPCZan5PDgg/qohD 07S1YPTBx5SAVkQVnxywMUheH4diRH6NWTPTkoeNgou95NorS2dSI791ipY8fZpv5vbl MN2w== X-Gm-Message-State: AOAM531NOjss075MSzliKJm7aeZwsiK6vHzHrUllhcPqACsOkgnoLPyZ pTXuyAfL4eeyc461D59FBRWb0j3FtzNx3Q== X-Google-Smtp-Source: ABdhPJwtSltIM4gUblocJRmcGPm4q0YdVPzA/pIJ470aDau9ErKY/ssCsQS5s8cUMeGG1DOA8wIp1w== X-Received: by 2002:a17:90b:3504:: with SMTP id ls4mr10729905pjb.111.1634271056529; Thu, 14 Oct 2021 21:10:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 02/67] accel/tcg: Move clear_helper_retaddr to cpu loop Date: Thu, 14 Oct 2021 21:09:48 -0700 Message-Id: <20211015041053.2769193-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271322873100005 Content-Type: text/plain; charset="utf-8" Currently there are only two places that require we reset this value before exiting to the main loop, but that will change. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 3 ++- accel/tcg/user-exec.c | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5fd1ed3422..410588d08a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -451,6 +451,7 @@ void cpu_exec_step_atomic(CPUState *cpu) * memory. */ #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { @@ -460,7 +461,6 @@ void cpu_exec_step_atomic(CPUState *cpu) qemu_plugin_disable_mem_helpers(cpu); } =20 - /* * As we start the exclusive region before codegen we must still * be in the region if we longjump out of either the codegen or @@ -905,6 +905,7 @@ int cpu_exec(CPUState *cpu) #endif =20 #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index c02d509ec6..3f3e793b7b 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -175,7 +175,6 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, * currently executing TB was modified and must be exited * immediately. Clear helper_retaddr for next execution. */ - clear_helper_retaddr(); cpu_exit_tb_from_sighandler(cpu, old_set); /* NORETURN */ =20 @@ -193,7 +192,6 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, * an exception. Undo signal and retaddr state prior to longjmp. */ sigprocmask(SIG_SETMASK, old_set, NULL); - clear_helper_retaddr(); =20 cc =3D CPU_GET_CLASS(cpu); cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271321180407.83708192779204; Thu, 14 Oct 2021 21:15:21 -0700 (PDT) Received: from localhost ([::1]:35348 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEcp-0006vQ-OW for importer@patchew.org; Fri, 15 Oct 2021 00:15:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYf-0006fq-KO for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:01 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:39596) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYc-00005L-Rv for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:01 -0400 Received: by mail-pj1-x102d.google.com with SMTP id ls18-20020a17090b351200b001a00250584aso8442778pjb.4 for ; Thu, 14 Oct 2021 21:10:58 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.10.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:10:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oWBO3F4xYVHiKUc+8+wn/0Gm+2aHBS/NMTMJJaAZTpE=; b=WgZSYMdM5MiEpebpmYIdI2+8BQ124sV9aynGIBIyP/3QtsS+A7ArDlL5tNSlZwJfTU Biq6QVu4gcNXAfwuFi/fIrMIdttIwP2gpphizZGasIx/Nm1gPLlCchXqBs50Z2NVDBSt lSSPj6EEmITk5PjtpKXOb5egjYQiNPwN2ZrtqxRDlyULZdz71hQsnu8CezSt2nTAOEgT TNyHIp9rcUf3Z2J1UV7RSNVu8vAdbx37OhfjuxaTaXje8rS8hUsqDhWUuhSiF5P3uNhF eOGmZ7Zmuu812U/PBKH65Qb+5zqCbia3/n5rR36eyRNiVxDUHfGSLL11M91W1iKDmssG VY6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oWBO3F4xYVHiKUc+8+wn/0Gm+2aHBS/NMTMJJaAZTpE=; b=wl91TrKdoGdIrqyFugYbVNg1MjgUCrdT11fy7Z5kdkiVt/DLiFuLdO3VtRAt3AqKXW NVWhx82SFGOoV1VjeObjBZ6QMyFkph7dPP0GSDRPV4fGnummCbn7MVdxV+OkLGKBrAds tC1rx9/LMU2u7psebi8jMK3ZoUTMtLsD17Ky03X7JATQBCzK97fBL9ynhb+UPD4TlHwj hKIA+ccWQZWFUfF2lq4RMuYjzZK4aaUdCepIqx5cn/lW+YTcjD5izLszEy+4TbRsVE0D n8XOfAtn4YWSiFEj9LFna4XJECyXi2lGuyQjbzNox1CHealwUYkljLicDT444iPzJYke XcpA== X-Gm-Message-State: AOAM533IT9ogewkTTQNug/lRUJJJhyQPFmMslvdyyrDjsMpcZ35f/Z4n pan4VkXZeFNL0X1Imp3e7EX1Z5byBkxosQ== X-Google-Smtp-Source: ABdhPJz1sbQThlrKg1UhgrL/EOAnjTMxjq47ygbjBjA0fwhfT4RNBIoGhNCr0RRm3nu3DfK3nqKlaw== X-Received: by 2002:a17:90a:4812:: with SMTP id a18mr24935113pjh.40.1634271057210; Thu, 14 Oct 2021 21:10:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 03/67] accel/tcg: Split out handle_sigsegv_accerr_write Date: Thu, 14 Oct 2021 21:09:49 -0700 Message-Id: <20211015041053.2769193-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271322834100003 This is the major portion of handle_cpu_signal which is specific to tcg, handling the page protections for the translations. Most of the rest will migrate to linux-user/ shortly. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- v2: Pass guest address to handle_sigsegv_accerr_write. --- include/exec/exec-all.h | 12 +++++ accel/tcg/user-exec.c | 103 ++++++++++++++++++++++++---------------- 2 files changed, 74 insertions(+), 41 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index e54f8e5d65..5f94d799aa 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -673,6 +673,18 @@ static inline tb_page_addr_t get_page_addr_code_hostp(= CPUArchState *env, */ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); =20 +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @host_addr: the host address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 3f3e793b7b..cb63e528c5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -114,6 +114,54 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_= write) return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; } =20 +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @guest_addr: the guest address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + * + * Note that it is important that we don't call page_unprotect() unless + * this is really a "write to nonwriteable page" fault, because + * page_unprotect() assumes that if it is called for an access to + * a page that's writeable this means we had two threads racing and + * another thread got there first and already made the page writeable; + * so we will retry the access. If we were to call page_unprotect() + * for some other kind of fault that should really be passed to the + * guest, we'd end up in an infinite loop of retrying the faulting access. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr) +{ + switch (page_unprotect(guest_addr, host_pc)) { + case 0: + /* + * Fault not caused by a page marked unwritable to protect + * cached translations, must be the guest binary's problem. + */ + return false; + case 1: + /* + * Fault caused by protection of cached translation; TBs + * invalidated, so resume execution. Retain helper_retaddr + * for a possible second fault. + */ + return true; + case 2: + /* + * Fault caused by protection of cached translation, and the + * currently executing TB was modified and must be exited + * immediately. Clear helper_retaddr for next execution. + */ + cpu_exit_tb_from_sighandler(cpu, old_set); + /* NORETURN */ + default: + g_assert_not_reached(); + } +} + /* * 'pc' is the host PC at which the exception was raised. * 'address' is the effective address of the memory exception. @@ -125,8 +173,9 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, { CPUState *cpu =3D current_cpu; CPUClass *cc; - unsigned long address =3D (unsigned long)info->si_addr; + unsigned long host_addr =3D (unsigned long)info->si_addr; MMUAccessType access_type =3D adjust_signal_pc(&pc, is_write); + abi_ptr guest_addr; =20 /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running @@ -143,49 +192,21 @@ static inline int handle_cpu_signal(uintptr_t pc, sig= info_t *info, =20 #if defined(DEBUG_SIGNAL) printf("qemu: SIGSEGV pc=3D0x%08lx address=3D%08lx w=3D%d oldset=3D0x%= 08lx\n", - pc, address, is_write, *(unsigned long *)old_set); + pc, host_addr, is_write, *(unsigned long *)old_set); #endif - /* XXX: locking issue */ - /* Note that it is important that we don't call page_unprotect() unless - * this is really a "write to nonwriteable page" fault, because - * page_unprotect() assumes that if it is called for an access to - * a page that's writeable this means we had two threads racing and - * another thread got there first and already made the page writeable; - * so we will retry the access. If we were to call page_unprotect() - * for some other kind of fault that should really be passed to the - * guest, we'd end up in an infinite loop of retrying the faulting - * access. - */ - if (is_write && info->si_signo =3D=3D SIGSEGV && info->si_code =3D=3D = SEGV_ACCERR && - h2g_valid(address)) { - switch (page_unprotect(h2g(address), pc)) { - case 0: - /* Fault not caused by a page marked unwritable to protect - * cached translations, must be the guest binary's problem. - */ - break; - case 1: - /* Fault caused by protection of cached translation; TBs - * invalidated, so resume execution. Retain helper_retaddr - * for a possible second fault. - */ - return 1; - case 2: - /* Fault caused by protection of cached translation, and the - * currently executing TB was modified and must be exited - * immediately. Clear helper_retaddr for next execution. - */ - cpu_exit_tb_from_sighandler(cpu, old_set); - /* NORETURN */ - - default: - g_assert_not_reached(); - } - } =20 /* Convert forcefully to guest address space, invalid addresses are still valid segv ones */ - address =3D h2g_nocheck(address); + guest_addr =3D h2g_nocheck(host_addr); + + /* XXX: locking issue */ + if (is_write && + info->si_signo =3D=3D SIGSEGV && + info->si_code =3D=3D SEGV_ACCERR && + h2g_valid(host_addr) && + handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { + return 1; + } =20 /* * There is no way the target can handle this other than raising @@ -194,7 +215,7 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, sigprocmask(SIG_SETMASK, old_set, NULL); =20 cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, + cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, MMU_USER_IDX, false, pc); g_assert_not_reached(); } --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271172961233.9969778844462; Thu, 14 Oct 2021 21:12:52 -0700 (PDT) Received: from localhost ([::1]:54924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEaR-0001Bb-Pk for importer@patchew.org; Fri, 15 Oct 2021 00:12:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38680) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYf-0006fy-Nj for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:01 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:38465) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYd-000077-Cd for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:01 -0400 Received: by mail-pj1-x1035.google.com with SMTP id g13-20020a17090a3c8d00b00196286963b9so8449598pjc.3 for ; Thu, 14 Oct 2021 21:10:58 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:10:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hPg0TWxPCq+nfWOlqCTkACXTywAZGmXvHVDfXz+ELxA=; b=ePhDaFwdkoIUlg1au87K7rxAPdx48d4LVSZRjofcCcROBwMK8nhxSI3csTLCVftxWO KX5P+tuO+//XWZWsMZIYFtkJM4Gr4B5hoSzeXxvsx+2yIgAxZJxn1ON06VoUqx81IPtN fh3jrt0QfekybvPfPdHIy68umQgfOdE/EWXtZSDAknjSMENUIHxw7N7bLF48/d9kae0/ xkBt12KlLxPIjG0hMpp1ysOsrGQu7NNW/c37huy5tFQ2fB9B/3+TmYgQiU6najvruhdu DGGtWw1x/3+EJYhlVcV92mcwD75qzyD3BN1PgKDgRuhw9D0PoCTayTaKl3GUddr8JkJq FjXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hPg0TWxPCq+nfWOlqCTkACXTywAZGmXvHVDfXz+ELxA=; b=20LOER6nKk1qtXdpFUJLpPB54nyEYsAyHBemNkkcxjFqmg96X7U25KtzULUonsqyrh MsXwIGbJlbZ5lkvPvHC6tByBvqaDqlBtB7QtmeVqp0bUk1t1+K8lmIN6WbfPM0dV7bfw UP+w0/cXNSZfFthk0ZVivKjHypYwzwhJGyHAaBDl0rM9yyrW1Km7wrvoB/ve3T2bZkoo ZTyO78Bf+wXBzAP03+tjxXoM3V/pFQ/M1TkemS7998u1411m4WLIUIE0J+MOObCIuSR3 uyfn6Ohr9kwAizDk6oILILnC4Jnqe8BPy/yRt8jV21PtZICo2oGiSFyzZLKul4AtRpmu wXsw== X-Gm-Message-State: AOAM532m9oBUC7+VS9AKLL1dPHtchpFpZ+lnC9/c/rtlmrzbS/zfuwLm y9NczCa26QyIX8cyRAhyMHVzka4hC7DMAw== X-Google-Smtp-Source: ABdhPJwpcqeH91Evad7jUEJ6V6QNo388CFagij2o4f0Qxn+szlz4puSL+n7KXJ/Br8ZPKq0G1Wjl7g== X-Received: by 2002:a17:90b:350f:: with SMTP id ls15mr10897543pjb.220.1634271057979; Thu, 14 Oct 2021 21:10:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 04/67] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Date: Thu, 14 Oct 2021 21:09:50 -0700 Message-Id: <20211015041053.2769193-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271174125100001 Content-Type: text/plain; charset="utf-8" Remove the comment about siglongjmp. We do use sigsetjmp in the main cpu loop, but we do not save the signal mask as most exits from the cpu loop do not require them. Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- accel/tcg/user-exec.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index cb63e528c5..744af19397 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -46,17 +46,6 @@ __thread uintptr_t helper_retaddr; =20 //#define DEBUG_SIGNAL =20 -/* exit the current TB from a signal handler. The host registers are - restored in a state compatible with the CPU emulator - */ -static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, - sigset_t *old_set) -{ - /* XXX: use siglongjmp ? */ - sigprocmask(SIG_SETMASK, old_set, NULL); - cpu_loop_exit_noexc(cpu); -} - /* * Adjust the pc to pass to cpu_restore_state; return the memop type. */ @@ -155,7 +144,8 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_= t *old_set, * currently executing TB was modified and must be exited * immediately. Clear helper_retaddr for next execution. */ - cpu_exit_tb_from_sighandler(cpu, old_set); + sigprocmask(SIG_SETMASK, old_set, NULL); + cpu_loop_exit_noexc(cpu); /* NORETURN */ default: g_assert_not_reached(); --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271175863574.8373246875263; Thu, 14 Oct 2021 21:12:55 -0700 (PDT) Received: from localhost ([::1]:55056 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEaU-0001H5-SD for importer@patchew.org; Fri, 15 Oct 2021 00:12:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYg-0006h4-7G for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:02 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:33775) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYd-00007Y-Vy for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:01 -0400 Received: by mail-pl1-x636.google.com with SMTP id y4so5636522plb.0 for ; Thu, 14 Oct 2021 21:10:59 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:10:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oOQU7Pbw0+lekQo/Dc4xCn9/9dfAsnRnEEjuG278GdE=; b=stISHxdxUYcJ+m/mrW/EMrcZISPQEdhH2XWaDecY0jEO20NKcvrdgzQb1UPvD0aouY ZgtEy5wmVv32wGXJUro7lcJYO5NfsXjO+Z0jmjNlK/MHYKq05c++dtZTC6MTZK4khnVB woMC8jAUSyQqiyZKWSVfHy5ddy+PCaTv46nIoQlGgJkcChCDPGUnoH+FAsQv+4w8kVFx BUCCN5GebAenGUvR8mLa8KsTQBTTmzUZE0S3dYSRVQ8dCJVWuzqvihKUOlf8X+iR6Q3R A9Gm6bHYWHN/KIdw2tb65R3NIH0FU7ZaBg5k5sa/wEPRu71u+dIZ0BB8O/mWDfaLznZN 7h7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oOQU7Pbw0+lekQo/Dc4xCn9/9dfAsnRnEEjuG278GdE=; b=odd3epmrTSJWelk3XRPSpzu2EPjuaXR77nrnYpc7Hhdk7UAaGLHXcNQO33PVdcwH6c N5ZIGzV+eAu6ZKPjvbEq7DIj85vL0FFBWW/thNkKt2UeFwY96QWXPYA+NWwanMKvMD1s OyNTEURyAlmbSHn28H/7GCWLH3T5k3Scob950l8k/ocYZzLqAdQEdSvZsZguhvznrBmj CCPHL+sXH0Ao2r6/kOl+9xLLenCLq3Qw0+yVSgJTClm6NTiYRdiJVJYLIEmeIB7S6FYl Ka7CSmyiEmBSvd1Qg0/l3/dkEPB1O2cCDWX6omHyuIVQelyKmFeyBaoBO3fHuBDVxYnh gZvg== X-Gm-Message-State: AOAM530xeDDEYnF39tqqWJwSmcf4aFSoL7iPMERW0zjcgji2NrdmGqmA 9vvp3MX+sDV7kdP/L7S25TRpTSODpDNcFA== X-Google-Smtp-Source: ABdhPJzzJtA+HiNsHmTdTJNirRZQ7SGVsp/ZMQiewOPyoUwbuQHBKONYa87c3j/k6X7C3n56d5o7vw== X-Received: by 2002:a17:90b:4b46:: with SMTP id mi6mr10276124pjb.161.1634271058598; Thu, 14 Oct 2021 21:10:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 05/67] configure: Merge riscv32 and riscv64 host architectures Date: Thu, 14 Oct 2021 21:09:51 -0700 Message-Id: <20211015041053.2769193-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271178171100005 The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- configure | 8 ++------ meson.build | 4 +--- linux-user/host/{riscv64 =3D> riscv}/hostdep.h | 4 ++-- linux-user/host/riscv32/hostdep.h | 11 ----------- linux-user/host/{riscv64 =3D> riscv}/safe-syscall.inc.S | 0 5 files changed, 5 insertions(+), 22 deletions(-) rename linux-user/host/{riscv64 =3D> riscv}/hostdep.h (94%) delete mode 100644 linux-user/host/riscv32/hostdep.h rename linux-user/host/{riscv64 =3D> riscv}/safe-syscall.inc.S (100%) diff --git a/configure b/configure index 039467c04b..d57ad58342 100755 --- a/configure +++ b/configure @@ -570,11 +570,7 @@ elif check_define __s390__ ; then cpu=3D"s390" fi elif check_define __riscv ; then - if check_define _LP64 ; then - cpu=3D"riscv64" - else - cpu=3D"riscv32" - fi + cpu=3D"riscv" elif check_define __arm__ ; then cpu=3D"arm" elif check_define __aarch64__ ; then @@ -587,7 +583,7 @@ ARCH=3D # Normalise host CPU name and set ARCH. # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64) + ppc|ppc64|s390x|sparc64|x32|riscv) ;; ppc64le) ARCH=3D"ppc64" diff --git a/meson.build b/meson.build index 6b7487b725..1a8fc2c4e0 100644 --- a/meson.build +++ b/meson.build @@ -52,7 +52,7 @@ have_block =3D have_system or have_tools python =3D import('python').find_installation() =20 supported_oses =3D ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', '= sunos', 'linux'] -supported_cpus =3D ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', = 'x86_64', +supported_cpus =3D ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] =20 cpu =3D host_machine.cpu_family() @@ -342,8 +342,6 @@ if not get_option('tcg').disabled() tcg_arch =3D 'i386' elif config_host['ARCH'] =3D=3D 'ppc64' tcg_arch =3D 'ppc' - elif config_host['ARCH'] in ['riscv32', 'riscv64'] - tcg_arch =3D 'riscv' endif add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tc= g_arch, language: ['c', 'cpp', 'objc']) diff --git a/linux-user/host/riscv64/hostdep.h b/linux-user/host/riscv/host= dep.h similarity index 94% rename from linux-user/host/riscv64/hostdep.h rename to linux-user/host/riscv/hostdep.h index 865f0fb9ff..2ba07456ae 100644 --- a/linux-user/host/riscv64/hostdep.h +++ b/linux-user/host/riscv/hostdep.h @@ -5,8 +5,8 @@ * See the COPYING file in the top-level directory. */ =20 -#ifndef RISCV64_HOSTDEP_H -#define RISCV64_HOSTDEP_H +#ifndef RISCV_HOSTDEP_H +#define RISCV_HOSTDEP_H =20 /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL diff --git a/linux-user/host/riscv32/hostdep.h b/linux-user/host/riscv32/ho= stdep.h deleted file mode 100644 index adf9edbf2d..0000000000 --- a/linux-user/host/riscv32/hostdep.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef RISCV32_HOSTDEP_H -#define RISCV32_HOSTDEP_H - -#endif diff --git a/linux-user/host/riscv64/safe-syscall.inc.S b/linux-user/host/r= iscv/safe-syscall.inc.S similarity index 100% rename from linux-user/host/riscv64/safe-syscall.inc.S rename to linux-user/host/riscv/safe-syscall.inc.S --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271502326900.1632396791414; Thu, 14 Oct 2021 21:18:22 -0700 (PDT) Received: from localhost ([::1]:43958 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEfk-0004Nu-VZ for importer@patchew.org; Fri, 15 Oct 2021 00:18:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYj-0006nY-Da for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:05 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:42654) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYe-00007j-Sq for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:05 -0400 Received: by mail-pg1-x529.google.com with SMTP id 66so7427845pgc.9 for ; Thu, 14 Oct 2021 21:11:00 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:10:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A9mkVrBs8KkxTXk1PYgQKfRHS5p1nm/1r22NtGvkuhs=; b=LzliRjNYDdOsxA/c9NGwIFQJfFDE7aO7DwVsTbt7JLT5VYBSA6+0JY3pFdQPcAHQEu Wd5QuK6KwWQ5IbUnM9rf9xynkwpWrcX3gXg8uO2mrWfBQ8vgP0eSJwHs1uYnvy9dMht4 Ed6/ZGj+pK4NVmDMZ7rMEZ8FzPpEuO2Hqzoo851XjWX2wckvIxUXG6YuyUuuJ9gZ47YW tjvmp6s50QgV3tdib0WH7vums1uD4kC3J4N5fZTD2rZMtmzb9Ez6FudvOFUEDXW9/kzO rz86vaGdR2llfxh7lJ7/zAHWYX77jgYZgLVyDD/gg89e8h2vQrLYRExIPTyz4P2ujkcG 8HRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A9mkVrBs8KkxTXk1PYgQKfRHS5p1nm/1r22NtGvkuhs=; b=y3VKEt4kD3WR9sVlUDJyKbBcbjR76GoLdUGrPIUYey6elwQTcpaAPobiUe9wrSqfmP 92h6A7VKFZ9GPNkF3OpRcnW1ZhKL3rZJWqrUEzXIsIegN5pshHxbOFPl53hKu+LP87m7 7oT7SYGnvvx+aXkueWihTNnlsGPChGJ/DmuZ2F6qwB2Na0vKLeo/E3r/hFdZ70ilkgBr w+vJCKIjiebr94yZjIC/CNAX7WYhF+jA/tazMjg/2VUDX5qnQauiSO/dTnrDpL1dazPj VwCWKVayj3BTUzxRYPPo7rbShuEWA+6otwQtexpw7wxiR0QMr5pD4vVSeCLlqOpr9xfe Ct3A== X-Gm-Message-State: AOAM532TGNpswZ9iW0eB2b1k9iqai6AedfueVOC3QAJBxSjSMNJHjxU/ YNkr/KduwulwJmC99cRDVfmYCf8jrqD8BA== X-Google-Smtp-Source: ABdhPJwpBNlgmvuWD6b2+nBYMHHVs/Gc1UYiXG0oDcBW3Y6my31yQXuYQAqXr3TPSAKHJ7k11hD+8A== X-Received: by 2002:a05:6a00:22d1:b0:44c:f752:a216 with SMTP id f17-20020a056a0022d100b0044cf752a216mr9108375pfj.45.1634271059437; Thu, 14 Oct 2021 21:10:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 06/67] linux-user: Reorg handling for SIGSEGV Date: Thu, 14 Oct 2021 21:09:52 -0700 Message-Id: <20211015041053.2769193-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271504384100007 Add stub host-signal.h for all linux-user hosts. Add new code replacing cpu_signal_handler. Full migration will happen one host at a time. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 1 + linux-user/host/arm/host-signal.h | 1 + linux-user/host/i386/host-signal.h | 1 + linux-user/host/mips/host-signal.h | 1 + linux-user/host/ppc/host-signal.h | 1 + linux-user/host/ppc64/host-signal.h | 1 + linux-user/host/riscv/host-signal.h | 1 + linux-user/host/s390/host-signal.h | 1 + linux-user/host/s390x/host-signal.h | 1 + linux-user/host/sparc/host-signal.h | 1 + linux-user/host/sparc64/host-signal.h | 1 + linux-user/host/x32/host-signal.h | 1 + linux-user/host/x86_64/host-signal.h | 1 + linux-user/signal.c | 109 ++++++++++++++++++++++---- 14 files changed, 106 insertions(+), 16 deletions(-) create mode 100644 linux-user/host/aarch64/host-signal.h create mode 100644 linux-user/host/arm/host-signal.h create mode 100644 linux-user/host/i386/host-signal.h create mode 100644 linux-user/host/mips/host-signal.h create mode 100644 linux-user/host/ppc/host-signal.h create mode 100644 linux-user/host/ppc64/host-signal.h create mode 100644 linux-user/host/riscv/host-signal.h create mode 100644 linux-user/host/s390/host-signal.h create mode 100644 linux-user/host/s390x/host-signal.h create mode 100644 linux-user/host/sparc/host-signal.h create mode 100644 linux-user/host/sparc64/host-signal.h create mode 100644 linux-user/host/x32/host-signal.h create mode 100644 linux-user/host/x86_64/host-signal.h diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch6= 4/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/aarch64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-s= ignal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/arm/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host= -signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/i386/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host= -signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/mips/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-s= ignal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/ho= st-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/ho= st-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/riscv/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host= -signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/ho= st-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390x/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/ho= st-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc6= 4/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-s= ignal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x32/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/= host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x86_64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/signal.c b/linux-user/signal.c index 14d8fdfde1..6900acb122 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/bitops.h" #include "exec/gdbstub.h" +#include "hw/core/tcg-cpu-ops.h" =20 #include #include @@ -29,6 +30,7 @@ #include "loader.h" #include "trace.h" #include "signal-common.h" +#include "host-signal.h" =20 static struct target_sigaction sigact_table[TARGET_NSIG]; =20 @@ -769,41 +771,116 @@ static inline void rewind_if_in_safe_syscall(void *p= uc) } #endif =20 -static void host_signal_handler(int host_signum, siginfo_t *info, - void *puc) +static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) { CPUArchState *env =3D thread_cpu->env_ptr; CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; - - int sig; target_siginfo_t tinfo; ucontext_t *uc =3D puc; struct emulated_sigtable *k; + int guest_sig; =20 +#ifdef HOST_SIGNAL_PLACEHOLDER /* the CPU emulator uses some host signals to detect exceptions, we forward to it some signals */ - if ((host_signum =3D=3D SIGSEGV || host_signum =3D=3D SIGBUS) + if ((host_sig =3D=3D SIGSEGV || host_sig =3D=3D SIGBUS) && info->si_code > 0) { - if (cpu_signal_handler(host_signum, info, puc)) + if (cpu_signal_handler(host_sig, info, puc)) { return; + } } +#else + uintptr_t pc =3D 0; + bool sync_sig =3D false; + + /* + * Non-spoofed SIGSEGV and SIGBUS are synchronous, and need special + * handling wrt signal blocking and unwinding. + */ + if ((host_sig =3D=3D SIGSEGV || host_sig =3D=3D SIGBUS) && info->si_co= de > 0) { + MMUAccessType access_type; + uintptr_t host_addr; + abi_ptr guest_addr; + bool is_write; + + host_addr =3D (uintptr_t)info->si_addr; + + /* + * Convert forcefully to guest address space: addresses outside + * reserved_va are still valid to report via SEGV_MAPERR. + */ + guest_addr =3D h2g_nocheck(host_addr); + + pc =3D host_signal_pc(uc); + is_write =3D host_signal_write(info, uc); + access_type =3D adjust_signal_pc(&pc, is_write); + + if (host_sig =3D=3D SIGSEGV) { + const struct TCGCPUOps *tcg_ops; + + if (info->si_code =3D=3D SEGV_ACCERR && h2g_valid(host_addr)) { + /* If this was a write to a TB protected page, restart. */ + if (is_write && + handle_sigsegv_accerr_write(cpu, &uc->uc_sigmask, + pc, guest_addr)) { + return; + } + + /* + * With reserved_va, the whole address space is PROT_NONE, + * which means that we may get ACCERR when we want MAPERR. + */ + if (page_get_flags(guest_addr) & PAGE_VALID) { + /* maperr =3D false; */ + } else { + info->si_code =3D SEGV_MAPERR; + } + } + + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + + tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, + MMU_USER_IDX, false, pc); + g_assert_not_reached(); + } else { + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + } + + sync_sig =3D true; + } +#endif =20 /* get target signal number */ - sig =3D host_to_target_signal(host_signum); - if (sig < 1 || sig > TARGET_NSIG) + guest_sig =3D host_to_target_signal(host_sig); + if (guest_sig < 1 || guest_sig > TARGET_NSIG) { return; - trace_user_host_signal(env, host_signum, sig); + } + trace_user_host_signal(env, host_sig, guest_sig); + + host_to_target_siginfo_noswap(&tinfo, info); + k =3D &ts->sigtab[guest_sig - 1]; + k->info =3D tinfo; + k->pending =3D guest_sig; + ts->signal_pending =3D 1; + +#ifndef HOST_SIGNAL_PLACEHOLDER + /* + * For synchronous signals, unwind the cpu state to the faulting + * insn and then exit back to the main loop so that the signal + * is delivered immediately. + */ + if (sync_sig) { + cpu->exception_index =3D EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, pc); + } +#endif =20 rewind_if_in_safe_syscall(puc); =20 - host_to_target_siginfo_noswap(&tinfo, info); - k =3D &ts->sigtab[sig - 1]; - k->info =3D tinfo; - k->pending =3D sig; - ts->signal_pending =3D 1; - - /* Block host signals until target signal handler entered. We + /* + * Block host signals until target signal handler entered. We * can't block SIGSEGV or SIGBUS while we're executing guest * code in case the guest code provokes one in the window between * now and it getting out to the main loop. Signals will be --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271502134586.8244753778862; Thu, 14 Oct 2021 21:18:22 -0700 (PDT) Received: from localhost ([::1]:43876 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEfk-0004Kt-Sx for importer@patchew.org; Fri, 15 Oct 2021 00:18:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38700) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYh-0006js-IM for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:03 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:45634) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYf-00008T-Hk for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:03 -0400 Received: by mail-pl1-x629.google.com with SMTP id s1so3778728plg.12 for ; Thu, 14 Oct 2021 21:11:01 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.10.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:10:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wzln/o2XfkekbyzBBOI7m5kdlAVyzk60/sywPn/m1vM=; b=mPnWzmZVnHWYkIxbgNTb8MUhag1MYGh6i2euExc/Y4f6URfsamntIBvGu9pp7+Q7h0 LFFRxeLT7vDnex+74ErhuQQ0MuKcb9fio1R9gtwdwXSNogEkbcZOyGHBsklrRj7LFJKJ wOHPwDkwartv6bQlGDTBJOybnP94FijRVTa+XgL7/zdJvz3kV1HpE771uhI0i4zK2o+O WotcA5toufANlumsf4s/7HDlcn5b+xFL5GnjQPCWMqLuVfo0Cg/Els6VACNKBPuUuiOJ vN4INObUmueeZTRfv1yyIkAKDU9o/2Vphjy1PYWPA4qnQmwDMsvj5qiZfLvn73McwKwF nQaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wzln/o2XfkekbyzBBOI7m5kdlAVyzk60/sywPn/m1vM=; b=3RnQmPYYyjHFrOc3LiyonrrynLdXen54T7MgD6T8Nhv0T7HSspnP/VE7OswrV/GfQt ZfeZdFNI0ckAVKxUjmSV5O7qwUC+9nD8tg5nPLVyQ6FHmCVUWFKZyjxRNZwF4S0LlKo3 I+us9+82JpssPaKIrURY2lb0LClPtTiDHsm0B5VbaLZlzObBej0/LbkMlSk52In/fsOJ 5M1Tn+yRQiLnEmvU0mTCvxTPfVWTdyUGubL+joKzsw27cNl4mTSSRIrIjv+mk5OtdEQ8 w85B233OSuUwZk+kKNZFe6clDt89+pv3rqNDVzFb14mJ1GbYBR64jVzuReC5n4SULzeL /BAg== X-Gm-Message-State: AOAM533i3fDh9sLuLR1Ukpgpj0dUFmVie/0YZFcY5FAOwFcMz6VIr2mW 0BS0LH9m8QJ+QUUOjAtJzg6q125qW3uf5w== X-Google-Smtp-Source: ABdhPJwGNLVjT9oApiSvcevjTZYxwL/y+HXti5+DOHBYRpUOB5rNKJJjBW8U/9mthDuT0UxRwvdiOg== X-Received: by 2002:a17:902:ab17:b0:13e:b2e0:58b with SMTP id ik23-20020a170902ab1700b0013eb2e0058bmr9004421plb.9.1634271060073; Thu, 14 Oct 2021 21:11:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 07/67] linux-user/host/x86: Populate host_signal.h Date: Thu, 14 Oct 2021 21:09:53 -0700 Message-Id: <20211015041053.2769193-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271504297100003 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- linux-user/host/i386/host-signal.h | 25 ++++- linux-user/host/x32/host-signal.h | 2 +- linux-user/host/x86_64/host-signal.h | 25 ++++- accel/tcg/user-exec.c | 136 +-------------------------- 4 files changed, 50 insertions(+), 138 deletions(-) diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host= -signal.h index f4b4d65031..ccbbee5082 100644 --- a/linux-user/host/i386/host-signal.h +++ b/linux-user/host/i386/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef I386_HOST_SIGNAL_H +#define I386_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_EIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] =3D=3D 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-s= ignal.h index f4b4d65031..26800591d3 100644 --- a/linux-user/host/x32/host-signal.h +++ b/linux-user/host/x32/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../x86_64/host-signal.h" diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/= host-signal.h index f4b4d65031..883d2fcf65 100644 --- a/linux-user/host/x86_64/host-signal.h +++ b/linux-user/host/x86_64/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef X86_64_HOST_SIGNAL_H +#define X86_64_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_RIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] =3D=3D 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 744af19397..474cb9cf82 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -29,19 +29,6 @@ #include "trace/trace-root.h" #include "internal.h" =20 -#undef EAX -#undef ECX -#undef EDX -#undef EBX -#undef ESP -#undef EBP -#undef ESI -#undef EDI -#undef EIP -#ifdef __linux__ -#include -#endif - __thread uintptr_t helper_retaddr; =20 //#define DEBUG_SIGNAL @@ -268,123 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong ad= dr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__i386__) - -#if defined(__NetBSD__) -#include -#include - -#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_e= ip)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define EIP_sig(context) ((context)->sc_eip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc =3D puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc =3D puc; -#else - ucontext_t *uc =3D puc; -#endif - unsigned long pc; - int trapno; - -#ifndef REG_EIP -/* for glibc 2.1 */ -#define REG_EIP EIP -#define REG_ERR ERR -#define REG_TRAPNO TRAPNO -#endif - pc =3D EIP_sig(uc); - trapno =3D TRAP_sig(uc); - return handle_cpu_signal(pc, info, - trapno =3D=3D PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(__x86_64__) - -#ifdef __NetBSD__ -#include -#define PC_sig(context) _UC_MACHINE_PC(context) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define PC_sig(context) ((context)->sc_rip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_ri= p)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - unsigned long pc; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc =3D puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc =3D puc; -#else - ucontext_t *uc =3D puc; -#endif - - pc =3D PC_sig(uc); - return handle_cpu_signal(pc, info, - TRAP_sig(uc) =3D=3D PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(_ARCH_PPC) +#if defined(_ARCH_PPC) =20 /*********************************************************************** * signal context platform-specific definitions @@ -895,11 +766,6 @@ int cpu_signal_handler(int host_signum, void *pinfo, =20 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } - -#else - -#error host CPU specific signal handler needed - #endif =20 /* The softmmu versions of these helpers are in cputlb.c. */ --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271502521369.81081905335566; Thu, 14 Oct 2021 21:18:22 -0700 (PDT) Received: from localhost ([::1]:43996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEfl-0004PK-Dy for importer@patchew.org; Fri, 15 Oct 2021 00:18:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYm-0006yL-I9 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:08 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:35603) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYj-0000B6-Ew for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:08 -0400 Received: by mail-pf1-x42d.google.com with SMTP id c29so7319846pfp.2 for ; Thu, 14 Oct 2021 21:11:03 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mZJwf7vUbtVzNt6WsxVhQTwK2EfiB3pa1Mn8uyvrhI4=; b=gWmcTobFCd0EJRqpTcf30s/KZwMfLMTvTUd0k1gbTVKI+jOQx/2FugOpJFqLeunKt4 d0FwtPoTDeBZRI+m/nUlYnsXDICe5eksAEedefTeJfOmqbPBr/UbdhBRVC7QN31pz0XA pnCuHF9rYAg6Os7z7Irg95CpOGbbXKPJ0nDamJtqNG63dyZtixNNxRv/tldnZMH9oEnW qRQEgGoDZ1wbiKbxUJhKouk8WkV2KOqmMaAT00Bb9tAcv1f2ytwPd25EE/Y/SotLBMvV QelRouqiKNCBBlWJDctTTQC13EP8SDqYTyNee5cIVbxv0FXCcbaIEgPUxrbN140WpnBX /RzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mZJwf7vUbtVzNt6WsxVhQTwK2EfiB3pa1Mn8uyvrhI4=; b=uj7fxa4Emwe/EFAR60jQmKK4zXGZn07XEmpZHG5tx5RjUhYfB31Y8ekNJ/IC2WgjSh DSOCVejgBEHP8ajIeZHS9jD2bMkL6SDhxoAKh+9VD07F8tdyPIn+oQZuVTSWry2l5866 CXy88NGoRYpybVPFQGNimLo3tb96p8mnZrcvIXgbTTDzkfBkWb7z6HOwr+FUYZTx3OW4 ZwaiYonVsg/IDM5zC7yrSu6ubf8+5UkEgK0nT37PL7wyKU3V2N01934Smc6At07EuIOx 6YumcpNBWS8879n79a9GfhmQ9RtIpqN59fA/7U/PSbyItIM6hxWVULKO1RXLHCeJiCxj 3a3A== X-Gm-Message-State: AOAM532+tWHKNFdzQt/FiircJ+wgVRkpr0X5hg9mXw+AAbBNllsb8zdm wSs578JNnn308iUmkDe6BdycS9jzcAZhcA== X-Google-Smtp-Source: ABdhPJzV00RNyA3oi5IWOXcxVK6l+ZNohJg/ISm9ynr1Bqkn+pZexIWweDv4IM2hIzgB+urCwxlAAg== X-Received: by 2002:a62:1553:0:b0:44c:67cf:e669 with SMTP id 80-20020a621553000000b0044c67cfe669mr9411921pfv.55.1634271061670; Thu, 14 Oct 2021 21:11:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 08/67] linux-user/host/ppc: Populate host_signal.h Date: Thu, 14 Oct 2021 21:09:54 -0700 Message-Id: <20211015041053.2769193-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271504309100004 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/ppc/host-signal.h | 25 ++++++++- linux-user/host/ppc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 79 +---------------------------- 3 files changed, 26 insertions(+), 80 deletions(-) diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-s= ignal.h index f4b4d65031..e09756c691 100644 --- a/linux-user/host/ppc/host-signal.h +++ b/linux-user/host/ppc/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef PPC_HOST_SIGNAL_H +#define PPC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.regs->nip; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.regs->trap !=3D 0x400 + && (uc->uc_mcontext.regs->dsisr & 0x02000000); +} + +#endif diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/ho= st-signal.h index f4b4d65031..a353c22a90 100644 --- a/linux-user/host/ppc64/host-signal.h +++ b/linux-user/host/ppc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../ppc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 474cb9cf82..e0cc765069 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,84 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(_ARCH_PPC) - -/*********************************************************************** - * signal context platform-specific definitions - * From Wine - */ -#ifdef linux -/* All Registers access - only for local access */ -#define REG_sig(reg_name, context) \ - ((context)->uc_mcontext.regs->reg_name) -/* Gpr Registers access */ -#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], conte= xt) -/* Program counter */ -#define IAR_sig(context) REG_sig(nip, context) -/* Machine State Register (Supervisor) */ -#define MSR_sig(context) REG_sig(msr, context) -/* Count register */ -#define CTR_sig(context) REG_sig(ctr, context) -/* User's integer exception register */ -#define XER_sig(context) REG_sig(xer, context) -/* Link register */ -#define LR_sig(context) REG_sig(link, context) -/* Condition register */ -#define CR_sig(context) REG_sig(ccr, context) - -/* Float Registers access */ -#define FLOAT_sig(reg_num, context) \ - (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) -#define FPSCR_sig(context) \ - (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) -/* Exception Registers access */ -#define DAR_sig(context) REG_sig(dar, context) -#define DSISR_sig(context) REG_sig(dsisr, context) -#define TRAP_sig(context) REG_sig(trap, context) -#endif /* linux */ - -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) -#include -#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) -#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) -#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) -#define XER_sig(context) ((context)->uc_mcontext.mc_xer) -#define LR_sig(context) ((context)->uc_mcontext.mc_lr) -#define CR_sig(context) ((context)->uc_mcontext.mc_cr) -/* Exception Registers access */ -#define DAR_sig(context) ((context)->uc_mcontext.mc_dar) -#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) -#endif /* __FreeBSD__|| __FreeBSD_kernel__ */ - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) - ucontext_t *uc =3D puc; -#else - ucontext_t *uc =3D puc; -#endif - unsigned long pc; - int is_write; - - pc =3D IAR_sig(uc); - is_write =3D 0; -#if 0 - /* ppc 4xx case */ - if (DSISR_sig(uc) & 0x00800000) { - is_write =3D 1; - } -#else - if (TRAP_sig(uc) !=3D 0x400 && (DSISR_sig(uc) & 0x02000000)) { - is_write =3D 1; - } -#endif - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__alpha__) +#if defined(__alpha__) =20 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271655802473.77449132297454; Thu, 14 Oct 2021 21:20:55 -0700 (PDT) Received: from localhost ([::1]:52434 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEiE-0001aB-Hs for importer@patchew.org; Fri, 15 Oct 2021 00:20:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38780) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYn-00071e-Nh for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:09 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:36383) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYk-0000Bi-0j for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:09 -0400 Received: by mail-pg1-x534.google.com with SMTP id 75so7458788pga.3 for ; Thu, 14 Oct 2021 21:11:05 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BJUdaZcFQkGn0Ur44U4wi+Gizq9wqvJWic/PiqjpH80=; b=H8DucyRdyFs7Dzgt2Ow6Ng+qQogi/7hnlrrEBhxFn7AhnvPexNFAl5g9sLDV+rwNL7 GNhhN5y8dVC8Zy1ilbb99b//lxDSIU6EBJyfWCQYBAOdKacWZrlmrVaFqa0Ik+oFLXh/ eg62JbYJx4hTxYtq+A7McCMjEz2+GtE9yh8On/HICZ/TRvQv4eBWnZ9yi3i/dQm72cgQ oaQLNos4sbWkmLhZQsudIuKOuFmlIOAUEWTwG4oyNi+gJO9NxkpSNsiMtE8cUjgppa1X KJCGTJHU1wQVwmSetX0XsgJTjUSilwHZMoH+e4q3BZf6n+6WsMApqPMh04pCFDyzvESu FIkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BJUdaZcFQkGn0Ur44U4wi+Gizq9wqvJWic/PiqjpH80=; b=Pip/6Ag3bzMO/E+Vc+SquTluMFrFHmAfrEigo6B9Q0o6lD+ZGGPR9lj4vFFqU65Y1r GuzTyszG51gNZhnjCuuPGdxWVeZutibPwP7Ml1lRSLi77k8xhg2PMmZK62PJr6csEfnt HGMUYqn8jQ85BM7p0f4K34uSWDii4rRw23bMZfwz15ZzQEDBb6fGyNwpdOe3f+UlSfTa RnKrKUUxGGl/XA/Iyi29QqcrQZtqdRfW59qkoa8ue172CqkBzpuuOgIxq532wjkd/Ohm oW/3O3DPMKUOxFYkKXPuX3SIwl95udW2pKxa3kW44+BHVokoLW7YW0mcJcGTOovljIRP cqXw== X-Gm-Message-State: AOAM532dBnZX/bFPIwPgIxqEzrugJRmbbBvO7PWieY8FBnRPeeXrTIAB 8vzyL6xcr4aPeWmMW2+JtuW0BxCrlG4Mhw== X-Google-Smtp-Source: ABdhPJzpX965P36+jPZiwOQOSw/JXlsSVaSxNpgk9Sjg3kudw9avthD23z4ghF1T4Qm9Qr8tqyzh0Q== X-Received: by 2002:aa7:9542:0:b0:44c:6db9:f596 with SMTP id w2-20020aa79542000000b0044c6db9f596mr9437073pfq.21.1634271063536; Thu, 14 Oct 2021 21:11:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 09/67] linux-user/host/alpha: Populate host_signal.h Date: Thu, 14 Oct 2021 21:09:55 -0700 Message-Id: <20211015041053.2769193-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271657571100001 Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/host/alpha/host-signal.h | 41 +++++++++++++++++++++++++++++ accel/tcg/user-exec.c | 31 +--------------------- 2 files changed, 42 insertions(+), 30 deletions(-) create mode 100644 linux-user/host/alpha/host-signal.h diff --git a/linux-user/host/alpha/host-signal.h b/linux-user/host/alpha/ho= st-signal.h new file mode 100644 index 0000000000..e27704d832 --- /dev/null +++ b/linux-user/host/alpha/host-signal.h @@ -0,0 +1,41 @@ +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ALPHA_HOST_SIGNAL_H +#define ALPHA_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.sc_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t *pc =3D (uint32_t *)host_signal_pc(uc); + uint32_t insn =3D *pc; + + /* XXX: need kernel patch to get write flag faster */ + switch (insn >> 26) { + case 0x0d: /* stw */ + case 0x0e: /* stb */ + case 0x0f: /* stq_u */ + case 0x24: /* stf */ + case 0x25: /* stg */ + case 0x26: /* sts */ + case 0x27: /* stt */ + case 0x2c: /* stl */ + case 0x2d: /* stq */ + case 0x2e: /* stl_c */ + case 0x2f: /* stq_c */ + return true; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e0cc765069..0db3c5cf3c 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,36 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__alpha__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - uint32_t *pc =3D uc->uc_mcontext.sc_pc; - uint32_t insn =3D *pc; - int is_write =3D 0; - - /* XXX: need kernel patch to get write flag faster */ - switch (insn >> 26) { - case 0x0d: /* stw */ - case 0x0e: /* stb */ - case 0x0f: /* stq_u */ - case 0x24: /* stf */ - case 0x25: /* stg */ - case 0x26: /* sts */ - case 0x27: /* stt */ - case 0x2c: /* stl */ - case 0x2d: /* stq */ - case 0x2e: /* stl_c */ - case 0x2f: /* stq_c */ - is_write =3D 1; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#elif defined(__sparc__) +#if defined(__sparc__) =20 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271321916281.8810400470005; Thu, 14 Oct 2021 21:15:21 -0700 (PDT) Received: from localhost ([::1]:35380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEcq-0006wo-Og for importer@patchew.org; Fri, 15 Oct 2021 00:15:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYl-0006wA-V2 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:07 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:40699) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYj-0000Ch-Ux for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:07 -0400 Received: by mail-pl1-x635.google.com with SMTP id v20so5592585plo.7 for ; Thu, 14 Oct 2021 21:11:05 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eZX7omI0tPPRPhD891DSXxNdsSqSoW7wps3jDTVHJCM=; b=lWSV+ihwzI0o0pFCII1olUxyGiYKqp7q4SiXIaK0czjck5LUuovV59k2c3dGJIfAFv wJ4/lcX8lakaC9twYQcEJp5x0/8x4Ta0r+iciiPehIOruDLqO4vgPSlO2CPXOK7ARuwI d/b4UbgTlTiuJCQUuYDMqR8l+5YwIYfn1agobvPxrkh1Xf1+IoHx4z/QYxVP+yxD6+Tf xRWszafOAWzglJJDKYNbxNVg0LfeWhckOZVgd6uCWKNRkTuLMM6RoccXF65YcXkFPe2w 5MsVXTT0e05KV9frkS49VLVzj6wUB66C5wfcP2NaDMl01THY5mqF1/us4xd3cGQEm7cU kEUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eZX7omI0tPPRPhD891DSXxNdsSqSoW7wps3jDTVHJCM=; b=2ayuPKaPQWp/5pNR6vZmtK/lu7i8TGdXcixHdigDpJ12RvIrNAyf2AKv9gBkTCTrpz vzmBD0d/r/fuKzVxe2UKG/ILN3RwzUTdEXGv4GGubtkg/BAfDmSPPuNpMG69AOmw8SCp zXPoCdDHNnP1bXhR6p8d8q/F4hUpOlaIBdPHXsoVT748ba5qBpXuGW6NSXn2OoLBrXKt nIDIdO3hzj5JpdN9tD2l0izALaAa6owJTzlUcyDyRWsAZB5Z4W0abOSJjOx1Q6ICdVCh p2zvF+JJvH6DMoO0/ck7+dISsR5+bjDBcHffw14f47nQ5Lb6K+BhtAugpmx74jxMZn03 REaw== X-Gm-Message-State: AOAM530efvaLVmzEVPnqjgh40Sfp2rfKo597W7KSgNh8ZRkh66RqUsAw dnNQJiRqA5A5rGpMICWu+9zPwqqNAoBEfw== X-Google-Smtp-Source: ABdhPJz+VvBKOzeY69yYPYg3gGbVQmGYEf4SCvks9+/L7SG8dCIxvKH4hcVqFXo4mSh0ZimlpyWcGg== X-Received: by 2002:a17:902:fe83:b0:13f:5415:2710 with SMTP id x3-20020a170902fe8300b0013f54152710mr8850968plm.16.1634271064464; Thu, 14 Oct 2021 21:11:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 10/67] linux-user/host/sparc: Populate host_signal.h Date: Thu, 14 Oct 2021 21:09:56 -0700 Message-Id: <20211015041053.2769193-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271322885100006 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Drop the Solaris code as completely unused. Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- linux-user/host/sparc/host-signal.h | 54 ++++++++++++++++++++++- linux-user/host/sparc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 62 +-------------------------- 3 files changed, 55 insertions(+), 63 deletions(-) diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/ho= st-signal.h index f4b4d65031..232943a1db 100644 --- a/linux-user/host/sparc/host-signal.h +++ b/linux-user/host/sparc/host-signal.h @@ -1 +1,53 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef SPARC_HOST_SIGNAL_H +#define SPARC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ +#ifdef __arch64__ + return uc->uc_mcontext.mc_gregs[MC_PC]; +#else + return uc->uc_mcontext.gregs[REG_PC]; +#endif +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn =3D *(uint32_t *)host_signal_pc(uc); + + if ((insn >> 30) =3D=3D 3) { + switch ((insn >> 19) & 0x3f) { + case 0x05: /* stb */ + case 0x15: /* stba */ + case 0x06: /* sth */ + case 0x16: /* stha */ + case 0x04: /* st */ + case 0x14: /* sta */ + case 0x07: /* std */ + case 0x17: /* stda */ + case 0x0e: /* stx */ + case 0x1e: /* stxa */ + case 0x24: /* stf */ + case 0x34: /* stfa */ + case 0x27: /* stdf */ + case 0x37: /* stdfa */ + case 0x26: /* stqf */ + case 0x36: /* stqfa */ + case 0x25: /* stfsr */ + case 0x3c: /* casa */ + case 0x3e: /* casxa */ + return true; + } + } + return false; +} + +#endif diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc6= 4/host-signal.h index f4b4d65031..1191fe2d40 100644 --- a/linux-user/host/sparc64/host-signal.h +++ b/linux-user/host/sparc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../sparc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0db3c5cf3c..17fe867aeb 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,67 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__sparc__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - int is_write; - uint32_t insn; -#if !defined(__arch64__) || defined(CONFIG_SOLARIS) - uint32_t *regs =3D (uint32_t *)(info + 1); - void *sigmask =3D (regs + 20); - /* XXX: is there a standard glibc define ? */ - unsigned long pc =3D regs[1]; -#else -#ifdef __linux__ - struct sigcontext *sc =3D puc; - unsigned long pc =3D sc->sigc_regs.tpc; - void *sigmask =3D (void *)sc->sigc_mask; -#elif defined(__OpenBSD__) - struct sigcontext *uc =3D puc; - unsigned long pc =3D uc->sc_pc; - void *sigmask =3D (void *)(long)uc->sc_mask; -#elif defined(__NetBSD__) - ucontext_t *uc =3D puc; - unsigned long pc =3D _UC_MACHINE_PC(uc); - void *sigmask =3D (void *)&uc->uc_sigmask; -#endif -#endif - - /* XXX: need kernel patch to get write flag faster */ - is_write =3D 0; - insn =3D *(uint32_t *)pc; - if ((insn >> 30) =3D=3D 3) { - switch ((insn >> 19) & 0x3f) { - case 0x05: /* stb */ - case 0x15: /* stba */ - case 0x06: /* sth */ - case 0x16: /* stha */ - case 0x04: /* st */ - case 0x14: /* sta */ - case 0x07: /* std */ - case 0x17: /* stda */ - case 0x0e: /* stx */ - case 0x1e: /* stxa */ - case 0x24: /* stf */ - case 0x34: /* stfa */ - case 0x27: /* stdf */ - case 0x37: /* stdfa */ - case 0x26: /* stqf */ - case 0x36: /* stqfa */ - case 0x25: /* stfsr */ - case 0x3c: /* casa */ - case 0x3e: /* casxa */ - is_write =3D 1; - break; - } - } - return handle_cpu_signal(pc, info, is_write, sigmask); -} - -#elif defined(__arm__) +#if defined(__arm__) =20 #if defined(__NetBSD__) #include --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271318878549.1282790020387; Thu, 14 Oct 2021 21:15:18 -0700 (PDT) Received: from localhost ([::1]:35208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEcn-0006ow-Rw for importer@patchew.org; Fri, 15 Oct 2021 00:15:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38804) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYo-00073Q-Mr for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:10 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:42658) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYk-0000DH-JJ for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:09 -0400 Received: by mail-pg1-x52d.google.com with SMTP id 66so7428043pgc.9 for ; Thu, 14 Oct 2021 21:11:06 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=btQGr7frnhamoWbiryuObxAGescEK943qi/jomZ8OHU=; b=LOcVIOc75Hq+kR/jqzxLv5knGddqUvREHUK6bsG3NLRWE9o3j+QZK1RHv0uvJToLrH CdUxeuflbLSg1BNaxg0kZ4X5fCJuwgqrQLAbNj54PgmNFoLqMBZ1DvBlrJQcMoUTgwxM GbO3jmlbu4oG7XJ65ErxtnlT2l67JJUcVCgdGWMYQJZPQE1A/ztDKgNAYjdgcMtBoU2i I6l8E0wPG8BDTyCLbfQUhjiICslS5b5w+XHeSFFoCnShnSA2L3Ib0S8ZCwnxmZic/l7K J4281W028D40ps8IctR74UUa6fYYXUT2a4Tcs/bSJKKSlkB1RZjjZqE6S/4Ji7eYyHxW hvmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=btQGr7frnhamoWbiryuObxAGescEK943qi/jomZ8OHU=; b=yIKneaH1BPcYmVif+aPLAG/C+XMvnOWHGwpKm+XoNfRCjdLeDGR2NIubg7F8Xpi1He ouKnSG+DJmmhk/bj03rUgRHnBXcHdo6hMS3K8Kql3sKru3H3CvYohcefKfhhg99YPnHx HXf27FVQyK7RZPj5yOBII/S9+3T8KLSMVjcYCTxA78d/HoF90OXSFBplxSiKBaEdj9Fr 2UtqhUQVPVs1NYjEsCPmsqghc1YI0IR/UZkXaSc2BTX0dy+jb0p57CQ4Lj+kmo60S6RP stEHA/80xtWgeMJ26Bl7OM0If16aATg51EpocYWCcrtz5CmgFMPXSD5aoMv9njbS+vfL LESg== X-Gm-Message-State: AOAM5333+VnuIo8aYXnVqE+VApyvnPICtf2mI6N0aEbJBI0IHoY9+K8b 2vlZEwz8Yd1THtk7Qv3MwYTgOq4AkyI= X-Google-Smtp-Source: ABdhPJxHaa2boBPAIGU8yIZJKb5QqWxuUwVIz/Z5swFFzMtaFs9U8XZuzHXspzgx5QNDOMprqOijVA== X-Received: by 2002:a63:2a92:: with SMTP id q140mr7429126pgq.412.1634271065178; Thu, 14 Oct 2021 21:11:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 11/67] linux-user/host/arm: Populate host_signal.h Date: Thu, 14 Oct 2021 21:09:57 -0700 Message-Id: <20211015041053.2769193-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271320849100001 Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- linux-user/host/arm/host-signal.h | 30 ++++++++++++++++++++- accel/tcg/user-exec.c | 45 +------------------------------ 2 files changed, 30 insertions(+), 45 deletions(-) diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-s= ignal.h index f4b4d65031..6932224c1c 100644 --- a/linux-user/host/arm/host-signal.h +++ b/linux-user/host/arm/host-signal.h @@ -1 +1,29 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ARM_HOST_SIGNAL_H +#define ARM_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.arm_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + /* + * In the FSR, bit 11 is WnR, assuming a v6 or + * later processor. On v5 we will always report + * this as a read, which will fail later. + */ + uint32_t fsr =3D uc->uc_mcontext.error_code; + return extract32(fsr, 11, 1); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 17fe867aeb..5656c654e1 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,50 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__arm__) - -#if defined(__NetBSD__) -#include -#include -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; -#if defined(__NetBSD__) - ucontext_t *uc =3D puc; - siginfo_t *si =3D pinfo; -#else - ucontext_t *uc =3D puc; -#endif - unsigned long pc; - uint32_t fsr; - int is_write; - -#if defined(__NetBSD__) - pc =3D uc->uc_mcontext.__gregs[_REG_R15]; -#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ =3D=3D 2 && __GLI= BC_MINOR__ <=3D 3)) - pc =3D uc->uc_mcontext.gregs[R15]; -#else - pc =3D uc->uc_mcontext.arm_pc; -#endif - -#ifdef __NetBSD__ - fsr =3D si->si_trap; -#else - fsr =3D uc->uc_mcontext.error_code; -#endif - /* - * In the FSR, bit 11 is WnR, assuming a v6 or - * later processor. On v5 we will always report - * this as a read, which will fail later. - */ - is_write =3D extract32(fsr, 11, 1); - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__aarch64__) +#if defined(__aarch64__) =20 #if defined(__NetBSD__) =20 --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271703801442.1022975609137; Thu, 14 Oct 2021 21:21:43 -0700 (PDT) Received: from localhost ([::1]:55662 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEj0-0003k6-RZ for importer@patchew.org; Fri, 15 Oct 2021 00:21:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYp-00074p-2L for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:11 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:45640) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYl-0000Dt-4r for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:10 -0400 Received: by mail-pl1-x62f.google.com with SMTP id s1so3778890plg.12 for ; Thu, 14 Oct 2021 21:11:06 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UZZkbCa2SkEzYuf3z0736s28yeuiumq4AY1dzCd1e9I=; b=cVrD63NqDChG2gle/bJX5ee3Cubsz/ViBK52ZdyducVxDuZsLgZtxo4Hl8cIHRhyw4 JZDRzNOhNhnmpYOPLKpFsFfugolmvCpmOvhgnASIwygLWLkDPCXuhqZvCqn8V25gfoL4 h1zr6FisQ0I7U1rAkI2mtV/F1L3vcJs7JFaWU5eqkt17hBYlY4ooEx+O+ug01qnKfAeX hCqQ9z9hIsl3Vt2LEBGdxQXP8xjO1+A2l5Gi8ZuTgI1V6NDsg3VF+vPkIZmBToAsww2v fvr6WuVs0Y0DJJ/rdrpjtUbP6YmUty9JGMR20qU6XOQeXzKWqQk7My8gZBsu8aQ0OGDX anig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UZZkbCa2SkEzYuf3z0736s28yeuiumq4AY1dzCd1e9I=; b=Gynxz23Ae9PSn0OtMPpJHuep8N0wy+2ADZT9MoJq3V2zYMCCAARHlP7DF+4nQLPqKZ qI3z1zJQiiOiNdNg9lhu3dFP1TEjers5n61YZxlibK/RDMWNOlyynhCtxq+8p5yN6B4P Q58KUTIoS9DZgojgr0Aiw0sL0s8/Lerm9+h19DeNSbTLqrNzUcyjU4/eXA/AK6rIqSiP AGVhjF1va8PX1Y+/doLLxEgaCxZ1bC1/iGKZV1pggtPY8p3U76yE8OHaKgdoNDaJ30/i RJMfbIIYLF4GiOxHCr7nBlf9vTwtGaNFECCpIOfnw4a8WcEsEq8+hNWEnrUth21hYzuo XX9A== X-Gm-Message-State: AOAM533q7GvCxJw04m+ru7UuGm4CNoikUBBX1+kiAhtL0WgIE8DP4ivu 2H/FP/XwHAXqACwuKnjJDh4NSfPvYOc4QQ== X-Google-Smtp-Source: ABdhPJxNQBOC7Qs15XyMa/XAegL5Mea1xOcbMeYnUYANlLrMplYkeuwJ18sqszwWqHjYucfFm1JoTQ== X-Received: by 2002:a17:90a:f292:: with SMTP id fs18mr10561071pjb.229.1634271065783; Thu, 14 Oct 2021 21:11:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 12/67] linux-user/host/aarch64: Populate host_signal.h Date: Thu, 14 Oct 2021 21:09:58 -0700 Message-Id: <20211015041053.2769193-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271705569100001 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- linux-user/host/aarch64/host-signal.h | 74 ++++++++++++++++++++- accel/tcg/user-exec.c | 94 +-------------------------- 2 files changed, 74 insertions(+), 94 deletions(-) diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch6= 4/host-signal.h index f4b4d65031..02a55c3372 100644 --- a/linux-user/host/aarch64/host-signal.h +++ b/linux-user/host/aarch64/host-signal.h @@ -1 +1,73 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef AARCH64_HOST_SIGNAL_H +#define AARCH64_HOST_SIGNAL_H + +/* Pre-3.16 kernel headers don't have these, so provide fallback definitio= ns */ +#ifndef ESR_MAGIC +#define ESR_MAGIC 0x45535201 +struct esr_context { + struct _aarch64_ctx head; + uint64_t esr; +}; +#endif + +static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) +{ + return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; +} + +static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) +{ + return (struct _aarch64_ctx *)((char *)hdr + hdr->size); +} + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + struct _aarch64_ctx *hdr; + uint32_t insn; + + /* Find the esr_context, which has the WnR bit in it */ + for (hdr =3D first_ctx(uc); hdr->magic; hdr =3D next_ctx(hdr)) { + if (hdr->magic =3D=3D ESR_MAGIC) { + struct esr_context const *ec =3D (struct esr_context const *)h= dr; + uint64_t esr =3D ec->esr; + + /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR b= it */ + return extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6, = 1) =3D=3D 1; + } + } + + /* + * Fall back to parsing instructions; will only be needed + * for really ancient (pre-3.16) kernels. + */ + insn =3D *(uint32_t *)host_signal_pc(uc); + + return (insn & 0xbfff0000) =3D=3D 0x0c000000 /* C3.3.1 */ + || (insn & 0xbfe00000) =3D=3D 0x0c800000 /* C3.3.2 */ + || (insn & 0xbfdf0000) =3D=3D 0x0d000000 /* C3.3.3 */ + || (insn & 0xbfc00000) =3D=3D 0x0d800000 /* C3.3.4 */ + || (insn & 0x3f400000) =3D=3D 0x08000000 /* C3.3.6 */ + || (insn & 0x3bc00000) =3D=3D 0x39000000 /* C3.3.13 */ + || (insn & 0x3fc00000) =3D=3D 0x3d800000 /* ... 128bit */ + /* Ignore bits 10, 11 & 21, controlling indexing. */ + || (insn & 0x3bc00000) =3D=3D 0x38000000 /* C3.3.8-12 */ + || (insn & 0x3fe00000) =3D=3D 0x3c800000 /* ... 128bit */ + /* Ignore bits 23 & 24, controlling indexing. */ + || (insn & 0x3a400000) =3D=3D 0x28000000; /* C3.3.7,14-16 */ +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5656c654e1..0915eb7f95 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,99 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__aarch64__) - -#if defined(__NetBSD__) - -#include -#include - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - ucontext_t *uc =3D puc; - siginfo_t *si =3D pinfo; - unsigned long pc; - int is_write; - uint32_t esr; - - pc =3D uc->uc_mcontext.__gregs[_REG_PC]; - esr =3D si->si_trap; - - /* - * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC - * is 0b10010x: then bit 6 is the WnR bit - */ - is_write =3D extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6, 1)= =3D=3D 1; - return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask); -} - -#else - -#ifndef ESR_MAGIC -/* Pre-3.16 kernel headers don't have these, so provide fallback definitio= ns */ -#define ESR_MAGIC 0x45535201 -struct esr_context { - struct _aarch64_ctx head; - uint64_t esr; -}; -#endif - -static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) -{ - return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; -} - -static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) -{ - return (struct _aarch64_ctx *)((char *)hdr + hdr->size); -} - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - uintptr_t pc =3D uc->uc_mcontext.pc; - bool is_write; - struct _aarch64_ctx *hdr; - struct esr_context const *esrctx =3D NULL; - - /* Find the esr_context, which has the WnR bit in it */ - for (hdr =3D first_ctx(uc); hdr->magic; hdr =3D next_ctx(hdr)) { - if (hdr->magic =3D=3D ESR_MAGIC) { - esrctx =3D (struct esr_context const *)hdr; - break; - } - } - - if (esrctx) { - /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ - uint64_t esr =3D esrctx->esr; - is_write =3D extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6= , 1) =3D=3D 1; - } else { - /* - * Fall back to parsing instructions; will only be needed - * for really ancient (pre-3.16) kernels. - */ - uint32_t insn =3D *(uint32_t *)pc; - - is_write =3D ((insn & 0xbfff0000) =3D=3D 0x0c000000 /* C3.3.1 */ - || (insn & 0xbfe00000) =3D=3D 0x0c800000 /* C3.3.2 */ - || (insn & 0xbfdf0000) =3D=3D 0x0d000000 /* C3.3.3 */ - || (insn & 0xbfc00000) =3D=3D 0x0d800000 /* C3.3.4 */ - || (insn & 0x3f400000) =3D=3D 0x08000000 /* C3.3.6 */ - || (insn & 0x3bc00000) =3D=3D 0x39000000 /* C3.3.13 = */ - || (insn & 0x3fc00000) =3D=3D 0x3d800000 /* ... 128b= it */ - /* Ignore bits 10, 11 & 21, controlling indexing. */ - || (insn & 0x3bc00000) =3D=3D 0x38000000 /* C3.3.8-1= 2 */ - || (insn & 0x3fe00000) =3D=3D 0x3c800000 /* ... 128b= it */ - /* Ignore bits 23 & 24, controlling indexing. */ - || (insn & 0x3a400000) =3D=3D 0x28000000); /* C3.3.7,1= 4-16 */ - } - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - -#elif defined(__s390__) +#if defined(__s390__) =20 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271782714979.0344192110013; Thu, 14 Oct 2021 21:23:02 -0700 (PDT) Received: from localhost ([::1]:60938 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEkH-0007JE-M5 for importer@patchew.org; Fri, 15 Oct 2021 00:23:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYp-00076Z-H4 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:11 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:46880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYm-0000EK-6x for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:11 -0400 Received: by mail-pg1-x52a.google.com with SMTP id m21so7413683pgu.13 for ; Thu, 14 Oct 2021 21:11:07 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZrcsdPFY+Q0/rnzaDekoblOXqp3EpRf37OahPazOQjQ=; b=wSRtpghWv6ADMw7WA93ruInRkipr+MT4xA5vd7hwX4lmo+Iz3j3s3MCucc9/JFySU8 pZn/QTW7A5tmyzJECOnYNrOeZYsEQhdnrCIJCAq/z/NPMJMKB/RcN5XclqxqTHFco/f6 +PizEJjQAESbY1XV0nlEMJVJrngQ3c0LUOdm9DLBo4eZo62KD2/ETF42poeqIBx+iBKB d54mSDPAOzaN+O4IWJhpGXN3zKyDTzr77D9efAlo/Ln24QBLFwnDGAl/EGHQeDhE5tOf PDGd45sgHk9JgP71teA6pF8Y1dybq60CaGaw6tqgaa1H1XM5UtJdbaIyOwxgigtV0rSW BE4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZrcsdPFY+Q0/rnzaDekoblOXqp3EpRf37OahPazOQjQ=; b=pjdadSwf5lwcZ5NOTSgaADLqK18OLk5P7mWXum471yvfJ5/4loDoaBCCN2gqkcQlc3 7V9IYsyXvZDOATGy37u3HY25YsM3Rb0sMEC339quOUhvPu8EEFoduvsR7sp1mFqpXc6l aIknzlsCATrdSKy97mXB64QMt1a6s//06TsgQvJRWEuGMndt+p0BK83e6VP9rd2s8Z5L QBJkMRsibeNe6g1t9OnIb7A121beZIrgXX7IRH8mHA62LwyLWH2t/z3Sztg4L0Owfe4u dAMrUiHXYaTT1o17d+nz/SWw6Xa0M7EPoNcSg4Dx6FtmRPqY7TN/cd/i/aQk1dHtBo0J 8dyg== X-Gm-Message-State: AOAM533CsMf1m/K2kMRnpEkHD5sx3gQOTAO9r8li08oGZwO7bCXrqDuS pXYBv8v5XnVEt9J4qsCqCH2C9vzjIwJYPg== X-Google-Smtp-Source: ABdhPJxtIN/7JKAo1kkN5bq5yBL6QR2DulUnNCLL7L/9rImk5Tl5Rd49S113siYaYTRHQ0D/U4mHKw== X-Received: by 2002:a63:36ca:: with SMTP id d193mr7262471pga.73.1634271066659; Thu, 14 Oct 2021 21:11:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 13/67] linux-user/host/s390: Populate host_signal.h Date: Thu, 14 Oct 2021 21:09:59 -0700 Message-Id: <20211015041053.2769193-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271784674100005 Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/host/s390/host-signal.h | 93 ++++++++++++++++++++++++++++- linux-user/host/s390x/host-signal.h | 2 +- accel/tcg/user-exec.c | 88 +-------------------------- 3 files changed, 94 insertions(+), 89 deletions(-) diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host= -signal.h index f4b4d65031..21f59b612a 100644 --- a/linux-user/host/s390/host-signal.h +++ b/linux-user/host/s390/host-signal.h @@ -1 +1,92 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef S390_HOST_SIGNAL_H +#define S390_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.psw.addr; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint16_t *pinsn =3D (uint16_t *)host_signal_pc(uc); + + /* + * ??? On linux, the non-rt signal handler has 4 (!) arguments instead + * of the normal 2 arguments. The 4th argument contains the "Translat= ion- + * Exception Identification for DAT Exceptions" from the hardware (aka + * "int_parm_long"), which does in fact contain the is_write value. + * The rt signal handler, as far as I can tell, does not give this val= ue + * at all. Not that we could get to it from here even if it were. + * So fall back to parsing instructions. Treat read-modify-write ones= as + * writes, which is not fully correct, but for tracking self-modifying= code + * this is better than treating them as reads. Checking si_addr page = flags + * might be a viable improvement, albeit a racy one. + */ + /* ??? This is not even close to complete. */ + switch (pinsn[0] >> 8) { + case 0x50: /* ST */ + case 0x42: /* STC */ + case 0x40: /* STH */ + case 0xba: /* CS */ + case 0xbb: /* CDS */ + return true; + case 0xc4: /* RIL format insns */ + switch (pinsn[0] & 0xf) { + case 0xf: /* STRL */ + case 0xb: /* STGRL */ + case 0x7: /* STHRL */ + return true; + } + break; + case 0xc8: /* SSF format insns */ + switch (pinsn[0] & 0xf) { + case 0x2: /* CSST */ + return true; + } + break; + case 0xe3: /* RXY format insns */ + switch (pinsn[2] & 0xff) { + case 0x50: /* STY */ + case 0x24: /* STG */ + case 0x72: /* STCY */ + case 0x70: /* STHY */ + case 0x8e: /* STPQ */ + case 0x3f: /* STRVH */ + case 0x3e: /* STRV */ + case 0x2f: /* STRVG */ + return true; + } + break; + case 0xeb: /* RSY format insns */ + switch (pinsn[2] & 0xff) { + case 0x14: /* CSY */ + case 0x30: /* CSG */ + case 0x31: /* CDSY */ + case 0x3e: /* CDSG */ + case 0xe4: /* LANG */ + case 0xe6: /* LAOG */ + case 0xe7: /* LAXG */ + case 0xe8: /* LAAG */ + case 0xea: /* LAALG */ + case 0xf4: /* LAN */ + case 0xf6: /* LAO */ + case 0xf7: /* LAX */ + case 0xfa: /* LAAL */ + case 0xf8: /* LAA */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/ho= st-signal.h index f4b4d65031..0e83f9358d 100644 --- a/linux-user/host/s390x/host-signal.h +++ b/linux-user/host/s390x/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../s390/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0915eb7f95..bfd964b578 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,93 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__s390__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - unsigned long pc; - uint16_t *pinsn; - int is_write =3D 0; - - pc =3D uc->uc_mcontext.psw.addr; - - /* - * ??? On linux, the non-rt signal handler has 4 (!) arguments instead - * of the normal 2 arguments. The 4th argument contains the "Translat= ion- - * Exception Identification for DAT Exceptions" from the hardware (aka - * "int_parm_long"), which does in fact contain the is_write value. - * The rt signal handler, as far as I can tell, does not give this val= ue - * at all. Not that we could get to it from here even if it were. - * So fall back to parsing instructions. Treat read-modify-write ones= as - * writes, which is not fully correct, but for tracking self-modifying= code - * this is better than treating them as reads. Checking si_addr page = flags - * might be a viable improvement, albeit a racy one. - */ - /* ??? This is not even close to complete. */ - pinsn =3D (uint16_t *)pc; - switch (pinsn[0] >> 8) { - case 0x50: /* ST */ - case 0x42: /* STC */ - case 0x40: /* STH */ - case 0xba: /* CS */ - case 0xbb: /* CDS */ - is_write =3D 1; - break; - case 0xc4: /* RIL format insns */ - switch (pinsn[0] & 0xf) { - case 0xf: /* STRL */ - case 0xb: /* STGRL */ - case 0x7: /* STHRL */ - is_write =3D 1; - } - break; - case 0xc8: /* SSF format insns */ - switch (pinsn[0] & 0xf) { - case 0x2: /* CSST */ - is_write =3D 1; - } - break; - case 0xe3: /* RXY format insns */ - switch (pinsn[2] & 0xff) { - case 0x50: /* STY */ - case 0x24: /* STG */ - case 0x72: /* STCY */ - case 0x70: /* STHY */ - case 0x8e: /* STPQ */ - case 0x3f: /* STRVH */ - case 0x3e: /* STRV */ - case 0x2f: /* STRVG */ - is_write =3D 1; - } - break; - case 0xeb: /* RSY format insns */ - switch (pinsn[2] & 0xff) { - case 0x14: /* CSY */ - case 0x30: /* CSG */ - case 0x31: /* CDSY */ - case 0x3e: /* CDSG */ - case 0xe4: /* LANG */ - case 0xe6: /* LAOG */ - case 0xe7: /* LAXG */ - case 0xe8: /* LAAG */ - case 0xea: /* LAALG */ - case 0xf4: /* LAN */ - case 0xf6: /* LAO */ - case 0xf7: /* LAX */ - case 0xfa: /* LAAL */ - case 0xf8: /* LAA */ - is_write =3D 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__mips__) +#if defined(__mips__) =20 #if defined(__misp16) || defined(__mips_micromips) #error "Unsupported encoding" --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271501457841.2240248822592; Thu, 14 Oct 2021 21:18:21 -0700 (PDT) Received: from localhost ([::1]:43864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEfj-0004KQ-Vk for importer@patchew.org; Fri, 15 Oct 2021 00:18:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38820) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYp-00074t-2x for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:11 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:43613) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYm-0000Er-Sr for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:10 -0400 Received: by mail-pj1-x102d.google.com with SMTP id e5-20020a17090a804500b001a116ad95caso816314pjw.2 for ; Thu, 14 Oct 2021 21:11:08 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SO98PYe76zHX1Te4ncmpUAjeZt6T0p/6OYCNnl9Too8=; b=YCqH71h74W+K/9on5xmPVBhVU6m+9TcSOsE+rSQptbYv2HYlOpa2Q2lAhiduBnr0BW x3+tV6bs5ZDm1R7SlVb2uirg7Qd1RmYVnmMCwYAmjJvwN+qeiE3Ap6ymx73f44yPWs8P LuZkmisP/TMWCU/yDSfM+hzMFm81dXTpwGtkQcdWfjPn44sImVTkvm/4Q6j01naZaGkt mkddgPZWRu6IVdDynYLUQsFiXleF4ys1v6y3LVq9sbUCT+YhB6fKzxKABnhymN7wfT3j BKhQCjmpRT1ESA3Eqmnbb8JJl8AmfwtESSnUpqHvOpNAI8AbMu0nD83TLhUU+2F0C7ES 4uKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SO98PYe76zHX1Te4ncmpUAjeZt6T0p/6OYCNnl9Too8=; b=JkT6TeoVBfWU5BetVSOmrVRxW+RXHDj0RXwnvBRopWzfKewKduXK3Ot+Yl25RLZLGE 4ZEe6hx6KCgV4RrfnhweVq6kzyAmT1GR+BRZw60E6Zo7LBS8D0mn4AvkWFBlsadaBLl+ zwwdYtFjxmDI0hKORPAKLZ6xWN7k4EfSZiwd/KTuSrcQBWzzXxpeuNcIVSZesW4q4OVJ 2gAw0AVxtgKISdD7GK3L1+6GfeAE8VsVHwH9wHaWc3QKNnXWVG0zx0hJ8cIAC4Q6qvax /AsILYJ7p3yL8g3a+w9nqC+9KbNHGGXaJu5tSzDbTRuvShzNPJz2Gqc/4zOKX+XiHSBl Tssg== X-Gm-Message-State: AOAM532B1jJr1PD0rNmenR0eqhTD9tafggeqv7ha3+2gpvwRPIuQ197p XnzjmRG5PrIDSPek71Q+bUCpbpuyYo77Tg== X-Google-Smtp-Source: ABdhPJxj2fP7/RlGTM8ddTWcPeUeV12K94juUIk9I9n0DC4K4AMGCJUeD00piqKqLO8NYZgpksTUOw== X-Received: by 2002:a17:902:ed0b:b0:13f:4318:491a with SMTP id b11-20020a170902ed0b00b0013f4318491amr8984469pld.4.1634271067411; Thu, 14 Oct 2021 21:11:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 14/67] linux-user/host/mips: Populate host_signal.h Date: Thu, 14 Oct 2021 21:10:00 -0700 Message-Id: <20211015041053.2769193-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271502479100001 Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- linux-user/host/mips/host-signal.h | 62 +++++++++++++++++++++++++++++- accel/tcg/user-exec.c | 52 +------------------------ 2 files changed, 62 insertions(+), 52 deletions(-) diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host= -signal.h index f4b4d65031..9c83e51130 100644 --- a/linux-user/host/mips/host-signal.h +++ b/linux-user/host/mips/host-signal.h @@ -1 +1,61 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_HOST_SIGNAL_H +#define MIPS_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +#if defined(__misp16) || defined(__mips_micromips) +#error "Unsupported encoding" +#endif + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn =3D *(uint32_t *)host_signal_pc(uc); + + /* Detect all store instructions at program counter. */ + switch ((insn >> 26) & 077) { + case 050: /* SB */ + case 051: /* SH */ + case 052: /* SWL */ + case 053: /* SW */ + case 054: /* SDL */ + case 055: /* SDR */ + case 056: /* SWR */ + case 070: /* SC */ + case 071: /* SWC1 */ + case 074: /* SCD */ + case 075: /* SDC1 */ + case 077: /* SD */ +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 + case 072: /* SWC2 */ + case 076: /* SDC2 */ +#endif + return true; + case 023: /* COP1X */ + /* + * Required in all versions of MIPS64 since + * MIPS64r1 and subsequent versions of MIPS32r2. + */ + switch (insn & 077) { + case 010: /* SWXC1 */ + case 011: /* SDXC1 */ + case 015: /* SUXC1 */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index bfd964b578..287f03dac5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,57 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__mips__) - -#if defined(__misp16) || defined(__mips_micromips) -#error "Unsupported encoding" -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - uintptr_t pc =3D uc->uc_mcontext.pc; - uint32_t insn =3D *(uint32_t *)pc; - int is_write =3D 0; - - /* Detect all store instructions at program counter. */ - switch((insn >> 26) & 077) { - case 050: /* SB */ - case 051: /* SH */ - case 052: /* SWL */ - case 053: /* SW */ - case 054: /* SDL */ - case 055: /* SDR */ - case 056: /* SWR */ - case 070: /* SC */ - case 071: /* SWC1 */ - case 074: /* SCD */ - case 075: /* SDC1 */ - case 077: /* SD */ -#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 - case 072: /* SWC2 */ - case 076: /* SDC2 */ -#endif - is_write =3D 1; - break; - case 023: /* COP1X */ - /* Required in all versions of MIPS64 since - MIPS64r1 and subsequent versions of MIPS32r2. */ - switch (insn & 077) { - case 010: /* SWXC1 */ - case 011: /* SDXC1 */ - case 015: /* SUXC1 */ - is_write =3D 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__riscv) +#if defined(__riscv) =20 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271919251973.1846581564604; Thu, 14 Oct 2021 21:25:19 -0700 (PDT) Received: from localhost ([::1]:41172 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEmU-0004Sx-7o for importer@patchew.org; Fri, 15 Oct 2021 00:25:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYp-00078M-Us for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:11 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:46882) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYn-0000Fv-Oh for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:11 -0400 Received: by mail-pg1-x52c.google.com with SMTP id m21so7413728pgu.13 for ; Thu, 14 Oct 2021 21:11:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yx+lHUm4xHRTq+oGBCcGRXU4RqMZyaNJqFFfjCahKRo=; b=Lgc2zpGZqXm7CyOJfiC9Skl5ehvkC+tlzr3c3BDJJBx14Vdipx2NMaMzzquR8Yg6Bs WSVw6VoTUrjMx72Va8fmipgjdatNapd0C+kS6eNwweeWP7nhYJ51EpaHN9jdQizEBQc1 Y8eAJve82wqreyBURLSV6xmD8kSaIAQzJhWFmF7gTDfEZzzAKLw3A9lfNVhQuAu2QOUE cd3OS3DtUZUzCKB3n5iHar3ucGa6mP6QKHcDB0td5n0KuGN0Q42ImzsFFKbWNnvKlq+0 FCwnCsdLQgSa8Bqrt5eeT+8xyJk0+b7HUBgtu5NSYsj7BX0YcVc5DgCQd/I8ganhzH78 tbsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yx+lHUm4xHRTq+oGBCcGRXU4RqMZyaNJqFFfjCahKRo=; b=4dFNarg4t6m0ZTan44rOMQyMe4qKntKGcS1G9Z0sDdVTkDHXp4ilriKoudopRDRWZ5 keT5CTPaihNOS29P+7hRAIxLrabLsV3NheuhYFN5rND6BKGRC4SUojrZsByKPLTHAzPI Z7uVNNOcE/CwFFlqSUSh+NhFFuxHU3FZ23AiQ5HTFBFqRccrIIXonw6PFOm4euzF7aIk TH4f6Vh/R9rfUyOXA5bQEChgj39z8L6OZrPYgsf6z6CH8QpYmQw5RCxxYxvYDOkcv7q9 lrTVaMGLsiO12BXwelzZVpdJ8LCaM8k2rhDA4pEfJapvmJW6hMnzo6DrBbbxTnz8af7p fPmw== X-Gm-Message-State: AOAM530nvtAuKbvlYO5x9M6lpr2e0P3UWtTQUyE1iiNVm5UHjHBjRkhI wqOBCbDkQN91iqnfFnJIrJYwX5FG1Hh5nw== X-Google-Smtp-Source: ABdhPJwiFEpvLe1Jn6rSE7enwqwhOXWUy9KW/riTNzr2QIL+7Fdflugi8W4KjySZw14eUbXKO03mGw== X-Received: by 2002:a65:64d7:: with SMTP id t23mr7219602pgv.237.1634271068252; Thu, 14 Oct 2021 21:11:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 15/67] linux-user/host/riscv: Populate host_signal.h Date: Thu, 14 Oct 2021 21:10:01 -0700 Message-Id: <20211015041053.2769193-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271920741100001 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- linux-user/host/riscv/host-signal.h | 85 +++++++++++++++++- accel/tcg/user-exec.c | 134 ---------------------------- 2 files changed, 84 insertions(+), 135 deletions(-) diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/ho= st-signal.h index f4b4d65031..5860dce7d7 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -1 +1,84 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef RISCV_HOST_SIGNAL_H +#define RISCV_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.__gregs[REG_PC]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn =3D *(uint32_t *)host_signal_pc(uc); + + /* + * Detect store by reading the instruction at the program + * counter. Note: we currently only generate 32-bit + * instructions so we thus only detect 32-bit stores + */ + switch (((insn >> 0) & 0b11)) { + case 3: + switch (((insn >> 2) & 0b11111)) { + case 8: + switch (((insn >> 12) & 0b111)) { + case 0: /* sb */ + case 1: /* sh */ + case 2: /* sw */ + case 3: /* sd */ + case 4: /* sq */ + return true; + default: + break; + } + break; + case 9: + switch (((insn >> 12) & 0b111)) { + case 2: /* fsw */ + case 3: /* fsd */ + case 4: /* fsq */ + return true; + default: + break; + } + break; + default: + break; + } + } + + /* Check for compressed instructions */ + switch (((insn >> 13) & 0b111)) { + case 7: + switch (insn & 0b11) { + case 0: /*c.sd */ + case 2: /* c.sdsp */ + return true; + default: + break; + } + break; + case 6: + switch (insn & 0b11) { + case 0: /* c.sw */ + case 3: /* c.swsp */ + return true; + default: + break; + } + break; + default: + break; + } + + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 287f03dac5..2d9ab0a8b8 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -139,64 +139,6 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset= _t *old_set, } } =20 -/* - * 'pc' is the host PC at which the exception was raised. - * 'address' is the effective address of the memory exception. - * 'is_write' is 1 if a write caused the exception and otherwise 0. - * 'old_set' is the signal set which should be restored. - */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) -{ - CPUState *cpu =3D current_cpu; - CPUClass *cc; - unsigned long host_addr =3D (unsigned long)info->si_addr; - MMUAccessType access_type =3D adjust_signal_pc(&pc, is_write); - abi_ptr guest_addr; - - /* For synchronous signals we expect to be coming from the vCPU - * thread (so current_cpu should be valid) and either from running - * code or during translation which can fault as we cross pages. - * - * If neither is true then something has gone wrong and we should - * abort rather than try and restart the vCPU execution. - */ - if (!cpu || !cpu->running) { - printf("qemu:%s received signal outside vCPU context @ pc=3D0x%" - PRIxPTR "\n", __func__, pc); - abort(); - } - -#if defined(DEBUG_SIGNAL) - printf("qemu: SIGSEGV pc=3D0x%08lx address=3D%08lx w=3D%d oldset=3D0x%= 08lx\n", - pc, host_addr, is_write, *(unsigned long *)old_set); -#endif - - /* Convert forcefully to guest address space, invalid addresses - are still valid segv ones */ - guest_addr =3D h2g_nocheck(host_addr); - - /* XXX: locking issue */ - if (is_write && - info->si_signo =3D=3D SIGSEGV && - info->si_code =3D=3D SEGV_ACCERR && - h2g_valid(host_addr) && - handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { - return 1; - } - - /* - * There is no way the target can handle this other than raising - * an exception. Undo signal and retaddr state prior to longjmp. - */ - sigprocmask(SIG_SETMASK, old_set, NULL); - - cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); -} - static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) @@ -255,82 +197,6 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__riscv) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - greg_t pc =3D uc->uc_mcontext.__gregs[REG_PC]; - uint32_t insn =3D *(uint32_t *)pc; - int is_write =3D 0; - - /* Detect store by reading the instruction at the program - counter. Note: we currently only generate 32-bit - instructions so we thus only detect 32-bit stores */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - is_write =3D 1; - break; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - is_write =3D 1; - break; - default: - break; - } - break; - default: - break; - } - } - - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - is_write =3D 1; - break; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - is_write =3D 1; - break; - default: - break; - } - break; - default: - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - /* The softmmu versions of these helpers are in cputlb.c. */ =20 /* --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271835312190.03755390966376; Thu, 14 Oct 2021 21:23:55 -0700 (PDT) Received: from localhost ([::1]:35968 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEl7-00012l-SK for importer@patchew.org; Fri, 15 Oct 2021 00:23:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYq-00078Z-1x for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:12 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:33414) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYo-0000Ga-AQ for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:11 -0400 Received: by mail-pj1-x102f.google.com with SMTP id q10-20020a17090a1b0a00b001a076a59640so6666915pjq.0 for ; Thu, 14 Oct 2021 21:11:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+vyWXP6Fx9Nim2ldoxF0eSsJbEhC7OEjuYcEJUYRKoA=; b=yfhKZec0LDBGBWcz/SFkgmWe4Hxqy1jeUB83z/VcalGpDi0LPuHI7ZhGxNuTB+8SfS bpPDNIbLbNZeGdNWdTfz5lwp9LTw1HE7gTd03TWio4q0tIrcwPvSBH5xCAT+y3BNFyf4 C2sjKa5+F9Ssw7cAzsYypfzbDXEUBVmM2OrMwteuFhgt9zef0Hn5B2be0Hluu6E85fiq wBTyU06C1/tzYUmCE7AtGoMHOUJU7apE7SZh6dCmGg01NHlkNoDwnGejk+MVbOoug3nQ xB3vyntKNIqfJSn/N3SczcJzki2dwjs9aY8WZEIxQ24tqosIDidie49OF2ncn733dbi/ 1IUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+vyWXP6Fx9Nim2ldoxF0eSsJbEhC7OEjuYcEJUYRKoA=; b=pGfFnf8BcEE+Z0wqZnBsHr92/c5nrgiSE5QgcXvqqiV5/HRxGFdxcQ5fE9fvukHMNv vugCP0pozRFHnJXvPjBiGL1iFiC2qG+FxmQPplcBktFTViO94qCJWWh8qVtSkBAvLajP vf4g2nGgDfPGtDAemPXeHZY2t0LG/IU8P6kjFULV7pf8mT171W3jGWZ/IGLZZKI/Ddvu mh6kEOp4PexpsEkGbzogcvSC9ywVhsMKQyf7SRE3vz4RA0jf1TylSAZs3UMsrsuo5/5o vM8+VI59zOklEoVEFd/4G5RbHhWqhraUwiu0dLToQJfD8T3fA8tOGKIdVIzqE/eRluL7 rJCw== X-Gm-Message-State: AOAM532tOc8or/rsE4xz7G45VYq/Sx2ND6JT9m4WIUH70kj5ihEFyDiQ g0PXRgBn8N4i5Pl5sf8XHuAAJKV0sw744Q== X-Google-Smtp-Source: ABdhPJymKCu4iLVqmVSkph3rYdEqul0TU58eykJoGhtsgsHLO78jjszR1pSpIuMVwQdSqc2FWdZHXg== X-Received: by 2002:a17:90b:193:: with SMTP id t19mr25128945pjs.95.1634271069025; Thu, 14 Oct 2021 21:11:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 16/67] target/arm: Fixup comment re handle_cpu_signal Date: Thu, 14 Oct 2021 21:10:02 -0700 Message-Id: <20211015041053.2769193-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271836762100001 Content-Type: text/plain; charset="utf-8" The named function no longer exists. Refer to host_signal_handler instead. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh --- target/arm/sve_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index dab5f1d1cd..07be55b7e1 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -6118,7 +6118,7 @@ DO_LDN_2(4, dd, MO_64) * linux-user/ in its get_user/put_user macros. * * TODO: Construct some helpers, written in assembly, that interact with - * handle_cpu_signal to produce memory ops which can properly report errors + * host_signal_handler to produce memory ops which can properly report err= ors * without racing. */ =20 --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271976897762.8073786641479; Thu, 14 Oct 2021 21:26:16 -0700 (PDT) Received: from localhost ([::1]:44474 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEnP-0006kx-Su for importer@patchew.org; Fri, 15 Oct 2021 00:26:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38856) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYr-0007Cy-6p for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:14 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:33480) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYp-0000H5-8Z for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:12 -0400 Received: by mail-pg1-x52a.google.com with SMTP id j190so698858pgd.0 for ; Thu, 14 Oct 2021 21:11:10 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T6s+8p22L/kJt7ysU37rV/HmGCKRECxNpTVVs5PRRQU=; b=REPHbbf4TEkbB7/C3FISZnFJs0Y0hSnNMIJyQe4CQKlb5yJcXYR694/1TVG9dSoGp1 ui1RonR0JLBznZhlMQDcCWvcSeq6IsoK0tQ9yK/uV1JZoZiZuZJ0PUYEpdj8Z2ZutgzR vz1DsACToajKO60xGhqhaSGxVHbGyI724yltsiST+GFJ+vY1S5Tn2wJPuwAmOkKQQYs1 Q3J4XA9ZdnLAQbi9hcHkgG71Jg81g3hRI24+SOk44VGQI5+9RQIGrYXDH5aDQAjISJkZ zHsfogb1kToVhHDQEMwd93LU09WR6pkcxSIP678CKRWGc8Fm3cJobI23JqH1lunrUsd6 016A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T6s+8p22L/kJt7ysU37rV/HmGCKRECxNpTVVs5PRRQU=; b=dsnEDLTKMxf8i7dRilfWwj1JDPBewM5+4/szz3jNtpbOLAw72G0owczrF6i3qtjBv5 d4pN5vVZpM6qnRCRnVyBKGClmEAO/Q4iiDT8n4jGEC9UplaFeJ552cp1cYgD3VsGmGo9 ipCefrO1DluZ1UcLyfVVU/vv66z//MWHBiDXrOeHs5tcgC/M7mieUTxAM5w6Qb7rU6BZ 7lsFxOJF5Zh3wqb9ldfktYGL1ZHTieO0VJblqP5T21Ea5TL9KC3F5hdyMsd5DtFVP7nt NDzaVGimF89MEmU/U5FK32IDZqztEMruOQC2h6yhWTcMK4Zrxpq4bbDyBubbeuPBiY93 28Vw== X-Gm-Message-State: AOAM532bnQOhnovnliQstFfZTQQFGIeT5n2GHUks6H6Uru0CDbG6jmIc DbHflbcPpy+jAFNam9iyA0hT+D+0TTb1AA== X-Google-Smtp-Source: ABdhPJwGK56lnndnTB9+AiSrpdAXbmo4Y7Rkny4jMhfYoFtwPARN1xPiFTQ7xPrbi2CJvyprpM3+lw== X-Received: by 2002:a63:7404:: with SMTP id p4mr7213000pgc.222.1634271069860; Thu, 14 Oct 2021 21:11:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 17/67] linux-user/host/riscv: Improve host_signal_write Date: Thu, 14 Oct 2021 21:10:03 -0700 Message-Id: <20211015041053.2769193-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271978970100001 Content-Type: text/plain; charset="utf-8" Do not read 4 bytes before we determine the size of the insn. Simplify triple switches in favor of checking major opcodes. Include the missing cases of compact fsd and fsdsp. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 83 ++++++++++------------------- 1 file changed, 28 insertions(+), 55 deletions(-) diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/ho= st-signal.h index 5860dce7d7..ab06d70964 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -17,65 +17,38 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) =20 static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { - uint32_t insn =3D *(uint32_t *)host_signal_pc(uc); - /* - * Detect store by reading the instruction at the program - * counter. Note: we currently only generate 32-bit - * instructions so we thus only detect 32-bit stores + * Detect store by reading the instruction at the program counter. + * Do not read more than 16 bits, because we have not yet determined + * the size of the instruction. */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - return true; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - return true; - default: - break; - } - break; - default: - break; - } + const uint16_t *pinsn =3D (const uint16_t *)host_signal_pc(uc); + uint16_t insn =3D pinsn[0]; + + /* 16-bit instructions */ + switch (insn & 0xe003) { + case 0xa000: /* c.fsd */ + case 0xc000: /* c.sw */ + case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */ + case 0xa002: /* c.fsdsp */ + case 0xc002: /* c.swsp */ + case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */ + return true; } =20 - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - return true; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - return true; - default: - break; - } - break; - default: - break; + /* 32-bit instructions, major opcodes */ + switch (insn & 0x7f) { + case 0x23: /* store */ + case 0x27: /* store-fp */ + return true; + case 0x2f: /* amo */ + /* + * The AMO function code is in bits 25-31, unread as yet. + * The AMO functions are LR (read), SC (write), and the + * rest are all read-modify-write. + */ + insn =3D pinsn[1]; + return (insn >> 11) !=3D 2; /* LR */ } =20 return false; --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271652649119.08804013116185; Thu, 14 Oct 2021 21:20:52 -0700 (PDT) Received: from localhost ([::1]:52256 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEiB-0001St-87 for importer@patchew.org; Fri, 15 Oct 2021 00:20:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38876) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYt-0007ES-58 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:15 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:47100) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYq-0000Hy-3V for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:13 -0400 Received: by mail-pf1-x42b.google.com with SMTP id i76so5149790pfe.13 for ; Thu, 14 Oct 2021 21:11:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BEoOYfyvrRlliP3CVpcV5+AEGq6qhapGY3bb4mVGTHg=; b=nguHstMxODNDspQVrHP+s1x9jH1NX2XHVabg7k2QUt0njxyAWzrQPWjdYm+tPslwmn 7KoZk0+8/2p7B1H7N8IfQ8afgpRILEN/jCcSyvda55430+XPuyrsHKvtWTR2RTBSfm9p AYTRT5NCVO9lWrFSijPcdRcfHXVdTkAtZGBWvqLJdXbcuUIox3O1oCSoIv7Wg3BBVh0B qLlg/pUKj1BfEc5dDI7UT6pwIhQHjPFmhIx50Q2MyzxwPeUEfxvSgvwUAS340MpWsWcy 0deCcMZoMDTiQ+SRR785uobCe5s3eEOlVdFBMVJl4unO+1QSJk/zEsE2P1roBVtAMQHE jiwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BEoOYfyvrRlliP3CVpcV5+AEGq6qhapGY3bb4mVGTHg=; b=7ly2PC9H2LSCEmEVzRgomMhsHi7htAMZJrxORqiHaLM/EtbJJPYcbAjl7Fsu3j0Uen MpCt9lWoyuCec55sk6Hu/ZzUSmaQR7F+9nNL1oEkvS6qqyyhI3nDKimyWxpNdR8hsVfh TADXFdlk3ngrdRNEtODDiiNMarz/+vL5f4uCXg4q/VgJNLipcVrYTfsaR7zFXBGm6dW5 zOUr8Ik2EDe2JIe7R156ve/5bqxZYTGPt3TT765hWUrQiZlC81yB2v2c2Wxa+z0s+Q1k 24WeYd3dhsxGfGsOtte4yjsktoVusG2WHzrGHI6Xj2bAtLR3CbMwZkJXccJyYa92tawj nh7A== X-Gm-Message-State: AOAM532z6RiTPjWG4JFi9jNtEQZ8AtrjqBaH5p9FQnwu4uj9LLNWEZCA oLhqOH7KxM+e9B4i9URdm+rCIT9uHa076g== X-Google-Smtp-Source: ABdhPJweQZ5lNt7leRr9QTmH5N3qPkmOwwtyybkbO/qLb6VdapRDKAVutkmLAF6peGTpeMNLHExcDA== X-Received: by 2002:a65:538e:: with SMTP id x14mr7352445pgq.364.1634271070690; Thu, 14 Oct 2021 21:11:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 18/67] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Date: Thu, 14 Oct 2021 21:10:04 -0700 Message-Id: <20211015041053.2769193-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271653644100002 Now that all of the linux-user hosts have been converted to host-signal.h, drop the compatibility code. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ------------ linux-user/signal.c | 14 -------------- 2 files changed, 26 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5f94d799aa..5dd663c153 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,18 +685,6 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_= write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); =20 -/** - * cpu_signal_handler - * @signum: host signal number - * @pinfo: host siginfo_t - * @puc: host ucontext_t - * - * To be called from the SIGBUS and SIGSEGV signal handler to inform the - * virtual cpu of exceptions. Returns true if the signal was handled by - * the virtual CPU. - */ -int cpu_signal_handler(int signum, void *pinfo, void *puc); - #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/linux-user/signal.c b/linux-user/signal.c index 6900acb122..b816678ba5 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -780,17 +780,6 @@ static void host_signal_handler(int host_sig, siginfo_= t *info, void *puc) ucontext_t *uc =3D puc; struct emulated_sigtable *k; int guest_sig; - -#ifdef HOST_SIGNAL_PLACEHOLDER - /* the CPU emulator uses some host signals to detect exceptions, - we forward to it some signals */ - if ((host_sig =3D=3D SIGSEGV || host_sig =3D=3D SIGBUS) - && info->si_code > 0) { - if (cpu_signal_handler(host_sig, info, puc)) { - return; - } - } -#else uintptr_t pc =3D 0; bool sync_sig =3D false; =20 @@ -850,7 +839,6 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) =20 sync_sig =3D true; } -#endif =20 /* get target signal number */ guest_sig =3D host_to_target_signal(host_sig); @@ -865,7 +853,6 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) k->pending =3D guest_sig; ts->signal_pending =3D 1; =20 -#ifndef HOST_SIGNAL_PLACEHOLDER /* * For synchronous signals, unwind the cpu state to the faulting * insn and then exit back to the main loop so that the signal @@ -875,7 +862,6 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) cpu->exception_index =3D EXCP_INTERRUPT; cpu_loop_exit_restore(cpu, pc); } -#endif =20 rewind_if_in_safe_syscall(puc); =20 --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271653080432.7514224596159; Thu, 14 Oct 2021 21:20:53 -0700 (PDT) Received: from localhost ([::1]:52402 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEiC-0001Z0-1w for importer@patchew.org; Fri, 15 Oct 2021 00:20:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYt-0007EW-6m for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:15 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:35718) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYq-0000Im-VW for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:14 -0400 Received: by mail-pg1-x52b.google.com with SMTP id e7so7463745pgk.2 for ; Thu, 14 Oct 2021 21:11:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p8GaNWW3vnRejpH0QBiQY2hh87QfB4bhIFphc+bCE2U=; b=dejJWWV6X/iZBhyVdKrm+gz+tC6AeGz+0aY28bMFsYencTyEotWAo553EGcPwSELU3 zwIsefSOFzV5g1WsO+kfnYdqZ0olHhZnrcvDOHeskI4p9pFGhxGOfA4q9Ir0G31yJ8nd c4IW/9Al4nb8XRt9daLBNElDkY0/A66q2kTXTIojYUnpt1Z5afWDW95WgDYbqykQtmkZ Xy1NW3CWN/jA0Wu+yd4t+NRzvlkf5HX38wyVsZ/kTyTmKL1nc/ySQi6LaneH2PMSgVdg mmRmOMzPd5o1o/grnD1xa29f4RPLd3yra86ZYkj4nywKtsmMjro+PspkUBMRK6Y3dJyt Q0rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p8GaNWW3vnRejpH0QBiQY2hh87QfB4bhIFphc+bCE2U=; b=OWAFRpANthmuTazM/95vo+0LAdQIzKukoedwJkNVJFafrDllfhzjWR7bnFuNm9MRyh W4rwsZaQAqVsNxHI8zd9qgR+h/Q7Z5J48s6u9XRcm8BUoi9DKshXOoJmIgKa7i168hwl 6qtIS1ZfODFOdMQPKX3nRNlq3rvitesxCOaGLlScafioIIY1fw07Pd+ez/06MV/DWpzc w9FvQH7H5GFOo1nydpXSOSFoQlsmd5pZ7ecW1FMy9jFZXSJQXGpOOjusLnXPGNOEXlPr huH3rLoKgtRZ/oNlEmHoIn/5XLMlf/Vuqk6EuVVWENkZO06bvX4JbKQZCkPJUZodv7Vd ZalA== X-Gm-Message-State: AOAM5338Lu9UyCIfaX3MWQ2cBpkqhuK0VyYR3IaevJuQdiL6eiadAuZF xLM+5rxEwR5aPtQaPEYEfUMGnWgqHgvcaA== X-Google-Smtp-Source: ABdhPJxAhfTFzVFzBChvDlzfe1+u8+Gg1oBPTGLfq1S/q0eOrOzeOPMVDndW2D3FgeW5qtl2lqmKfA== X-Received: by 2002:a63:6943:: with SMTP id e64mr7281160pgc.480.1634271071338; Thu, 14 Oct 2021 21:11:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 19/67] hw/core: Add TCGCPUOps.record_sigsegv Date: Thu, 14 Oct 2021 21:10:05 -0700 Message-Id: <20211015041053.2769193-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271653638100001 Add a new user-only interface for updating cpu state before raising a signal. This will replace tlb_fill for user-only and should result in less boilerplate for each guest. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 6cbe17f2e6..41718b695b 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -111,6 +111,32 @@ struct TCGCPUOps { */ bool (*io_recompile_replay_branch)(CPUState *cpu, const TranslationBlock *tb); +#else + /** + * record_sigsegv: + * @cpu: cpu context + * @addr: faulting guest address + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * We are about to raise SIGSEGV with si_code set for @maperr, + * and si_addr set for @addr. Record anything further needed + * for the signal ucontext_t. + * + * If the emulated kernel does not provide anything to the signal + * handler with anything besides the user context registers, and + * the siginfo_t, then this hook need do nothing and may be omitted. + * Otherwise, record the data and return; the caller will raise + * the signal, unwind the cpu state, and return to the main loop. + * + * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided + * so that a "normal" cpu exception can be raised. In this case, + * the signal must be raised by the architecture cpu_loop. + */ + void (*record_sigsegv)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ =20 --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271780278213.88569816073107; Thu, 14 Oct 2021 21:23:00 -0700 (PDT) Received: from localhost ([::1]:60734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEkF-0007AB-3v for importer@patchew.org; Fri, 15 Oct 2021 00:22:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38934) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYw-0007HN-SN for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:19 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:34599) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYs-0000Iw-DW for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:17 -0400 Received: by mail-pg1-x52a.google.com with SMTP id 133so7465608pgb.1 for ; Thu, 14 Oct 2021 21:11:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3zF39zy0stf9vN9RkqNLbl56ZD/55nxRqij6sSa5b3g=; b=vlSwlBzpTSzCOo6uDy228i1fRtfDFH0D9XV9HPegBJ5Z9jsFc81UGpszuHaWihay7w nFU1R5qcTFHR4B01h6nj17EmnZbRFnJpGofbURv7rSq0D0lKtsJisvjuzqLNSCb3bpUa i4zxIHIgHhMtBOGHH6jLDBGI8UVWlYRYeDDaEjumBIa1NdBItYueJ+2kV45ZXaOFBW3e C3akOdbiNt3DsIOT6sbxsdUhh9xLA0IRGN5TkpBWDYpWKo2mohoL6Xq92fp5Zo6BGJd/ aNYnsk7FRvA66/s3iYqtC8cQHDoEG0M0QRipRqHKtuCPFjdf9GbYdt3xS3aruYWw3mHr sPiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3zF39zy0stf9vN9RkqNLbl56ZD/55nxRqij6sSa5b3g=; b=AW7CNARYitMpbTwF+OWzmOeuvLwPDhPOzam4NPfOv9KyzvdgwFjTBmQRSqXkUvJK2Y V6BR6HITBX9ZREX04w3UhCB9nV7Yx1xHbFbvhCmyENyaywfe1u70ES/snXDPv3TRrcjf eepqUuJBaUIG/y0WeJP9w7VQ1JO73UoUbNDcygUUxRLDYnQWZ42pFXDnkokclAF4geF9 ZxSLKUOjql+rcP9ijyTG7mvCrH/rUGilKwcN9chSB/b/hMrsu2s7P+nZIJ5QUoExbwa9 KetbEAFawjqTFzXcdFPmH72gGkpaJYUPQY0sWTPAV+4Azc0NhzDZFCfD2UyINV8lwe6T GjwA== X-Gm-Message-State: AOAM532dOLlt6Q3vt72FswFmzUH/O++1GV0Zp+CZYTZ6NQgRXnMVu0wK 2FMArvbZpYl7C86aCYPg5Uz8p00mDLDCTw== X-Google-Smtp-Source: ABdhPJwlc2AmtxuN3GHe6HBly4AydikBczGDG2FGvygNi9krTpsDe9pnEbjGAi5hOVKYIAnwdTkTvw== X-Received: by 2002:a63:7450:: with SMTP id e16mr3552724pgn.482.1634271072146; Thu, 14 Oct 2021 21:11:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 20/67] linux-user: Add cpu_loop_exit_sigsegv Date: Thu, 14 Oct 2021 21:10:06 -0700 Message-Id: <20211015041053.2769193-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271780808100001 This is a new interface to be provided by the os emulator for raising SIGSEGV on fault. Use the new record_sigsegv target hook. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 15 +++++++++++++++ accel/tcg/user-exec.c | 33 ++++++++++++++++++--------------- linux-user/signal.c | 30 ++++++++++++++++++++++-------- 3 files changed, 55 insertions(+), 23 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5dd663c153..f74578500c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,6 +685,21 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_= write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); =20 +/** + * cpu_loop_exit_sigsegv: + * @cpu: the cpu context + * @addr: the guest address of the fault + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGSEGV, and jump to the main cpu loop. + */ +void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 2d9ab0a8b8..5646f8e527 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -143,35 +143,38 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) { - int flags; + int acc_flag; + bool maperr; =20 switch (access_type) { case MMU_DATA_STORE: - flags =3D PAGE_WRITE; + acc_flag =3D PAGE_WRITE_ORG; break; case MMU_DATA_LOAD: - flags =3D PAGE_READ; + acc_flag =3D PAGE_READ; break; case MMU_INST_FETCH: - flags =3D PAGE_EXEC; + acc_flag =3D PAGE_EXEC; break; default: g_assert_not_reached(); } =20 - if (!guest_addr_valid_untagged(addr) || - page_check_range(addr, 1, flags) < 0) { - if (nonfault) { - return TLB_INVALID_MASK; - } else { - CPUState *cpu =3D env_cpu(env); - CPUClass *cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type, - MMU_USER_IDX, false, ra); - g_assert_not_reached(); + if (guest_addr_valid_untagged(addr)) { + int page_flags =3D page_get_flags(addr); + if (page_flags & acc_flag) { + return 0; /* success */ } + maperr =3D !(page_flags & PAGE_VALID); + } else { + maperr =3D true; } - return 0; + + if (nonfault) { + return TLB_INVALID_MASK; + } + + cpu_loop_exit_sigsegv(env_cpu(env), addr, access_type, maperr, ra); } =20 int probe_access_flags(CPUArchState *env, target_ulong addr, diff --git a/linux-user/signal.c b/linux-user/signal.c index b816678ba5..135983747d 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -688,9 +688,27 @@ void force_sigsegv(int oldsig) } force_sig(TARGET_SIGSEGV); } - #endif =20 +void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, bool maperr, uintptr= _t ra) +{ + const struct TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + + if (tcg_ops->record_sigsegv) { + tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); + } else if (tcg_ops->tlb_fill) { + tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, = ra); + g_assert_not_reached(); + } + + force_sig_fault(TARGET_SIGSEGV, + maperr ? TARGET_SEGV_MAPERR : TARGET_SEGV_ACCERR, + addr); + cpu->exception_index =3D EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, ra); +} + /* abort execution with signal */ static void QEMU_NORETURN dump_core_and_abort(int target_sig) { @@ -806,7 +824,7 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) access_type =3D adjust_signal_pc(&pc, is_write); =20 if (host_sig =3D=3D SIGSEGV) { - const struct TCGCPUOps *tcg_ops; + bool maperr =3D true; =20 if (info->si_code =3D=3D SEGV_ACCERR && h2g_valid(host_addr)) { /* If this was a write to a TB protected page, restart. */ @@ -821,18 +839,14 @@ static void host_signal_handler(int host_sig, siginfo= _t *info, void *puc) * which means that we may get ACCERR when we want MAPERR. */ if (page_get_flags(guest_addr) & PAGE_VALID) { - /* maperr =3D false; */ + maperr =3D false; } else { info->si_code =3D SEGV_MAPERR; } } =20 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); - - tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; - tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); + cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc= ); } else { sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); } --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163427208768866.64482257270095; Thu, 14 Oct 2021 21:28:07 -0700 (PDT) Received: from localhost ([::1]:49712 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEpC-0001lS-Op for importer@patchew.org; Fri, 15 Oct 2021 00:28:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYu-0007GO-WD for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:18 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:38689) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYs-0000Jd-Rb for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:16 -0400 Received: by mail-pf1-x42c.google.com with SMTP id k26so7298806pfi.5 for ; Thu, 14 Oct 2021 21:11:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v0FpA57qaJCc2VnO4R+7jKC7WxQwlNYWwLwncqceS+8=; b=MJNpwSV+rzbgBC2STQO6Glp4RW0EK4sXF1uS1Bfrnn3wCJqHDiQCV04MTtIYhc4rum ZbFXpwotAFVWnCXyZjZBTDZE1c+oxKLckfKHjWpN1GA1/tQr/C3gCJDferz4fUKJFMI0 KMwoYQU4H54JRIvBBz4Rem+FT9BlB4p+MDFPunhzt4SnriMTjUq5hT8PnDoH1a8QZ3Hi cCCBdlB7Fbj24gBD6FR9giPjO9S/a3MUMm3SdSRbpQa+iSQAwA/RF+oQT16Kexx6x3Ap lJ0x7CCYUBfDoLOQUbFhohn7d4GDsM1+NOx8amPwQrubsm9fSdL8xSRtRckEkMkOXcRI +zNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v0FpA57qaJCc2VnO4R+7jKC7WxQwlNYWwLwncqceS+8=; b=6NX3P1OQS5VmWn2XmNa6Q+S7vXVlF6+MtfyFSXAydVnkoZ61Ivp3tUb9dc+K9Rxjmw F1YrK/7fYJ7b+Cog6KHSJajvhpkvH6Za9aTs6DkWD76HExdejzlGm5zJ43Cwba/kcoes Et0bL3JqOFLW2eSU27RL2H4Zoj6EiaWiX0pCdNdRralGxaC5YBAPb0IDSK945uPlXr8P bdPzKArprfjWdAYH7MTVuesfHtWFNOwo5D7/vdRyezZDsX17doQaFNrSHcr7Rt3T2ZGb 4q6kPtE9wow6sMg1NcnF/1LgYhZFSUZ+KF6yD3KrM1ILTHi1uKLGMUWiuM4VjinMkuj+ UnPg== X-Gm-Message-State: AOAM531cCQSVbjVDjeCWoQ1o5DfzNRyYTtNIXzTOtRsBRf8L7wncbSdV zWPK91Ax3PxYF7WI9pOBo/8gPf24GIgfRw== X-Google-Smtp-Source: ABdhPJyENV9gkgEB1Zlyh4hvXuUoKMynD59xG8x1GvgXgSpRKpHFrR7mDNzCvx46kad1iyDvaEu3FQ== X-Received: by 2002:a63:454e:: with SMTP id u14mr7311465pgk.314.1634271072929; Thu, 14 Oct 2021 21:11:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 21/67] target/alpha: Implement alpha_cpu_record_sigsegv Date: Thu, 14 Oct 2021 21:10:07 -0700 Message-Id: <20211015041053.2769193-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272089429100001 Content-Type: text/plain; charset="utf-8" Record trap_arg{0,1,2} for the linux-user signal frame. Fill in the stores to trap_arg{1,2} that were missing from the previous user-only alpha_cpu_tlb_fill function. Use maperr to simplify computation of trap_arg1. Remove the code for EXCP_MMFAULT from cpu_loop, as that part is now handled by cpu_loop_exit_sigsegv. Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 13 +++++++++---- linux-user/alpha/cpu_loop.c | 8 -------- target/alpha/cpu.c | 6 ++++-- target/alpha/helper.c | 39 ++++++++++++++++++++++++++++++++----- 4 files changed, 47 insertions(+), 19 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 772828cc26..d49cc36d07 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -439,9 +439,6 @@ void alpha_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU =20 void alpha_cpu_list(void); -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); =20 @@ -449,7 +446,15 @@ uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); -#ifndef CONFIG_USER_ONLY + +#ifdef CONFIG_USER_ONLY +void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr); +#else +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 1b00a81385..4cc8e0a55c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -54,14 +54,6 @@ void cpu_loop(CPUAlphaState *env) fprintf(stderr, "External interrupt. Exit\n"); exit(EXIT_FAILURE); break; - case EXCP_MMFAULT: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D (page_get_flags(env->trap_arg0) & PAGE_VALID - ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); - info._sifields._sigfault._addr =3D env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 93e16a2ffb..69f32c3078 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -218,9 +218,11 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { =20 static const struct TCGCPUOps alpha_tcg_ops =3D { .initialize =3D alpha_translate_init, - .tlb_fill =3D alpha_cpu_tlb_fill, =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D alpha_cpu_record_sigsegv, +#else + .tlb_fill =3D alpha_cpu_tlb_fill, .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, .do_interrupt =3D alpha_cpu_do_interrupt, .do_transaction_failed =3D alpha_cpu_do_transaction_failed, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 81550d9e2f..b7e7f73b15 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -120,15 +120,44 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned = reg, uint64_t val) } =20 #if defined(CONFIG_USER_ONLY) -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { AlphaCPU *cpu =3D ALPHA_CPU(cs); + target_ulong mmcsr, cause; =20 - cs->exception_index =3D EXCP_MMFAULT; + /* Assuming !maperr, infer the missing protection. */ + switch (access_type) { + case MMU_DATA_LOAD: + mmcsr =3D MM_K_FOR; + cause =3D 0; + break; + case MMU_DATA_STORE: + mmcsr =3D MM_K_FOW; + cause =3D 1; + break; + case MMU_INST_FETCH: + mmcsr =3D MM_K_FOE; + cause =3D -1; + break; + default: + g_assert_not_reached(); + } + if (maperr) { + if (address < BIT_ULL(TARGET_VIRT_ADDR_SPACE_BITS - 1)) { + /* Userspace address, therefore page not mapped. */ + mmcsr =3D MM_K_TNV; + } else { + /* Kernel or invalid address. */ + mmcsr =3D MM_K_ACV; + } + } + + /* Record the arguments that PALcode would give to the kernel. */ cpu->env.trap_arg0 =3D address; - cpu_loop_exit_restore(cs, retaddr); + cpu->env.trap_arg1 =3D mmcsr; + cpu->env.trap_arg2 =3D cause; } #else /* Returns the OSF/1 entMM failure indication, or -1 on success. */ --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272152325749.8711369340465; Thu, 14 Oct 2021 21:29:12 -0700 (PDT) Received: from localhost ([::1]:52876 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEqF-0003qs-A8 for importer@patchew.org; Fri, 15 Oct 2021 00:29:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYw-0007HY-UT for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:19 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:44928) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYt-0000Kq-2z for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:18 -0400 Received: by mail-pf1-x42c.google.com with SMTP id v8so3157928pfu.11 for ; Thu, 14 Oct 2021 21:11:14 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gDo26nxZuCe6knbSSj4pxxnp0xROgd5wgByOtwEaQmw=; b=SUyDN/bfj0pqlmb4veDFS7djOwRGHBtR8olsDB7rbMU9HqnIaNvkuCOH2u+Bg77bML NpXcn9smrHVUR3O/lG6oCWaiN4/XfH+wiNyxttxthkCuuaKE4dfLJEemRbw0XCLfmTYu pn2ODCUAqMZ3N3jZLVP8sRpii8uYMuL0JDCEONcQolzf0WptIX1o8nWV26pWhSLbnq8p J8hTjb87HrVA1vkBGtRsftOaBl9U8o6EoflgSRiYXjTLUVqWcY6GCSE11wdM8bDZkJUl zU6kb6e4+7yOgIy9+2siq9U30ySKrB5HgriUdnBIfQX8e/GBVjEFuW6BbcX5n3EU/obd Csow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gDo26nxZuCe6knbSSj4pxxnp0xROgd5wgByOtwEaQmw=; b=W0b8GJYyyRs1ZZ7hDe3dSGdRVorINJ8gJKcNNiNNtPX4OVRrcSMRPKNHVx4x0FYHIL 0Z087h4nYLm0qrhXstSQpspg5FUpxjbEK3fNvmxLADFZR1zt3Z4O0n5KjRtQHKQVLuzw f9WKHkN2/XVsc0z58DOsmoIQnbgcNGD6lzRhbXTAsQBZA9W2lQLTS2By9zJyN0G0WSMI S79rS8ln2cmP8ihRpyeXp0o7gbTbQtwNPSsuNb6sMXj4nXsxmyl48+ReE+kxnY3a1jVC 4vn6Ss20dYS7zVO1/BGWAK0s3m48OSRBMg06gOJ6PCZkpXi2quWaL6BpIjzR1QGnJERu OdGg== X-Gm-Message-State: AOAM532RpKQwrEu+/2cEsqMxp2cVKZziOWveuZ/veMlKQbsf+I+/XfeG ofjVNFu4m5STnsJncAL0cvFni/28Ljg= X-Google-Smtp-Source: ABdhPJwoJKTjMk+tU3sWsMBavZDmilq/W1HrOF+gpbYjo96csj4Wcch/2cb8Xx4TpMJHPUe+PZ6Jzg== X-Received: by 2002:a63:b204:: with SMTP id x4mr7163143pge.212.1634271073744; Thu, 14 Oct 2021 21:11:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 22/67] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Date: Thu, 14 Oct 2021 21:10:08 -0700 Message-Id: <20211015041053.2769193-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272152590100001 Use the new os interface for raising the exception, rather than calling arm_cpu_tlb_fill directly. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- target/arm/mte_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 724175210b..e09b7e46a2 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -84,10 +84,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int= ptr_mmu_idx, uintptr_t index; =20 if (!(flags & (ptr_access =3D=3D MMU_DATA_STORE ? PAGE_WRITE_ORG : PAG= E_READ))) { - /* SIGSEGV */ - arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, - ptr_mmu_idx, false, ra); - g_assert_not_reached(); + cpu_loop_exit_sigsegv(env_cpu(env), ptr, ptr_access, + !(flags & PAGE_VALID), ra); } =20 /* Require both MAP_ANON and PROT_MTE for the page. */ --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271782135801.7067753435603; Thu, 14 Oct 2021 21:23:02 -0700 (PDT) Received: from localhost ([::1]:60890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEkH-0007GU-4G for importer@patchew.org; Fri, 15 Oct 2021 00:23:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38970) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYy-0007IF-Oa for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:21 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:41651) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYu-0000LZ-OU for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:20 -0400 Received: by mail-pg1-x52d.google.com with SMTP id d23so7431577pgh.8 for ; Thu, 14 Oct 2021 21:11:15 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FxRJbycecCGMYDwBryMZJTmIk0vSiUV5vp8YTTExVU4=; b=WfyhWSFhThST52KP8KpQtC1f6BFvlgInLK1K7tG13gge7HdeG8zvOUZEV0TX6dEAwb AkEek++IEgX97pMJbM6+RpzhjtlAJbkrRPEXvb3U7ABA7m4x/sY5KQfW9C1g0dysnvu7 ko7Bp9rxPaH3QjXkR3MIPBHUCA9k6ToCsIKgPwnOs4s4rrZvQDTepoS4OH8gnjgPB1I1 OnflPw7do3vRJln4Z94uxUOv8S3Cv3kNo6NBA+rD5MljJe+tn5aNn3g/GBiY1JzhRSAx GYG4+/E00kHsRnrGbzkIEQCV2a80umbFrtFE+vTtuJurg9j7y7MO7sNqbVV5+039A90I ICFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FxRJbycecCGMYDwBryMZJTmIk0vSiUV5vp8YTTExVU4=; b=bAZIe/wjMoxRVQrPTBFK8K3JGH6ixVnOxInyXhf5a4XTEzHOFCv+jTBMM+wTelsyb6 nmjbyvOH/pKFwcwjRQkKaAOPkcWu2RKmDVIIQo3nMCwOWGVDQkfLjFDutp7/qF3vbCNp /W2CVR5s+6Eok90OT4svRMYc4b/h8354kuQ/PzMR5JQtzs6lMgkJ7cf2BRpJdqhxkwJE nD+/l/4hvegl+YTiskgcXPwyL772uGSHY7Qki4QTye8+p4d3vmBzjemZFc4UAfdKKRnF x6rQILHiDZ20c7DGMtGfQ3l0WyiCx+4Nh/4tWSRuD0LXX52Ry/8K79N8d7qyjKSldiCi cTrQ== X-Gm-Message-State: AOAM530O88iQx/0FMoDnFiRw0P/si6vng39d8Kq8VHyEt0z83Uob4Ve9 XWdVsvu5vDzhV4jr1tAnjk6jcHAaq50eCA== X-Google-Smtp-Source: ABdhPJyS3DUcE5dLsKXKqx0/VjXT0CZ/uimkDZdfOC1XdezFUfUiA2MGLlgb/TocXcQ9csEEQf0GJA== X-Received: by 2002:a63:7153:: with SMTP id b19mr7582928pgn.84.1634271074537; Thu, 14 Oct 2021 21:11:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 23/67] target/arm: Implement arm_cpu_record_sigsegv Date: Thu, 14 Oct 2021 21:10:09 -0700 Message-Id: <20211015041053.2769193-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271782660100003 Content-Type: text/plain; charset="utf-8" Because of the complexity of setting ESR, continue to use arm_deliver_fault. This means we cannot remove the code within cpu_loop that decodes EXCP_DATA_ABORT and EXCP_PREFETCH_ABORT. But using the new hook means that we don't have to do the page_get_flags check manually, and we'll be able to restrict the tlb_fill hook to sysemu later. Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- target/arm/internals.h | 6 ++++++ target/arm/cpu.c | 6 ++++-- target/arm/cpu_tcg.c | 6 ++++-- target/arm/tlb_helper.c | 36 +++++++++++++++++++----------------- 4 files changed, 33 insertions(+), 21 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3612107ab2..5a7aaf0f51 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -544,9 +544,15 @@ static inline bool arm_extabort_type(MemTxResult resul= t) return result !=3D MEMTX_DECODE_ERROR; } =20 +#ifdef CONFIG_USER_ONLY +void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif =20 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 641a8c2d3d..7a18a58ca0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2031,10 +2031,12 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D= { static const struct TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, - .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, =20 -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D arm_cpu_record_sigsegv, +#else + .tlb_fill =3D arm_cpu_tlb_fill, .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .do_interrupt =3D arm_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0d5adccf1a..7b3bea2fbb 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -898,10 +898,12 @@ static void pxa270c5_initfn(Object *obj) static const struct TCGCPUOps arm_v7m_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, - .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, =20 -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D arm_cpu_record_sigsegv, +#else + .tlb_fill =3D arm_cpu_tlb_fill, .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, .do_interrupt =3D arm_v7m_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 3107f9823e..dc5860180f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -147,28 +147,12 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } =20 -#endif /* !defined(CONFIG_USER_ONLY) */ - bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { ARMCPU *cpu =3D ARM_CPU(cs); ARMMMUFaultInfo fi =3D {}; - -#ifdef CONFIG_USER_ONLY - int flags =3D page_get_flags(useronly_clean_ptr(address)); - if (flags & PAGE_VALID) { - fi.type =3D ARMFault_Permission; - } else { - fi.type =3D ARMFault_Translation; - } - fi.level =3D 3; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); -#else hwaddr phys_addr; target_ulong page_size; int prot, ret; @@ -210,5 +194,23 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, cpu_restore_state(cs, retaddr, true); arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); } -#endif } +#else +void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) +{ + ARMMMUFaultInfo fi =3D { + .type =3D maperr ? ARMFault_Translation : ARMFault_Permission, + .level =3D 3, + }; + ARMCPU *cpu =3D ARM_CPU(cs); + + /* + * We report both ESR and FAR to signal handlers. + * For now, it's easiest to deliver the fault normally. + */ + cpu_restore_state(cs, ra, true); + arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); +} +#endif /* !defined(CONFIG_USER_ONLY) */ --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272311072809.9576422411135; Thu, 14 Oct 2021 21:31:51 -0700 (PDT) Received: from localhost ([::1]:33030 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEso-00012T-0S for importer@patchew.org; Fri, 15 Oct 2021 00:31:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39020) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ2-0007Nm-LJ for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:24 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:44931) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYu-0000Li-Op for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:23 -0400 Received: by mail-pf1-x42f.google.com with SMTP id v8so3157975pfu.11 for ; Thu, 14 Oct 2021 21:11:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LvK67GkX13tDj2L9Y8ql/Gd7bbn2JZgBQ3dF7lXKOxQ=; b=OInV1vFi/5JfHTupLob/xkMvp2vXB14v82QmIc1vo9SGBFpSFkgfOald66VQVhZTgO F+4AKVuA6CbjhvvNYPnvz/n95Hs+YqqhNX7Y75z7YR1ZcXTfyvQ/ETVf1YuqrqP8BcbC MXZr0FkkzTUwdfUt5TIys9pWtvFw27hKT3QEMDAX2Kjf1jYH5Uq1dvF10HKsBg5yB73x wm6qpqx3hfpPdi5FigzxtHoN6ReCaF1/LEbdnDP0fzyDHuQ4msKgYMY+Gv+tAHlnVDtV EQg8XbAc/V/lV64fDh/IKxG8h73D4r0fs0Mn7WVCO78OwG8auvXBhXdVebcso3FXifGb f39A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LvK67GkX13tDj2L9Y8ql/Gd7bbn2JZgBQ3dF7lXKOxQ=; b=GuGQ/szDAba612Jx0uHYiAdtlhaFdydrEZKVxBZqfw8K60j9DJZaU2JlU1xJFwtscR IgIg37xXIaZHEGr+KmtT3MaGX2Q0n5WlJn7wL9K5C3nOYl/0xFB7zErAdUm6E2GlvG/h f4aomritytf8SdzpeLslFul7coFUAiJLr1vmSqf1f9lw7mQk5et8AUq9ncNpclDNCFua 7X7tfqKqzb+BRY6GBq4YIpr4TeNGnbrEpgA1CY6EuNAbYHdQuDXxbp2UWdxoaWxDpamh cXNyss9f1OMLambqIsXyXdmUZJNqv+NBocGhyHULqyDKr26wLiBbhZODVVKE0JSiLOkM 0zHA== X-Gm-Message-State: AOAM530kQEa9yrf5WqlXcFlxNl7+Cptl/U9XuiJ7iGDeOZRjPJPrX4R8 QcO4biNGWAGa6joJFmu+S0BDrnV7wf9pMA== X-Google-Smtp-Source: ABdhPJzjcC/GeGPHyEqZa+81JGmEVHO/SebwMRqz2izTfw5Gq/CW11NbwAScDrlKXUnBfzMs4mz7qQ== X-Received: by 2002:a63:e741:: with SMTP id j1mr7429435pgk.86.1634271075199; Thu, 14 Oct 2021 21:11:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 24/67] target/cris: Make cris_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:10 -0700 Message-Id: <20211015041053.2769193-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272311987100001 The fallback code in cpu_loop_exit_sigsegv is sufficient for cris linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. This makes all of the code in helper.c sysemu only, so remove the ifdefs and move the file to cris_softmmu_ss. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/cris/cpu.h | 8 ++++---- linux-user/cris/cpu_loop.c | 10 ---------- target/cris/cpu.c | 4 ++-- target/cris/helper.c | 18 ------------------ target/cris/meson.build | 7 +++++-- 5 files changed, 11 insertions(+), 36 deletions(-) diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 6603565f83..b445b194ea 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -189,6 +189,10 @@ extern const VMStateDescription vmstate_cris_cpu; void cris_cpu_do_interrupt(CPUState *cpu); void crisv10_cpu_do_interrupt(CPUState *cpu); bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req); + +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif =20 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); @@ -251,10 +255,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bo= ol ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } =20 -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0 diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index b9085619c4..0d5d268609 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -37,16 +37,6 @@ void cpu_loop(CPUCRISState *env) process_queued_cpu_work(cs); =20 switch (trapnr) { - case 0xaa: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->pregs[PR_EDA]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index c2e7483f5b..ed6c781342 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -205,9 +205,9 @@ static const struct SysemuCPUOps cris_sysemu_ops =3D { =20 static const struct TCGCPUOps crisv10_tcg_ops =3D { .initialize =3D cris_initialize_crisv10_tcg, - .tlb_fill =3D cris_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D cris_cpu_tlb_fill, .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .do_interrupt =3D crisv10_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -215,9 +215,9 @@ static const struct TCGCPUOps crisv10_tcg_ops =3D { =20 static const struct TCGCPUOps crisv32_tcg_ops =3D { .initialize =3D cris_initialize_tcg, - .tlb_fill =3D cris_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D cris_cpu_tlb_fill, .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .do_interrupt =3D cris_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/helper.c b/target/cris/helper.c index 36926faf32..a0d6ecdcd3 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -39,22 +39,6 @@ #define D_LOG(...) do { } while (0) #endif =20 -#if defined(CONFIG_USER_ONLY) - -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - CRISCPU *cpu =3D CRIS_CPU(cs); - - cs->exception_index =3D 0xaa; - cpu->env.pregs[PR_EDA] =3D address; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - - static void cris_shift_ccs(CPUCRISState *env) { uint32_t ccs; @@ -304,5 +288,3 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 return ret; } - -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/meson.build b/target/cris/meson.build index 67c3793c85..c1e326d950 100644 --- a/target/cris/meson.build +++ b/target/cris/meson.build @@ -2,13 +2,16 @@ cris_ss =3D ss.source_set() cris_ss.add(files( 'cpu.c', 'gdbstub.c', - 'helper.c', 'op_helper.c', 'translate.c', )) =20 cris_softmmu_ss =3D ss.source_set() -cris_softmmu_ss.add(files('mmu.c', 'machine.c')) +cris_softmmu_ss.add(files( + 'helper.c', + 'machine.c', + 'mmu.c', +)) =20 target_arch +=3D {'cris': cris_ss} target_softmmu_arch +=3D {'cris': cris_softmmu_ss} --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272267584341.1851293263452; Thu, 14 Oct 2021 21:31:07 -0700 (PDT) Received: from localhost ([::1]:58096 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEs6-0007K7-IF for importer@patchew.org; Fri, 15 Oct 2021 00:31:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38992) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ0-0007LQ-K0 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:22 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:40931) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYv-0000MR-MK for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:22 -0400 Received: by mail-pf1-x42f.google.com with SMTP id o133so7289603pfg.7 for ; Thu, 14 Oct 2021 21:11:17 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z8ecs4LTwGjkTaIMjFwaDU18rjRNxTTeFlYdhpfOXR8=; b=Y5qiD56RsJ8Nq4PW05mNcjMMjwYz2jfPvkW213stwBafxD4PnzgoAYsX1S6nD2Yff5 de+rItUoevaMOdp9l6RQsoWkmi2bTp04yWCaqGqdijdPL17LA3YrNMdKVD3gocNVwcyD kjrpR9U/ZB4FX3dxKpM2yzJA5da660XKvyph7gxMPQNT3RSJ6z/QoQr/F4DeP70SeP5D uc1gu+m2vvDyGsLofkx0IwnME4q0QyYpt27YpksB0IwLjEuPrG8Pc0Ah9bNJ10Zxo+8P 9nKp/gFFNURkgBvFH+y4ksW33d7QdVxSGLR5JG57+51T9Fxxp8jOQjIM3zLd0wUBAZSD Y+RQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z8ecs4LTwGjkTaIMjFwaDU18rjRNxTTeFlYdhpfOXR8=; b=lPD086icM7Ut+6n/ZgF6gWCpa1hd8xPwN2HVCWJCmbRSw4Tza+ZyqY9u2DrscZCCMg B+A/yFU5iQ0JYlSDk+53UNMsQA2kyMWXrK6SndvYV4cw9qQGrVNix/LSHouyqROJtr2t 3knzvfrr23fBOqRVIRT97NStcjYLMdkcM/b84LHFrOt4m6LLbgLx85tFKOtb+AcN2/Fv Z1j2H+s8yKBFUHRjP0lkDLj4b7icp6/Jnq8W1YE/ppL+xP5BTVYNeUGFWHDbiv0icQtd lpWIzxlGu5agtoZCXXut1XGogv+O+IZVgeSW7IPVZ6FQZ+X/1sdz68hAAw7Xc+6WzFZ+ y/rQ== X-Gm-Message-State: AOAM530/xjU5q6CxDrZsx2EKCMbFtCERAHtk6NnI9QD9hqmW/X0RMTwN rlyru+XxYVszQHQoboMbF63XOa0nPth92Q== X-Google-Smtp-Source: ABdhPJyUfAOWeBarOFNzrTPDPvUEbiowt6bfPgHUa0EN7Bqnll40toZDAkWNpyfmi16VtIlPO8XXOw== X-Received: by 2002:a65:62d1:: with SMTP id m17mr7324322pgv.370.1634271076273; Thu, 14 Oct 2021 21:11:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 25/67] target/hexagon: Remove hexagon_cpu_tlb_fill Date: Thu, 14 Oct 2021 21:10:11 -0700 Message-Id: <20211015041053.2769193-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Taylor Simpson , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272269018100001 Content-Type: text/plain; charset="utf-8" The fallback code in cpu_loop_exit_sigsegv is sufficient for hexagon linux-user. Remove the code from cpu_loop that raises SIGSEGV. Reviewed-by: Taylor Simpson Signed-off-by: Richard Henderson --- linux-user/hexagon/cpu_loop.c | 24 +----------------------- target/hexagon/cpu.c | 23 ----------------------- 2 files changed, 1 insertion(+), 46 deletions(-) diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index bee2a9e4ea..6b24cbaba9 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -28,8 +28,7 @@ void cpu_loop(CPUHexagonState *env) { CPUState *cs =3D env_cpu(env); - int trapnr, signum, sigcode; - target_ulong sigaddr; + int trapnr; target_ulong syscallnum; target_ulong ret; =20 @@ -39,10 +38,6 @@ void cpu_loop(CPUHexagonState *env) cpu_exec_end(cs); process_queued_cpu_work(cs); =20 - signum =3D 0; - sigcode =3D 0; - sigaddr =3D 0; - switch (trapnr) { case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ @@ -65,12 +60,6 @@ void cpu_loop(CPUHexagonState *env) env->gpr[0] =3D ret; } break; - case HEX_EXCP_FETCH_NO_UPAGE: - case HEX_EXCP_PRIV_NO_UREAD: - case HEX_EXCP_PRIV_NO_UWRITE: - signum =3D TARGET_SIGSEGV; - sigcode =3D TARGET_SEGV_MAPERR; - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); break; @@ -79,17 +68,6 @@ void cpu_loop(CPUHexagonState *env) trapnr); exit(EXIT_FAILURE); } - - if (signum) { - target_siginfo_t info =3D { - .si_signo =3D signum, - .si_errno =3D 0, - .si_code =3D sigcode, - ._sifields._sigfault._addr =3D sigaddr - }; - queue_signal(env, info.si_signo, QEMU_SI_KILL, &info); - } - process_pending_signals(env); } } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 3338365c16..160a46a3d5 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -245,34 +245,11 @@ static void hexagon_cpu_init(Object *obj) qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_prope= rty); } =20 -static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ -#ifdef CONFIG_USER_ONLY - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index =3D HEX_EXCP_FETCH_NO_UPAGE; - break; - case MMU_DATA_LOAD: - cs->exception_index =3D HEX_EXCP_PRIV_NO_UREAD; - break; - case MMU_DATA_STORE: - cs->exception_index =3D HEX_EXCP_PRIV_NO_UWRITE; - break; - } - cpu_loop_exit_restore(cs, retaddr); -#else -#error System mode not implemented for Hexagon -#endif -} - #include "hw/core/tcg-cpu-ops.h" =20 static const struct TCGCPUOps hexagon_tcg_ops =3D { .initialize =3D hexagon_translate_init, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, - .tlb_fill =3D hexagon_tlb_fill, }; =20 static void hexagon_cpu_class_init(ObjectClass *c, void *data) --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272461557973.76102940951; Thu, 14 Oct 2021 21:34:21 -0700 (PDT) Received: from localhost ([::1]:41468 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEvE-0006oP-Dw for importer@patchew.org; Fri, 15 Oct 2021 00:34:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ2-0007No-LU for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:24 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:34605) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYw-0000Nj-Hv for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:23 -0400 Received: by mail-pg1-x530.google.com with SMTP id 133so7465770pgb.1 for ; Thu, 14 Oct 2021 21:11:17 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xDn64Ar0c4NUi8qPBLq+7M9+nijncdxsp88/28xGJnw=; b=Yov1R+NL044SWENOR1xG+VONSMx58VYed3LLoUluBL2dM/Wpek9T8T16O7dkctxn7J ND58+ed9JcpXTNwEj3XfFWQdDtKlnw8cPTsmnvPt52Q9atGaKQQwG1n18UIC93r7uULA 9awjU3UnOFXRyi/YNs0Ik/eC1MjtkMmPPaML83cWiMXjK2NqdsE1PFe6u+7sx7ciyRIx /6FSrv+hTJ9pMn+giMKD4jV3HYmY8yCxCl/iWXpMmKGJVh0AVd/Cisb9J7KDzNPp83aZ JYT3xPHU+MQZtWST7kBnG/pV78VbXJqn8+OZRUTw/Pzj6yrEfLxKmzsD/JV6rn5hPHyz s+iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xDn64Ar0c4NUi8qPBLq+7M9+nijncdxsp88/28xGJnw=; b=3hBA1WE0rZ/PzZepRb8tYibxQtLmciBNqXHvoOXiBoPl9BkdSKjnMpdHmhPJtFmcS0 2SubHS7qdsNrGjn+lMkep/w0U508YwhhXfl2t528J2QMJ3XWnYsZ0JwgIq93O+awWuju uRLdQs3+NPFDTVSjj4nad8Kswbz6Qb1eflKc9isXIUrt3PneeLoOJeECSql9qRXwEc7m Fa3be278VIA3VVkBNl7R5KE4gss8Wn4bogKJYPWYoavRRS8+lcz6qpr+6+ezjvM74+it RL8XWAqghrZwu6jFJO7KMA+Q2QtqPDBlbHCew5deRkGnOnrYMHQR91KmBUdCiQyMFXkx Ulwg== X-Gm-Message-State: AOAM533AheQ08wQ2svfBPDQzmTl4+zkTdONYuvWbFTzU4X3ppxm16lhk U5/6axH/oz/pN4a0bQkABm98+OE/wxIHcQ== X-Google-Smtp-Source: ABdhPJxMYfYWxWgWuiUZinA7zUovUF9paWxR3en5cE89UvlFOwblBZ0kD5eRETlLJtT13yrAegeNvQ== X-Received: by 2002:a63:d94b:: with SMTP id e11mr7211521pgj.295.1634271076937; Thu, 14 Oct 2021 21:11:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 26/67] target/hppa: Make hppa_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:12 -0700 Message-Id: <20211015041053.2769193-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272461931100003 Content-Type: text/plain; charset="utf-8" The fallback code in cpu_loop_exit_sigsegv is sufficient for hppa linux-user. Remove the code from cpu_loop that raised SIGSEGV. This makes all of the code in mem_helper.c sysemu only, so remove the ifdefs and move the file to hppa_softmmu_ss. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 +- linux-user/hppa/cpu_loop.c | 16 ---------------- target/hppa/cpu.c | 2 +- target/hppa/mem_helper.c | 15 --------------- target/hppa/meson.build | 6 ++++-- 5 files changed, 6 insertions(+), 35 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d3cb7a279f..294fd7297f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -323,10 +323,10 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vad= dr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); +#ifndef CONFIG_USER_ONLY bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 81607a9b27..e0a62deeb9 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -144,22 +144,6 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f =3D env->gr[31]; env->iaoq_b =3D env->gr[31] + 4; break; - case EXCP_ITLB_MISS: - case EXCP_DTLB_MISS: - case EXCP_NA_ITLB_MISS: - case EXCP_NA_DTLB_MISS: - case EXCP_IMP: - case EXCP_DMP: - case EXCP_DMB: - case EXCP_PAGE_REF: - case EXCP_DMAR: - case EXCP_DMPI: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr =3D env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 89cba9d7a2..23eb254228 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -145,9 +145,9 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { static const struct TCGCPUOps hppa_tcg_ops =3D { .initialize =3D hppa_translate_init, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, - .tlb_fill =3D hppa_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D hppa_cpu_tlb_fill, .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, .do_interrupt =3D hppa_cpu_do_interrupt, .do_unaligned_access =3D hppa_cpu_do_unaligned_access, diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index afc5b56c3e..bf07445cd1 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -24,20 +24,6 @@ #include "hw/core/cpu.h" #include "trace.h" =20 -#ifdef CONFIG_USER_ONLY -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - HPPACPU *cpu =3D HPPA_CPU(cs); - - /* ??? Test between data page fault and data memory protection trap, - which would affect si_code. */ - cs->exception_index =3D EXCP_DMP; - cpu->env.cr[CR_IOR] =3D address; - cpu_loop_exit_restore(cs, retaddr); -} -#else static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) { int i; @@ -392,4 +378,3 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulon= g vaddr) hppa_tlb_entry *ent =3D hppa_find_tlb(env, vaddr); return ent ? ent->ar_type : -1; } -#endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/meson.build b/target/hppa/meson.build index 8a7ff82efc..021e42a2d0 100644 --- a/target/hppa/meson.build +++ b/target/hppa/meson.build @@ -7,13 +7,15 @@ hppa_ss.add(files( 'gdbstub.c', 'helper.c', 'int_helper.c', - 'mem_helper.c', 'op_helper.c', 'translate.c', )) =20 hppa_softmmu_ss =3D ss.source_set() -hppa_softmmu_ss.add(files('machine.c')) +hppa_softmmu_ss.add(files( + 'machine.c', + 'mem_helper.c', +)) =20 target_arch +=3D {'hppa': hppa_ss} target_softmmu_arch +=3D {'hppa': hppa_softmmu_ss} --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272426950971.8614659161088; Thu, 14 Oct 2021 21:33:46 -0700 (PDT) Received: from localhost ([::1]:38288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEuf-0004ey-N9 for importer@patchew.org; Fri, 15 Oct 2021 00:33:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ8-0007Se-94 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:33489) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYy-0000OQ-Ab for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:26 -0400 Received: by mail-pg1-x533.google.com with SMTP id j190so699112pgd.0 for ; Thu, 14 Oct 2021 21:11:18 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bcv7+vrfVWDaxhREKP7oW3QycojCjuZf0xWMtNuZYi8=; b=nqjIwyO7/ZRFzBPLOzhopXQZLFm+44ULxd4SnMfqxFopMonT56mMtoiQiD3DaMjYqQ I356AZsJYnrdLddc2Ilv2QCStubgYhuPMVEDfdYZa2Y4y2qLi1DZ1XAVxAs2fNSWJi/4 EXIg0+Optnbz12ixi1cvonfEegRbuwVYr7HZ66WFMGhSRAy+yBy6RLxyUxGeFXfJS93x v5UR1hAYDW2tk4Hbw695Ysdqfaiq6FsvnJXdW06uCndeB7rho3807nYOpQhQzYfiAZ/8 8X5CY/GMu1AvmS96k7BfD9TOELsnFdZvNe3mp4jo8DYEk7Fv0wnV927gPxhVPguMczTm TUjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bcv7+vrfVWDaxhREKP7oW3QycojCjuZf0xWMtNuZYi8=; b=sHrRtzo57idoP+VOtFYmSPjrvAkC0sVM8QzQKwUsLcSf6UI3ipChjOSn8wqmnbV6Lq 2kLvrcQIKpaS09vKjqH6PKbZR/G03D110zmdXsa01j2YkL9zHbc/CTHKKlWzFd72+7AD 3ggil9Elpw7Dmh/AzUC0QJumkPHo8gHi6rH8ne7SxXi6C1Vr7cMXn4cja3BYDQFN1k3F wBJOF9GrK/m5u/42k6zgtZbz6LGXEzCtHvDFSflzcO4PZh5/IFfrelicSbKRoDby2jfW QMeBi/FWAU6XGB55hIa6gggjDUdRuy1+Q5B5pzT3R60NYtFyXZ4zeGkMCT1hJGMQ3WtN 9Oig== X-Gm-Message-State: AOAM530Nx3jmVe7xFpPf7IRZC3Op/y61OlQ+AcxVGP48z5wCIcPS25Ke RRD46R52Zy1FOmnKpYjLYUhR5X5QQydTCw== X-Google-Smtp-Source: ABdhPJxTZ/Y7ATUdyRUEp+2teEwdKAVvEbY7cDTIU5PhrJUvTaAfziQ8RtEVF+HNLEpZpmTg75ctMw== X-Received: by 2002:a63:7447:: with SMTP id e7mr7408673pgn.261.1634271077653; Thu, 14 Oct 2021 21:11:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 27/67] target/i386: Implement x86_cpu_record_sigsegv Date: Thu, 14 Oct 2021 21:10:13 -0700 Message-Id: <20211015041053.2769193-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272428269100001 Record cr2, error_code, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. Use the maperr parameter to properly set PG_ERROR_P_MASK. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 6 ++++++ target/i386/tcg/tcg-cpu.c | 3 ++- target/i386/tcg/user/excp_helper.c | 23 +++++++++++++++++------ 3 files changed, 25 insertions(+), 7 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 60ca09e95e..0a4401e917 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -43,9 +43,15 @@ bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif =20 /* helper.c */ +#ifdef CONFIG_USER_ONLY +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif =20 void breakpoint_handler(CPUState *cs); =20 diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 3ecfae34cb..6fdfdf9598 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -72,10 +72,11 @@ static const struct TCGCPUOps x86_tcg_ops =3D { .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .cpu_exec_enter =3D x86_cpu_exec_enter, .cpu_exec_exit =3D x86_cpu_exec_exit, - .tlb_fill =3D x86_cpu_tlb_fill, #ifdef CONFIG_USER_ONLY .fake_user_interrupt =3D x86_cpu_do_interrupt, + .record_sigsegv =3D x86_cpu_record_sigsegv, #else + .tlb_fill =3D x86_cpu_tlb_fill, .do_interrupt =3D x86_cpu_do_interrupt, .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, .debug_excp_handler =3D breakpoint_handler, diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp= _helper.c index a89b5228fd..cd507e2a1b 100644 --- a/target/i386/tcg/user/excp_helper.c +++ b/target/i386/tcg/user/excp_helper.c @@ -22,18 +22,29 @@ #include "exec/exec-all.h" #include "tcg/helper-tcg.h" =20 -bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; =20 + /* + * The error_code that hw reports as part of the exception frame + * is copied to linux sigcontext.err. The exception_index is + * copied to linux sigcontext.trapno. Short of inventing a new + * place to store the trapno, we cannot let our caller raise the + * signal and set exception_index to EXCP_INTERRUPT. + */ env->cr[2] =3D addr; - env->error_code =3D (access_type =3D=3D MMU_DATA_STORE) << PG_ERROR_W_= BIT; - env->error_code |=3D PG_ERROR_U_MASK; + env->error_code =3D ((access_type =3D=3D MMU_DATA_STORE) << PG_ERROR_W= _BIT) + | (maperr ? 0 : PG_ERROR_P_MASK) + | PG_ERROR_U_MASK; cs->exception_index =3D EXCP0E_PAGE; + + /* Disable do_interrupt_user. */ env->exception_is_int =3D 0; env->exception_next_eip =3D -1; - cpu_loop_exit_restore(cs, retaddr); + + cpu_loop_exit_restore(cs, ra); } --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271973512786.5786094297006; Thu, 14 Oct 2021 21:26:13 -0700 (PDT) Received: from localhost ([::1]:44182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEnM-0006ZI-HT for importer@patchew.org; Fri, 15 Oct 2021 00:26:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ8-0007Sc-8r for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:40808) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYy-0000Oh-At for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:26 -0400 Received: by mail-pg1-x52d.google.com with SMTP id q5so7431227pgr.7 for ; Thu, 14 Oct 2021 21:11:19 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/utnMsLyouv7LilvnHYZPxrZ8zRoC/jZ7xS1qGJE894=; b=HFNiH3O02qLQBBvg1obEw2pNCXQWPNxXjz71Cf5BbG5AvpYlzdMJe/sD+bvGM6Fx9l fiNqUI8Bi5APeNu7pdIuLltRnbVaM7jdeRRSw3Yc+vIfowM6ulpM8yFc8EZv4BeW84Af RGf2C3HifUpwLeoqYbhDM5uZ2jh60UfMiove169hA9WSVY4ZkhmMdGOkwoSuB5h+NjXT t3CjQISIpblujY6oYVDHjLe9PhC4D5UWacoyabohT/HhV29yminaocXYrSH55fV9IBxJ Ko5iCL8zF3L502A4DRqw2Ewfqi6J5+OD7Be1yi0t4na0zkftH/iNppyN/VRiBpOtSHjY AqQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/utnMsLyouv7LilvnHYZPxrZ8zRoC/jZ7xS1qGJE894=; b=tL7ENj2TLlebFz7jltO5JAKUJPK8bfcWQ8QNLcgutXpFoPYm+i/om6WH5j5YdsrDV+ h5SDsYXQ1MPbRCJEJO9RAQidLQggM2zMHaaOLvFr8NHgCC44s1YgqsKnrRZn8u0Yx0Al m0073njPhIiGYty4Xc4pRkKfa7FA43CzXeWPZslKIPveJ75r/I7aeVh4YHDXSGZdhhsn uuKhXeoiDFX+1DCXYlvcE+0J+hlARAO88plUSlpB08B7tkfCl4FhXCjO/YIejeCCckIj /0ixl+07sWwe4V5L8khlZ2FnKHkmhPs0mdABEJ5XHNkXsQiXnVgCMirIWEhUn9kPcA/6 otYQ== X-Gm-Message-State: AOAM530gzQfyhaDdvOvM6DfB/AlAr5fx+zMe3ErXcZvywoE1FKoe1Vgx gdr5PIFrJBsBqxkUHETLvHzpgmsoM2KTAw== X-Google-Smtp-Source: ABdhPJy2sXE27u1ekcYk+V3nKaRKoPOrMiJoqnFJ+uvilE/23y7HLM3tS6RL18r1N4AoWJWv5L9yCA== X-Received: by 2002:a63:2a92:: with SMTP id q140mr7429761pgq.412.1634271078458; Thu, 14 Oct 2021 21:11:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 28/67] target/m68k: Make m68k_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:14 -0700 Message-Id: <20211015041053.2769193-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271974753100001 The fallback code in cpu_loop_exit_sigsegv is sufficient for m68k linux-user. Remove the code from cpu_loop that handled EXCP_ACCESS. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 10 ---------- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 6 +----- 3 files changed, 2 insertions(+), 16 deletions(-) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index ebf32be78f..790bd558c3 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -90,16 +90,6 @@ void cpu_loop(CPUM68KState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; - case EXCP_ACCESS: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->mmu.ar; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_DEBUG: info.si_signo =3D TARGET_SIGTRAP; info.si_errno =3D 0; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 66d22d1189..c7aeb7da9c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -515,9 +515,9 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { =20 static const struct TCGCPUOps m68k_tcg_ops =3D { .initialize =3D m68k_tcg_init, - .tlb_fill =3D m68k_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D m68k_cpu_tlb_fill, .cpu_exec_interrupt =3D m68k_cpu_exec_interrupt, .do_interrupt =3D m68k_cpu_do_interrupt, .do_transaction_failed =3D m68k_cpu_transaction_failed, diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 137a3e1a3d..5728e48585 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -978,16 +978,12 @@ void m68k_set_irq_level(M68kCPU *cpu, int level, uint= 8_t vector) } } =20 -#endif - bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType qemu_access_type, int mmu_idx, bool probe, uintptr_t retaddr) { M68kCPU *cpu =3D M68K_CPU(cs); CPUM68KState *env =3D &cpu->env; - -#ifndef CONFIG_USER_ONLY hwaddr physical; int prot; int access_type; @@ -1051,12 +1047,12 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, if (!(access_type & ACCESS_STORE)) { env->mmu.ssw |=3D M68K_RW_040; } -#endif =20 cs->exception_index =3D EXCP_ACCESS; env->mmu.ar =3D address; cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ =20 uint32_t HELPER(bitrev)(uint32_t x) { --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272529735942.6325750151601; Thu, 14 Oct 2021 21:35:29 -0700 (PDT) Received: from localhost ([::1]:46612 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEwK-0001pS-NV for importer@patchew.org; Fri, 15 Oct 2021 00:35:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39152) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZC-0007WK-Sy for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:36 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:41898) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ0-0000PL-Bt for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:34 -0400 Received: by mail-pl1-x62e.google.com with SMTP id e10so713643plh.8 for ; Thu, 14 Oct 2021 21:11:20 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uBSoYrit32aNGLBOXaD1hzT0A4rXkiN+8LxdOJhc9ag=; b=hvWe4qLdlujEDwSl0Psa3dI+rRN5jNmxftq8B7i3XGU5t1k4/NUF80hDI98Y0jBfvF OON0CR27ANELG42hAwn+H17RmiZ5BN32Bixo3qNqwmX8LilbumnaO9C8pl5/PqRsbI3u 4PchaQAcdUjnOEezNP1Jcrx7/YaLEU7sa90YsrO6nRV0IolMJAQJvfScPuDLRLn5NJ+Z zW81cTmsYbG/5suB2XadIKGSO28KBhxF4utC/Pcj5lT2ZhxSVDAlTYDJtWa7M8/YR80j xkq47JeCXtMe/M42o25ER4CZFIaJn5Kw1sW2MtEJPL3hk7p45+vea/ePfNybnlE2bZHK O+kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uBSoYrit32aNGLBOXaD1hzT0A4rXkiN+8LxdOJhc9ag=; b=GuMILCN6U7Bj033WCkmFIOhbOM11pjA1ksx0DWdATh3y0Z8iz9eGrEd8Ki4uSFdsiM kvyWC1H9dOUvc6o68IQdwlauawPnTjJz0hi4jmF3oNxm3VoomApFNBY4kqgDelOHr9YV UEdrQ/x7UxS99LQ9M9lPprM8Wa7XhBF+2A7Y3dVpx03C6KWjwTUO1AFDnivW2v8QV4IT 1MUnkmkBpH9zb2p3nCSgPyIchwkn8b2pc1dVjKP+qU7ohsGh39PkR9XKsL+MLmlSy0/G bGSQBH1wMW3OdArUBNJ8vapkETEHAXO9gYDgtmC1AolC/Flr1HBCAuNUgPMj9/Pq5EGy fBlA== X-Gm-Message-State: AOAM531CIL5mpKmQ8DYskjV6hMIutXJpFWlODEokycD8C5nfjD5lqgpW O9trTzUhQLJe4uZ8ndzkMXa14Wke+klNlQ== X-Google-Smtp-Source: ABdhPJxyb5wn+bGjHd65vB1aflzIAndYIrzqqo66JO/m9KVj4KVIS/2pMxkX0kDPkTf3bSaD4Uzw/Q== X-Received: by 2002:a17:902:7e01:b0:13f:7f2e:753e with SMTP id b1-20020a1709027e0100b0013f7f2e753emr6950346plm.88.1634271079247; Thu, 14 Oct 2021 21:11:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 29/67] target/microblaze: Make mb_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:15 -0700 Message-Id: <20211015041053.2769193-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272530295100001 Content-Type: text/plain; charset="utf-8" The fallback code in cpu_loop_exit_sigsegv is sufficient for microblaze linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 8 ++++---- linux-user/microblaze/cpu_loop.c | 10 ---------- target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 13 +------------ 4 files changed, 6 insertions(+), 27 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b7a848bbae..e9cd0b88de 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -394,10 +394,6 @@ void mb_tcg_init(void); #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ =20 -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - typedef CPUMBState CPUArchState; typedef MicroBlazeCPU ArchCPU; =20 @@ -415,6 +411,10 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *en= v, target_ulong *pc, } =20 #if !defined(CONFIG_USER_ONLY) +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c index 52222eb93f..a94467dd2d 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -37,16 +37,6 @@ void cpu_loop(CPUMBState *env) process_queued_cpu_work(cs); =20 switch (trapnr) { - case 0xaa: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 15db277925..b9c888b87e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -365,9 +365,9 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { static const struct TCGCPUOps mb_tcg_ops =3D { .initialize =3D mb_tcg_init, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, - .tlb_fill =3D mb_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D mb_cpu_tlb_fill, .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, .do_interrupt =3D mb_cpu_do_interrupt, .do_transaction_failed =3D mb_cpu_transaction_failed, diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index dd2aecd1d5..a607fe68e5 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -24,18 +24,7 @@ #include "qemu/host-utils.h" #include "exec/log.h" =20 -#if defined(CONFIG_USER_ONLY) - -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - cs->exception_index =3D 0xaa; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, MMUAccessType access_type) { --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272077181667.3048318297064; Thu, 14 Oct 2021 21:27:57 -0700 (PDT) Received: from localhost ([::1]:49608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEp0-0001hX-Uj for importer@patchew.org; Fri, 15 Oct 2021 00:27:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39064) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ4-0007QR-KB for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:27 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:34547) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ0-0000PR-Bu for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:26 -0400 Received: by mail-pl1-x635.google.com with SMTP id g5so5614833plg.1 for ; Thu, 14 Oct 2021 21:11:20 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tIWq1Y9Lh6wr1x/ixIjLaUf11V/zxN9xw2JRcPgovYc=; b=a/sYVd+UX7TZVckOcnEM+bcpnsACj/r+4bKYFBAB+UOgzyfHevirk7crsSwBoXuZ6c 0LK5rrAAD93ql+K/9ylRCP/FqsmhyKcRwbnpBX/Er7fNN9l9kl2Mr3b5FnkW/Mfnsf2J ytJCb3cq9xlopOlFgmcdJ9ovWNXczFzF6v/MK3g57zc9k6uUi7nwebNWp8t4wLCRI8z6 lsKYexKLVOegebBkFpx1PaCUFzNTtjJewerYzxmEb4nXk3FYOer9rd3Y6dJcSCvQFzzv XKb9KSIbxH+uZ4LCQk+BlStkk4CptD/8hAr/IkgK2NG0zvtTfln06WHMRApmlkw8j33/ DCGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tIWq1Y9Lh6wr1x/ixIjLaUf11V/zxN9xw2JRcPgovYc=; b=ac+9wzQBLa9X3wSkR3TPjcKbuMG/4M8a1GV75CImkDlJlvEfFQJvxLhv02Vnd+9zKF fJzRLP9+AAgFrvjHGbiSH0z2pce2ur43TGzS99NPqoiyP/Wk27BCceHKbEjmPCOWTujb 9TwCZSfkI6aG4NieOvc6OrilxZVMwGN2uzRjfU4YK0EKSYuwcykbwe3bywcmiQyoo8CD +zNMak5/ZW0uZY0uOceaN1a2ia4V+PgFJHqo5jtiSt6onRytHJnV4QL6Z5EIdSFcklzh 9irPxeKzu5fLaNR+FwQxdW7HEkyGgw9DNcurKbVfioiExTzu32g3yNxm58r7MpNh4n8h nKmA== X-Gm-Message-State: AOAM533uOISa3WbXURyZgHYOypR7pQWTqKiCn8X83N0uaIpedefaPgoa iPkw2mX1jIB1nHLNsX4hb4nuMeuqjRvMJQ== X-Google-Smtp-Source: ABdhPJzhWFtrysm7ydQRUa/8yv+JRSbrZ9zpAplw32nf2a76WwEhpJ/sevdBLxLq4t0JVHbpIMS7DA== X-Received: by 2002:a17:90a:c081:: with SMTP id o1mr25714632pjs.24.1634271079903; Thu, 14 Oct 2021 21:11:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 30/67] target/mips: Make mips_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:16 -0700 Message-Id: <20211015041053.2769193-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272079033100001 The fallback code in cpu_loop_exit_sigsegv is sufficient for mips linux-user. This means we can remove tcg/user/tlb_helper.c entirely. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- target/mips/tcg/tcg-internal.h | 7 ++-- linux-user/mips/cpu_loop.c | 11 ------ target/mips/cpu.c | 2 +- target/mips/tcg/user/tlb_helper.c | 59 ------------------------------- target/mips/tcg/meson.build | 3 -- target/mips/tcg/user/meson.build | 3 -- 6 files changed, 5 insertions(+), 80 deletions(-) delete mode 100644 target/mips/tcg/user/tlb_helper.c delete mode 100644 target/mips/tcg/user/meson.build diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index bad3deb611..466768aec4 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -18,9 +18,6 @@ void mips_tcg_init(void); =20 void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; @@ -60,6 +57,10 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, MemTxResult response, uintptr_t retadd= r); void cpu_mips_tlb_flush(CPUMIPSState *env); =20 +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + #endif /* !CONFIG_USER_ONLY */ =20 #endif diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cb03fb066b..b735c99a24 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -158,17 +158,6 @@ done_syscall: } env->active_tc.gpr[2] =3D ret; break; - case EXCP_TLBL: - case EXCP_TLBS: - case EXCP_AdEL: - case EXCP_AdES: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->CP0_BadVAddr; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_CpU: case EXCP_RI: info.si_signo =3D TARGET_SIGILL; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 00e0c55d0e..4aae23934b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -539,9 +539,9 @@ static const struct SysemuCPUOps mips_sysemu_ops =3D { static const struct TCGCPUOps mips_tcg_ops =3D { .initialize =3D mips_tcg_init, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, - .tlb_fill =3D mips_cpu_tlb_fill, =20 #if !defined(CONFIG_USER_ONLY) + .tlb_fill =3D mips_cpu_tlb_fill, .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .do_interrupt =3D mips_cpu_do_interrupt, .do_transaction_failed =3D mips_cpu_do_transaction_failed, diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c deleted file mode 100644 index 210c6d529e..0000000000 --- a/target/mips/tcg/user/tlb_helper.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * MIPS TLB (Translation lookaside buffer) helpers. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#include "qemu/osdep.h" - -#include "cpu.h" -#include "exec/exec-all.h" -#include "internal.h" - -static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type) -{ - CPUState *cs =3D env_cpu(env); - - env->error_code =3D 0; - if (access_type =3D=3D MMU_INST_FETCH) { - env->error_code |=3D EXCP_INST_NOTAVAIL; - } - - /* Reference to kernel address from user mode or supervisor mode */ - /* Reference to supervisor address from user mode */ - if (access_type =3D=3D MMU_DATA_STORE) { - cs->exception_index =3D EXCP_AdES; - } else { - cs->exception_index =3D EXCP_AdEL; - } - - /* Raise exception */ - if (!(env->hflags & MIPS_HFLAG_DM)) { - env->CP0_BadVAddr =3D address; - } -} - -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - /* data access */ - raise_mmu_exception(env, address, access_type); - do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); -} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 8f6f7508b6..98003779ae 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -28,9 +28,6 @@ mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'mxu_translate.c', )) =20 -if have_user - subdir('user') -endif if have_system subdir('sysemu') endif diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.= build deleted file mode 100644 index 79badcd321..0000000000 --- a/target/mips/tcg/user/meson.build +++ /dev/null @@ -1,3 +0,0 @@ -mips_user_ss.add(files( - 'tlb_helper.c', -)) --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634271917807144.72001271948056; Thu, 14 Oct 2021 21:25:17 -0700 (PDT) Received: from localhost ([::1]:41116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEmS-0004QQ-R2 for importer@patchew.org; Fri, 15 Oct 2021 00:25:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ2-0007OK-Ph for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:26 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:38456) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ0-0000Pb-Bk for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:23 -0400 Received: by mail-pj1-x102a.google.com with SMTP id g13-20020a17090a3c8d00b00196286963b9so8450178pjc.3 for ; Thu, 14 Oct 2021 21:11:21 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uF38/TBQjdWDQM8FyXjqkWfqx61a2FgTbzu2sn+FnBE=; b=jF3RtzXzt5MZzqir004gfvqFOPQopXnZQNA1a5y917Sy5Vq/K35jRfw9abd1JuYe0g 3/ais4O6lVkzC+eGfHxRleTx9PBqlS6uhSctPcdkD1J3CftPCP6yBVdSD4vIgSpMxO7l CGm4NOOZdRu5qDg/mvmHCvlk80I4F4jaPDZ8hD3mUA6ZGx1FJbKRtARTLKh/aYXYChxZ VbKTEY0xszS//0ar/w4CLNM5ex24zd2ziiMaZ4ZCyMQSjKhJXq/g+Wkls6goxWTXQOsJ T0O1CqzygQuQZbW9XMayxJbGkv8PDdf4Z8xMXY3bAPSg7h4/Xa2K0dimsRCttvvH2Zp7 fQKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uF38/TBQjdWDQM8FyXjqkWfqx61a2FgTbzu2sn+FnBE=; b=N9OQskrcwkay3qWzoOzcS4bkrv/SB/lFw8XSW1Dsmb2AUoYvTR6SEpM3Ivg+IGgpBd Lrjhw7cFrGMzXnFLjMVDeqnxT6WB7WtmNEG5z9WntozJLnYnXZZ2iZ9PVBYR6AKgWmna oRHH2kQGr8039Y0oLERD01BiJVAKWdK9FI73gBpfmbFgEyjHkUcMI2VVMa+xsjEo6mum tvhICd+pLsfb9fzKWWoiezn8hb7HpX0s7Td71tMwzQNkabZ5eqozy0NVBJZIt+1Fl2L6 QxU5AQirnTmPf3gH0coeWnhsYBeJG8u/5b4dUKXaEHnUJT/qac/dCGS/blglNIXjlw8o PtBw== X-Gm-Message-State: AOAM531xmEc+SwWgWwi2GNPgkO3ljHElN1HcYcXiTq7fC2swQ6f/yuyB a2aApgZ7yok3z7jJq+4cd4QyWLMaAxu2og== X-Google-Smtp-Source: ABdhPJzYa3GYjMDs9UV21DhsTEtne9J0MV/hAVK9fFdd+qV8H+L4RGu5NMr4SiwqIC3NensgrklJIw== X-Received: by 2002:a17:902:f54c:b0:13f:1e7:e467 with SMTP id h12-20020a170902f54c00b0013f01e7e467mr8958318plf.40.1634271080682; Thu, 14 Oct 2021 21:11:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 31/67] target/nios2: Implement nios2_cpu_record_sigsegv Date: Thu, 14 Oct 2021 21:10:17 -0700 Message-Id: <20211015041053.2769193-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634271918679100001 Because the linux-user kuser page handling is currently implemented by detecting magic addresses in the unnamed 0xaa trap, we cannot simply remove nios2_cpu_tlb_fill and rely on the fallback code. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 6 ++++++ target/nios2/cpu.c | 6 ++++-- target/nios2/helper.c | 7 ++++--- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index a80587338a..1a69ed7a49 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -218,9 +218,15 @@ static inline int cpu_mmu_index(CPUNios2State *env, bo= ol ifetch) MMU_SUPERVISOR_IDX; } =20 +#ifdef CONFIG_USER_ONLY +void nios2_cpu_record_sigsegv(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif =20 static inline int cpu_interrupts_enabled(CPUNios2State *env) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 947bb09bc1..421cad114a 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -220,9 +220,11 @@ static const struct SysemuCPUOps nios2_sysemu_ops =3D { =20 static const struct TCGCPUOps nios2_tcg_ops =3D { .initialize =3D nios2_tcg_init, - .tlb_fill =3D nios2_cpu_tlb_fill, =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D nios2_cpu_record_sigsegv, +#else + .tlb_fill =3D nios2_cpu_tlb_fill, .cpu_exec_interrupt =3D nios2_cpu_exec_interrupt, .do_interrupt =3D nios2_cpu_do_interrupt, .do_unaligned_access =3D nios2_cpu_do_unaligned_access, diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 53be8398e9..e5c98650e1 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -38,10 +38,11 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[R_EA] =3D env->regs[R_PC] + 4; } =20 -bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { + /* FIXME: Disentangle kuser page from linux-user sigsegv handling. */ cs->exception_index =3D 0xaa; cpu_loop_exit_restore(cs, retaddr); } --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272627548851.6337496587903; Thu, 14 Oct 2021 21:37:07 -0700 (PDT) Received: from localhost ([::1]:49940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbExu-00048S-HF for importer@patchew.org; Fri, 15 Oct 2021 00:37:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39116) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ8-0007Sd-8x for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:44001) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ1-0000Pf-2r for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:26 -0400 Received: by mail-pl1-x62f.google.com with SMTP id y1so5586572plk.10 for ; Thu, 14 Oct 2021 21:11:22 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jv32Frh7rweOdu9XSPHyzH/l4ZHzlE4pw5zka9V4K8I=; b=C0pn/RJfXeJosErKpF0THofxdQkU9lnKZFfdZP0/LmJtrOTLRh2sja8+LvDAnxBE9E 7Q28onp9VrZBy0b0b5/0RuRGBEN0TlqBfawR+vX7twnStRdy9AdA0Yu91tlZdVa+o0LN q2RExSMrS2L9YnLzlR/4nNXBLMgw4Cy88VJ3Uqw96ZtpODPJRidRFEmHJoHUICLmf+f0 egXvyDWA21g+kyjL+FZY018SYymKDJLpN4nU88izN9feal5O2I3FiCRexUezox0gv9rt qg4DTQqMv9r8evGzhZdiZf9lLhh0w/4m3iSsCX/brdNj0uXNLxvPNG1gvHbNf9J8cJDH vTcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jv32Frh7rweOdu9XSPHyzH/l4ZHzlE4pw5zka9V4K8I=; b=nAvd7QMY/l1Ddx1RzrbS7WxkqZpVtsu2fz7IhE4binpnOs/U0T30FVKpRizfL6DH2t vHbWYTUFVRphLstSskz+6Mo9FxiJ2LCCulrVnVEDjrVztAYm/4unIM3KyZ7k70rQvOE3 vyz/4MYoOgUKD8aeJFYzEGk0u3YbsoyXNNn+jb6GfFp7E9hWACw5YB7yKoBw+Ciob40R bFJYhQl3B9ccv3N7NXfz2y5caqTtACijHucXrFB9+0DQkAP0JoqIEhs7/O27H2uKmtZ/ ewnjqsFDW21DPeooeWqsV2TC+OV0HK4X8dLo0LpUCKBEg4tWTD5GpjLjLmRA19Q/qb3x J0Qw== X-Gm-Message-State: AOAM533H6KwnjmMKq4h60xEt0IhHFjt0Y6CYkzk+ZUDjfznNAkvgW17w 9ISqz4ivg1/wUgUieiTPOG4PLx7Txz6Xig== X-Google-Smtp-Source: ABdhPJyOkMeDFPAE+tcPkTPKJTTKf281Nvo9Ivgu4VcKcltBhxDkezGBsH7JA4dH+aYjNfnWjvR41w== X-Received: by 2002:a17:90b:34a:: with SMTP id fh10mr25171713pjb.51.1634271081301; Thu, 14 Oct 2021 21:11:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 32/67] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE Date: Thu, 14 Oct 2021 21:10:18 -0700 Message-Id: <20211015041053.2769193-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272629712100001 Content-Type: text/plain; charset="utf-8" The kernel vectors both of these through unhandled_exception, which results in force_sig(SIGSEGV). This isn't very useful for userland when enabling overflow traps or fpu traps, but c'est la vie. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- linux-user/openrisc/cpu_loop.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index f6360db47c..de5417a262 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -56,13 +56,17 @@ void cpu_loop(CPUOpenRISCState *env) break; case EXCP_DPF: case EXCP_IPF: - case EXCP_RANGE: info.si_signo =3D TARGET_SIGSEGV; info.si_errno =3D 0; info.si_code =3D TARGET_SEGV_MAPERR; info._sifields._sigfault._addr =3D env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; + case EXCP_RANGE: + case EXCP_FPE: + /* ??? The kernel vectors both of these to unhandled_exception= . */ + force_sig(TARGET_SIGSEGV); + break; case EXCP_ALIGN: info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; @@ -77,13 +81,6 @@ void cpu_loop(CPUOpenRISCState *env) info._sifields._sigfault._addr =3D env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_FPE: - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - info.si_code =3D 0; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_INTERRUPT: /* We processed the pending cpu work above. */ break; --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273095997774.8870729734159; Thu, 14 Oct 2021 21:44:55 -0700 (PDT) Received: from localhost ([::1]:46646 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF5S-0004j6-ID for importer@patchew.org; Fri, 15 Oct 2021 00:44:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39136) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ9-0007Uk-Hz for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:32 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:38458) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ4-0000Pp-5i for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:31 -0400 Received: by mail-pj1-x102c.google.com with SMTP id g13-20020a17090a3c8d00b00196286963b9so8450204pjc.3 for ; Thu, 14 Oct 2021 21:11:23 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B4SaQQZmznpnKQ4FPXFeYarEGh4avP+2dHJ0pw3Dp+w=; b=snB7U9BCAyYe79gwGw9WOqvRKi//GMKY+iNOK2sJKjzfRA55j1iKbN7m8xfEzqp8GH NVrShqskimLkzaAXTeq0B7v5DxLm3ixD1pI/cDFQIGMXDPjCjIJM9WvB8oJpb0csY/C7 JfvTPB08qq7oBuwITG4iug9WXXrqPSKw0KitEi+NzbBLpFJUyLs8uT29tkFHZLd4VngO feg/XRnYKfXzEiMAhJmr/tWJCcNFlkQtLWlilUWJ79PGaFIG4BrDU9qzCz1mvUO+wFKJ JN5u6Szc8Iqjd3a+3tC6ukXWsIERmfSwy/3GDMZE9VMepwzDZw7a5OlMufuUec0M1Atq VL9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B4SaQQZmznpnKQ4FPXFeYarEGh4avP+2dHJ0pw3Dp+w=; b=VY9GIurILq7VbcSXhcm2nVyBygujAErBxpmVal6eLRHKpasRYGX51hRBSIP+wPglTF QiJ6wXKoB9VlsMea8csjSoXaC6KmfvNz1nT0oABNon2oh0jddiFVGmkKmKd4GQsmmo2x NF4mVOam1K0JybhnkSfSBmuu4tGskoNE9334LVPfqEWcE5obHu9jferCAbcWChdxBvRC v2Cb342LeUGeyJsD9J9dDUM7CLhnnU1Mynlcm7E6QuozmEOuA28nom/UAWIsp+qlk11u lskuipB9Q1F8b/DpDGixLJCpivGIZRxyyy3axBzTe5bPRjxKYocx8MyU976KEWM4T4vN WaSA== X-Gm-Message-State: AOAM530XMUyl+uRReejQ4rTr39HAfF9pz0Lnw3LzfNTk1Zms4jNX4+mu OnloV85RYnA/UmN3UMdIplvv3ejSUwSnQQ== X-Google-Smtp-Source: ABdhPJwyyWk4X6vL89lqLNsn/t1c63GZ+CAlhXY5f5X3aBEV6a1mMPR8/yWcTH00u97BKPfiAqOQBA== X-Received: by 2002:a17:90b:3749:: with SMTP id ne9mr25406946pjb.192.1634271082148; Thu, 14 Oct 2021 21:11:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 33/67] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:19 -0700 Message-Id: <20211015041053.2769193-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273097406100001 The fallback code in cpu_loop_exit_sigsegv is sufficient for openrisc linux-user. This makes all of the code in mmu.c sysemu only, so remove the ifdefs and move the file to openrisc_softmmu_ss. Remove the code from cpu_loop that handled EXCP_DPF. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 7 ++++--- linux-user/openrisc/cpu_loop.c | 8 -------- target/openrisc/cpu.c | 2 +- target/openrisc/mmu.c | 9 --------- target/openrisc/meson.build | 2 +- 5 files changed, 6 insertions(+), 22 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 187a4a114e..ee069b080c 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -317,14 +317,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu= , vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg= ); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); int print_insn_or1k(bfd_vma addr, disassemble_info *info); =20 #define cpu_list cpu_openrisc_list =20 #ifndef CONFIG_USER_ONLY +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + extern const VMStateDescription vmstate_openrisc_cpu; =20 void openrisc_cpu_do_interrupt(CPUState *cpu); diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index de5417a262..fb37fb7651 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -54,14 +54,6 @@ void cpu_loop(CPUOpenRISCState *env) cpu_set_gpr(env, 11, ret); } break; - case EXCP_DPF: - case EXCP_IPF: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_RANGE: case EXCP_FPE: /* ??? The kernel vectors both of these to unhandled_exception= . */ diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 27cb04152f..dfbafc5236 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -186,9 +186,9 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { =20 static const struct TCGCPUOps openrisc_tcg_ops =3D { .initialize =3D openrisc_translate_init, - .tlb_fill =3D openrisc_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D openrisc_cpu_tlb_fill, .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .do_interrupt =3D openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 94df8c7bef..e561ef245b 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -23,11 +23,8 @@ #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "qemu/host-utils.h" -#ifndef CONFIG_USER_ONLY #include "hw/loader.h" -#endif =20 -#ifndef CONFIG_USER_ONLY static inline void get_phys_nommu(hwaddr *phys_addr, int *prot, target_ulong address) { @@ -94,7 +91,6 @@ static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_ad= dr, int *prot, return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS; } } -#endif =20 static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, int exception) @@ -112,8 +108,6 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, in= t size, { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); int excp =3D EXCP_DPF; - -#ifndef CONFIG_USER_ONLY int prot; hwaddr phys_addr; =20 @@ -138,13 +132,11 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, = int size, if (probe) { return false; } -#endif =20 raise_mmu_exception(cpu, addr, excp); cpu_loop_exit_restore(cs, retaddr); } =20 -#ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); @@ -177,4 +169,3 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, v= addr addr) return phys_addr; } } -#endif diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build index e445dec4a0..84322086ec 100644 --- a/target/openrisc/meson.build +++ b/target/openrisc/meson.build @@ -10,7 +10,6 @@ openrisc_ss.add(files( 'fpu_helper.c', 'gdbstub.c', 'interrupt_helper.c', - 'mmu.c', 'sys_helper.c', 'translate.c', )) @@ -19,6 +18,7 @@ openrisc_softmmu_ss =3D ss.source_set() openrisc_softmmu_ss.add(files( 'interrupt.c', 'machine.c', + 'mmu.c', )) =20 target_arch +=3D {'openrisc': openrisc_ss} --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272799099811.4691112578272; Thu, 14 Oct 2021 21:39:59 -0700 (PDT) Received: from localhost ([::1]:58420 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF0g-0001eH-4O for importer@patchew.org; Fri, 15 Oct 2021 00:39:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ8-0007Sg-Cf for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:33480) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ4-0000Ps-5w for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:28 -0400 Received: by mail-pg1-x529.google.com with SMTP id j190so699318pgd.0 for ; Thu, 14 Oct 2021 21:11:24 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KnTU5CAKa2qgMNASytkbtJZqSTjvEtUQYaIow0w1ICM=; b=a7eb1zlPqc3bP74CRPkCEpi9STnrvC1+Nx38ng5VMiw1u4SP68TXmb5k3zmOYdTheJ uzd1EOHxZfMXcd1EwbG/0Yp/1aXzQMCv/q5cvsB6snoWOdvoG7wIPxO8ZFVtKUvIDn5B 2zMD22pwk8cetaUarx3mu/yyh/3LEyEwxTyzwHcUdmE6AdfUkKsgIQ2jbKaowLwHAEfv ULDaHPo9/Hqm2ICL+wfgrw776FlkNixZfTdciNu1d/2OKbd6LuM0/Vuh38XsPsAL4gpM 7ERRJAOUtjxmX+tkhBHQt+LUPM1or9efDV28ogto3olNNNTp4Ns5fjX7vIbrlTJRO6hx FSyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KnTU5CAKa2qgMNASytkbtJZqSTjvEtUQYaIow0w1ICM=; b=rcWTlmnUIpea4scPh1ALYysHLnQSGIpmeJWftLWjnFMmwMDs7gy6DAttHj/Ci79YqM mV1ysDpsCG5W3QGGi4uAJVPqL1LEDdDU0eRbPUTGxQgdCUgjB4tXZJj/oU/p5nXqUggH 5mjwS7/VefHCH21nV9uYqUuouWsrDqkNhoAO4wN9Xx8HWCmLYQYUzeJTbLCbKjPUnaMj 2Zp6jLoCMQ5aDlOHTkzajqGE4AOBn0cVv9pgQE2A7yBhMeAKnaUH5xYNdYMvw4O3ldJs KbJQHsF9Rsp4RhlSf9iiYgh7QCZgjTHnQs76JuexhaR3xey+TzY12ZLPeWaOaeQKYRuZ +hsQ== X-Gm-Message-State: AOAM532P494Q9XOqWTE16K3JumHkWn0sGlxFCWTaKNoXTrgY/F1jDh1w vjVayfCbJQ5UCLjVCmUr/tYEUykWY1E= X-Google-Smtp-Source: ABdhPJwK75goxqZ7bLJfTY23K42iHeiqqsBOtrzyMf1FpXisrleH6VoBgrPmNdPLRvmCJcmiR3vmwA== X-Received: by 2002:a63:7404:: with SMTP id p4mr7213586pgc.222.1634271082769; Thu, 14 Oct 2021 21:11:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 34/67] target/ppc: Implement ppc_cpu_record_sigsegv Date: Thu, 14 Oct 2021 21:10:20 -0700 Message-Id: <20211015041053.2769193-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272800385100001 Record DAR, DSISR, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. This is exactly what the user-mode ppc_cpu_tlb_fill does, so simply rename it as ppc_cpu_record_sigsegv. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- target/ppc/cpu.h | 3 --- target/ppc/internal.h | 9 +++++++++ target/ppc/cpu_init.c | 6 ++++-- target/ppc/user_only_helper.c | 15 +++++++++++---- 4 files changed, 24 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index baa4e7c34d..2242d57718 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1279,9 +1279,6 @@ extern const VMStateDescription vmstate_ppc_cpu; =20 /*************************************************************************= ****/ void ppc_translate_init(void); -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); =20 #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1(CPUPPCState *env, target_ulong value); diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 55284369f5..339974b7d8 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0) #define PTE_PTEM_MASK 0x7FFFFFBF #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) =20 +#ifdef CONFIG_USER_ONLY +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif =20 #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6aad01d1d3..ec8da08f0b 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -9014,9 +9014,11 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { =20 static const struct TCGCPUOps ppc_tcg_ops =3D { .initialize =3D ppc_translate_init, - .tlb_fill =3D ppc_cpu_tlb_fill, =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D ppc_cpu_record_sigsegv, +#else + .tlb_fill =3D ppc_cpu_tlb_fill, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .do_interrupt =3D ppc_cpu_do_interrupt, .cpu_exec_enter =3D ppc_cpu_exec_enter, diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index aa3f867596..7ff76f7a06 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -21,16 +21,23 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "internal.h" =20 - -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; int exception, error_code; =20 + /* + * Both DSISR and the "trap number" (exception vector offset, + * looked up from exception_index) are present in the linux-user + * signal frame. + * FIXME: we don't actually populate the trap number properly. + * It would be easiest to fill in an env->trap value now. + */ if (access_type =3D=3D MMU_INST_FETCH) { exception =3D POWERPC_EXCP_ISI; error_code =3D 0x40000000; --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272146555944.7804245763132; Thu, 14 Oct 2021 21:29:06 -0700 (PDT) Received: from localhost ([::1]:52668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEq9-0003iW-69 for importer@patchew.org; Fri, 15 Oct 2021 00:29:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39122) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ8-0007Sh-F7 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:51030) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ4-0000QD-68 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: by mail-pj1-x102b.google.com with SMTP id gn3so806949pjb.0 for ; Thu, 14 Oct 2021 21:11:24 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8XNUdw8ZsBPFhbrTI2TXzCgV9ZFmSEvuHYyy7MRm+qg=; b=eibrXC3pq7bwWEGw+/JDgf1MeNPENERuEkP9wb61HWujRIG89jHx4Xh0EOHquef3nW 20YPz2r+UMGFMrJQUYjZzQgaICuD20TQNGVT9lGDrIt4hdavEB1uzmT2pQe3qJ80VtXA 8xEDWopZSjxd3VQ4hXec01yubEZ4R24aGVFgyh4k9TIjHix0XqSnpusGw/jabSD3i5BP E0zwVrDQUbrfZ9dh92zPa2CL6OK2lSLSY7L1MoUKKS1WKMXdSAAYXLo6IzhoGmK2NtLi 6mjSokBWBiuGgW7rzyM3MC6dpGDvgKyoLtRjVTrbO4lXhNjOeRSK+BDh/oqRjXkGJ1tE InqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8XNUdw8ZsBPFhbrTI2TXzCgV9ZFmSEvuHYyy7MRm+qg=; b=aThp6ofk/bGB5tBevj7k0fcxvL6GWz61k5QAn5Jt8O0mFlt1Hhd/ZVyQZsUJXpsk/P CpPfbEQlG4p9uO5KcSJYO3Ntf5JYA044LCzUq978aQ3DL8YEpcpof5WyLFeX2xu9sGHp mMxfiRYEnYvR7rWELeIxpLqMJpUjdr4aAia3eMjE0kuiuMenSOBQaqW0U7FyIdWH+pRp 80Tx4Yg92pdBBbk8IA7KemjSGkakgnmAaH8WsYKSyrcfShMElcznNHeGjcAZzpljBQAO jHq1/VYXNOjibbWQSJQ30aEMRP3LgTSGXvSncnq/wXz8MkzomD+H7S+MBoG9E1y+97/L n12Q== X-Gm-Message-State: AOAM532JRWJNCNo1iybFpE3vztDirB7WKQ9Xf0fd4IkDz/B8QI57x1by C2SLFIIkL8UgitGSaTQLE+hzhWiigMfkCw== X-Google-Smtp-Source: ABdhPJzAA1oe9AAy55RdQqUkboVi2GRC3XrUDpbxakJmg1JAGmyUPYsCza+rkj37j2Frx1seIqWPiw== X-Received: by 2002:a17:90b:4a81:: with SMTP id lp1mr10840882pjb.124.1634271083385; Thu, 14 Oct 2021 21:11:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 35/67] target/riscv: Make riscv_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:21 -0700 Message-Id: <20211015041053.2769193-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272147866100001 The fallback code in cpu_loop_exit_sigsegv is sufficient for riscv linux-user. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- linux-user/riscv/cpu_loop.c | 7 ------- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 21 +-------------------- 3 files changed, 2 insertions(+), 28 deletions(-) diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 9859a366e4..aef019b1c8 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -87,13 +87,6 @@ void cpu_loop(CPURISCVState *env) sigcode =3D TARGET_TRAP_BRKPT; sigaddr =3D env->pc; break; - case RISCV_EXCP_INST_PAGE_FAULT: - case RISCV_EXCP_LOAD_PAGE_FAULT: - case RISCV_EXCP_STORE_PAGE_FAULT: - signum =3D TARGET_SIGSEGV; - sigcode =3D TARGET_SEGV_MAPERR; - sigaddr =3D env->badaddr; - break; case RISCV_EXCP_SEMIHOST: env->gpr[xA0] =3D do_common_semihosting(cs); env->pc +=3D 4; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d69d1887e..2ab89a3f70 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -653,9 +653,9 @@ static const struct SysemuCPUOps riscv_sysemu_ops =3D { static const struct TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, - .tlb_fill =3D riscv_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D riscv_cpu_tlb_fill, .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d41d5cd27c..b520d6fc78 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -748,7 +748,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(env, cs->exception_index, retaddr); } -#endif /* !CONFIG_USER_ONLY */ =20 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -756,7 +755,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; -#ifndef CONFIG_USER_ONLY vaddr im_address; hwaddr pa =3D 0; int prot, prot2, prot_pmp; @@ -888,25 +886,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } =20 return true; - -#else - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index =3D RISCV_EXCP_INST_PAGE_FAULT; - break; - case MMU_DATA_LOAD: - cs->exception_index =3D RISCV_EXCP_LOAD_PAGE_FAULT; - break; - case MMU_DATA_STORE: - cs->exception_index =3D RISCV_EXCP_STORE_PAGE_FAULT; - break; - default: - g_assert_not_reached(); - } - env->badaddr =3D address; - cpu_loop_exit_restore(cs, retaddr); -#endif } +#endif /* !CONFIG_USER_ONLY */ =20 /* * Handle Traps --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272940666685.0941337491586; Thu, 14 Oct 2021 21:42:20 -0700 (PDT) Received: from localhost ([::1]:38490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF2x-0007NL-IZ for importer@patchew.org; Fri, 15 Oct 2021 00:42:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39130) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ9-0007UM-6t for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:32 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:44659) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ4-0000Rc-5j for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: by mail-pl1-x62f.google.com with SMTP id t11so5587767plq.11 for ; Thu, 14 Oct 2021 21:11:25 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=66Bl8EQR5t0ae9YRNU1Dduo8SF5bSu1MJ1ucFe28OE8=; b=Yrp9Qtc+SjFsD0nJ4e7B6+81uBpyb+KaeXdnBzQteaCoRZfo9lcEwfZNfoGyaf/I8k t7UiqTt31bDPaI4JGT0qRMxvzWX/usiXdM3K4O/qHrJVA078cAoVFuSp4CFbpSQr4Dfi baXBVcZ4NLhLgZpIuyCQg9M8kALjO4JgPaSYO6uVO9e8hCRHcs41PXwyosBGqhKe9pYc LZRZdj7l+R4paJYDCKxkzAUATcCPhICrE1wb+WzjJEXzd6kQ+agLhIi1KGTSL8xplGyo nfcGVEyvNTr5Gs+3FMxjeMihDZYVM2s7hy/lQirMbNJ0wzbpiMSTVbbRkWje300ZRZ0m 6ljQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=66Bl8EQR5t0ae9YRNU1Dduo8SF5bSu1MJ1ucFe28OE8=; b=WkdQhNrJh6rQp8EXnHYhVBK86RV8nZwj8KOOOpWAkwnW8hw3Tth0r/zrceQ1b7kSAD wsUmsLZ/Ty4q3r9SYKM0Ioxb2FsQ4iPISSarjFxXOpeLfADVDEMy9i8jd2rGBzXPXBQU maRdH6Kz4NxOjwIxjVeHGaWmHjflMaC7heY7hK6v3HLHFOEIUIzDaJFMcq1Ze39HK+fV 2jUP1g93LxvbC8zl84bVSVO57XZqHMoK03UoFbLPWj5b4kGZQEuPmiPzbMG2HNRB29e1 svGAgGZbPbLGkPzhgMCHYUIh/ddD/8gqnj6x2D0fGfAnS7ER7WTRq6+0YUrOkxftmOt6 /CYw== X-Gm-Message-State: AOAM531BJ0cyT+ESbPCBLmB9omDX1UsQX2erJSHjpebpDhWHp2rciqBO dP9I45YuTIxkt9gech0GpaCfge5liyP3BA== X-Google-Smtp-Source: ABdhPJysUxGWaoCJ4lmGNwUgodLuZoMMwPPpRsu+81KcBlfCLtITD5DjsO9qfqSOStuQh4VYE46jRw== X-Received: by 2002:a17:90b:4a48:: with SMTP id lb8mr11106849pjb.236.1634271084168; Thu, 14 Oct 2021 21:11:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 36/67] target/s390x: Use probe_access_flags in s390_probe_access Date: Thu, 14 Oct 2021 21:10:22 -0700 Message-Id: <20211015041053.2769193-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272941415100001 Content-Type: text/plain; charset="utf-8" Not sure why the user-only code wasn't rewritten to use probe_access_flags at the same time that the sysemu code was converted. For the purpose of user-only, this is an exact replacement. Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 17e3f83641..362a30d99e 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -141,20 +141,12 @@ static int s390_probe_access(CPUArchState *env, targe= t_ulong addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t ra) { +#if defined(CONFIG_USER_ONLY) + return probe_access_flags(env, addr, access_type, mmu_idx, + nonfault, phost, ra); +#else int flags; =20 -#if defined(CONFIG_USER_ONLY) - flags =3D page_get_flags(addr); - if (!(flags & (access_type =3D=3D MMU_DATA_LOAD ? PAGE_READ : PAGE_WR= ITE_ORG))) { - env->__excp_addr =3D addr; - flags =3D (flags & PAGE_VALID) ? PGM_PROTECTION : PGM_ADDRESSING; - if (nonfault) { - return flags; - } - tcg_s390_program_interrupt(env, flags, ra); - } - *phost =3D g2h(env_cpu(env), addr); -#else /* * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr= =3D=3DNULL * to detect if there was an exception during tlb_fill(). @@ -173,8 +165,8 @@ static int s390_probe_access(CPUArchState *env, target_= ulong addr, int size, (access_type =3D=3D MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ), ra); } -#endif return 0; +#endif } =20 static int access_prepare_nf(S390Access *access, CPUS390XState *env, --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272312052474.2741098987349; Thu, 14 Oct 2021 21:31:52 -0700 (PDT) Received: from localhost ([::1]:33042 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEsp-00012m-14 for importer@patchew.org; Fri, 15 Oct 2021 00:31:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39134) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ9-0007Uh-9l for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:32 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:56141) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ4-0000S8-7C for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: by mail-pj1-x102e.google.com with SMTP id om14so6317168pjb.5 for ; Thu, 14 Oct 2021 21:11:25 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ij1YRgU0peRo+QSVg6ezzkIr6IGfKaWXUXRkApukMz0=; b=zjgBXPzOpbCputW+Yq8ae/JelNCmUvLWwkFCLopPHSAyz3iODARYwDN9DJabP4nYkv 2gSxGAWu3RPtqmoG1PmLQ8/eBVau5MA3dsHcKHn/fl3UGIbxD+FcwUdl1DmF2wF+iNKs D8DBU1h5lfMX3GDQRdegbPZaBqSuOQ07+tbjYGhknUtz7g+R16isYts2VZVjwz6bTBcs EXPDbt5zLbn3N/BrOFuMsNJBDXYDi2e+pEWvChOq5cxBeHAtsD+WoZmXgLoYrOpA6MbA k1vu/n9NR/6z+BWACOsTIkzs/jiQ/ziQzyzazKxDMfOlcwZNNV2GQNVUqDrQ1emkYjgR YDxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ij1YRgU0peRo+QSVg6ezzkIr6IGfKaWXUXRkApukMz0=; b=I9wxcm8V0JuZEDCx9N60A3pUIzlKP8UNjGSfCu/pkirgsGthI9XBp2IE1ar47/cJch 9vUsyKHYe6YGpgopfXFigUes/TNWJifA4hV6Xb22MjhQ6sak5RQTZTCGaE8vmaaSj5K5 hADHuJ2aGLwnoAyI6EuUDC7ouANB3XNXiJx4oFkbdr4DlhxSwsAk8clmva81+9OmELLY 91BMUG0TkVn8JSsgvn+/DLegJv2NbcqPcOp2feMkJBMM1/IxNZ2RMMWIluSxOrrdA2cm d29BFplT2ussAtTO5sisinJhuGZb6TFFEb3OsPPilLluwzdCvFkdPUCNcffM5yGbn90X zvgg== X-Gm-Message-State: AOAM531vt8tmLcHjJjvf4CDpoa++niVKqLZg6w/SKUm5L66ZbfW9pr5q ZtxSvadI/2RlIOaF7Y3SRtnWQTiQV3+6pg== X-Google-Smtp-Source: ABdhPJxD9YOooMjSwE/24H2kRARUPRGVJOdOSunu9+rh02kVIdOJPU8Zisx+qG0RiZ3XJaH1xqaA5A== X-Received: by 2002:a17:90a:4b47:: with SMTP id o7mr25830092pjl.198.1634271084999; Thu, 14 Oct 2021 21:11:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 37/67] target/s390x: Implement s390_cpu_record_sigsegv Date: Thu, 14 Oct 2021 21:10:23 -0700 Message-Id: <20211015041053.2769193-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272313853100003 Move the masking of the address from cpu_loop into s390_cpu_record_sigsegv -- this is governed by hw, not linux. This does mean we have to raise our own exception, rather than return to the fallback. Use maperr to choose between PGM_PROTECTION and PGM_ADDRESSING. Use the appropriate si_code for each in cpu_loop. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/s390x-internal.h | 13 ++++++++++--- linux-user/s390x/cpu_loop.c | 13 ++++++------- target/s390x/cpu.c | 6 ++++-- target/s390x/tcg/excp_helper.c | 18 +++++++++++------- 4 files changed, 31 insertions(+), 19 deletions(-) diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 27d4a03ca1..163aa4f94a 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -270,13 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; =20 +#ifdef CONFIG_USER_ONLY +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr); +#else +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif + =20 /* fpu_helper.c */ uint32_t set_cc_nz_f32(float32 v); diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index 69b69981f6..d089c8417e 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -24,8 +24,6 @@ #include "cpu_loop-common.h" #include "signal-common.h" =20 -/* s390x masks the fault address it reports in si_addr for SIGSEGV and SIG= BUS */ -#define S390X_FAIL_ADDR_MASK -4096LL =20 static int get_pgm_data_si_code(int dxc_code) { @@ -111,12 +109,13 @@ void cpu_loop(CPUS390XState *env) n =3D TARGET_ILL_ILLOPC; goto do_signal_pc; case PGM_PROTECTION: + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_ACCERR, + env->__excp_addr); + break; case PGM_ADDRESSING: - sig =3D TARGET_SIGSEGV; - /* XXX: check env->error_code */ - n =3D TARGET_SEGV_MAPERR; - addr =3D env->__excp_addr & S390X_FAIL_ADDR_MASK; - goto do_signal; + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, + env->__excp_addr); + break; case PGM_EXECUTE: case PGM_SPECIFICATION: case PGM_SPECIAL_OP: diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7b7b05f1d3..593dda75c4 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -266,9 +266,11 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 static const struct TCGCPUOps s390_tcg_ops =3D { .initialize =3D s390x_translate_init, - .tlb_fill =3D s390_cpu_tlb_fill, =20 -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D s390_cpu_record_sigsegv, +#else + .tlb_fill =3D s390_cpu_tlb_fill, .cpu_exec_interrupt =3D s390_cpu_exec_interrupt, .do_interrupt =3D s390_cpu_do_interrupt, .debug_excp_handler =3D s390x_cpu_debug_excp_handler, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 3d6662a53c..b923d080fc 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -89,16 +89,20 @@ void s390_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D -1; } =20 -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { S390CPU *cpu =3D S390_CPU(cs); =20 - trigger_pgm_exception(&cpu->env, PGM_ADDRESSING); - /* On real machines this value is dropped into LowMem. Since this - is userland, simply put this someplace that cpu_loop can find it. = */ - cpu->env.__excp_addr =3D address; + trigger_pgm_exception(&cpu->env, maperr ? PGM_ADDRESSING : PGM_PROTECT= ION); + /* + * On real machines this value is dropped into LowMem. Since this + * is userland, simply put this someplace that cpu_loop can find it. + * S390 only gives the page of the fault, not the exact address. + * C.f. the construction of TEC in mmu_translate(). + */ + cpu->env.__excp_addr =3D address & TARGET_PAGE_MASK; cpu_loop_exit_restore(cs, retaddr); } =20 --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163427246058047.1324955408835; Thu, 14 Oct 2021 21:34:20 -0700 (PDT) Received: from localhost ([::1]:41458 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEvD-0006o7-9U for importer@patchew.org; Fri, 15 Oct 2021 00:34:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39144) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZA-0007V3-Qr for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:34 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:46709) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ5-0000Sk-0x for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:31 -0400 Received: by mail-pl1-x636.google.com with SMTP id 21so5576384plo.13 for ; Thu, 14 Oct 2021 21:11:26 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8ZM/9TjmIZZ72copbPvsL/6T35TidGs+EyZyHS5h5dE=; b=i184fE/Q5n892VsRHF0GLiaznZF6PLo9NrUWOp7yXwyqTGPXJzLKvJBaBXmj00nP7c 7BwCBmglrvz855LFjDO6RGLIZzyP3JCdI/G3hlu7/KvuHb6CAs1TtmmrNxv0NHk5Ga1y 2S4wFQ7m6o5/NkluEXdU8gfWD0x7MAXX5KKLOl4LOldf2IROyHDGHDNWWWRGLChg+OPi 5+RgDw+tEAO7anwwm5z+sYqVjn5T4my9cuDNzt+fUzXC6iFHLGKH5jfyvhMU0ioU9HqL nJhuU/AqkZukW2zmuiNrTZ8fD18ACJdW8oDJqPA0mcQVJtMRnReReerS/ptuMNekshDl hJsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8ZM/9TjmIZZ72copbPvsL/6T35TidGs+EyZyHS5h5dE=; b=KXQ+d7LqIUYXnmXBToSdtSraBFsQieS3Ey9poEWf+LNsfgbIXI5gptrQymF4LPzz6u kUAsteMGAE6PhdrA6RDpOO55g3qA1JHC/9hvDJy0p9dqc8GJCfVZUlY2IFtY1Wwri5t3 D3grGhG8GqlGXykhguKtzDzgaTMZz2ig2GCWO1YhpKta0VJoju8inBk2hnEZ8JHX7glJ jXKXaeUL1ySh1WGf9flpbquC/sbDstJhkfnltdHyIQ5a2JB6EXr+cRsb5RKuvOb/4VxE X4ZL+F9boYTTJ1RaY8aILispViB+V2+dzoumSljddOyJ/+al38BZzXRsJneudVgY+B44 wpTQ== X-Gm-Message-State: AOAM532ir48GquBUUbq79B+0D6OBm0sAjLDqds6/n+y45FdqtuoXCyAF fBiv6koafYuz4lMTEr+acx20TnLI0S9MGw== X-Google-Smtp-Source: ABdhPJyGgkdxVM/Vl77emmLQx6t1kH83JXnZ7tC9WWyTnhu88jVidlXMAaUMweN63wiy+KyrqaYrqg== X-Received: by 2002:a17:90b:4f88:: with SMTP id qe8mr10791972pjb.223.1634271085623; Thu, 14 Oct 2021 21:11:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 38/67] target/sh4: Make sh4_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:24 -0700 Message-Id: <20211015041053.2769193-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272461792100001 Content-Type: text/plain; charset="utf-8" The fallback code in cpu_loop_exit_sigsegv is sufficient for sh4 linux-user. Remove the code from cpu_loop that raised SIGSEGV. Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 6 +++--- linux-user/sh4/cpu_loop.c | 8 -------- target/sh4/cpu.c | 2 +- target/sh4/helper.c | 9 +-------- 4 files changed, 5 insertions(+), 20 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index dc81406646..4cfb109f56 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -213,12 +213,12 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, va= ddr addr, uintptr_t retaddr) QEMU_NORETURN; =20 void sh4_translate_init(void); +void sh4_cpu_list(void); + +#if !defined(CONFIG_USER_ONLY) bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); - -void sh4_cpu_list(void); -#if !defined(CONFIG_USER_ONLY) void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void cpu_sh4_invalidate_tlb(CPUSH4State *s); diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index 65b8972e3c..ac9b01840c 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -65,14 +65,6 @@ void cpu_loop(CPUSH4State *env) info.si_code =3D TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case 0xa0: - case 0xc0: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->tea; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); arch_interrupt =3D false; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 2047742d03..06b2691dc4 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -236,9 +236,9 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { static const struct TCGCPUOps superh_tcg_ops =3D { .initialize =3D sh4_translate_init, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, - .tlb_fill =3D superh_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D superh_cpu_tlb_fill, .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, .do_interrupt =3D superh_cpu_do_interrupt, .do_unaligned_access =3D superh_cpu_do_unaligned_access, diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 53cb9c3b63..6a620e36fc 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -796,8 +796,6 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) return false; } =20 -#endif /* !CONFIG_USER_ONLY */ - bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -806,11 +804,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, CPUSH4State *env =3D &cpu->env; int ret; =20 -#ifdef CONFIG_USER_ONLY - ret =3D (access_type =3D=3D MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE : - access_type =3D=3D MMU_INST_FETCH ? MMU_ITLB_VIOLATION : - MMU_DTLB_VIOLATION_READ); -#else target_ulong physical; int prot; =20 @@ -829,7 +822,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, if (ret !=3D MMU_DTLB_MULTIPLE && ret !=3D MMU_ITLB_MULTIPLE) { env->pteh =3D (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_M= ASK); } -#endif =20 env->tea =3D address; switch (ret) { @@ -868,3 +860,4 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272268726549.6248655488948; Thu, 14 Oct 2021 21:31:08 -0700 (PDT) Received: from localhost ([::1]:58154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEs7-0007NI-NN for importer@patchew.org; Fri, 15 Oct 2021 00:31:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39148) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZB-0007V6-Lf for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:34 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:55088) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ8-0000Sz-1k for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:33 -0400 Received: by mail-pj1-x1036.google.com with SMTP id np13so6324867pjb.4 for ; Thu, 14 Oct 2021 21:11:27 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OFBASZgYo/dnEXgBhwjQsgVMikt4qFVfoC5aZFh8E0o=; b=H1tX4L/B1JPBqT8wf8L9696kVk9MMnG2KbM9vqiQBci/F3M+06X6kRSzkY4BRLfxVG /EZY360+UCQzWVWbOopkEGXVs5QErETUM5LMvqP0dY6LmQ/l5NWBtaeS2zDkR9QMUtn/ MrZVXFYPoy8yBCefAhVrlxeDLx34ThLsBLzG0ZvL2aJXg5jauI/wfQxlvZctQuP4k1IK uSbELWIUZGRQac5nhwzu0PvRZIitFqKf+jaLzNVkCZLE80MJVmc7UZWwXHLqQHDj6fa5 Ai3ahgN2xJI3L0GIQUzEifKysAawjEapgZFtCH9uRJd7zMZOI+vwT75/JNfcFnxufCXL 7dVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OFBASZgYo/dnEXgBhwjQsgVMikt4qFVfoC5aZFh8E0o=; b=hAAuoIrgfGi3xXj1lUDjrszuhnr6+/inY6GadUhQ/nMa5PrqBeO3k7DXnA/JDZjklR 44IQAmIdGSuEAv8AXR7SteRpbpcP9ptIoAgsyz4fsR4DGq9UfJZtQx/2oY0YCccDz/fr trAJf8tOczwX5yojQ9XxrbQ94TtpTKvp7Y2TgkE9+V5L2cQxkTrUm5xxMYRWNYankyO/ 1+rEUi2KUiJ7bICfHUZmR6ixmp7NgXDEJrui2+d4rTI9Ok/TUXOg9dwkCEPLHMGbZG5c X6hPW3D6Uu2EhZkVAhXDMF34aoS6rB+m99OrWVh6GuVKVrVb+UoTG3Ijzl4/5JeM3BIl GLIg== X-Gm-Message-State: AOAM5324XVJGgMqmW3T12d596m5veSgUWsU5dqPGCn/iHmzJr44DdMJp 0U3cfQPvVfno+ul2+fXo3MWWz2m2QGJFWw== X-Google-Smtp-Source: ABdhPJxzYxu2Q0JH9ggGDtQOa/PVwrBqT3S/2A/Ag2P7eMzOxY6AS/Df3lTVleKD6rx6RKAlthKHEg== X-Received: by 2002:a17:90a:4502:: with SMTP id u2mr25090671pjg.186.1634271086500; Thu, 14 Oct 2021 21:11:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 39/67] target/sparc: Make sparc_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:25 -0700 Message-Id: <20211015041053.2769193-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272269160100005 The fallback code in cpu_loop_exit_sigsegv is sufficient for sparc linux-user. This makes all of the code in mmu_helper.c sysemu only, so remove the ifdefs and move the file to sparc_softmmu_ss. Remove the code from cpu_loop that handled TT_DFAULT and TT_TFAULT. Cc: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 25 ------------------------- target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 25 ------------------------- target/sparc/meson.build | 2 +- 4 files changed, 2 insertions(+), 52 deletions(-) diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index ad29b4eb6a..0ba65e431c 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -219,17 +219,6 @@ void cpu_loop (CPUSPARCState *env) case TT_WIN_UNF: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->mmuregs[4]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #else case TT_SPILL: /* window overflow */ save_window(env); @@ -237,20 +226,6 @@ void cpu_loop (CPUSPARCState *env) case TT_FILL: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - if (trapnr =3D=3D TT_DFAULT) - info._sifields._sigfault._addr =3D env->dmmu.mmuregs[4= ]; - else - info._sifields._sigfault._addr =3D cpu_tsptr(env)->tpc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #ifndef TARGET_ABI32 case 0x16e: flush_windows(env); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 21dd27796d..55268ed2a1 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -865,9 +865,9 @@ static const struct SysemuCPUOps sparc_sysemu_ops =3D { static const struct TCGCPUOps sparc_tcg_ops =3D { .initialize =3D sparc_tcg_init, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, - .tlb_fill =3D sparc_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D sparc_cpu_tlb_fill, .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, .do_interrupt =3D sparc_cpu_do_interrupt, .do_transaction_failed =3D sparc_cpu_do_transaction_failed, diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a44473a1c7..2ad47391d0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -25,30 +25,6 @@ =20 /* Sparc MMU emulation */ =20 -#if defined(CONFIG_USER_ONLY) - -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; - - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D TT_TFAULT; - } else { - cs->exception_index =3D TT_DFAULT; -#ifdef TARGET_SPARC64 - env->dmmu.mmuregs[4] =3D address; -#else - env->mmuregs[4] =3D address; -#endif - } - cpu_loop_exit_restore(cs, retaddr); -} - -#else - #ifndef TARGET_SPARC64 /* * Sparc V8 Reference MMU (SRMMU) @@ -926,4 +902,3 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) } return phys_addr; } -#endif diff --git a/target/sparc/meson.build b/target/sparc/meson.build index a3638b9503..a801802ee2 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -6,7 +6,6 @@ sparc_ss.add(files( 'gdbstub.c', 'helper.c', 'ldst_helper.c', - 'mmu_helper.c', 'translate.c', 'win_helper.c', )) @@ -16,6 +15,7 @@ sparc_ss.add(when: 'TARGET_SPARC64', if_true: files('int6= 4_helper.c', 'vis_helpe sparc_softmmu_ss =3D ss.source_set() sparc_softmmu_ss.add(files( 'machine.c', + 'mmu_helper.c', 'monitor.c', )) =20 --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272427927126.56131387876849; Thu, 14 Oct 2021 21:33:47 -0700 (PDT) Received: from localhost ([::1]:38350 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEug-0004hi-P9 for importer@patchew.org; Fri, 15 Oct 2021 00:33:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc3-0006PB-0J for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:31 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:33779) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc1-0002kB-Ci for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:30 -0400 Received: by mail-pl1-x62e.google.com with SMTP id y4so5640967plb.0 for ; Thu, 14 Oct 2021 21:14:28 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kAcqfrBKLTctf7S2SRnWlKvQ84+gE9eIlExzwRxWIv4=; b=Z7n/HqexPf03mPIK5CBZaZhWMlm5GOptriO4bhptblllp3qr4tbFRThMMYhtVqHxrf oD+b1dolGgDJp4SKiJcFgh5OrAd9Kj77xpsY8E6yNUlI/wg4n3gDZn7qqH6iN73yxvUk qJNgVZ0a+RkH1hKEF2OyPrSxd2hxzZeqUgEeuZZ72PvRfCumlqU8wDlR6VWctpuVJUef W8j3qaGnwp+310jhG/diF/y3a5aLDZqbQkWv0WvWMco9N+JjQmdgU/ZYTUyGm3PuBblP N7+F6znwenHxaHzqTGV5h1ZVmJQKmaXIkJSsqXEQ/wZGFuXFondzbDbwVLhBcNOyfx9J nCqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kAcqfrBKLTctf7S2SRnWlKvQ84+gE9eIlExzwRxWIv4=; b=sSEykkskwIWmrB+1ikDEGZJni+tP+E88pyeUpjMLvp2h0pVoVJnyxQqDLDJJks+b7w CChnn0GB/q6huter19HCGFcuEnLVfDW9DmdMPkxTkYPk1YjVF5lBjS9OLSijuONyKVSS E8gEkkTI7cG7rPJdaqsy084xWlSyyuIx6ogCXY1Ds5/F5QMJazdNRrGlohF1Bc2oJwiD uoF5DjT0bnjXh9lG4W4g5z+dWWe4vuszAM7s+Rysudv7KOFfX8pCZt6khBkbOQl/mzqy LtJY4fnRAzCk6Y36kCj9sZhyLKXgwT1Aik+B2Zmj3rerjg2KsIiTYKwcPzvTruNpsnp7 31dw== X-Gm-Message-State: AOAM532YssS2uxlsojCFXkcLKBuxP6UzbKg1zFEqmyArYSkqc33HYcyL KHN8Y4vcUo174wnyVIqlg6+34mdBWSyRMg== X-Google-Smtp-Source: ABdhPJw+dlQDzpQTiVE2oVGv1GXkXJGD2lNeRtn43pHSEOqgaNn/hhspX7i6c2cs+VMlabYtJwn/Rw== X-Received: by 2002:a17:90a:428e:: with SMTP id p14mr25294389pjg.92.1634271267726; Thu, 14 Oct 2021 21:14:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 40/67] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:26 -0700 Message-Id: <20211015041053.2769193-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272430130100003 The fallback code in cpu_loop_exit_sigsegv is sufficient for xtensa linux-user. Remove the code from cpu_loop that raised SIGSEGV. Acked-by: Max Filippov Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 +- linux-user/xtensa/cpu_loop.c | 9 --------- target/xtensa/cpu.c | 2 +- target/xtensa/helper.c | 22 +--------------------- 4 files changed, 3 insertions(+), 32 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index f9a510ca46..02143f2f77 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -563,10 +563,10 @@ struct XtensaCPU { }; =20 =20 +#ifndef CONFIG_USER_ONLY bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index 622afbcd34..a83490ab35 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -226,15 +226,6 @@ void cpu_loop(CPUXtensaState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; =20 - case LOAD_PROHIBITED_CAUSE: - case STORE_PROHIBITED_CAUSE: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr =3D env->sregs[EXCVADDR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - default: fprintf(stderr, "exccause =3D %d\n", env->sregs[EXCCAUSE]); g_assert_not_reached(); diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c1cbd03595..224f723236 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -192,10 +192,10 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = =3D { =20 static const struct TCGCPUOps xtensa_tcg_ops =3D { .initialize =3D xtensa_translate_init, - .tlb_fill =3D xtensa_cpu_tlb_fill, .debug_excp_handler =3D xtensa_breakpoint_handler, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D xtensa_cpu_tlb_fill, .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, .do_interrupt =3D xtensa_cpu_do_interrupt, .do_transaction_failed =3D xtensa_cpu_do_transaction_failed, diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f18ab383fd..29d216ec1b 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -242,27 +242,7 @@ void xtensa_cpu_list(void) } } =20 -#ifdef CONFIG_USER_ONLY - -bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; - - qemu_log_mask(CPU_LOG_INT, - "%s: rw =3D %d, address =3D 0x%08" VADDR_PRIx ", size = =3D %d\n", - __func__, access_type, address, size); - env->sregs[EXCVADDR] =3D address; - env->sregs[EXCCAUSE] =3D (access_type =3D=3D MMU_DATA_STORE ? - STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE= ); - cs->exception_index =3D EXC_USER; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272530567445.5125737991665; Thu, 14 Oct 2021 21:35:30 -0700 (PDT) Received: from localhost ([::1]:46642 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEwL-0001qo-HG for importer@patchew.org; Fri, 15 Oct 2021 00:35:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39414) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc3-0006Rc-P6 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:31 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:44015) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc2-0002l4-1E for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:31 -0400 Received: by mail-pl1-x633.google.com with SMTP id y1so5590513plk.10 for ; Thu, 14 Oct 2021 21:14:29 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AlAKO3pHLk0w42dzpdqlCWgmBC5kkngUdLfuQLXO9ho=; b=gxL/J4fg2UqVuhFY6kvo4FD2c3UJHB2s+ejjFT81o8CcYpDVxep5lRnhe2MIRfXK/q mwQsVwq+gKm+K5gjGZv6kylWShC9TRbDrCtLqKKWZA0CG7EZTfC+Muz3rOnw+aCPrszS 6M1J0hILeIkwBTbxfWWodD52rUvKYUqf3ein5e/ndFnG5wSx+bLzrAuGsNeWq3mVBUyX LC2yidsOofv9vUgiOjKGHFTjpXU80v5ceo1RcDHZGOnEF/kpBtzTrMs3frO9fNlgSWco /tsJRWtCZfm49G8kqaTqiPT5RaBlHDxiCDmoQtaJXnvg25AFKKfqF1EUtOKFQH70wkJR SKPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AlAKO3pHLk0w42dzpdqlCWgmBC5kkngUdLfuQLXO9ho=; b=AJW9pqncHV37JwufH1I//GndVW2W+qq3F1fbU1yWpLdAQalVXw4FDLOl6rMz4yTpvN nxYohLKoiQWwUlnJCeWV6SajGBsIKaDbGYaaSvKXl+H0idwJhqDMGG7ZdriDMplArlqA FgJGyWuglSFbNtkBJi6+RtEs04u9T1yfacHvMM8nn+8X9JZtO9dekbfmOYAK5kEhQyNL eiCMoktPRkOXfSc9cmvKvDwtphbDdnY6+wvLUMGeWvDrfxIEltDM7lXhtXNXYlfSGey4 8Ef+Mhvysudy+eeg0hO/CZJ/z0tkyx4+GgD/n0ZjesUqm0VkBhvt5CZITz9eFiBHx/h/ M1JA== X-Gm-Message-State: AOAM533Ttdbhy72u46hxtic5+DDycIM0fRYJp9oPwGDjE8d5Pexn1PEu juQniGIC7ZCj7EjCX4wqUayLwJDLdY38nQ== X-Google-Smtp-Source: ABdhPJzFOxaobo995zRGx3+zs/20QSmwRBbhC7jHTNQvoo83tUWnoKKx0ef8N7pc2jpFyXQ0p/28vg== X-Received: by 2002:a17:90a:8593:: with SMTP id m19mr10608225pjn.82.1634271268518; Thu, 14 Oct 2021 21:14:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 41/67] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Date: Thu, 14 Oct 2021 21:10:27 -0700 Message-Id: <20211015041053.2769193-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272532464100001 We have replaced tlb_fill with record_sigsegv for user mode. Move the declaration to restrict it to system emulation. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 22 ++++++++++------------ linux-user/signal.c | 3 --- 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 41718b695b..8eadd404c8 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -35,18 +35,6 @@ struct TCGCPUOps { void (*cpu_exec_enter)(CPUState *cpu); /** @cpu_exec_exit: Callback for cpu_exec cleanup */ void (*cpu_exec_exit)(CPUState *cpu); - /** - * @tlb_fill: Handle a softmmu tlb miss or user-only address fault - * - * For system mode, if the access is valid, call tlb_set_page - * and return true; if the access is invalid, and probe is - * true, return false; otherwise raise an exception and do - * not return. For user-only mode, always raise an exception - * and do not return. - */ - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); =20 @@ -68,6 +56,16 @@ struct TCGCPUOps { #ifdef CONFIG_SOFTMMU /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** + * @tlb_fill: Handle a softmmu tlb miss + * + * If the access is valid, call tlb_set_page and return true; + * if the access is invalid and probe is true, return false; + * otherwise raise an exception and do not return. + */ + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); /** * @do_transaction_failed: Callback for handling failed memory transac= tions * (ie bus faults or external aborts; not MMU faults) diff --git a/linux-user/signal.c b/linux-user/signal.c index 135983747d..9d60abc038 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -697,9 +697,6 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong = addr, =20 if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); - } else if (tcg_ops->tlb_fill) { - tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, = ra); - g_assert_not_reached(); } =20 force_sig_fault(TARGET_SIGSEGV, --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272699594600.7199472437819; Thu, 14 Oct 2021 21:38:19 -0700 (PDT) Received: from localhost ([::1]:52620 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEz4-00063B-H4 for importer@patchew.org; Fri, 15 Oct 2021 00:38:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc4-0006U8-Ce for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:32 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:39604) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc2-0002lr-MW for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:32 -0400 Received: by mail-pj1-x1029.google.com with SMTP id ls18-20020a17090b351200b001a00250584aso8447411pjb.4 for ; Thu, 14 Oct 2021 21:14:30 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9lqN/uiH3UUIeVg5yhYMxWg7ld7QYTaBAGHdI8OeAIs=; b=P5B71VSi1+VMlTDxlHkiYLGQsICQM6ftakBQ+W5AWd7paiMDzsaXXwtuMMt75eOFro SVl2Id2rdy+lQfOiAbK4okwACo7ulJaDwy5CwbzTbkwWqWzMSc4iFrSIXENbenU/xf/F H/rNSprsA+KSmeR3BDfazcX1soyZVQ/v6hn0MEZ2QFM7MftW18Caf9BHHkhd9GVa+lql V4U7j8tZsaSuyFKSNPtmQngNquNZJPwIdoIh8WbBFG0V+Zx9FP1KrYI6Awx0a0ErvkcZ cdDO4VruWnI/BzA/+scwuXQZCc4dmfMnDgMbAL216hDGm+VGTqLhc3k+iZfOYwTEfRgz KNFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9lqN/uiH3UUIeVg5yhYMxWg7ld7QYTaBAGHdI8OeAIs=; b=NPcxTi5nCDaSFxT1HYSHMZ77TMWX/FACNKY5L/nYIdR1TX6U7S/yREhNoTIws5xnKt epuRFqX6OXRgw7+Gksb5wFBMxLkIH6uGK2UXfC4lZwY/FAxgVRr1QOLkmbo0X3WnmuCF 9yl9tAdJuzMKnbcu2kpOGUQBXPiCbKjAulLClzNVQb6jynEcLE0H3Wvoo1U/eLffHkqE rOLHTLGus2JnoFv0E2aTU6KoYgAFQ5Sfj8K/EMF52fW+0K8nKGrcSf+V9ocDZgCgXqcm BAsXGXTJLgHfMndKjeKZRecBi+Vx7wND34EDtZBaUVq9G375AVWrEl5SzSJgZxBvVy8I XlrA== X-Gm-Message-State: AOAM530M95F07GJuoykNE43wei6qDU4YZt5F8fDxZXGxyos/Q5AUnWGf wTdflZbw9mvPlY6QsJienPNfQaQGsNI= X-Google-Smtp-Source: ABdhPJymYvhWniIWzjO+QJSnE1JfZ0eQutcTKxS2xTahydRJZdmWC9HAXMSRH48i6XaJQY1AEDVXPQ== X-Received: by 2002:a17:90a:1507:: with SMTP id l7mr10749099pja.141.1634271269353; Thu, 14 Oct 2021 21:14:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 42/67] Revert "cpu: Move cpu_common_props to hw/core/cpu.c" Date: Thu, 14 Oct 2021 21:10:28 -0700 Message-Id: <20211015041053.2769193-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272701833100001 Content-Type: text/plain; charset="utf-8" This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f. Despite a comment saying why cpu_common_props cannot be placed in a file that is compiled once, it was moved anyway. Revert that. Since then, Property is not defined in hw/core/cpu.h, so it is now easier to declare a function to install the properties rather than the Property array itself. Cc: Eduardo Habkost Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 1 + cpu.c | 21 +++++++++++++++++++++ hw/core/cpu-common.c | 17 +---------------- 3 files changed, 23 insertions(+), 16 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b7d5bc1200..1a10497af3 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1008,6 +1008,7 @@ void QEMU_NORETURN cpu_abort(CPUState *cpu, const cha= r *fmt, ...) GCC_FMT_ATTR(2, 3); =20 /* $(top_srcdir)/cpu.c */ +void cpu_class_init_props(DeviceClass *dc); void cpu_exec_initfn(CPUState *cpu); void cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); diff --git a/cpu.c b/cpu.c index e1799a15bc..9bce67ef55 100644 --- a/cpu.c +++ b/cpu.c @@ -179,6 +179,27 @@ void cpu_exec_unrealizefn(CPUState *cpu) cpu_list_remove(cpu); } =20 +static Property cpu_common_props[] =3D { +#ifndef CONFIG_USER_ONLY + /* + * Create a memory property for softmmu CPU object, + * so users can wire up its memory. (This can't go in hw/core/cpu.c + * because that file is compiled only once for both user-mode + * and system builds.) The default if no link is set up is to use + * the system address space. + */ + DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, + MemoryRegion *), +#endif + DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, fal= se), + DEFINE_PROP_END_OF_LIST(), +}; + +void cpu_class_init_props(DeviceClass *dc) +{ + device_class_set_props(dc, cpu_common_props); +} + void cpu_exec_initfn(CPUState *cpu) { cpu->as =3D NULL; diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index e2f5a64604..9e3241b430 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -257,21 +257,6 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu) return cpu->cpu_index; } =20 -static Property cpu_common_props[] =3D { -#ifndef CONFIG_USER_ONLY - /* Create a memory property for softmmu CPU object, - * so users can wire up its memory. (This can't go in hw/core/cpu.c - * because that file is compiled only once for both user-mode - * and system builds.) The default if no link is set up is to use - * the system address space. - */ - DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, - MemoryRegion *), -#endif - DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, fal= se), - DEFINE_PROP_END_OF_LIST(), -}; - static void cpu_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -286,7 +271,7 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) dc->realize =3D cpu_common_realizefn; dc->unrealize =3D cpu_common_unrealizefn; dc->reset =3D cpu_common_reset; - device_class_set_props(dc, cpu_common_props); + cpu_class_init_props(dc); /* * Reason: CPUs still need special care by board code: wiring up * IRQs, adding reset handlers, halting non-first CPUs, ... --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273274720402.4695832831545; Thu, 14 Oct 2021 21:47:54 -0700 (PDT) Received: from localhost ([::1]:54862 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF8L-00022n-NN for importer@patchew.org; Fri, 15 Oct 2021 00:47:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc5-0006YW-Iv for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:33 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:54254) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc3-0002me-Oe for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:33 -0400 Received: by mail-pj1-x102c.google.com with SMTP id ls18so6335456pjb.3 for ; Thu, 14 Oct 2021 21:14:31 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wpoZicnTiBlydK+sFdKdK9FSFNaqNFWg+Zx3DgtSaaA=; b=X5WBD+7bcnTQNUibf/XWQDujaRiE8XXZglpfDAgA/kP2gXTnWVRfywtW6143hmEk8d Zld794Ip4VggTwMRRDnXmgzJA2l7Oy4R3qmhNIrN4Lc0Y9/X9sR5srDHuMSZKMO7GP9q YY0MOK4xt4q4TaZ1s379aeHzYDk6Z9R5XnECzyknD/r15KSctF2wvREpWFpZLGiam7Uc MP2BCWbpGPLgWNrKbQ/IMv9XtMU62er3ockLXT7xIHS0HywDxQ15NMJ751MQMNhR9dsR 9ZUp5EyNiczLVKBfcipn0yq3pfa/djHvdebJnvAQnAdd4GYDV6sdzhDZzTwBrmz6LgJw 551A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wpoZicnTiBlydK+sFdKdK9FSFNaqNFWg+Zx3DgtSaaA=; b=hBeqLpII2pcioL+RCB0LZPK6ec+SgUU4tFCyIgelOA9LSNz2R1xc0t3MFssaBIbXVF SptIk2xkek6I/RwFhgqX+Os7NadWSwJE4PIXEcstZ4gq7t/8s8ouexVvCvxbT9CcNcOT Wxm8yDyIW5gqOiYJX9Bk11UuMbKg2JwssEjW+3M3EMB7ODNBcwxJpePY/yvxO+MXXcxi Ox02t8sUN++a7iFMygDOevnm88BhMGFNxE5AG54rEcgFbovhZlJZ6juY4I837j2XkiOA VsxtGUmeHhD4+oQcDyr2Qi9olelaYPd66DB0cqGnX8Iu3weRDum1AiZUMa31imeHw26r Hi0w== X-Gm-Message-State: AOAM531H9F76pszPBipeHd/svRdrm/ojk0N9FutNy9nqCBd6r7yFhDgq n2bpqnQ+u8UxkBC6QnEu+OBLWF5w5JbkVg== X-Google-Smtp-Source: ABdhPJwIcZN2Dzt846KqpzYg1mu+XXRMZV38reNMWJMLam1ZUFU6Ck8/Av29r1xauTlWYvvyzz7+aA== X-Received: by 2002:a17:90b:4011:: with SMTP id ie17mr25111929pjb.41.1634271270276; Thu, 14 Oct 2021 21:14:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 43/67] hw/core: Add TCGCPUOps.record_sigbus Date: Thu, 14 Oct 2021 21:10:29 -0700 Message-Id: <20211015041053.2769193-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273275204100001 Content-Type: text/plain; charset="utf-8" Add a new user-only interface for updating cpu state before raising a signal. This will take the place of do_unaligned_access for user-only and should result in less boilerplate for each guest. Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- include/hw/core/tcg-cpu-ops.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 8eadd404c8..e13898553a 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -135,6 +135,29 @@ struct TCGCPUOps { void (*record_sigsegv)(CPUState *cpu, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); + /** + * record_sigbus: + * @cpu: cpu context + * @addr: misaligned guest address + * @access_type: access was read/write/execute + * @ra: host pc for unwinding + * + * We are about to raise SIGBUS with si_code BUS_ADRALN, + * and si_addr set for @addr. Record anything further needed + * for the signal ucontext_t. + * + * If the emulated kernel does not provide the signal handler with + * anything besides the user context registers, and the siginfo_t, + * then this hook need do nothing and may be omitted. + * Otherwise, record the data and return; the caller will raise + * the signal, unwind the cpu state, and return to the main loop. + * + * If it is simpler to re-use the sysemu do_unaligned_access code, + * @ra is provided so that a "normal" cpu exception can be raised. + * In this case, the signal must be raised by the architecture cpu_loo= p. + */ + void (*record_sigbus)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, uintptr_t ra); #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ =20 --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272849608689.574189344725; Thu, 14 Oct 2021 21:40:49 -0700 (PDT) Received: from localhost ([::1]:60896 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF1U-0003Jo-HU for importer@patchew.org; Fri, 15 Oct 2021 00:40:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39448) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc5-0006Yt-N7 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:33 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:44017) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc4-0002mo-5K for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:33 -0400 Received: by mail-pl1-x635.google.com with SMTP id y1so5590553plk.10 for ; Thu, 14 Oct 2021 21:14:31 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=67r73sMxmFAFlBR0ViNOs8odKIpwZUQrX4e2focSvME=; b=PDYhmQPC1wqr9JTz7mYBYfET4px6+8klt9olHF+41DAhgt7tLeUyyWOPba8RW7b4RB EIX89Lkfo+jZVUwe92XAnA6Mjesxyna20E1NBcWbTP9TSe4y7nuo6Zk7jGLE9mDPzwYO yj3SklMZb5O7RmFl1F0RhIoB+C0iXMwjviHr/zb68/7MkJco473o6iNCIaGkAGNl4I5a BoXhJvQ2frhpm9HuOdDEmle8fOqEyDqLP0LH3URDlxELuvd6L7nS7hUpvIxX4qZ+NxjS MLgRcCYAKHhVo+ggGmEEmMrkmI0b1vjtZOkQPU+MOLCsZbvqygDx1QzY/NiQ9A/cVf3t /M6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=67r73sMxmFAFlBR0ViNOs8odKIpwZUQrX4e2focSvME=; b=Z/p1ewz3L24+b3gHBaSVMt/WW5mNiTSPeRNLnYdCK9j0LaO7Z6DVGfMQfMfc1Z+XZM DSvehxNxxtC+oBuHIvdBKsjT54+CB58vw1QKAJc/fdbFyYXVBpPMD5vbwc7+VROX8V7M zG3s5otOVTS27+Ymf+U8vn/8eBYGOjczVjrRJOdEOBV0hzMOEP7uWVA4DXVR52nUBLPa XdKV4kHTFS98F7DuEvSPoepjv0vWJ+3NXcw3k9zDeWpdhIAj9aqB85o7y69x/dWRvvEP ibk9bYsRPmHvZ1dFGEFaPh++h0c5FAXwxagsQieVsBvRIy2EddLwnz4kQuH0/+0fAovj jhWg== X-Gm-Message-State: AOAM530e4oXeNb4HREwQFqPxyJU6R+Q/dFK9JY+rjBO23m2Sk4/AjIr5 2kEqbGLMLjgnkldN2lM7yT4feajoZVVTfA== X-Google-Smtp-Source: ABdhPJzAM28XGjKxjkrghZfO9fcaPZ0uo2Es0pMWNrKCArcREgjLDe7nnQbboVtLalwFaxCWSLOiPw== X-Received: by 2002:a17:90a:e7c8:: with SMTP id kb8mr10707601pjb.95.1634271270863; Thu, 14 Oct 2021 21:14:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 44/67] linux-user: Add cpu_loop_exit_sigbus Date: Thu, 14 Oct 2021 21:10:30 -0700 Message-Id: <20211015041053.2769193-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272851271100001 Content-Type: text/plain; charset="utf-8" This is a new interface to be provided by the os emulator for raising SIGBUS on fault. Use the new record_sigbus target hook. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh --- include/exec/exec-all.h | 14 ++++++++++++++ linux-user/signal.c | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f74578500c..6bb2a0f7ec 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -700,6 +700,20 @@ void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu= , target_ulong addr, MMUAccessType access_type, bool maperr, uintptr_t ra); =20 +/** + * cpu_loop_exit_sigbus: + * @cpu: the cpu context + * @addr: the guest address of the alignment fault + * @access_type: access was read/write/execute + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGBUS, and jump to the main cpu loop. + */ +void QEMU_NORETURN cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + uintptr_t ra); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/linux-user/signal.c b/linux-user/signal.c index 9d60abc038..df2c8678d0 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -706,6 +706,20 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong= addr, cpu_loop_exit_restore(cpu, ra); } =20 +void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, uintptr_t ra) +{ + const struct TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + + if (tcg_ops->record_sigbus) { + tcg_ops->record_sigbus(cpu, addr, access_type, ra); + } + + force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, addr); + cpu->exception_index =3D EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, ra); +} + /* abort execution with signal */ static void QEMU_NORETURN dump_core_and_abort(int target_sig) { --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163427274071761.731520607699736; Thu, 14 Oct 2021 21:39:00 -0700 (PDT) Received: from localhost ([::1]:55020 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEzj-0007mI-6z for importer@patchew.org; Fri, 15 Oct 2021 00:38:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39472) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc6-0006d5-VS for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:34 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:44677) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc4-0002nb-TV for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:34 -0400 Received: by mail-pl1-x634.google.com with SMTP id t11so5591572plq.11 for ; Thu, 14 Oct 2021 21:14:32 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rjBYeTS3X9ZvDGx0FPpXOAHGwl8wPIvp5ueP48Sb5aY=; b=aii45HRDIzXwwLEg2C5lkj+nmA/V8MBOpjqmMSeRWc3RsuZAcfF8QHVBlrdR9EFXQf cEz6iG8bqfTDrpyQIdZktvg/3RqJQKN4Gix+qOb1G022r5PysBiEkr56Grmb8H62pQdF q3LQ5EZAWuyqYQm8HQAYrTHHTBQyxWkftDqqJJmUf43DvMRrZJURhO3t8AIe6eii++D+ WL4VozPXh4f3HK6vChuEYfIH6TQiOTPEtk8sJtj+gcy8sD4/UwVXHSy2lNrsq5RX3Iiy 4nQsAxRPsEgsywE4a2QtPxaENxCvKv1iqLB8BJXRm5n/trb3uBNc+HisnYrg+da/R729 fHuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rjBYeTS3X9ZvDGx0FPpXOAHGwl8wPIvp5ueP48Sb5aY=; b=Nl1JDQVPcNdIgX+jQkgB73l8Fggnt673kdsh+YQzlLH93/X+3QYEdsNd/z0ouemS+t e1ImX3nw/pBtDIeIlcdTq/VmczyE1yajFHZaT1tpL52hyFsSF2GLooE28hfaT4nCezcJ v3YhGweEkCLI3cDSwLv3jevqFrjvxcRxEl1fI0o8jgr1zgX7Dt3BdQiuzU55FMs14aZy nb3p7LgVQ25esRzR9ZvaO1rS37zvRMLUGXLUJTuoNJrB6iOIJWIiOzryXDxH/tcgujAj 0uwOStKvr+Ee5KBQnJWfJ3n4wTa0jpyUd0iIlYBpNq8ZFOS/iSKomb2YNXdbcFHYLqrI Fcqg== X-Gm-Message-State: AOAM5301QjaeL3GINHGpFrHiDT6J21CYqG0tqBq6bKHcoM1gZ8kjFAJ2 QzQe6cExzV0XfmOiCEVLNg+LY4M9tiA= X-Google-Smtp-Source: ABdhPJw8OwSx+jHgzgBLb6D0TUeusvbmWpRtcPj88/WW+unUk74BNXShsP/RWnrgbHUHuGIkpGHtKQ== X-Received: by 2002:a17:90a:7e82:: with SMTP id j2mr10774963pjl.165.1634271271566; Thu, 14 Oct 2021 21:14:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 45/67] target/alpha: Implement alpha_cpu_record_sigbus Date: Thu, 14 Oct 2021 21:10:31 -0700 Message-Id: <20211015041053.2769193-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272741585100001 Content-Type: text/plain; charset="utf-8" Record trap_arg{0,1,2} for the linux-user signal frame. Raise SIGBUS directly from cpu_loop_exit_sigbus, which means we can remove the code for EXCP_UNALIGN in cpu_loop. Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 8 +++++--- linux-user/alpha/cpu_loop.c | 7 ------- target/alpha/cpu.c | 1 + target/alpha/mem_helper.c | 30 ++++++++++++++++++++++-------- 4 files changed, 28 insertions(+), 18 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index d49cc36d07..afd975c878 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -282,9 +282,6 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; =20 #define cpu_list alpha_cpu_list =20 @@ -451,10 +448,15 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned = reg, uint64_t val); void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr); +void alpha_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr); #else bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 4cc8e0a55c..4029849d5c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -54,13 +54,6 @@ void cpu_loop(CPUAlphaState *env) fprintf(stderr, "External interrupt. Exit\n"); exit(EXIT_FAILURE); break; - case EXCP_UNALIGN: - info.si_signo =3D TARGET_SIGBUS; - info.si_errno =3D 0; - info.si_code =3D TARGET_BUS_ADRALN; - info._sifields._sigfault._addr =3D env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_OPCDEC: do_sigill: info.si_signo =3D TARGET_SIGILL; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 69f32c3078..a8990d401b 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -221,6 +221,7 @@ static const struct TCGCPUOps alpha_tcg_ops =3D { =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D alpha_cpu_record_sigsegv, + .record_sigbus =3D alpha_cpu_record_sigbus, #else .tlb_fill =3D alpha_cpu_tlb_fill, .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 75e72bc337..47283a0612 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -23,18 +23,12 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" =20 -/* Softmmu support */ -#ifndef CONFIG_USER_ONLY -void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t = retaddr) { - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; uint64_t pc; uint32_t insn; =20 - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(env_cpu(env), retaddr, true); =20 pc =3D env->pc; insn =3D cpu_ldl_code(env, pc); @@ -42,6 +36,26 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, env->trap_arg0 =3D addr; env->trap_arg1 =3D insn >> 26; /* opcode */ env->trap_arg2 =3D (insn >> 21) & 31; /* dest regno */ +} + +#ifdef CONFIG_USER_ONLY +void alpha_cpu_record_sigbus(CPUState *cs, vaddr addr, + MMUAccessType access_type, uintptr_t retaddr) +{ + AlphaCPU *cpu =3D ALPHA_CPU(cs); + CPUAlphaState *env =3D &cpu->env; + + do_unaligned_access(env, addr, retaddr); +} +#else +void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + AlphaCPU *cpu =3D ALPHA_CPU(cs); + CPUAlphaState *env =3D &cpu->env; + + do_unaligned_access(env, addr, retaddr); cs->exception_index =3D EXCP_UNALIGN; env->error_code =3D 0; cpu_loop_exit(cs); --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272892291311.7527818747544; Thu, 14 Oct 2021 21:41:32 -0700 (PDT) Received: from localhost ([::1]:35098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF2B-000537-71 for importer@patchew.org; Fri, 15 Oct 2021 00:41:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39550) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc9-0006ko-VB for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:37 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:54255) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc6-0002oI-Gz for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:37 -0400 Received: by mail-pj1-x102d.google.com with SMTP id ls18so6335513pjb.3 for ; Thu, 14 Oct 2021 21:14:33 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AiCyvdTR/3QA/VxcdfSHeMxoA2jAV+mFfUYWeOlFIz4=; b=AzkuZD2wasbwRAkK/Rm9AAlJbUBaieGLOuuv/TzRUq5RWybUIHzXtVVW2HtDVgac1n x8RXUqif3C9stTlp36sxcOM3StMDtjlI/A12QccAkhHSxVII999Xf4f+2JzEz/O/FG3w Df1j2G3PJqAeZl5r0DGuJWIwxYsFMAFRa3lAZqgABsf7hDYN2Gh1HowoXBybc8IoLj+d ooxbfW44K2/20DTZT4E5URUfqNKdlv7E8mn/AIaHJL1VIIy1aj+RlGCZMv5pP32aoyvF oVslzpCwX0A4OL71uRdYfke9NorMycj1eRtAGtkWAdPSOcEDi0AbUziN6kIWvQvyT3pE eiSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AiCyvdTR/3QA/VxcdfSHeMxoA2jAV+mFfUYWeOlFIz4=; b=E53rSLfe7/WNoGg+nobS4240GvlOGV1CenPmre3FtiRTmzb1jsnfDbsYcwB1dyksQa S2Ku+SaSk9yYCmRmN1Vgk5YuJ38AN9z6CHykTI8XfmQ92Ryd81n/SguYMOZ8mxpzN/f9 e3+e2JeQg/4baxJIQQ9KV71NkRQxKV7rW/INccHtkn7euWiHMX+pc1mXwm53fkAvM8Q+ lR4OeXHy4f2MMSi5vownpBx/ZIVsSoba47OAQn3xxrjzzMI4opw4Hwyf2eDxO36vzY9s Qe9ubIvpatxqbcmomn4RYegWDdc8zJYqX508fgcNgY1aYoF/yymSxcxVBRhy491hukVm qpcw== X-Gm-Message-State: AOAM530QumXklisqlofGUM3VTaU4xEs4luChvxX1TFWUri2SdtwU6Uu4 OtnGorQ37fUS4+29buzJbPkJeUVSt+pgwQ== X-Google-Smtp-Source: ABdhPJwl5+4GsG7xGYQ+0SJPm3TBHiJ+CRgmnJr/5079EmZ9XzGLBCFBq7RsPgHNa+QuhsKE7fuXIA== X-Received: by 2002:a17:90a:3b49:: with SMTP id t9mr24795706pjf.218.1634271272144; Thu, 14 Oct 2021 21:14:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 46/67] target/arm: Implement arm_cpu_record_sigbus Date: Thu, 14 Oct 2021 21:10:32 -0700 Message-Id: <20211015041053.2769193-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272893287100001 Content-Type: text/plain; charset="utf-8" Because of the complexity of setting ESR, re-use the existing arm_cpu_do_unaligned_access function. This means we have to handle the exception ourselves in cpu_loop, transforming it to the appropriate signal. Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- target/arm/internals.h | 2 ++ linux-user/aarch64/cpu_loop.c | 12 +++++++++--- linux-user/arm/cpu_loop.c | 30 ++++++++++++++++++++++++++---- target/arm/cpu.c | 1 + target/arm/cpu_tcg.c | 1 + target/arm/tlb_helper.c | 6 ++++++ 6 files changed, 45 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5a7aaf0f51..89f7610ebc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -548,6 +548,8 @@ static inline bool arm_extabort_type(MemTxResult result) void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); +void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, + MMUAccessType access_type, uintptr_t ra); #else bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 034b737435..97e0728b67 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -79,7 +79,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); - int trapnr, ec, fsc, si_code; + int trapnr, ec, fsc, si_code, si_signo; abi_long ret; =20 for (;;) { @@ -121,20 +121,26 @@ void cpu_loop(CPUARMState *env) fsc =3D extract32(env->exception.syndrome, 0, 6); switch (fsc) { case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo =3D TARGET_SIGSEGV; si_code =3D TARGET_SEGV_MAPERR; break; case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo =3D TARGET_SIGSEGV; si_code =3D TARGET_SEGV_ACCERR; break; case 0x11: /* Synchronous Tag Check Fault */ + si_signo =3D TARGET_SIGSEGV; si_code =3D TARGET_SEGV_MTESERR; break; + case 0x21: /* Alignment fault */ + si_signo =3D TARGET_SIGBUS; + si_code =3D TARGET_BUS_ADRALN; + break; default: g_assert_not_reached(); } - - force_sig_fault(TARGET_SIGSEGV, si_code, env->exception.vaddre= ss); + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index ae09adcb95..01cb6eb534 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -25,6 +25,7 @@ #include "cpu_loop-common.h" #include "signal-common.h" #include "semihosting/common-semi.h" +#include "target/arm/syndrome.h" =20 #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ @@ -280,7 +281,7 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint32_= t opcode) void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); - int trapnr; + int trapnr, si_signo, si_code; unsigned int n, insn; abi_ulong ret; =20 @@ -423,9 +424,30 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* XXX: check env->error_code */ - force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, - env->exception.vaddress); + /* For user-only we don't set TTBCR_EAE, so look at the FSR. */ + switch (env->exception.fsr & 0x1f) { + case 0x1: /* Alignment */ + si_signo =3D TARGET_SIGBUS; + si_code =3D TARGET_BUS_ADRALN; + break; + case 0x3: /* Access flag fault, level 1 */ + case 0x6: /* Access flag fault, level 2 */ + case 0x9: /* Domain fault, level 1 */ + case 0xb: /* Domain fault, level 2 */ + case 0xd: /* Permision fault, level 1 */ + case 0xf: /* Permision fault, level 2 */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_ACCERR; + break; + case 0x5: /* Translation fault, level 1 */ + case 0x7: /* Translation fault, level 2 */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_MAPERR; + break; + default: + g_assert_not_reached(); + } + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a18a58ca0..a211804fd3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2035,6 +2035,7 @@ static const struct TCGCPUOps arm_tcg_ops =3D { =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D arm_cpu_record_sigsegv, + .record_sigbus =3D arm_cpu_record_sigbus, #else .tlb_fill =3D arm_cpu_tlb_fill, .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 7b3bea2fbb..13d0e9b195 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -902,6 +902,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops =3D { =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D arm_cpu_record_sigsegv, + .record_sigbus =3D arm_cpu_record_sigbus, #else .tlb_fill =3D arm_cpu_tlb_fill, .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index dc5860180f..12a934e924 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -213,4 +213,10 @@ void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, cpu_restore_state(cs, ra, true); arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); } + +void arm_cpu_record_sigbus(CPUState *cs, vaddr addr, + MMUAccessType access_type, uintptr_t ra) +{ + arm_cpu_do_unaligned_access(cs, addr, access_type, MMU_USER_IDX, ra); +} #endif /* !defined(CONFIG_USER_ONLY) */ --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273394255952.2681904602055; Thu, 14 Oct 2021 21:49:54 -0700 (PDT) Received: from localhost ([::1]:34716 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFAH-0007Yg-4I for importer@patchew.org; Fri, 15 Oct 2021 00:49:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39492) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc7-0006fs-Nw for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:35 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:34751) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc6-0002ow-58 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:35 -0400 Received: by mail-pj1-x1032.google.com with SMTP id q2-20020a17090a2e0200b001a0fd4efd49so2155569pjd.1 for ; Thu, 14 Oct 2021 21:14:33 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fbekWwHWkYvCfsIkbs+I86iCi1VerGNgnv3kr2JgTV8=; b=gtye64QlPCiBbLjHqNVos/qlT7dkyTO2SNa3K4gwysvsfAekGxicpmUOyT72zufiel SK4eS+hHbKMi+j8KA4COItmQZ5rec1NpVQeAZtK16vIh8Ov9ep4TLGhevwyCwweIcKsT lGjuIU/0VO19NmNRm0K3QbYV+sdijmuaNuuh4ZzWgy8UJRbtvWVUeCQDWWnEZbKiF5Qv nTJdykhv60j58SEcvHwI7mFVZJhF2GQkLSbpbig44NnntLkV9njJ4ne+LmGPkuXAS20p x+Dt1yvyRKAlITtCn1z2Gd50alyT7OUsD4Zfl1CrD7b4W077AZr5BLkER2L+eKsqaiDa kRUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fbekWwHWkYvCfsIkbs+I86iCi1VerGNgnv3kr2JgTV8=; b=t0DrO0TPmLQSg36OIKE7mr2K0X56Pb2rwkQ3hi4ENmoaiIjJJ4SICYmsv75HkkVUC4 ZVN5Ahq+VQ0WuneIcBTwKEy9AAaKcb9a7oi9NXjkNFE0oJ7H6r5pVBN9ioACFVJqwiBO wKg8mng6PIl+C5UIC+py/BVkh0NvAWaDgD/pSs78E7ChfsPId5fiwEloHl/rRAuU3WMj pvRV2xZIXm58I0bFGdm2NpjRAh8MCVpXX2gQBiiCUmRwaSeyUlCqZJpjoZvURQEVwH75 kbCgILxZNAJXEDa3G5adxTtSLUHIMVFpoMPSSuLh//kpgeU/3EsmUnagI+/uUP3SYmF8 pXZA== X-Gm-Message-State: AOAM531HjLQ5/of1OZkOfanB+H37tScjIfD6NGN/BQWSadCWNNYvDm28 +gTqE3tpzmq9lMJ+iBXo2IidXML5IUkwJA== X-Google-Smtp-Source: ABdhPJyrC4taB19rFvD5tGgEqfMlDd2S01m16UzMcYEo1LvnbwZULad9wWQLDzXPDtGCvO4U6DFy4g== X-Received: by 2002:a17:90a:5108:: with SMTP id t8mr25228071pjh.201.1634271272784; Thu, 14 Oct 2021 21:14:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 47/67] linux-user/hppa: Remove EXCP_UNALIGN handling Date: Thu, 14 Oct 2021 21:10:33 -0700 Message-Id: <20211015041053.2769193-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273395066100001 Content-Type: text/plain; charset="utf-8" We will raise SIGBUS directly from cpu_loop_exit_sigbus. Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index e0a62deeb9..375576c8f0 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -144,13 +144,6 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f =3D env->gr[31]; env->iaoq_b =3D env->gr[31] + 4; break; - case EXCP_UNALIGN: - info.si_signo =3D TARGET_SIGBUS; - info.si_errno =3D 0; - info.si_code =3D 0; - info._sifields._sigfault._addr =3D env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ILL: case EXCP_PRIV_OPR: case EXCP_PRIV_REG: --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273567916917.3574573491771; Thu, 14 Oct 2021 21:52:47 -0700 (PDT) Received: from localhost ([::1]:41696 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFD3-0003vM-CX for importer@patchew.org; Fri, 15 Oct 2021 00:52:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc8-0006iK-H7 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:36 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:36632) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc6-0002pj-Sx for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:36 -0400 Received: by mail-pl1-x636.google.com with SMTP id f21so5614484plb.3 for ; Thu, 14 Oct 2021 21:14:34 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6inZETYo7qpmjRK6t8YVcWmKQsxE4jryCUSCrlDOgJc=; b=TFtza0gXQUWkgNtMoeuWv7RWk7RnSLsiD/44n+VWMCt1DFxZ3YVS/OslUNihITMFp0 X3y+B74y8URJoQCIsdA30NpAxxXbi1jluRvZH4O0lIazJGzvVnxHtLBY3hdvUehJRuTF lScGm6BDIV4YdTXrdZ+KK9MAR1mUHb1rT7tZ0hjmrA6uN4A/L1oPkMQtcm144CVDZQtM 1SnTb9VQe8KB98V0gVpcAKJo1Egb6ecUXu60sVwcmu07Q8edu9KhuN33lT/2yjBpbx/N B6KhtJmaVW4RA/bHHN07FVmTLihqoZY9bDMp5FNUl8y000lo6g86KADmcJxErOFwgEND ff5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6inZETYo7qpmjRK6t8YVcWmKQsxE4jryCUSCrlDOgJc=; b=kp3fsknnMBMlMWK62OAkjbh6P0/uqtbXnpBJKR/9mz7+Kcwx7uwMZrmmnq2EyMp1mo dEckkx9jlDlnLkQlBM/ECU4ZE14jEqdIpeR2gWFEK8eiL4250YEikFFhRlHpB/HnPa70 mDp7ItMdv6nWiDoRE9gQB2i5K0opIJuD+PUIpFL+fs7WfGPh4m/N+J1ZFzP1z8PZaG9L oxOWwQI+joOlE+o5gCH3zmjDexlespwtCLWsap9PhJXgMdhTrm/ZhCAOCgUe/g8a9/qL ovjasJ/S6mgmU/POSYjCMbZMd7QW/pq7tuCW+wt9VfMmjcLrL9qLSQlo1SsRPKkaVozv +alg== X-Gm-Message-State: AOAM531zojT+b/XRF/gKa8LHO2oWK7MC2R1ocqgVAl8WYne4blQPIgi5 fjuT3J3rWJShynXqv7mU7q5qfioCeIDAQQ== X-Google-Smtp-Source: ABdhPJxl6iHXmrw7qws7vj3CCinsx4rNIt4Lzlf6eRFgQchQwtSyInFaSNGv7PulzKmbUDUQTWzoxw== X-Received: by 2002:a17:90b:4c86:: with SMTP id my6mr10961200pjb.203.1634271273613; Thu, 14 Oct 2021 21:14:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 48/67] target/microblaze: Do not set MO_ALIGN for user-only Date: Thu, 14 Oct 2021 21:10:34 -0700 Message-Id: <20211015041053.2769193-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273569569100001 Content-Type: text/plain; charset="utf-8" The kernel will fix up unaligned accesses, so emulate that by allowing unaligned accesses to succeed. Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a14ffed784..ef44bca2fd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -727,6 +727,7 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int = ra, int rb) } #endif =20 +#ifndef CONFIG_USER_ONLY static void record_unaligned_ess(DisasContext *dc, int rd, MemOp size, bool store) { @@ -739,6 +740,7 @@ static void record_unaligned_ess(DisasContext *dc, int = rd, =20 tcg_set_insn_start_param(dc->insn_start, 1, iflags); } +#endif =20 static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) @@ -760,12 +762,19 @@ static bool do_load(DisasContext *dc, int rd, TCGv ad= dr, MemOp mop, } } =20 + /* + * For system mode, enforce alignment if the cpu configuration + * requires it. For user-mode, the Linux kernel will have fixed up + * any unaligned access, so emulate that by *not* setting MO_ALIGN. + */ +#ifndef CONFIG_USER_ONLY if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, false); mop |=3D MO_ALIGN; } +#endif =20 tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop); =20 @@ -906,12 +915,19 @@ static bool do_store(DisasContext *dc, int rd, TCGv a= ddr, MemOp mop, } } =20 + /* + * For system mode, enforce alignment if the cpu configuration + * requires it. For user-mode, the Linux kernel will have fixed up + * any unaligned access, so emulate that by *not* setting MO_ALIGN. + */ +#ifndef CONFIG_USER_ONLY if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, true); mop |=3D MO_ALIGN; } +#endif =20 tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); =20 --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272743524402.734024977221; Thu, 14 Oct 2021 21:39:03 -0700 (PDT) Received: from localhost ([::1]:55152 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEzm-0007rG-H4 for importer@patchew.org; Fri, 15 Oct 2021 00:39:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39532) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc9-0006j0-0U for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:37 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:39689) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc7-0002pt-Dl for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:36 -0400 Received: by mail-pl1-x62f.google.com with SMTP id c4so5603165pls.6 for ; Thu, 14 Oct 2021 21:14:35 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=54O7y5F6cil48JbVjJeuP4tBSWG4MHFPBxntrZflWpI=; b=j2F0q+XNNa4YJAjmRIlOE/2uI6va5is0BkOliZCkPSdM7yJyMQUqHTbOAtG48UZmKP WOFj2VBzpwAVJe5hwAnT4DoEAL5/c88wBCspBHTdpkXBGWryHUcwNKrFNHYyJYJ5vzE5 +QpsoqzihaJgoAt8eR5JWf3O3gNbkjQPeunVM43bjcegqJ/xO95tMCxNBLk3qlrgcy8y OGawaDSThIqkTadqRim9C45riL3gzXFxbwMlQJgengKjWvp1hqIviEHxzzt2DsI3LFRM 4Ze6QHSc6WoYdJkA+YGjp/li2WJcfbqdv04PtKwCbJM3LlbiiN0WSUtWqaZpRiO+ZtGX fKcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=54O7y5F6cil48JbVjJeuP4tBSWG4MHFPBxntrZflWpI=; b=chrrrNmB4YuhsrnPokHtTdvtCc86gnihwLmCz2yFg8C01MkvSivMB88vfRT2kkY4xH RQBMS8VqEXVr/2EN5X/Tt2+yTtPjaIvrpAOWAdpjvsZwAe25zsdDqKdbjaj5ykp4/SRF PX0n3Ds63sQIwpfgy56BVValh59yErVYlEgQFBZ5d87sh5EsIrN/UCYRedB+6bl0Ee0r 9CZCWZb+r16B3XrmEvYuLzX599P0avhE0sdDkJhYt51Gght4+MsXtB2Q/zhYsOTDUlj6 66BjJ7eSZ8bAOTAmGAiWQfGiqopwyU9YLgXUfcBphy+YL2RYx19WFxM9PeYgVXBsZJEY imJQ== X-Gm-Message-State: AOAM530wfwpPSz7/I6njoW8w/YBRFkz2j6RAyPcafxxSRv0XlvQWUp0J 01PogRa28a1Ll8y9/x5yauROpRiU9B3fIw== X-Google-Smtp-Source: ABdhPJwwVXBlIe3Qb1+uLTnVo+s4TZUlVwe3fFjyTGwhYoW35utpqRZlLSpcPs8olfaO8G10pvhamw== X-Received: by 2002:a17:90b:2248:: with SMTP id hk8mr10808447pjb.102.1634271274244; Thu, 14 Oct 2021 21:14:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 49/67] target/ppc: Move SPR_DSISR setting to powerpc_excp Date: Thu, 14 Oct 2021 21:10:35 -0700 Message-Id: <20211015041053.2769193-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272745662100001 Content-Type: text/plain; charset="utf-8" By doing this while sending the exception, we will have already done the unwinding, which makes the ppc_cpu_do_unaligned_access code a bit cleaner. Update the comment about the expected instruction format. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b7d1767920..88a8de4b80 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -454,13 +454,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int = excp_model, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception = */ - /* Get rS/rD and rA from faulting opcode */ /* - * Note: the opcode fields will not be set properly for a - * direct store load/store, but nobody cares as nobody - * actually uses direct store segments. + * Get rS/rD and rA from faulting opcode. + * Note: We will only invoke ALIGN for atomic operations, + * so all instructions are X-form. */ - env->spr[SPR_DSISR] |=3D (env->error_code & 0x03FF0000) >> 16; + { + uint32_t insn =3D cpu_ldl_code(env, env->nip); + env->spr[SPR_DSISR] |=3D (insn & 0x03FF0000) >> 16; + } break; case POWERPC_EXCP_PROGRAM: /* Program exception = */ switch (env->error_code & ~0xF) { @@ -1462,14 +1464,9 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr= vaddr, int mmu_idx, uintptr_t retaddr) { CPUPPCState *env =3D cs->env_ptr; - uint32_t insn; - - /* Restore state and reload the insn we executed, for filling in DSISR= . */ - cpu_restore_state(cs, retaddr, true); - insn =3D cpu_ldl_code(env, env->nip); =20 cs->exception_index =3D POWERPC_EXCP_ALIGN; - env->error_code =3D insn & 0x03FF0000; - cpu_loop_exit(cs); + env->error_code =3D 0; + cpu_loop_exit_restore(cs, retaddr); } #endif --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634272893134577.7219600593628; Thu, 14 Oct 2021 21:41:33 -0700 (PDT) Received: from localhost ([::1]:35216 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF2C-000598-5H for importer@patchew.org; Fri, 15 Oct 2021 00:41:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcB-0006of-0B for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:39 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:47027) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc8-0002qu-5g for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:38 -0400 Received: by mail-pj1-x1030.google.com with SMTP id pi19-20020a17090b1e5300b0019fdd3557d3so6349087pjb.5 for ; Thu, 14 Oct 2021 21:14:35 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hDIIDmSt3XkX7dozNp8YyanBuOQiSpBj16JErrhb+ZE=; b=poa10+caLetC1TkeKR3MlvgZXCAxCqn5i/UC4qHieAqXuO9i7Rs43cei0jD0G5GCEr Np53kigyP8NuOVoViNmyiEaR+tIRhJWxJ6YxLLV9hkSzeYWS70iIsFVtkHMmyw9b44HS IZvP/2BoprZPLRMPszGApssvhsvqC//aAsF6D8Kl3qAAzjEqOSjl/Tv9h0Kfas8FLNR9 6vzLZv9KY5qOC0mHOLVq0DPstXSY/o5uNaCTtVJ9V5cNx6w5EBXf1110I+BLgQTsmqo1 P71rkJ1LMSxfBGeJZvP63nJX+nz4L3u4Tep6hlwFzetllgz+Xb4wEaIKnRVNNBHyDsw+ aIOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hDIIDmSt3XkX7dozNp8YyanBuOQiSpBj16JErrhb+ZE=; b=ZxVoGw1bLskcSnUB+4IAEBbJLyNCWcI9XiOLKcda0+tidS2k5anOF/9Cgl/EVz2wJu YNec80nCrwZOEuKKOHe5CtqRJpHeln+g5uJn3HZPeGBQI8SItAl+Qb/pUdC0s70gi5qK qLqCGmNizaY8we/e0RIjECvj7jCh8UuLq2bp3hJtm8N3eUkggoMdczb/qUsNLGFIFuXF 7OEfGeQiKcrMU2siScfvp3bpvIFMZ5DSw9piJ/yMydJavJRt4Gf+P4gFzA4X+tpbz4A0 9RBQZhXy0L89zqZE7vo+MiM+CjjITfmr8ccATjzcmRwMgrUIRkJpqloGXMtA4tOGX8r0 hpbg== X-Gm-Message-State: AOAM532GAJq81LnbESH6l2HNex7yOqHx/z9CO+F9NrVspMmwMjcF4+QE cHGUyYDS3jWvN5QgLtj6ejgA7yh/E0+NAg== X-Google-Smtp-Source: ABdhPJzfS8jlkmiVDWYrUrOdLpYyVB8POA1EYIs1ciAODpk+I7S70lYmlGpL2RQ26rUNxgAbwW8P3w== X-Received: by 2002:a17:90b:20d2:: with SMTP id ju18mr24090948pjb.66.1634271274874; Thu, 14 Oct 2021 21:14:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 50/67] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Date: Thu, 14 Oct 2021 21:10:36 -0700 Message-Id: <20211015041053.2769193-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272895260100003 Content-Type: text/plain; charset="utf-8" We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: qemu-ppc@nongnu.org Reviewed-by: Warner Losh Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 88a8de4b80..e568a54536 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1465,6 +1465,20 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr= vaddr, { CPUPPCState *env =3D cs->env_ptr; =20 + switch (env->mmu_model) { + case POWERPC_MMU_SOFT_4xx: + case POWERPC_MMU_SOFT_4xx_Z: + env->spr[SPR_40x_DEAR] =3D vaddr; + break; + case POWERPC_MMU_BOOKE: + case POWERPC_MMU_BOOKE206: + env->spr[SPR_BOOKE_DEAR] =3D vaddr; + break; + default: + env->spr[SPR_DAR] =3D vaddr; + break; + } + cs->exception_index =3D POWERPC_EXCP_ALIGN; env->error_code =3D 0; cpu_loop_exit_restore(cs, retaddr); --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163427298315556.63408249313784; Thu, 14 Oct 2021 21:43:03 -0700 (PDT) Received: from localhost ([::1]:40844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF3e-0000ZB-59 for importer@patchew.org; Fri, 15 Oct 2021 00:43:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcA-0006me-Gj for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:38 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:34743) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc8-0002ry-R0 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:38 -0400 Received: by mail-pj1-x1029.google.com with SMTP id q2-20020a17090a2e0200b001a0fd4efd49so2155610pjd.1 for ; Thu, 14 Oct 2021 21:14:36 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=edXkrbkqOm07djX1rJHm1DMaa+Lm/qwNrJ4BGEQSsuM=; b=DcsIbhOXtOpJQ3sIQFiwPPcqKUYVCuprF4dE7U9AHVOCI0PEqoTiq9cI+fRA7VRPyL erZXJaGP56aDLBtw6xdo2/v5dfF4eB9WSzVnWlj/VBhPbm7ghWg3FhUdZQmWr7EzPVV8 z5r/va21f+jI8T73I+Y4V1VdW8CWbeCo9Pw2cjdpTUMJ/2pPRh35olV3FE/0Mcd0NM3A ObaSCOvxmKVR4afzm63HbzDqNx7iYxkGYNU8JhpgH4mrV6sQEdNt7iEkJ+dQD1Mej0xL t1tSs4YhfLLPt/exgiAbnp6YCN9RvkXRIt3yGd3LKKxOtRDjm9rMh5/vymJsUvId/TMs cJdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=edXkrbkqOm07djX1rJHm1DMaa+Lm/qwNrJ4BGEQSsuM=; b=a9BQpWG2MDTUw9dzITvCKO+xZ3sNII+dVkyka6kVPbAplu1czfT4wUgtqkadFesFVK 0O0h/shO0LDJLSm4S6i+kaAK1X3z371hDSUofx+DxWlH01/X9+TmHtv79cJoMK6vqo8I PI3AOvDJY6sZ/XueyqO0GwyWaweTYoWrxlcBpzuueFij7Tuuvqqn2PT6Oj2deL8eEwXx 4zIVDx/RC9TKL7+qai+qORwOgibseNk22cpr8RV7gEVpLwqBfukEAiQDJehFDZTQd+mn URIHuoxNDtttKAIyQwQaMwUbBQAtcBv1lZ0ixh4QffsyMiAPSQcQzHA8b5u3Mb6xCYtk RdYw== X-Gm-Message-State: AOAM530yYgbx4gL+TOL3exiHSDrRFUHedmRBrw0o4Krn3GSM6YPZc8vJ JRYvMBuL2LhEoJqqdxpAG3CTRYByXqxecg== X-Google-Smtp-Source: ABdhPJxROBuU8cAY4qr9jjynrs0CUoqv6kqMdXHCSQ0HV6Ijr+gR9FfImjtVXxfuv2mY1zEDwQOU1Q== X-Received: by 2002:a17:90a:fa91:: with SMTP id cu17mr8127896pjb.91.1634271275654; Thu, 14 Oct 2021 21:14:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 51/67] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Date: Thu, 14 Oct 2021 21:10:37 -0700 Message-Id: <20211015041053.2769193-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634272983571100001 Content-Type: text/plain; charset="utf-8" This is not used by, nor required by, user-only. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh --- target/ppc/internal.h | 8 +++----- target/ppc/excp_helper.c | 8 +++----- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 339974b7d8..6aa9484f34 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -211,11 +211,6 @@ void helper_compute_fprf_float16(CPUPPCState *env, flo= at16 arg); void helper_compute_fprf_float32(CPUPPCState *env, float32 arg); void helper_compute_fprf_float128(CPUPPCState *env, float128 arg); =20 -/* Raise a data fault alignment exception for the specified virtual addres= s */ -void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; - /* translate.c */ =20 int ppc_fixup_cpu(PowerPCCPU *cpu); @@ -291,6 +286,9 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; #endif =20 #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index e568a54536..17607adbe4 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1454,11 +1454,8 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_= ulong rb) =20 book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL); } -#endif -#endif /* CONFIG_TCG */ -#endif +#endif /* TARGET_PPC64 */ =20 -#ifdef CONFIG_TCG void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) @@ -1483,4 +1480,5 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr = vaddr, env->error_code =3D 0; cpu_loop_exit_restore(cs, retaddr); } -#endif +#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273789150238.35225495861653; Thu, 14 Oct 2021 21:56:29 -0700 (PDT) Received: from localhost ([::1]:48174 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFGe-0008Lv-1l for importer@patchew.org; Fri, 15 Oct 2021 00:56:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39600) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcB-0006r4-Pv for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:41 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:44944) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc9-0002s9-M2 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:39 -0400 Received: by mail-pf1-x42c.google.com with SMTP id v8so3163199pfu.11 for ; Thu, 14 Oct 2021 21:14:37 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tQ9zUqcauybUZbu3B5IksrNIUQen6fZFWQH9MsgW1Ec=; b=IB9jlkuJ2hEfEe9R/lGSIK+VBe2GZI8HMMg4llZabuKw0K/vn5ynPlf7je5V+6zO8x WAXfBWEvufH1yvJ3kf5v0faes/lkyo8NiNhlqgRRhmekhgkkh+fB+h7kte4PLYVKrslA 5k1iMksyUg1ZYrb2SlFxXSvrM1W00qCbZ8yLJ2+mKacNE8X+ogAmSLMc+J62GlUsaJv8 yXYx3b8FgcjP3UxAPqswM+GhU0PdnezInrQkDpbBhqVeVsEYX8gOhYHb7fOBXFQZ+tsL BC0jAM6C86K5G74DEHm4XLA1N/0AC6LC+ULNEnePCrwohnYAUogMBiRrqruZsZHMezEA +joA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tQ9zUqcauybUZbu3B5IksrNIUQen6fZFWQH9MsgW1Ec=; b=LtczXO2P55EAGaVUcZz2WWlCCW+TkSlJDWgfT18p9seM7ibdQirce4Zg9Vv9e7cCCd EWi7dfprXxAEaUBTj/PTgQV3sGust3uyjfsSIOACZK4MoarCcqNguIBSDBFU46UY3I8A sbjxkMUMhyBpbQzJqCRY1xfZB/4sBuv1HztDCZOWUt0eLvccOOC3tkhEOwykSW7ZhjXR CF5N71UM31xqn3PUERPpy7sJclq3Zn5g/yXYgCSu5FBTaEseVI8q1CZexE7dlZehty12 3MKk25HZcEsweqB0Y9nRy3XuGBbXrCtjP4+7PIRepQy7Seq1AbPLLFDllzEmWewksBP5 sxKg== X-Gm-Message-State: AOAM530XcBTAt7oCbhqkrztZCpSskGZzA2d5VRGUM8/S0/CRnEGG08Gj f+0yCxKLSpZnRLDvsdnLd46gcN/T/EtL+w== X-Google-Smtp-Source: ABdhPJzH/UGrLLxP37+J0vKGl/3HYNYLyvd3ojvkGmiYr8QVP1es3Pbrhtwh7uXgwP54GAA1JEFicA== X-Received: by 2002:a63:e041:: with SMTP id n1mr7471986pgj.211.1634271276299; Thu, 14 Oct 2021 21:14:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 52/67] target/s390x: Implement s390x_cpu_record_sigbus Date: Thu, 14 Oct 2021 21:10:38 -0700 Message-Id: <20211015041053.2769193-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273791175100001 Content-Type: text/plain; charset="utf-8" For s390x, the only unaligned accesses that are signaled are atomic, and we don't actually want to raise SIGBUS for those, but instead raise a SPECIFICATION error, which the kernel will report as SIGILL. Split out a do_unaligned_access function to share between the user-only s390x_cpu_record_sigbus and the sysemu s390x_do_unaligned_access. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/s390x/s390x-internal.h | 8 +++++--- target/s390x/cpu.c | 1 + target/s390x/tcg/excp_helper.c | 27 ++++++++++++++++++++------- 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 163aa4f94a..1a178aed41 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -270,18 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; =20 #ifdef CONFIG_USER_ONLY void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr); +void s390_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr); #else bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; #endif =20 =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 593dda75c4..ccdbaf84d5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -269,6 +269,7 @@ static const struct TCGCPUOps s390_tcg_ops =3D { =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D s390_cpu_record_sigsegv, + .record_sigbus =3D s390_cpu_record_sigbus, #else .tlb_fill =3D s390_cpu_tlb_fill, .cpu_exec_interrupt =3D s390_cpu_exec_interrupt, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index b923d080fc..4e7648f301 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -82,6 +82,19 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t= dxc) tcg_s390_data_exception(env, dxc, GETPC()); } =20 +/* + * Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, + * this is only for the atomic operations, for which we want to raise a + * specification exception. + */ +static void QEMU_NORETURN do_unaligned_access(CPUState *cs, uintptr_t reta= ddr) +{ + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); +} + #if defined(CONFIG_USER_ONLY) =20 void s390_cpu_do_interrupt(CPUState *cs) @@ -106,6 +119,12 @@ void s390_cpu_record_sigsegv(CPUState *cs, vaddr addre= ss, cpu_loop_exit_restore(cs, retaddr); } =20 +void s390_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr) +{ + do_unaligned_access(cs, retaddr); +} + #else /* !CONFIG_USER_ONLY */ =20 static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) @@ -593,17 +612,11 @@ void s390x_cpu_debug_excp_handler(CPUState *cs) } } =20 -/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, - this is only for the atomic operations, for which we want to raise a - specification exception. */ void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - S390CPU *cpu =3D S390_CPU(cs); - CPUS390XState *env =3D &cpu->env; - - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); + do_unaligned_access(cs, retaddr); } =20 static void QEMU_NORETURN monitor_event(CPUS390XState *env, --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273026581969.4846423975495; Thu, 14 Oct 2021 21:43:46 -0700 (PDT) Received: from localhost ([::1]:43318 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF4L-0002Q0-Ha for importer@patchew.org; Fri, 15 Oct 2021 00:43:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcB-0006r6-VM for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:41 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:43602) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcA-0002sd-GN for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:39 -0400 Received: by mail-pg1-x530.google.com with SMTP id r2so7430327pgl.10 for ; Thu, 14 Oct 2021 21:14:38 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QuBUrcbK5IHnv9/MH2TrxQjSj4HGL7JlA8tE+X8E85A=; b=giCakC6l2MtvrckNHO00CDJOIHxjYyiiplMsqYrxIqY7SO11XjAkdl7LxsrcGAL39Z kg+U6SdomLFrTarLwoH76IJ+m7F9S9ufaoMWP433H4wFRsQJ5Mvs/d+wu82L1TMOa0+w wznc58l2+DtSlgByNYs/o9Y+CTD+7pFmjTKLdzYip32HwwDd2kq8OhlK6utG+JThcAQh xtTuPD3IkvreuKzlG4hAy8S+mtc9RNfWsUJxqB7jjep5vgaZfB1S9YAPzFbdeea9bE/N b5tOG7GqCzc9u/fzvs6Oz3jSrkte1GLF5V0+CCwHA3Jjw0UqnkxqmWUsbZs5EficOYiR zgvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QuBUrcbK5IHnv9/MH2TrxQjSj4HGL7JlA8tE+X8E85A=; b=mzXjpMN+wSWmq75H+0gST5AROvfFcVxbQGiicWp/wZeM0WY2bYhcdI/Ne789+R2eHE FtNWdOCT21GGEBtzi5SatGNKlz+nZ+SDyn9B3SXCdXcT529lt5Y0CtjrfoRTC+eRrfmF ql+8fL3yVvBm+kgPYmH+gx9qtzNZt6TCowDe1rDsYojxTspnbiOlPrkYYSNN+t5qkPPY fvY4NxoFRJXpk2moRRufUkoYGlzp+X90oD25ihwjeC/pu0AGTAqV2YzAM/7T1fOVBtli CZUyQblHUP4Exl5Gu7mW/kkIrewkRaH/cEjInkWxt29hPcQxh/z5+0G2h3Q6bAKA0QCT bFng== X-Gm-Message-State: AOAM530A/Dw1wHaJecqYtzDkoUuD4T2NWdFTplLtZ5XwqJRitTMxuoZO 2O9MWyMENiVyTCd7eYfl43SiEUnEhNc= X-Google-Smtp-Source: ABdhPJy1EUFJmFetlUMUjzDWcwIA6wSmo07G9VldpWVaS1mhWvujnh9OEzrqyEqT00HibQtuiAxQjg== X-Received: by 2002:a63:e116:: with SMTP id z22mr7227749pgh.223.1634271277080; Thu, 14 Oct 2021 21:14:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 53/67] linux-user/hppa: Remove POWERPC_EXCP_ALIGN handling Date: Thu, 14 Oct 2021 21:10:39 -0700 Message-Id: <20211015041053.2769193-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SUBJ_WIPE_DEBT=1.004 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273027382100001 Content-Type: text/plain; charset="utf-8" We will raise SIGBUS directly from cpu_loop_exit_sigbus. Signed-off-by: Richard Henderson --- linux-user/ppc/cpu_loop.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 840b23736b..483e669300 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -162,14 +162,6 @@ void cpu_loop(CPUPPCState *env) cpu_abort(cs, "External interrupt while in user mode. " "Aborting\n"); break; - case POWERPC_EXCP_ALIGN: /* Alignment exception = */ - /* XXX: check this */ - info.si_signo =3D TARGET_SIGBUS; - info.si_errno =3D 0; - info.si_code =3D TARGET_BUS_ADRALN; - info._sifields._sigfault._addr =3D env->nip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case POWERPC_EXCP_PROGRAM: /* Program exception = */ case POWERPC_EXCP_HV_EMU: /* HV emulation = */ /* XXX: check this */ --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273186616136.88042570655216; Thu, 14 Oct 2021 21:46:26 -0700 (PDT) Received: from localhost ([::1]:48930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF6v-0006Jt-EX for importer@patchew.org; Fri, 15 Oct 2021 00:46:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39630) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcC-0006rR-VQ for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:41 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:43708) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcB-0002ti-GB for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:40 -0400 Received: by mail-pf1-x436.google.com with SMTP id 187so7279059pfc.10 for ; Thu, 14 Oct 2021 21:14:38 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KU5GqqnHBwJE2oQY4NvVS8KLTvZHsylgeTI1DbvIUb8=; b=caXEo8XfcVNqQC/PP328NXImnbbtyaPSavWBwvAB8S1sFXsgzGxEDM0d/OTLxO8T3G j5JkZd52oY+nRfjZbQ53ifiztefYGieujZI03+qLI1jEEtFK0KyTDNkYRHMo4enAd5ym /TZBt9pGxA4jjN5A9PttOczJhsWgvXEcH4Tb8FyhxMqvXhj/XcBi7HQJceD1j7mB76cZ AWF8/hvn9spNNvAr19X2HA8clizEy+gJhjnq/6Ux7ZahOxG4k1YgAWTYkxRVpHnylCIF ZsVM7lC3olLeQ8FtjOJohuM6AcCAt8/4U6KpU3ymYLG3tSe9MM7XIsqH1X99ntyKNXlW ZvZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KU5GqqnHBwJE2oQY4NvVS8KLTvZHsylgeTI1DbvIUb8=; b=idiLh04DVC1IXavqpuKOqnwuOXsypp3zuVHdr6oq5zUtDgrPEzVuMXW4vLng8plhhZ kms6CW/pcxRpRF22WvXLy6DWrvP3Hm28Gf0KPacGOlLkUh+cfWFDooGqs1g0o+cLbPpb 0SfjTwut1jBGCyTtWMjr7oQGMZU9hLeoSgsaVekaUvwbXNa6ooc3lohzTHehfYdGSnlq 2CfORpxNyG+O+9rC4UmfPb5txeXAgRHUeE8r3JHVHO+wZ9/TlSIQcLJ3dAfElg0knvw0 S3jCTk8U1OWWGydsWFxjDkcE/q8Y9abDPBNmVifM85eWStagp0EXRKOaH6ncecn9SEqg FNgg== X-Gm-Message-State: AOAM533x+LBZq4b20QGz1fp1XibpmXiBUhsaqi61e822Jrp46Jg1+YXN nwjOL6zXJXlUQRPjuBzymPhGWcD9ZOJK4g== X-Google-Smtp-Source: ABdhPJyu8mHwae1Kf2Cd51kyKDr2xVwkAVltFhogh2lRvMBeL1Wiusj+hZhdAwpC522zcutYdYZt5g== X-Received: by 2002:a63:7450:: with SMTP id e16mr3562995pgn.482.1634271277964; Thu, 14 Oct 2021 21:14:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 54/67] target/sh4: Set fault address in superh_cpu_do_unaligned_access Date: Thu, 14 Oct 2021 21:10:40 -0700 Message-Id: <20211015041053.2769193-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, Yoshinori Sato Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273188533100001 We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sh4/op_helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index c0cbb95382..d6d70c339f 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -29,6 +29,9 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { + CPUSH4State *env =3D cs->env_ptr; + + env->tea =3D addr; switch (access_type) { case MMU_INST_FETCH: case MMU_DATA_LOAD: @@ -37,6 +40,8 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, case MMU_DATA_STORE: cs->exception_index =3D 0x100; break; + default: + g_assert_not_reached(); } cpu_loop_exit_restore(cs, retaddr); } --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163427322792718.16896330897123; Thu, 14 Oct 2021 21:47:07 -0700 (PDT) Received: from localhost ([::1]:51480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF7a-0008AF-QL for importer@patchew.org; Fri, 15 Oct 2021 00:47:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39632) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcD-0006tE-Jx for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:43 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:46614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcC-0002ul-24 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:41 -0400 Received: by mail-pf1-x435.google.com with SMTP id i76so5155377pfe.13 for ; Thu, 14 Oct 2021 21:14:39 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P+LiSx7CkE3blKbhg5ALaxOT08dtFOhalcqlNc9ibvc=; b=fkD5lzW8XEdW/8JddIYnS/3TBxtw+Z4dI0TbGhaI8Owa2wXINxDYLYYG4N0ClA3Xy5 dhDSus9p4jC14sPZXFqh/5UkbhTjlcZyyXyG91Pc1iMvM+H4ALkI8K1yTYG3WR6ltsDu Hym9K1DLHee57sI1ZPRMWz+K0/X8AWVEFEPHOXQfCqqzTfS1JHM5yh29ZRBtmCcTKSYE T34yzzIkzG8r00mnTgYPVuGP2AW8hGXvzBQOp9Yh8LqJWKvFAhBuVdLvVpRVT5uOKpeA eXG1K2QfwdE22EpTNl6Ay8mHRSBlIS3+3RLxvh6Sqo1outCX4mPwXXKpdT4q6XUN56gy zM/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P+LiSx7CkE3blKbhg5ALaxOT08dtFOhalcqlNc9ibvc=; b=0H4ZZ0/6vDxD5ue4Uv3d2sfGhoiyN0pDRJobSQNepeQOQcDrMZ1Ik5fYFemyvuPNCx obxgKGhmxlfYdRIc7K88JfTH347NdE6mW98wx0itD556QGmt3e6j5eGXWBQ+b4PVllTQ yMRPxe5CDp8V2/fu9FyeOvzsNcSC40AAYHac6iX8qk5aTAiDWp7ftXIk3cDCuKFiIRTd o4/j1UBHUEphGdJIJ4JTYlnScYwRSr7fBTMNp7/TSHHDpiBcZnlmMICPdB4aH7fSod/d IXdTefPjzBFEhBhtwN55jhm6Wg0C4eql0oDC0Qe0uVeG5d1ndPXPI6LOY48tJBTHgHvc Bc/A== X-Gm-Message-State: AOAM5327KRvoBiREg1589wcPGIez2KbEj8J/wekSXYUtKuUxhBzI9iLl lFCvRRS5ra35qEZq7kO+YqTucPllO9oMbQ== X-Google-Smtp-Source: ABdhPJyIMeZXstxhSDuBUlW0f2ojhgl+kBxtHzTX4Def2j2uv4bzrtpd1rjvfssj56E05IiGspePJg== X-Received: by 2002:a63:f313:: with SMTP id l19mr7496427pgh.40.1634271278750; Thu, 14 Oct 2021 21:14:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 55/67] target/sparc: Remove DEBUG_UNALIGNED Date: Thu, 14 Oct 2021 21:10:41 -0700 Message-Id: <20211015041053.2769193-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273228690100001 The printf should have been qemu_log_mask, the parameters themselves no longer compile, and because this is placed before unwinding the PC is actively wrong. We get better (and correct) logging on the other side of raising the exception, in sparc_cpu_do_interrupt. Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index bbf3601cb1..0549b6adf1 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -27,7 +27,6 @@ =20 //#define DEBUG_MMU //#define DEBUG_MXCC -//#define DEBUG_UNALIGNED //#define DEBUG_UNASSIGNED //#define DEBUG_ASI //#define DEBUG_CACHE_CONTROL @@ -364,10 +363,6 @@ static void do_check_align(CPUSPARCState *env, target_= ulong addr, uint32_t align, uintptr_t ra) { if (addr & align) { -#ifdef DEBUG_UNALIGNED - printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FM= T_lx - "\n", addr, env->pc); -#endif cpu_raise_exception_ra(env, TT_UNALIGNED, ra); } } @@ -1968,10 +1963,6 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPU= State *cs, vaddr addr, SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; =20 -#ifdef DEBUG_UNALIGNED - printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx - "\n", addr, env->pc); -#endif cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } #endif --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273915564928.7055677357313; Thu, 14 Oct 2021 21:58:35 -0700 (PDT) Received: from localhost ([::1]:54466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFIg-00045t-Hc for importer@patchew.org; Fri, 15 Oct 2021 00:58:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcF-0006uo-F0 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:45 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:36422) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcC-0002vY-L1 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:43 -0400 Received: by mail-pj1-x102e.google.com with SMTP id qe4-20020a17090b4f8400b0019f663cfcd1so8463604pjb.1 for ; Thu, 14 Oct 2021 21:14:40 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fVhlPoABQmS8wc89+ovGDAnkicIV2MZx6WAeJyRD9lM=; b=qMqrOYwmtt+X1d0REGIMNZhO8FyCFOvBnfzL6sGzIsnCYp+PVN1RxFaSefSnooOMwY s0XyYPAyUrYx0ufnTgPRgEExTbn1oa8x3metExFrZEMM/2HOPL3FThXsTET6x80/8WxM +VfQ5goAHMARJYhTd17CadYKIaemfgdaRgG8/pAQUIYZyHov6wxaJ8qcUOkBV71EsyRg 3qB92KxHmjjS+KUE3RlNMJ24bRXJfYc9bvHR2dxTjIytJfHhVLG+oUhnNKEG3QtVBMc4 e8YaOAIzUyuNxMTiD2A70s4Lgaj/2/L/6dBXoufU+h5Jd8kq4yvUBGdcIyRbGpNyUXw6 Iefw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fVhlPoABQmS8wc89+ovGDAnkicIV2MZx6WAeJyRD9lM=; b=zyDFXpB/Gf+/y/NL9Go0OGa796C3yNXdIYxvLIz+SkvMbljoyLCxU0AjOrAK2i59Sa +p157bMUixFvloFEyz1TL8PuGPSYY+uMbk+IfDbSqXnt9K0Cu1XbKdSsHoNSkkUO9AuT 5OmvletN5Q4MjZ+No3z08Cy0EVf8S+6cI1E/pAKm9kNbT9Ets2l6wFL6oIfCe80NKj2P 9NWiQwXT/reCQDRnmfDragdTKNO3x5HpRqYX0tuyx8X2f+YWEFUJtIw/1JOdf7lGzjZn Z5MC5ComESfoxqHz1FBUh557qmTkkBMtZr5xiF4fgutQ2icTWkldBJr0p4uuGG3yZdsl AohQ== X-Gm-Message-State: AOAM530KlbhpBbl+sa77IX4itIczBZFjpVYv9k41w+/TaQIEwlqXSOmF SS9HcCxxhrAnlwXc40SeF8am/eLZkRp28w== X-Google-Smtp-Source: ABdhPJwreN+RQFlDaWqgYKYgiZ6+pXcegt+8Q62IiHilUKK8Hfzwpr9uL+Fd1tqV/zCrZknwS7lZyw== X-Received: by 2002:a17:90a:4306:: with SMTP id q6mr11026428pjg.17.1634271279361; Thu, 14 Oct 2021 21:14:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 56/67] target/sparc: Split out build_sfsr Date: Thu, 14 Oct 2021 21:10:42 -0700 Message-Id: <20211015041053.2769193-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273916143100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/mmu_helper.c | 72 +++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 26 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 2ad47391d0..014601e701 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -502,16 +502,60 @@ static inline int ultrasparc_tag_match(SparcTLBEntry = *tlb, return 0; } =20 +static uint64_t build_sfsr(CPUSPARCState *env, int mmu_idx, int rw) +{ + uint64_t sfsr =3D SFSR_VALID_BIT; + + switch (mmu_idx) { + case MMU_PHYS_IDX: + sfsr |=3D SFSR_CT_NOTRANS; + break; + case MMU_USER_IDX: + case MMU_KERNEL_IDX: + sfsr |=3D SFSR_CT_PRIMARY; + break; + case MMU_USER_SECONDARY_IDX: + case MMU_KERNEL_SECONDARY_IDX: + sfsr |=3D SFSR_CT_SECONDARY; + break; + case MMU_NUCLEUS_IDX: + sfsr |=3D SFSR_CT_NUCLEUS; + break; + default: + g_assert_not_reached(); + } + + if (rw =3D=3D 1) { + sfsr |=3D SFSR_WRITE_BIT; + } else if (rw =3D=3D 4) { + sfsr |=3D SFSR_NF_BIT; + } + + if (env->pstate & PS_PRIV) { + sfsr |=3D SFSR_PR_BIT; + } + + if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ + sfsr |=3D SFSR_OW_BIT; /* overflow (not read before another fault)= */ + } + + /* FIXME: ASI field in SFSR must be set */ + + return sfsr; +} + static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, MemTxAttrs *attrs, target_ulong address, int rw, int mmu= _idx) { CPUState *cs =3D env_cpu(env); unsigned int i; + uint64_t sfsr; uint64_t context; - uint64_t sfsr =3D 0; bool is_user =3D false; =20 + sfsr =3D build_sfsr(env, mmu_idx, rw); + switch (mmu_idx) { case MMU_PHYS_IDX: g_assert_not_reached(); @@ -520,29 +564,18 @@ static int get_physical_address_data(CPUSPARCState *e= nv, hwaddr *physical, /* fallthru */ case MMU_KERNEL_IDX: context =3D env->dmmu.mmu_primary_context & 0x1fff; - sfsr |=3D SFSR_CT_PRIMARY; break; case MMU_USER_SECONDARY_IDX: is_user =3D true; /* fallthru */ case MMU_KERNEL_SECONDARY_IDX: context =3D env->dmmu.mmu_secondary_context & 0x1fff; - sfsr |=3D SFSR_CT_SECONDARY; break; - case MMU_NUCLEUS_IDX: - sfsr |=3D SFSR_CT_NUCLEUS; - /* FALLTHRU */ default: context =3D 0; break; } =20 - if (rw =3D=3D 1) { - sfsr |=3D SFSR_WRITE_BIT; - } else if (rw =3D=3D 4) { - sfsr |=3D SFSR_NF_BIT; - } - for (i =3D 0; i < 64; i++) { /* ctx match, vaddr match, valid? */ if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical= )) { @@ -592,22 +625,9 @@ static int get_physical_address_data(CPUSPARCState *en= v, hwaddr *physical, return 0; } =20 - if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status registe= r */ - sfsr |=3D SFSR_OW_BIT; /* overflow (not read before - another fault) */ - } - - if (env->pstate & PS_PRIV) { - sfsr |=3D SFSR_PR_BIT; - } - - /* FIXME: ASI field in SFSR must be set */ - env->dmmu.sfsr =3D sfsr | SFSR_VALID_BIT; - + env->dmmu.sfsr =3D sfsr; env->dmmu.sfar =3D address; /* Fault address register */ - env->dmmu.tag_access =3D (address & ~0x1fffULL) | context; - return 1; } } --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163427303581166.68031376663646; Thu, 14 Oct 2021 21:43:55 -0700 (PDT) Received: from localhost ([::1]:44084 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF4U-0002wO-Jv for importer@patchew.org; Fri, 15 Oct 2021 00:43:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39670) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcF-0006ub-95 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:45 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:37551) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcD-0002w2-KU for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:42 -0400 Received: by mail-pf1-x433.google.com with SMTP id q19so7313409pfl.4 for ; Thu, 14 Oct 2021 21:14:41 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=muffzeHX3yZuoAcxrWs0UhKgv9u/j8rmCNk7xQHU/Hc=; b=W4LeJ9a2EKradOZjo4wTuB8xqkNzf2KdkMde9V6GZwVepTf93PrFCJ7GPovl6AMirM midF8TuBN6hjPUiNdG1PF5HSd0HpGw8r2+F25/rLP/SiFkktHj7/RE5UY6VpA0iRVP05 mKwe+lvis30h42xwgbYNYrl+GO7EqM4hxg2Ad64jqliABa1Lbg594rNd1jMvZtKwB6fh 8DnywRUl/WMPkVvS8ZY5OP2ikhv1AesClKhjY5I/gkKd1K9DKIl8X79hgn5onURepMMP awkRuMvS6nEyNJ8TwhyBWjCgm3M1k4QzMAH2UrX7Nf6MMcwq3Ja7yv8WE6C9vIrdrkoj vYPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=muffzeHX3yZuoAcxrWs0UhKgv9u/j8rmCNk7xQHU/Hc=; b=j3Sm+Qtq+3xxFwZ8Ra7KMi7y1yktYJ2UTSp9XNhh+YVEKOE/UXMziGjEJKZopGbfPT RA0RKMdPpZBgyhYJUqCU3sP1bsr8OukfuLhhS8NdQ/5gD8eR64LpYlUy5dkzzLd88yTJ 6kRyjue59g7jAnk+ybgUSd3taafvIZrYl0tTgF9spTiNOI6heycFrfBlIfmX/4qicdqH HNUZq2/yf3a0MUkOszvGq4sgNjdKg/nmM62bO27LkmkuRoPA4THLWS2nq2ZCkP3cuq7B uuuUpdc9V9r68wO9wGwhcs4IHr2tqzqu4eAPs/NUwGNfh9jBpIpi3+QREr1Kh6H+jw2R h+yw== X-Gm-Message-State: AOAM531vOxn8ZVup055L4N7jCgZKAXONVYppO5Qg2P4pdHIAOWi86Xi5 It03T7PJzvg7o/WCZWgkXOl67NOMK64zkA== X-Google-Smtp-Source: ABdhPJyRALf14qi93sh71sMo0PVj3s2Myq763fLTP2I0AItLKY7NIVT1WMz4yJHgYU59gr8++pdP4A== X-Received: by 2002:a65:6aa8:: with SMTP id x8mr7419834pgu.136.1634271280135; Thu, 14 Oct 2021 21:14:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 57/67] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Date: Thu, 14 Oct 2021 21:10:43 -0700 Message-Id: <20211015041053.2769193-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273037892100001 Content-Type: text/plain; charset="utf-8" We ought to have been recording the virtual address for reporting to the guest trap handler. Move the function to mmu_helper.c, so that we can re-use code shared with get_physical_address_data. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 13 ------------- target/sparc/mmu_helper.c | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 0549b6adf1..a3e1cf9b6e 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1953,16 +1953,3 @@ void sparc_cpu_do_transaction_failed(CPUState *cs, h= waddr physaddr, is_asi, size, retaddr); } #endif - -#if !defined(CONFIG_USER_ONLY) -void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, - uintptr_t retaddr) -{ - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; - - cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); -} -#endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 014601e701..f2668389b0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -922,3 +922,23 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vad= dr addr) } return phys_addr; } + +#ifndef CONFIG_USER_ONLY +void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, + uintptr_t retaddr) +{ + SPARCCPU *cpu =3D SPARC_CPU(cs); + CPUSPARCState *env =3D &cpu->env; + +#ifdef TARGET_SPARC64 + env->dmmu.sfsr =3D build_sfsr(env, mmu_idx, access_type); + env->dmmu.sfar =3D addr; +#else + env->mmuregs[4] =3D addr; +#endif + + cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); +} +#endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273366046515.930031730631; Thu, 14 Oct 2021 21:49:26 -0700 (PDT) Received: from localhost ([::1]:60352 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF9p-0005oT-28 for importer@patchew.org; Fri, 15 Oct 2021 00:49:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcI-0006yL-Es for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:47 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:33780) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcD-0002wS-W9 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:46 -0400 Received: by mail-pl1-x62e.google.com with SMTP id y4so5641229plb.0 for ; Thu, 14 Oct 2021 21:14:41 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pdzh8Ws2GkGBVDH5ETDlAj3vOFqZvQW52CUEjET/TWY=; b=CJCNLq7rj3AkfgcC6utiwUZqfc7wtb7dTqJ/NvvKces23Khe4OjVa6lQDM2OdBxNsp yZbGB1KpIwMxGJiyK7Ev5GtVKxDrJzX2W5PYUbM41t7qPwQ3UcxPbLQWYRNnfpryASZY /B+bmEjEe6eRWqvtzg/3JOgYdJD3tMjIHmIO9mCOTJJqF33m7Lt4Kg+ejvAXsKAiQUIj 9lVkYs+1MSN91/sMUCl/VjDVP1SDkuyAGIq3zdDEVkm9MxcKhhKQ9uCBGJEfHzGdKzC3 MZ1bmHWz4JVARFvVLc5l60WOuNxFZ12FKlXXJoaE4fHZFN4RrBNI8rLNe3cHnfvipQUJ P6ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pdzh8Ws2GkGBVDH5ETDlAj3vOFqZvQW52CUEjET/TWY=; b=F7sVfWgwjXO06CyjIXmpVLHiympjouTwNrWAuKBvQSmocZzVytfHt6KePDOva4mdgr xssNho6qLUpnd6J4GIsLi6eM8/5m+J+ULyPu/1s2fHeT65erJ+kQwxpCflmHuUGHJQOe sNwvyd5X0uAZnLcKR3YEkTX4eW2GI9bH4mTO8aqVnyWXCsBWV27xXzmEsNlYgjwlASgH DhgJ3s0XP9O8RhRHjq9rUvGgSKz5iQylm47wttXMXHe1KzVy5WurX8ChBvcL2A0FBRLD h2cnUA3VAid2lUlA5M55dQAsSpT/v3wbibOAqv14xVQRk00PUZ3DHSkW+zET9C8wCouF BshA== X-Gm-Message-State: AOAM531tnKl4dZoVutRPW1cfWEmCLRJvlZXLoE0VQM6PyThLNkHBozno p8Zc2BGnDcfo8LkOAEsdzMkWcAoMAZpZMQ== X-Google-Smtp-Source: ABdhPJyNkPWdaWJg+lnQ+ivJg0bZnYcsQZ+d+WK+fKdvtt+ZZdAt9r22tyVgAtHFbpXpPzvwKz5hVA== X-Received: by 2002:a17:90a:7345:: with SMTP id j5mr25397984pjs.48.1634271280785; Thu, 14 Oct 2021 21:14:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 58/67] accel/tcg: Report unaligned atomics for user-only Date: Thu, 14 Oct 2021 21:10:44 -0700 Message-Id: <20211015041053.2769193-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273367847100001 Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which has access to complete alignment info from the TCGMemOpIdx arg. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh --- accel/tcg/user-exec.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5646f8e527..92cbffd7c6 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -476,11 +476,22 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, MemOpIdx oi, int size, int prot, uintptr_t retaddr) { + MemOp mop =3D get_memop(oi); + int a_bits =3D get_alignment_bits(mop); + void *ret; + + /* Enforce guest required alignment. */ + if (unlikely(addr & ((1 << a_bits) - 1))) { + MMUAccessType t =3D prot =3D=3D PAGE_READ ? MMU_DATA_LOAD : MMU_DA= TA_STORE; + cpu_loop_exit_sigbus(env_cpu(env), addr, t, retaddr); + } + /* Enforce qemu required alignment. */ if (unlikely(addr & (size - 1))) { cpu_loop_exit_atomic(env_cpu(env), retaddr); } - void *ret =3D g2h(env_cpu(env), addr); + + ret =3D g2h(env_cpu(env), addr); set_helper_retaddr(retaddr); return ret; } --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273313230672.806471984961; Thu, 14 Oct 2021 21:48:33 -0700 (PDT) Received: from localhost ([::1]:57224 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF8y-0003ex-8P for importer@patchew.org; Fri, 15 Oct 2021 00:48:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcI-0006yK-C9 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:47 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:37684) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcE-0002xM-SJ for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:45 -0400 Received: by mail-pl1-x62d.google.com with SMTP id n11so5612973plf.4 for ; Thu, 14 Oct 2021 21:14:42 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VGqZOPjwuoviGfiS5SB/EShJZs+j0SuqFPzdROiPbhU=; b=bHyCnYFAxOJGBUQhByKTz2G+C+TKM1+9Twr4BQ50SSIdgcpIQVvnNjjNizrhi9vHUX No1gRmsFkRLfVOMn/hUltUj+RX82BMudTBQXRIIjUupe/C0UBvBr+TTgVP4ewFOBTZyg BT4F60+TMaMBQUrt8u5fb+VwATekXE6rLfmm58c5X4fD5ACGtdkL/Gh/3gergKeo61EP qNvWotd3fgjdcXb0CuIBTcG7R5w6zGyGkzbiDYRXRSzF0NuJm8sU6Rd1aGKAXY59MbUz h8MMGs6ANt1k9Ofb6Ovu3Bs7N+lKvYCaUsoHHhnimtkpT9tScRKHapzFggTkEB0W1sxz 7lHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VGqZOPjwuoviGfiS5SB/EShJZs+j0SuqFPzdROiPbhU=; b=uE33lICWkEKYzRDqNeO8geEli/xWeMmC2HKmccHcg/OxMzD3/atwBTAI5ZNsY76FCj 8CO+ObbNVPF7ndK8fhh6fE1EmHuIWNGqnokEACGcqem2y0SxG9z68IZ70CqeKNglNSoJ LFKZKXKk1Ik7QpEaiVDMerv1hjQ1rdCvoY7+zoRxnR5EMEtmOmTvCzhXe+HC+fbvXVJ1 NtUTQT8hs26ApIjObgBD48bbaoLKerHnAdKofAbZoZs3KSVi7mufvouOtzJ1NpYMLsgC jVhQX3ypFJ1p5vY+dU+o3+rI1TTMufcEkixKQuNzkzTqJ4e4M7+UJeGFrmBNqw30jFEb wjDQ== X-Gm-Message-State: AOAM532xUc1xipTTHxxFBzsBV3u9xHQENX4qHFcEBnkEfLQc4sTEUmly s0KbObc4k9M1VQwV6z4SLaCzkGclA6HhAQ== X-Google-Smtp-Source: ABdhPJxydz6Nn+1x41mzg1aPvKLt6MOOarFyIcE4PGnjiSmHitY5Ansp5Mteo3gNVdk4oA+dbscz9Q== X-Received: by 2002:a17:90a:ac0a:: with SMTP id o10mr24726301pjq.125.1634271281599; Thu, 14 Oct 2021 21:14:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 59/67] accel/tcg: Report unaligned load/store for user-only Date: Thu, 14 Oct 2021 21:10:45 -0700 Message-Id: <20211015041053.2769193-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273315351100001 Content-Type: text/plain; charset="utf-8" Use the new cpu_loop_exit_sigbus for cpu_mmu_lookup. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- accel/tcg/user-exec.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 92cbffd7c6..7d50dd54f6 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -220,9 +220,14 @@ static void validate_memop(MemOpIdx oi, MemOp expected) static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type) { + MemOp mop =3D get_memop(oi); + int a_bits =3D get_alignment_bits(mop); void *ret; =20 - /* TODO: Enforce guest required alignment. */ + /* Enforce guest required alignment. */ + if (unlikely(addr & ((1 << a_bits) - 1))) { + cpu_loop_exit_sigbus(env_cpu(env), addr, type, ra); + } =20 ret =3D g2h(env_cpu(env), addr); set_helper_retaddr(ra); --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273238315190.0318216124308; Thu, 14 Oct 2021 21:47:18 -0700 (PDT) Received: from localhost ([::1]:52186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF7l-0000Cv-51 for importer@patchew.org; Fri, 15 Oct 2021 00:47:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39728) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcI-0006yM-Sd for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:47 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:40508) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcH-0002yV-4L for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:46 -0400 Received: by mail-pj1-x102b.google.com with SMTP id pf6-20020a17090b1d8600b0019fa884ab85so8448130pjb.5 for ; Thu, 14 Oct 2021 21:14:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jfz53S3QlKXNPBsRIkUXBiTrLPBdQUAc4SLrCyr0OTo=; b=A0yhjLY4qMrUUkp4IsRQUircTvsF2E9Goj6FX9hb+mk3KYILAQcKhBJKjmyW3RywlC 69tgcffCEdhhWeLg8vNReYdndXkzixw2BIrJc4xxR6UESL2TjdFXpSU5HUbQdtELwhe0 a8wstvyKmmRobT+YFY858l/KJjcsPfjoBdY6+2wV19l/K540V2PYBL/4HUuGauFOumEd j2GwVznXKlO7pLDCFF2BY5XvB7I8r9ymL+GDklUp4vC5nYDeRhLZcvSXUPhmzaVw9yvM t3cB8AgCtKId9QvGG8aKiy97azkp0Q3nkrjCqgIvGuhGtQ2aafuibtqCm4F9LsVDoYya kM8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jfz53S3QlKXNPBsRIkUXBiTrLPBdQUAc4SLrCyr0OTo=; b=txfUXDXsW//8p7xxiO3rO/hhfUgR9CvUaSi3TioZLrwlMC85eCmWgV9+8Q0UlUxlqk H5QhSq10fcHixuaMYMpExzo+6DBmcmIuIX5Jzngs90NTq4INAvcLmPUuCigDD+LmezTp dg0/Za/mOL1hgFxYwgZQmBtfkBlgJZYzQkKlQFiHccpsND3tLNmJpGAXwoYRLBrhsAcG 7DgqDnzyy/qMLpuEBT+BWGAF2dO5KgMphfxxsZGpwceIMgSZBRwEpukCql3edi6Ck/pu LE7X9zSwtYpZzUs/ob5h31KjGPGO3C/Wvb/x8mnBv9QA2QzZVCFgwN5vLHvjYBwYce5I GpvQ== X-Gm-Message-State: AOAM530Z2TPBTqlHjEDVp/f7fmbjgZBcMdR4jdPbBtnGwRRR6hBcL+/T 8UgG2ko4OqOiGV7yfZeOjydhWtGiI3hjJg== X-Google-Smtp-Source: ABdhPJx872YZfcltXh5JP/IVfW4lBXXotPxx66TN/JbNRe2DmOjDCmM0TWAEwYnmR/qlfQVbPJ9LFQ== X-Received: by 2002:a17:90a:8593:: with SMTP id m19mr10609330pjn.82.1634271282199; Thu, 14 Oct 2021 21:14:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 60/67] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Date: Thu, 14 Oct 2021 21:10:46 -0700 Message-Id: <20211015041053.2769193-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273239325100001 Content-Type: text/plain; charset="utf-8" To be called from tcg generated code on hosts that support unaligned accesses natively, in response to an access that is supposed to be aligned. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh --- include/tcg/tcg-ldst.h | 5 +++++ accel/tcg/user-exec.c | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 8c86365611..bf40942de4 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -70,5 +70,10 @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong a= ddr, uint32_t val, void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr); =20 +#else + +void QEMU_NORETURN helper_unaligned_ld(CPUArchState *env, target_ulong add= r); +void QEMU_NORETURN helper_unaligned_st(CPUArchState *env, target_ulong add= r); + #endif /* CONFIG_SOFTMMU */ #endif /* TCG_LDST_H */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 7d50dd54f6..0473ead5ab 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "qemu/atomic128.h" #include "trace/trace-root.h" +#include "tcg/tcg-ldst.h" #include "internal.h" =20 __thread uintptr_t helper_retaddr; @@ -217,6 +218,16 @@ static void validate_memop(MemOpIdx oi, MemOp expected) #endif } =20 +void helper_unaligned_ld(CPUArchState *env, target_ulong addr) +{ + cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_LOAD, GETPC()); +} + +void helper_unaligned_st(CPUArchState *env, target_ulong addr) +{ + cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_STORE, GETPC()); +} + static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type) { --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273513102475.9428456067152; Thu, 14 Oct 2021 21:51:53 -0700 (PDT) Received: from localhost ([::1]:39592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFCC-0002XE-4Q for importer@patchew.org; Fri, 15 Oct 2021 00:51:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcJ-00070N-Nj for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:49 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:34744) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcH-0002yj-6s for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:47 -0400 Received: by mail-pj1-x102a.google.com with SMTP id q2-20020a17090a2e0200b001a0fd4efd49so2155715pjd.1 for ; Thu, 14 Oct 2021 21:14:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9im4CvhbPoyQ1RG+uvEuwMG0n0qsYjZQphEGRSBJSzY=; b=EThQgfXVM3+gTYBP9riZDdoy7+261/jK33Yl47MmSU3iZ5wuNAQhHQ1LyE8ousV8iH 1AjrG+9rCqBtcryjB1w0B3O6wHWejaW2rlvS0pKjP8jr/WtTvMkugxPr3sADthjBjCls B4ylcrg9BnnlXZyZyvOQ4ZuWnlsZD866jOv1Y0T4cIjsvQqpTfDpz1WlDaN6GO1QKQTl uG+4Xh+32n+YeUZzBDfzEruvVQrqnrnCVEgay2gso4Udk86qLTQCkQj3yvbx1W5MoLbX +3ru5fDt7DSamH5Dv/fbh3xeIkL1nGYBROkdt0DdZULC1rI4TjQ67w5USrW/awd7kEHA iTsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9im4CvhbPoyQ1RG+uvEuwMG0n0qsYjZQphEGRSBJSzY=; b=JTPMjfef1fVec1BRQ+Ts+J3knvehYXY6rgpYnY1V6n47PgLlKmV5gh7ArkyaUH+E5V jqUnXv643pNih2ywG8YNmfRcovP5DcLUaPAAtU9S8dOREzLcSLPj4jZrUY4hnEqPVLzK 87XfDUwpbu185/3Yu+u5N66ERSYYtffZpLBsQ6b+k9zL9qWqH0Jn0fy7LMIRJdO5iayu be78/E/FhxBhHbQquoT4jj3egUnXAe5ryc2E1YA26r/yLTNTzp2RLiIg6S0arVZFyuVV AwcQH9uiu1N4b7lEhnpSEccaD/oNM3tzK1rHluUpKQnPe/jb2eqJbosWA0X4V+IrOa/2 lLUQ== X-Gm-Message-State: AOAM531lmD+tS54dJsEk7mmuNbydDx1TuIZyfF6YietG7oNCIMUXM/FX peWzqG7Ns3LiOkf43VTjCpbcPM1DWTrnog== X-Google-Smtp-Source: ABdhPJxsxOFbWni+7leUobr/WdP9cvIIZATWUyzaX2hApjBgtAqbVRRhN/L5AJC2xRFa2ep7PzHHoA== X-Received: by 2002:a17:90a:1507:: with SMTP id l7mr10750149pja.141.1634271282818; Thu, 14 Oct 2021 21:14:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 61/67] linux-user: Handle BUS_ADRALN in host_signal_handler Date: Thu, 14 Oct 2021 21:10:47 -0700 Message-Id: <20211015041053.2769193-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273515137100001 Content-Type: text/plain; charset="utf-8" Handle BUS_ADRALN via cpu_loop_exit_sigbus, but allow other SIGBUS si_codes to continue into the host-to-guest signal coversion code. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- linux-user/signal.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/signal.c b/linux-user/signal.c index df2c8678d0..81c45bfce9 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -860,6 +860,9 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc= ); } else { sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + if (info->si_code =3D=3D BUS_ADRALN) { + cpu_loop_exit_sigbus(cpu, guest_addr, access_type, pc); + } } =20 sync_sig =3D true; --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634274083156882.8576360386141; Thu, 14 Oct 2021 22:01:23 -0700 (PDT) Received: from localhost ([::1]:59338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFLN-0007Lc-V8 for importer@patchew.org; Fri, 15 Oct 2021 01:01:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcN-00077S-TY for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:52 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:51043) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcH-0002zo-5h for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:51 -0400 Received: by mail-pj1-x102b.google.com with SMTP id gn3so811314pjb.0 for ; Thu, 14 Oct 2021 21:14:44 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mnqEEgywou2/cA2oB9Is2HfT4xL6ufMEEmIOEI3fkHA=; b=rOXSZWqbdk+BM7eSytOFj5w9whUkaOULo5cQIcz395fdhbcpNl4tU5rEA4laPsLvT0 NIVRgxeHU1EkB3RG/iE7F0q6LWioG3flXOIIde95ZSpOZGg9/V5whOhWanf6cGMHy1to G1rNtp7T2MHUUinvD7T/TL3j0iqmaPdqL3FROWp1FgRaqn9zTJkSOBZBGyoipSitz9ev CDIps/TiENbbpei0lqVSjAVlWyKCZKFs4d35vwicMr/JHMWVkegqFwMvGJksgKAqPko4 reIUSNY0CkYn2ANWRos6wMHiRV+2GnLQT7M1tOFn6PZBN6qImGNG79yhwyQ8A3smb/b0 UTrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mnqEEgywou2/cA2oB9Is2HfT4xL6ufMEEmIOEI3fkHA=; b=ubZcnPCQMg5vKWlOvAqNxbkDG/Gm9FFyJxneC7t48EXt6ylutoYwJm0tRBb/hX5sGR zr1nOOjbQ0UBnaFRtVNmuA6A7yC5tweqZqe5dw4LY5LbAouvBvtZdaEasiN3R7J1O7lM kKfvNIjnLh8Uov14OLV2athl81Dvq9bUGgF25mdEDpj/mFjTvwOWdy60/xh8SNIGPDho B3xmMSt93HJ7mlHMXG1l4idk7i74VWNK3vOz8EXz+KqQ5Gw7iVoBJNkOG3d9uRmx0mBY Zba89BhS41OsPgYvvdA/D9FmEUSbn6ESXMSjmP4CBye7J33FlSGalgGcS3DLNVJ/S37v LL9Q== X-Gm-Message-State: AOAM530fOTRwTkU6aI6csmh33S9cXM0uDiHKo0/OpXDjoWkMFFMY3dFc nVvo9xiNVNTM4otAfUuARnPpvgfs6BS4/w== X-Google-Smtp-Source: ABdhPJxFQGOr/dCJTQIMIJK8ra/8f+A0bH2tRc4ghRB4qRkrJOrmoUbnrZ0aP1I7AyTX5ofUGBU0ow== X-Received: by 2002:a17:90a:e7c8:: with SMTP id kb8mr10708596pjb.95.1634271283741; Thu, 14 Oct 2021 21:14:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 62/67] linux-user: Split out do_prctl and subroutines Date: Thu, 14 Oct 2021 21:10:48 -0700 Message-Id: <20211015041053.2769193-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634274083813100005 Content-Type: text/plain; charset="utf-8" Since the prctl constants are supposed to be generic, supply any that are not provided by the host. Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE, PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR_SET_TAGGED_ADDR_CTRL, PR_GET_TAGGED_ADDR_CTRL. Return EINVAL for guests that do not support these options rather than pass them on to the host. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 160 ++++++++++ linux-user/aarch64/target_syscall.h | 23 -- linux-user/alpha/target_prctl.h | 1 + linux-user/arm/target_prctl.h | 1 + linux-user/cris/target_prctl.h | 1 + linux-user/hexagon/target_prctl.h | 1 + linux-user/hppa/target_prctl.h | 1 + linux-user/i386/target_prctl.h | 1 + linux-user/m68k/target_prctl.h | 1 + linux-user/microblaze/target_prctl.h | 1 + linux-user/mips/target_prctl.h | 88 ++++++ linux-user/mips/target_syscall.h | 6 - linux-user/mips64/target_prctl.h | 1 + linux-user/mips64/target_syscall.h | 6 - linux-user/nios2/target_prctl.h | 1 + linux-user/openrisc/target_prctl.h | 1 + linux-user/ppc/target_prctl.h | 1 + linux-user/riscv/target_prctl.h | 1 + linux-user/s390x/target_prctl.h | 1 + linux-user/sh4/target_prctl.h | 1 + linux-user/sparc/target_prctl.h | 1 + linux-user/x86_64/target_prctl.h | 1 + linux-user/xtensa/target_prctl.h | 1 + linux-user/syscall.c | 433 +++++++++------------------ 24 files changed, 414 insertions(+), 320 deletions(-) create mode 100644 linux-user/aarch64/target_prctl.h create mode 100644 linux-user/alpha/target_prctl.h create mode 100644 linux-user/arm/target_prctl.h create mode 100644 linux-user/cris/target_prctl.h create mode 100644 linux-user/hexagon/target_prctl.h create mode 100644 linux-user/hppa/target_prctl.h create mode 100644 linux-user/i386/target_prctl.h create mode 100644 linux-user/m68k/target_prctl.h create mode 100644 linux-user/microblaze/target_prctl.h create mode 100644 linux-user/mips/target_prctl.h create mode 100644 linux-user/mips64/target_prctl.h create mode 100644 linux-user/nios2/target_prctl.h create mode 100644 linux-user/openrisc/target_prctl.h create mode 100644 linux-user/ppc/target_prctl.h create mode 100644 linux-user/riscv/target_prctl.h create mode 100644 linux-user/s390x/target_prctl.h create mode 100644 linux-user/sh4/target_prctl.h create mode 100644 linux-user/sparc/target_prctl.h create mode 100644 linux-user/x86_64/target_prctl.h create mode 100644 linux-user/xtensa/target_prctl.h diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_= prctl.h new file mode 100644 index 0000000000..3f5a5d3933 --- /dev/null +++ b/linux-user/aarch64/target_prctl.h @@ -0,0 +1,160 @@ +/* + * AArch64 specific prctl functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef AARCH64_TARGET_PRCTL_H +#define AARCH64_TARGET_PRCTL_H + +static abi_long do_prctl_get_vl(CPUArchState *env) +{ + ARMCPU *cpu =3D env_archcpu(env); + if (cpu_isar_feature(aa64_sve, cpu)) { + return ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_get_vl do_prctl_get_vl + +static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) +{ + /* + * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT. + * Note the kernel definition of sve_vl_valid allows for VQ=3D512, + * i.e. VL=3D8192, even though the current architectural maximum is VQ= =3D16. + */ + if (cpu_isar_feature(aa64_sve, env_archcpu(env)) + && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { + ARMCPU *cpu =3D env_archcpu(env); + uint32_t vq, old_vq; + + old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; + vq =3D MAX(arg2 / 16, 1); + vq =3D MIN(vq, cpu->sve_max_vq); + + if (vq < old_vq) { + aarch64_sve_narrow_vq(env, vq); + } + env->vfp.zcr_el[1] =3D vq - 1; + arm_rebuild_hflags(env); + return vq * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_set_vl do_prctl_set_vl + +static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) +{ + ARMCPU *cpu =3D env_archcpu(env); + + if (cpu_isar_feature(aa64_pauth, cpu)) { + int all =3D (PR_PAC_APIAKEY | PR_PAC_APIBKEY | + PR_PAC_APDAKEY | PR_PAC_APDBKEY | PR_PAC_APGAKEY); + int ret =3D 0; + Error *err =3D NULL; + + if (arg2 =3D=3D 0) { + arg2 =3D all; + } else if (arg2 & ~all) { + return -TARGET_EINVAL; + } + if (arg2 & PR_PAC_APIAKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apia, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APIBKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apib, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APDAKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apda, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APDBKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apdb, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APGAKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apga, + sizeof(ARMPACKey), &err); + } + if (ret !=3D 0) { + /* + * Some unknown failure in the crypto. The best + * we can do is log it and fail the syscall. + * The real syscall cannot fail this way. + */ + qemu_log_mask(LOG_UNIMP, "PR_PAC_RESET_KEYS: Crypto failure: %= s", + error_get_pretty(err)); + error_free(err); + return -TARGET_EIO; + } + return 0; + } + return -TARGET_EINVAL; +} +#define do_prctl_reset_keys do_prctl_reset_keys + +static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long = arg2) +{ + abi_ulong valid_mask =3D PR_TAGGED_ADDR_ENABLE; + ARMCPU *cpu =3D env_archcpu(env); + + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |=3D PR_MTE_TCF_MASK; + valid_mask |=3D PR_MTE_TAG_MASK; + } + + if (arg2 & ~valid_mask) { + return -TARGET_EINVAL; + } + env->tagged_addr_enable =3D arg2 & PR_TAGGED_ADDR_ENABLE; + + if (cpu_isar_feature(aa64_mte, cpu)) { + switch (arg2 & PR_MTE_TCF_MASK) { + case PR_MTE_TCF_NONE: + case PR_MTE_TCF_SYNC: + case PR_MTE_TCF_ASYNC: + break; + default: + return -EINVAL; + } + + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * Note that the syscall values are consistent with hw. + */ + env->cp15.sctlr_el[1] =3D + deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHI= FT); + + /* + * Write PR_MTE_TAG to GCR_EL1[Exclude]. + * Note that the syscall uses an include mask, + * and hardware uses an exclude mask -- invert. + */ + env->cp15.gcr_el1 =3D + deposit64(env->cp15.gcr_el1, 0, 16, ~arg2 >> PR_MTE_TAG_SHIFT); + arm_rebuild_hflags(env); + } + return 0; +} +#define do_prctl_set_tagged_addr_ctrl do_prctl_set_tagged_addr_ctrl + +static abi_long do_prctl_get_tagged_addr_ctrl(CPUArchState *env) +{ + ARMCPU *cpu =3D env_archcpu(env); + abi_long ret =3D 0; + + if (env->tagged_addr_enable) { + ret |=3D PR_TAGGED_ADDR_ENABLE; + } + if (cpu_isar_feature(aa64_mte, cpu)) { + /* See do_prctl_set_tagged_addr_ctrl. */ + ret |=3D extract64(env->cp15.sctlr_el[1], 38, 2) << PR_MTE_TCF_SHI= FT; + ret =3D deposit64(ret, PR_MTE_TAG_SHIFT, 16, ~env->cp15.gcr_el1); + } + return ret; +} +#define do_prctl_get_tagged_addr_ctrl do_prctl_get_tagged_addr_ctrl + +#endif /* AARCH64_TARGET_PRCTL_H */ diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/targe= t_syscall.h index 76f6c3391d..819f112ab0 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -20,27 +20,4 @@ struct target_pt_regs { #define TARGET_MCL_FUTURE 2 #define TARGET_MCL_ONFAULT 4 =20 -#define TARGET_PR_SVE_SET_VL 50 -#define TARGET_PR_SVE_GET_VL 51 - -#define TARGET_PR_PAC_RESET_KEYS 54 -# define TARGET_PR_PAC_APIAKEY (1 << 0) -# define TARGET_PR_PAC_APIBKEY (1 << 1) -# define TARGET_PR_PAC_APDAKEY (1 << 2) -# define TARGET_PR_PAC_APDBKEY (1 << 3) -# define TARGET_PR_PAC_APGAKEY (1 << 4) - -#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 -#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 -# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) -/* MTE tag check fault modes */ -# define TARGET_PR_MTE_TCF_SHIFT 1 -# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) -/* MTE tag inclusion mask */ -# define TARGET_PR_MTE_TAG_SHIFT 3 -# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIF= T) - #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prct= l.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/alpha/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/arm/target_prctl.h b/linux-user/arm/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/arm/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/cris/target_prctl.h b/linux-user/cris/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/cris/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/hexagon/target_prctl.h b/linux-user/hexagon/target_= prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/hexagon/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/hppa/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/i386/target_prctl.h b/linux-user/i386/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/i386/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/m68k/target_prctl.h b/linux-user/m68k/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/m68k/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/microblaze/target_prctl.h b/linux-user/microblaze/t= arget_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/microblaze/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/mips/target_prctl.h b/linux-user/mips/target_prctl.h new file mode 100644 index 0000000000..e028333db9 --- /dev/null +++ b/linux-user/mips/target_prctl.h @@ -0,0 +1,88 @@ +/* + * MIPS specific prctl functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef MIPS_TARGET_PRCTL_H +#define MIPS_TARGET_PRCTL_H + +static abi_long do_prctl_get_fp_mode(CPUArchState *env) +{ + abi_long ret =3D 0; + + if (env->CP0_Status & (1 << CP0St_FR)) { + ret |=3D PR_FP_MODE_FR; + } + if (env->CP0_Config5 & (1 << CP0C5_FRE)) { + ret |=3D PR_FP_MODE_FRE; + } + return ret; +} +#define do_prctl_get_fp_mode do_prctl_get_fp_mode + +static abi_long do_prctl_set_fp_mode(CPUArchState *env, abi_long arg2) +{ + bool old_fr =3D env->CP0_Status & (1 << CP0St_FR); + bool old_fre =3D env->CP0_Config5 & (1 << CP0C5_FRE); + bool new_fr =3D arg2 & PR_FP_MODE_FR; + bool new_fre =3D arg2 & PR_FP_MODE_FRE; + const unsigned int known_bits =3D PR_FP_MODE_FR | PR_FP_MODE_FRE; + + /* If nothing to change, return right away, successfully. */ + if (old_fr =3D=3D new_fr && old_fre =3D=3D new_fre) { + return 0; + } + /* Check the value is valid */ + if (arg2 & ~known_bits) { + return -TARGET_EOPNOTSUPP; + } + /* Setting FRE without FR is not supported. */ + if (new_fre && !new_fr) { + return -TARGET_EOPNOTSUPP; + } + if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* FR1 is not supported */ + return -TARGET_EOPNOTSUPP; + } + if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) + && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { + /* cannot set FR=3D0 */ + return -TARGET_EOPNOTSUPP; + } + if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { + /* Cannot set FRE=3D1 */ + return -TARGET_EOPNOTSUPP; + } + + int i; + fpr_t *fpr =3D env->active_fpu.fpr; + for (i =3D 0; i < 32 ; i +=3D 2) { + if (!old_fr && new_fr) { + fpr[i].w[!FP_ENDIAN_IDX] =3D fpr[i + 1].w[FP_ENDIAN_IDX]; + } else if (old_fr && !new_fr) { + fpr[i + 1].w[FP_ENDIAN_IDX] =3D fpr[i].w[!FP_ENDIAN_IDX]; + } + } + + if (new_fr) { + env->CP0_Status |=3D (1 << CP0St_FR); + env->hflags |=3D MIPS_HFLAG_F64; + } else { + env->CP0_Status &=3D ~(1 << CP0St_FR); + env->hflags &=3D ~MIPS_HFLAG_F64; + } + if (new_fre) { + env->CP0_Config5 |=3D (1 << CP0C5_FRE); + if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { + env->hflags |=3D MIPS_HFLAG_FRE; + } + } else { + env->CP0_Config5 &=3D ~(1 << CP0C5_FRE); + env->hflags &=3D ~MIPS_HFLAG_FRE; + } + + return 0; +} +#define do_prctl_set_fp_mode do_prctl_set_fp_mode + +#endif /* MIPS_TARGET_PRCTL_H */ diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_sysc= all.h index f59057493a..1ce0a5bbf4 100644 --- a/linux-user/mips/target_syscall.h +++ b/linux-user/mips/target_syscall.h @@ -36,10 +36,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) return 0x40000; } =20 -/* MIPS-specific prctl() options */ -#define TARGET_PR_SET_FP_MODE 45 -#define TARGET_PR_GET_FP_MODE 46 -#define TARGET_PR_FP_MODE_FR (1 << 0) -#define TARGET_PR_FP_MODE_FRE (1 << 1) - #endif /* MIPS_TARGET_SYSCALL_H */ diff --git a/linux-user/mips64/target_prctl.h b/linux-user/mips64/target_pr= ctl.h new file mode 100644 index 0000000000..18da9ae619 --- /dev/null +++ b/linux-user/mips64/target_prctl.h @@ -0,0 +1 @@ +#include "../mips/target_prctl.h" diff --git a/linux-user/mips64/target_syscall.h b/linux-user/mips64/target_= syscall.h index cd1e1b4969..74f12365bc 100644 --- a/linux-user/mips64/target_syscall.h +++ b/linux-user/mips64/target_syscall.h @@ -33,10 +33,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) return 0x40000; } =20 -/* MIPS-specific prctl() options */ -#define TARGET_PR_SET_FP_MODE 45 -#define TARGET_PR_GET_FP_MODE 46 -#define TARGET_PR_FP_MODE_FR (1 << 0) -#define TARGET_PR_FP_MODE_FRE (1 << 1) - #endif /* MIPS64_TARGET_SYSCALL_H */ diff --git a/linux-user/nios2/target_prctl.h b/linux-user/nios2/target_prct= l.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/nios2/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/openrisc/target_prctl.h b/linux-user/openrisc/targe= t_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/openrisc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/ppc/target_prctl.h b/linux-user/ppc/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/ppc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/riscv/target_prctl.h b/linux-user/riscv/target_prct= l.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/riscv/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/s390x/target_prctl.h b/linux-user/s390x/target_prct= l.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/s390x/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/sh4/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/sparc/target_prctl.h b/linux-user/sparc/target_prct= l.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/sparc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/x86_64/target_prctl.h b/linux-user/x86_64/target_pr= ctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/x86_64/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/xtensa/target_prctl.h b/linux-user/xtensa/target_pr= ctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/xtensa/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 544f5b662f..a417396981 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6291,9 +6291,155 @@ abi_long do_arch_prctl(CPUX86State *env, int code, = abi_ulong addr) return ret; } #endif /* defined(TARGET_ABI32 */ - #endif /* defined(TARGET_I386) */ =20 +/* + * These constants are generic. Supply any that are missing from the host. + */ +#ifndef PR_SET_NAME +# define PR_SET_NAME 15 +# define PR_GET_NAME 16 +#endif +#ifndef PR_SET_FP_MODE +# define PR_SET_FP_MODE 45 +# define PR_GET_FP_MODE 46 +# define PR_FP_MODE_FR (1 << 0) +# define PR_FP_MODE_FRE (1 << 1) +#endif +#ifndef PR_SVE_SET_VL +# define PR_SVE_SET_VL 50 +# define PR_SVE_GET_VL 51 +# define PR_SVE_VL_LEN_MASK 0xffff +# define PR_SVE_VL_INHERIT (1 << 17) +#endif +#ifndef PR_PAC_RESET_KEYS +# define PR_PAC_RESET_KEYS 54 +# define PR_PAC_APIAKEY (1 << 0) +# define PR_PAC_APIBKEY (1 << 1) +# define PR_PAC_APDAKEY (1 << 2) +# define PR_PAC_APDBKEY (1 << 3) +# define PR_PAC_APGAKEY (1 << 4) +#endif +#ifndef PR_SET_TAGGED_ADDR_CTRL +# define PR_SET_TAGGED_ADDR_CTRL 55 +# define PR_GET_TAGGED_ADDR_CTRL 56 +# define PR_TAGGED_ADDR_ENABLE (1UL << 0) +#endif +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) +#endif + +#include "target_prctl.h" + +static abi_long do_prctl_inval0(CPUArchState *env) +{ + return -TARGET_EINVAL; +} + +static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) +{ + return -TARGET_EINVAL; +} + +#ifndef do_prctl_get_fp_mode +#define do_prctl_get_fp_mode do_prctl_inval0 +#endif +#ifndef do_prctl_set_fp_mode +#define do_prctl_set_fp_mode do_prctl_inval1 +#endif +#ifndef do_prctl_get_vl +#define do_prctl_get_vl do_prctl_inval0 +#endif +#ifndef do_prctl_set_vl +#define do_prctl_set_vl do_prctl_inval1 +#endif +#ifndef do_prctl_reset_keys +#define do_prctl_reset_keys do_prctl_inval1 +#endif +#ifndef do_prctl_set_tagged_addr_ctrl +#define do_prctl_set_tagged_addr_ctrl do_prctl_inval1 +#endif +#ifndef do_prctl_get_tagged_addr_ctrl +#define do_prctl_get_tagged_addr_ctrl do_prctl_inval0 +#endif + +static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, + abi_long arg3, abi_long arg4, abi_long arg5) +{ + abi_long ret; + + switch (option) { + case PR_GET_PDEATHSIG: + { + int deathsig; + ret =3D get_errno(prctl(PR_GET_PDEATHSIG, &deathsig, + arg3, arg4, arg5)); + if (!is_error(ret) && arg2 && put_user_s32(deathsig, arg2)) { + return -TARGET_EFAULT; + } + return ret; + } + case PR_GET_NAME: + { + void *name =3D lock_user(VERIFY_WRITE, arg2, 16, 1); + if (!name) { + return -TARGET_EFAULT; + } + ret =3D get_errno(prctl(PR_GET_NAME, (uintptr_t)name, + arg3, arg4, arg5)); + unlock_user(name, arg2, 16); + return ret; + } + case PR_SET_NAME: + { + void *name =3D lock_user(VERIFY_READ, arg2, 16, 1); + if (!name) { + return -TARGET_EFAULT; + } + ret =3D get_errno(prctl(PR_SET_NAME, (uintptr_t)name, + arg3, arg4, arg5)); + unlock_user(name, arg2, 0); + return ret; + } + case PR_GET_FP_MODE: + return do_prctl_get_fp_mode(env); + case PR_SET_FP_MODE: + return do_prctl_set_fp_mode(env, arg2); + case PR_SVE_GET_VL: + return do_prctl_get_vl(env); + case PR_SVE_SET_VL: + return do_prctl_set_vl(env, arg2); + case PR_PAC_RESET_KEYS: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_reset_keys(env, arg2); + case PR_SET_TAGGED_ADDR_CTRL: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_set_tagged_addr_ctrl(env, arg2); + case PR_GET_TAGGED_ADDR_CTRL: + if (arg2 || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_get_tagged_addr_ctrl(env); + case PR_GET_SECCOMP: + case PR_SET_SECCOMP: + /* Disable seccomp to prevent the target disabling syscalls we nee= d. */ + return -TARGET_EINVAL; + default: + /* Most prctl options have no pointer arguments */ + return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + } +} + #define NEW_STACK_SIZE 0x40000 =20 =20 @@ -10630,290 +10776,7 @@ static abi_long do_syscall1(void *cpu_env, int nu= m, abi_long arg1, return ret; #endif case TARGET_NR_prctl: - switch (arg1) { - case PR_GET_PDEATHSIG: - { - int deathsig; - ret =3D get_errno(prctl(arg1, &deathsig, arg3, arg4, arg5)); - if (!is_error(ret) && arg2 - && put_user_s32(deathsig, arg2)) { - return -TARGET_EFAULT; - } - return ret; - } -#ifdef PR_GET_NAME - case PR_GET_NAME: - { - void *name =3D lock_user(VERIFY_WRITE, arg2, 16, 1); - if (!name) { - return -TARGET_EFAULT; - } - ret =3D get_errno(prctl(arg1, (unsigned long)name, - arg3, arg4, arg5)); - unlock_user(name, arg2, 16); - return ret; - } - case PR_SET_NAME: - { - void *name =3D lock_user(VERIFY_READ, arg2, 16, 1); - if (!name) { - return -TARGET_EFAULT; - } - ret =3D get_errno(prctl(arg1, (unsigned long)name, - arg3, arg4, arg5)); - unlock_user(name, arg2, 0); - return ret; - } -#endif -#ifdef TARGET_MIPS - case TARGET_PR_GET_FP_MODE: - { - CPUMIPSState *env =3D ((CPUMIPSState *)cpu_env); - ret =3D 0; - if (env->CP0_Status & (1 << CP0St_FR)) { - ret |=3D TARGET_PR_FP_MODE_FR; - } - if (env->CP0_Config5 & (1 << CP0C5_FRE)) { - ret |=3D TARGET_PR_FP_MODE_FRE; - } - return ret; - } - case TARGET_PR_SET_FP_MODE: - { - CPUMIPSState *env =3D ((CPUMIPSState *)cpu_env); - bool old_fr =3D env->CP0_Status & (1 << CP0St_FR); - bool old_fre =3D env->CP0_Config5 & (1 << CP0C5_FRE); - bool new_fr =3D arg2 & TARGET_PR_FP_MODE_FR; - bool new_fre =3D arg2 & TARGET_PR_FP_MODE_FRE; - - const unsigned int known_bits =3D TARGET_PR_FP_MODE_FR | - TARGET_PR_FP_MODE_FRE; - - /* If nothing to change, return right away, successfully. */ - if (old_fr =3D=3D new_fr && old_fre =3D=3D new_fre) { - return 0; - } - /* Check the value is valid */ - if (arg2 & ~known_bits) { - return -TARGET_EOPNOTSUPP; - } - /* Setting FRE without FR is not supported. */ - if (new_fre && !new_fr) { - return -TARGET_EOPNOTSUPP; - } - if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { - /* FR1 is not supported */ - return -TARGET_EOPNOTSUPP; - } - if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) - && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { - /* cannot set FR=3D0 */ - return -TARGET_EOPNOTSUPP; - } - if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { - /* Cannot set FRE=3D1 */ - return -TARGET_EOPNOTSUPP; - } - - int i; - fpr_t *fpr =3D env->active_fpu.fpr; - for (i =3D 0; i < 32 ; i +=3D 2) { - if (!old_fr && new_fr) { - fpr[i].w[!FP_ENDIAN_IDX] =3D fpr[i + 1].w[FP_ENDIAN_ID= X]; - } else if (old_fr && !new_fr) { - fpr[i + 1].w[FP_ENDIAN_IDX] =3D fpr[i].w[!FP_ENDIAN_ID= X]; - } - } - - if (new_fr) { - env->CP0_Status |=3D (1 << CP0St_FR); - env->hflags |=3D MIPS_HFLAG_F64; - } else { - env->CP0_Status &=3D ~(1 << CP0St_FR); - env->hflags &=3D ~MIPS_HFLAG_F64; - } - if (new_fre) { - env->CP0_Config5 |=3D (1 << CP0C5_FRE); - if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { - env->hflags |=3D MIPS_HFLAG_FRE; - } - } else { - env->CP0_Config5 &=3D ~(1 << CP0C5_FRE); - env->hflags &=3D ~MIPS_HFLAG_FRE; - } - - return 0; - } -#endif /* MIPS */ -#ifdef TARGET_AARCH64 - case TARGET_PR_SVE_SET_VL: - /* - * We cannot support either PR_SVE_SET_VL_ONEXEC or - * PR_SVE_VL_INHERIT. Note the kernel definition - * of sve_vl_valid allows for VQ=3D512, i.e. VL=3D8192, - * even though the current architectural maximum is VQ=3D16. - */ - ret =3D -TARGET_EINVAL; - if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env)) - && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { - CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D env_archcpu(env); - uint32_t vq, old_vq; - - old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; - vq =3D MAX(arg2 / 16, 1); - vq =3D MIN(vq, cpu->sve_max_vq); - - if (vq < old_vq) { - aarch64_sve_narrow_vq(env, vq); - } - env->vfp.zcr_el[1] =3D vq - 1; - arm_rebuild_hflags(env); - ret =3D vq * 16; - } - return ret; - case TARGET_PR_SVE_GET_VL: - ret =3D -TARGET_EINVAL; - { - ARMCPU *cpu =3D env_archcpu(cpu_env); - if (cpu_isar_feature(aa64_sve, cpu)) { - ret =3D ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; - } - } - return ret; - case TARGET_PR_PAC_RESET_KEYS: - { - CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D env_archcpu(env); - - if (arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - int all =3D (TARGET_PR_PAC_APIAKEY | TARGET_PR_PAC_API= BKEY | - TARGET_PR_PAC_APDAKEY | TARGET_PR_PAC_APDBK= EY | - TARGET_PR_PAC_APGAKEY); - int ret =3D 0; - Error *err =3D NULL; - - if (arg2 =3D=3D 0) { - arg2 =3D all; - } else if (arg2 & ~all) { - return -TARGET_EINVAL; - } - if (arg2 & TARGET_PR_PAC_APIAKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apia, - sizeof(ARMPACKey), &er= r); - } - if (arg2 & TARGET_PR_PAC_APIBKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apib, - sizeof(ARMPACKey), &er= r); - } - if (arg2 & TARGET_PR_PAC_APDAKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apda, - sizeof(ARMPACKey), &er= r); - } - if (arg2 & TARGET_PR_PAC_APDBKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apdb, - sizeof(ARMPACKey), &er= r); - } - if (arg2 & TARGET_PR_PAC_APGAKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apga, - sizeof(ARMPACKey), &er= r); - } - if (ret !=3D 0) { - /* - * Some unknown failure in the crypto. The best - * we can do is log it and fail the syscall. - * The real syscall cannot fail this way. - */ - qemu_log_mask(LOG_UNIMP, - "PR_PAC_RESET_KEYS: Crypto failure: = %s", - error_get_pretty(err)); - error_free(err); - return -TARGET_EIO; - } - return 0; - } - } - return -TARGET_EINVAL; - case TARGET_PR_SET_TAGGED_ADDR_CTRL: - { - abi_ulong valid_mask =3D TARGET_PR_TAGGED_ADDR_ENABLE; - CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D env_archcpu(env); - - if (cpu_isar_feature(aa64_mte, cpu)) { - valid_mask |=3D TARGET_PR_MTE_TCF_MASK; - valid_mask |=3D TARGET_PR_MTE_TAG_MASK; - } - - if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - env->tagged_addr_enable =3D arg2 & TARGET_PR_TAGGED_ADDR_E= NABLE; - - if (cpu_isar_feature(aa64_mte, cpu)) { - switch (arg2 & TARGET_PR_MTE_TCF_MASK) { - case TARGET_PR_MTE_TCF_NONE: - case TARGET_PR_MTE_TCF_SYNC: - case TARGET_PR_MTE_TCF_ASYNC: - break; - default: - return -EINVAL; - } - - /* - * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. - * Note that the syscall values are consistent with hw. - */ - env->cp15.sctlr_el[1] =3D - deposit64(env->cp15.sctlr_el[1], 38, 2, - arg2 >> TARGET_PR_MTE_TCF_SHIFT); - - /* - * Write PR_MTE_TAG to GCR_EL1[Exclude]. - * Note that the syscall uses an include mask, - * and hardware uses an exclude mask -- invert. - */ - env->cp15.gcr_el1 =3D - deposit64(env->cp15.gcr_el1, 0, 16, - ~arg2 >> TARGET_PR_MTE_TAG_SHIFT); - arm_rebuild_hflags(env); - } - return 0; - } - case TARGET_PR_GET_TAGGED_ADDR_CTRL: - { - abi_long ret =3D 0; - CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D env_archcpu(env); - - if (arg2 || arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - if (env->tagged_addr_enable) { - ret |=3D TARGET_PR_TAGGED_ADDR_ENABLE; - } - if (cpu_isar_feature(aa64_mte, cpu)) { - /* See above. */ - ret |=3D (extract64(env->cp15.sctlr_el[1], 38, 2) - << TARGET_PR_MTE_TCF_SHIFT); - ret =3D deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16, - ~env->cp15.gcr_el1); - } - return ret; - } -#endif /* AARCH64 */ - case PR_GET_SECCOMP: - case PR_SET_SECCOMP: - /* Disable seccomp to prevent the target disabling syscalls we - * need. */ - return -TARGET_EINVAL; - default: - /* Most prctl options have no pointer arguments */ - return get_errno(prctl(arg1, arg2, arg3, arg4, arg5)); - } + return do_prctl(cpu_env, arg1, arg2, arg3, arg4, arg5); break; #ifdef TARGET_NR_arch_prctl case TARGET_NR_arch_prctl: --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273685107119.4775520405326; Thu, 14 Oct 2021 21:54:45 -0700 (PDT) Received: from localhost ([::1]:45756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFEy-0006dc-2X for importer@patchew.org; Fri, 15 Oct 2021 00:54:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcJ-00070P-T1 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:49 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:45904) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcI-00030d-2S for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:47 -0400 Received: by mail-pf1-x42c.google.com with SMTP id f11so3410927pfc.12 for ; Thu, 14 Oct 2021 21:14:45 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OxMgM7wzD4BcAcUx2qJmodE4BwJ9QwGNSAt09qoFyFU=; b=n2oEhFHE1FfC+NGrQFPyUFWLxN7nZbYmgUcOZZXMymDYfFnaE6FG98C8jxVGAVAb/n r1niXz3J9VA8S2nYLT+fA8trxPYESN4A0Un874SfVpqHg7AIKpnoYjMmLENVKLa1qZCw Cxa8mXZvQQCBdA7K/SDZkZfsdN6KV+4FjzvLQr0+/Ifg09Sr8fLGI5YQQbemE4ZVlj2u 2W9/z4NaU+Bl1gXhrsGh4bu0c+fmR2V91e6y3qceyS9vjKeF5v+RHhupR1rWqu6IQ2rC WvA5FaNT6zY7+pLWlSEXPAYrq/XPLECr8v/EsnXuVx+VGRa9/rR/qylSHAIGTM81MmMN l6aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OxMgM7wzD4BcAcUx2qJmodE4BwJ9QwGNSAt09qoFyFU=; b=C3g0YuyKDQ+6B7EQ+pO/QmIt4LglhoT7DrivFnUyQUMmSf2BnhvvsZ941BqfE9XC6o tUsELF3Cb0lkwMrtkTWzxXuXVfXYvK4178FysZNHYDq3U3tTf6LYyZi6UrQ7rmjpKv3r IjUNOQZTQAD4f6c9CuqnlDUsLblUwCll5cNfdtA3M54j1eK8HLE0gOfwElxMr5P6Ddq1 ESkaI2dPhZ2TXxDz/sGffhprFG4FJUaNVqEQMKk0WTPyNpEdfJJCeh5PBKVEVSWKZiJO KHL1o+3jAcLY+K5vAnSj2UE4yG0jo7WLxeZ+ry9UXd/P1raHux65xXcGNEoSCis5Iyxe FEag== X-Gm-Message-State: AOAM531Udum5GvQZTGhQKqGlcvsT27jfJE6sdare3I3GqYkbTZ9KujhK +l+EnBwoEw7zXEt5geYr7Bwr4v5K6rfAAw== X-Google-Smtp-Source: ABdhPJzU5WyYM2wvrxYswB4YVz+8MpfLMk4k83W+vO8WZDLXvJZ3MuKEkp6U2EFWe6MfC5VeKgc2nw== X-Received: by 2002:a05:6a00:8d0:b0:44c:26e6:1c13 with SMTP id s16-20020a056a0008d000b0044c26e61c13mr9506973pfu.28.1634271284454; Thu, 14 Oct 2021 21:14:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 63/67] linux-user: Disable more prctl subcodes Date: Thu, 14 Oct 2021 21:10:49 -0700 Message-Id: <20211015041053.2769193-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273685910100001 Content-Type: text/plain; charset="utf-8" Create a list of subcodes that we want to pass on, a list of subcodes that should not be passed on because they would affect the running qemu itself, and a list that probably could be implemented but require extra work. Do not pass on unknown subcodes. Signed-off-by: Richard Henderson --- linux-user/syscall.c | 56 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 52 insertions(+), 4 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index a417396981..7635c2397a 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6334,6 +6334,13 @@ abi_long do_arch_prctl(CPUX86State *env, int code, a= bi_ulong addr) # define PR_MTE_TAG_SHIFT 3 # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) #endif +#ifndef PR_SET_IO_FLUSHER +# define PR_SET_IO_FLUSHER 57 +# define PR_GET_IO_FLUSHER 58 +#endif +#ifndef PR_SET_SYSCALL_USER_DISPATCH +# define PR_SET_SYSCALL_USER_DISPATCH 59 +#endif =20 #include "target_prctl.h" =20 @@ -6430,13 +6437,54 @@ static abi_long do_prctl(CPUArchState *env, abi_lon= g option, abi_long arg2, return -TARGET_EINVAL; } return do_prctl_get_tagged_addr_ctrl(env); + + case PR_GET_DUMPABLE: + case PR_SET_DUMPABLE: + case PR_GET_KEEPCAPS: + case PR_SET_KEEPCAPS: + case PR_GET_TIMING: + case PR_SET_TIMING: + case PR_GET_TIMERSLACK: + case PR_SET_TIMERSLACK: + case PR_MCE_KILL: + case PR_MCE_KILL_GET: + case PR_GET_NO_NEW_PRIVS: + case PR_SET_NO_NEW_PRIVS: + case PR_GET_IO_FLUSHER: + case PR_SET_IO_FLUSHER: + /* Some prctl options have no pointer arguments and we can pass on= . */ + return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + + case PR_GET_CHILD_SUBREAPER: + case PR_SET_CHILD_SUBREAPER: + case PR_GET_SPECULATION_CTRL: + case PR_SET_SPECULATION_CTRL: + case PR_GET_TID_ADDRESS: + /* TODO */ + return -TARGET_EINVAL; + + case PR_GET_FPEXC: + case PR_SET_FPEXC: + /* Was used for SPE on PowerPC. */ + return -TARGET_EINVAL; + + case PR_GET_ENDIAN: + case PR_SET_ENDIAN: + case PR_GET_FPEMU: + case PR_SET_FPEMU: + case PR_SET_MM: case PR_GET_SECCOMP: case PR_SET_SECCOMP: - /* Disable seccomp to prevent the target disabling syscalls we nee= d. */ - return -TARGET_EINVAL; + case PR_SET_SYSCALL_USER_DISPATCH: + case PR_GET_THP_DISABLE: + case PR_SET_THP_DISABLE: + case PR_GET_TSC: + case PR_SET_TSC: + case PR_GET_UNALIGN: + case PR_SET_UNALIGN: default: - /* Most prctl options have no pointer arguments */ - return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + /* Disable to prevent the target disabling stuff we need. */ + return -TARGET_EINVAL; } } =20 --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273433432235.489183262506; Thu, 14 Oct 2021 21:50:33 -0700 (PDT) Received: from localhost ([::1]:37208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFAu-0000pG-66 for importer@patchew.org; Fri, 15 Oct 2021 00:50:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcK-00070R-Hz for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:49 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:40699) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcI-00030m-Eu for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:48 -0400 Received: by mail-pl1-x62b.google.com with SMTP id v20so5597180plo.7 for ; Thu, 14 Oct 2021 21:14:45 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kgbxRfaLnXEAdarkY+uz+mGv9JnWFVB+tvkZlav9GvM=; b=aU/NZ9fb7fK43uXivA7vwfLR31Sy/r9Ewf2AEE1QITN2wKlQLndOwlSuw17Nx7ayGR 3kPIyUmKiztLN9QwOFBhGm50+MjL9IlsyzhgYOWkn+FM6Alwv4Kvl9UFteKbDM9AeCcq D1qvjT2anwmGiIEXMVcZ4KaV5AkkkkMVsmB7uz9Oqr081QTKuPse57tlORu3wYIsndyZ 47LDeGSYdSunbB2sagXgeYJAVfywrgQjbWe+mRB3Ojlu8OC4mLooCCLr+WetCAdZI8JK e7KF+cHbTyxjEeHVswB7JqCNTkyhl3tczwq+R3z8HKfCDUe+q4ZGFJHVVYBauwC2+DWX eB/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kgbxRfaLnXEAdarkY+uz+mGv9JnWFVB+tvkZlav9GvM=; b=PrOR5DMwM8Axo9spXFiMCJCNZVHs/JXD0XY7eTtvAJmY8VHaE3sVgnpEJRh6E8qJ6o AZApSbV9dntIHu1CU9RI5D38/o/AYNZVbaFH1xSz+01P0nbGaD4rKk4LnM1K+9JdLHUB bsO4Du0kU2+2HzdghRfzvT7ZwtGsarSo0VW07lWfpzB5JyqwjiJPa5VWPcyyja8xiUvt WjCddzBA4ahXYMYpdS15kTrGplXpqiPXQc481U1AQXV5RZR4xfSyfCwwh+o5FEesKtOf rS+r0oFlJCPaDTTnTgCkzHhoqbbwiA66EfL4t4a9IjI+sRiD3JFxJSMuaVEeYKmbdV0n oXHA== X-Gm-Message-State: AOAM530O6RfMiZZMMmab1gYlCWVHscY+QlpYCf/PWmh+nv6W8NLSiMvN tRMGvgrCkkLsj8VJWiYMaDiXUlj4IeKVew== X-Google-Smtp-Source: ABdhPJwtXBsVIOdXqz8VKa/eGDAoRm4+Kp05q7QrT0qZfnRbT0Wfj5xeDPKzXg6MhB10BP3FrTAkKw== X-Received: by 2002:a17:90b:388c:: with SMTP id mu12mr10977559pjb.146.1634271285073; Thu, 14 Oct 2021 21:14:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 64/67] linux-user: Add code for PR_GET/SET_UNALIGN Date: Thu, 14 Oct 2021 21:10:50 -0700 Message-Id: <20211015041053.2769193-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273435497100001 Content-Type: text/plain; charset="utf-8" This requires extra work for each target, but adds the common syscall code, and the necessary flag in CPUState. Signed-off-by: Richard Henderson Reviewed-by: Warner Losh --- include/hw/core/cpu.h | 3 +++ linux-user/generic/target_prctl_unalign.h | 27 +++++++++++++++++++++++ cpu.c | 20 ++++++++++++----- linux-user/syscall.c | 13 +++++++++-- 4 files changed, 56 insertions(+), 7 deletions(-) create mode 100644 linux-user/generic/target_prctl_unalign.h diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1a10497af3..6202bbf9c3 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -412,6 +412,9 @@ struct CPUState { =20 bool ignore_memory_transaction_failures; =20 + /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ + bool prctl_unalign_sigbus; + struct hax_vcpu_state *hax_vcpu; =20 struct hvf_vcpu_state *hvf; diff --git a/linux-user/generic/target_prctl_unalign.h b/linux-user/generic= /target_prctl_unalign.h new file mode 100644 index 0000000000..bc3b83af2a --- /dev/null +++ b/linux-user/generic/target_prctl_unalign.h @@ -0,0 +1,27 @@ +/* + * Generic prctl unalign functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef GENERIC_TARGET_PRCTL_UNALIGN_H +#define GENERIC_TARGET_PRCTL_UNALIGN_H + +static abi_long do_prctl_get_unalign(CPUArchState *env, target_long arg2) +{ + CPUState *cs =3D env_cpu(env); + uint32_t res =3D PR_UNALIGN_NOPRINT; + if (cs->prctl_unalign_sigbus) { + res |=3D PR_UNALIGN_SIGBUS; + } + return put_user_u32(res, arg2); +} +#define do_prctl_get_unalign do_prctl_get_unalign + +static abi_long do_prctl_set_unalign(CPUArchState *env, target_long arg2) +{ + env_cpu(env)->prctl_unalign_sigbus =3D arg2 & PR_UNALIGN_SIGBUS; + return 0; +} +#define do_prctl_set_unalign do_prctl_set_unalign + +#endif /* GENERIC_TARGET_PRCTL_UNALIGN_H */ diff --git a/cpu.c b/cpu.c index 9bce67ef55..9e388d9cd3 100644 --- a/cpu.c +++ b/cpu.c @@ -179,13 +179,23 @@ void cpu_exec_unrealizefn(CPUState *cpu) cpu_list_remove(cpu); } =20 +/* + * This can't go in hw/core/cpu.c because that file is compiled only + * once for both user-mode and system builds. + */ static Property cpu_common_props[] =3D { -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY /* - * Create a memory property for softmmu CPU object, - * so users can wire up its memory. (This can't go in hw/core/cpu.c - * because that file is compiled only once for both user-mode - * and system builds.) The default if no link is set up is to use + * Create a property for the user-only object, so users can + * adjust prctl(PR_SET_UNALIGN) from the command-line. + * Has no effect if the target does not support the feature. + */ + DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, + prctl_unalign_sigbus, false), +#else + /* + * Create a memory property for softmmu CPU object, so users can + * wire up its memory. The default if no link is set up is to use * the system address space. */ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 7635c2397a..ac3bc8a330 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6375,6 +6375,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, a= bi_long arg2) #ifndef do_prctl_get_tagged_addr_ctrl #define do_prctl_get_tagged_addr_ctrl do_prctl_inval0 #endif +#ifndef do_prctl_get_unalign +#define do_prctl_get_unalign do_prctl_inval1 +#endif +#ifndef do_prctl_set_unalign +#define do_prctl_set_unalign do_prctl_inval1 +#endif =20 static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5) @@ -6438,6 +6444,11 @@ static abi_long do_prctl(CPUArchState *env, abi_long= option, abi_long arg2, } return do_prctl_get_tagged_addr_ctrl(env); =20 + case PR_GET_UNALIGN: + return do_prctl_get_unalign(env, arg2); + case PR_SET_UNALIGN: + return do_prctl_set_unalign(env, arg2); + case PR_GET_DUMPABLE: case PR_SET_DUMPABLE: case PR_GET_KEEPCAPS: @@ -6480,8 +6491,6 @@ static abi_long do_prctl(CPUArchState *env, abi_long = option, abi_long arg2, case PR_SET_THP_DISABLE: case PR_GET_TSC: case PR_SET_TSC: - case PR_GET_UNALIGN: - case PR_SET_UNALIGN: default: /* Disable to prevent the target disabling stuff we need. */ return -TARGET_EINVAL; --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16342738582151005.8895521038626; Thu, 14 Oct 2021 21:57:38 -0700 (PDT) Received: from localhost ([::1]:52042 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFHl-0002TZ-2x for importer@patchew.org; Fri, 15 Oct 2021 00:57:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39792) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcL-00071J-G8 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:49 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:36393) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcJ-00031U-2M for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:49 -0400 Received: by mail-pf1-x429.google.com with SMTP id m26so7315250pff.3 for ; Thu, 14 Oct 2021 21:14:46 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ibr1nNRFVeuBeAqywwGzrumnaR34sN1fg0KpH5ukJvY=; b=PBgmaZxspbnMhUR0+fkJ9nXkmDq+6mFffz7MMQxHfTXIgQAdHlC8JsgSXYaitvns7R Cxm1YfWq+Raly4pPFAQTcOcsEO7Tv5DNLYsVvSqD/OWabYYy9tj9PuqVjkNRrIH8ZstQ DLkPmMMbVXb7dCTOhJYXd6ePFfINp72U7cCVzUlcxYUOYzJ+t3YdGz8IZC/mHn3mJKY9 XW4uDnkcf6U7cV/i3Oo2SbR5nQNTSa2eBPp7H0vNYmTk0UUPeMlg+AOtaVfHCqgd6LEP zFZe6JEuXjXVJT5/CM+4InZj0Nq/bSJBW4u0YPnOpwRhC+SPDYuFp+R5u+XR1KIPrYCn nkKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ibr1nNRFVeuBeAqywwGzrumnaR34sN1fg0KpH5ukJvY=; b=3Ku7a/2ySxfzyeIS/pv7PkahoI+SVm7nZbBTvkmKJ9GZzwBSImPlqX+Fd9SMZ7BIzg cA+K2taH5skjNkpm8AVgGWE2MbY7eY1n7eXpIiTwR48hfJYd4FToGuGJwOHJsLCLoUwD xeTN2lRpo92rhbNP6n2Un3UVsmgOnuclfCX+kWhZYHxzWY/p3L0z8TFSqfkRMMdW+AjA luhe4v5sl8PqmfUQ/feUDIfKuqRXRqFouPyc6WVss1ex3mNZVDrzIN4g7DgzFXBaESaF eR0094LYvztaCj/ebub2hzruFvOoNwvKCs7FUOT5rjpojgkbC96BsorGw2jGMGOXU47X FDEA== X-Gm-Message-State: AOAM530F9W2PErr6m2jT+OOVKwbLeK+D7w9yt3fAbsdXS8gxFBAvV2w8 defH2NtIiSbDb3ULHz3bK3H4HN8MOt0mlg== X-Google-Smtp-Source: ABdhPJzQUHlh5wSFTP781KTVbQfCdfTkg4izzCeMsRSJBeYnszClOZoKM66FvDQ3VudlaX7aGciAgQ== X-Received: by 2002:a62:60c2:0:b0:448:7376:20c4 with SMTP id u185-20020a6260c2000000b00448737620c4mr9275709pfb.11.1634271285695; Thu, 14 Oct 2021 21:14:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 65/67] target/alpha: Implement prctl_unalign_sigbus Date: Thu, 14 Oct 2021 21:10:51 -0700 Message-Id: <20211015041053.2769193-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273860099100001 Content-Type: text/plain; charset="utf-8" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- linux-user/alpha/target_prctl.h | 2 +- target/alpha/cpu.h | 5 +++++ target/alpha/translate.c | 31 ++++++++++++++++++++++--------- 3 files changed, 28 insertions(+), 10 deletions(-) diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prct= l.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/alpha/target_prctl.h +++ b/linux-user/alpha/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index afd975c878..e819211503 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -383,6 +383,8 @@ enum { #define ENV_FLAG_TB_MASK \ (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) =20 +#define TB_FLAG_UNALIGN (1u << 1) + static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) { int ret =3D env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_= IDX; @@ -470,6 +472,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *= env, target_ulong *pc, *pc =3D env->pc; *cs_base =3D 0; *pflags =3D env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } =20 #ifdef CONFIG_USER_ONLY diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 0eee3a1bcc..2656037b8b 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -45,7 +45,9 @@ typedef struct DisasContext DisasContext; struct DisasContext { DisasContextBase base; =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#else uint64_t palbr; #endif uint32_t tbflags; @@ -68,6 +70,12 @@ struct DisasContext { TCGv sink; }; =20 +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Target-specific return values from translate_one, indicating the state of the TB. Note that DISAS_NEXT indicates that we are not exiting the TB. */ @@ -270,7 +278,7 @@ static inline DisasJumpType gen_invalid(DisasContext *c= tx) static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_f(dest, tmp32); tcg_temp_free_i32(tmp32); } @@ -278,7 +286,7 @@ static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv = addr) static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv tmp =3D tcg_temp_new(); - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); gen_helper_memory_to_g(dest, tmp); tcg_temp_free(tmp); } @@ -286,14 +294,14 @@ static void gen_ldg(DisasContext *ctx, TCGv dest, TCG= v addr) static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_s(dest, tmp32); tcg_temp_free_i32(tmp32); } =20 static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr) { - tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } =20 static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -324,6 +332,8 @@ static void gen_load_int(DisasContext *ctx, int ra, int= rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else if (!locked) { + op |=3D UNALIGN(ctx); } =20 dest =3D ctx->ir[ra]; @@ -340,7 +350,7 @@ static void gen_stf(DisasContext *ctx, TCGv src, TCGv a= ddr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); gen_helper_f_to_memory(tmp32, addr); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } =20 @@ -348,7 +358,7 @@ static void gen_stg(DisasContext *ctx, TCGv src, TCGv a= ddr) { TCGv tmp =3D tcg_temp_new(); gen_helper_g_to_memory(tmp, src); - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); tcg_temp_free(tmp); } =20 @@ -356,13 +366,13 @@ static void gen_sts(DisasContext *ctx, TCGv src, TCGv= addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); gen_helper_s_to_memory(tmp32, src); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } =20 static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr) { - tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } =20 static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -383,6 +393,8 @@ static void gen_store_int(DisasContext *ctx, int ra, in= t rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else { + op |=3D UNALIGN(ctx); } =20 src =3D load_gpr(ctx, ra); @@ -2942,6 +2954,7 @@ static void alpha_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cpu) =20 #ifdef CONFIG_USER_ONLY ctx->ir =3D cpu_std_ir; + ctx->unalign =3D (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN= ); #else ctx->palbr =3D env->palbr; ctx->ir =3D (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_i= r); --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163427361869488.78208906103782; Thu, 14 Oct 2021 21:53:38 -0700 (PDT) Received: from localhost ([::1]:43680 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFDt-0005Gj-Oo for importer@patchew.org; Fri, 15 Oct 2021 00:53:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcN-000750-6s for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:51 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:46714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcJ-00032k-Ui for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:49 -0400 Received: by mail-pl1-x630.google.com with SMTP id 21so5580430plo.13 for ; Thu, 14 Oct 2021 21:14:47 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FDh0xRrxNKle4pRoEftfiIirEtPOD6rcCJZUiwu3wG8=; b=AbWK5js1cEcf25Lqs2nMz92zO3RIGU3Gg0TwHJUzOIzRCegLZ6fkXMAtZQJTH256Nw /9ruQnyxU5anw/Acq5ZE93JbnlDad+3yTr6FVIbHxTjuQWaAKhI9JFNlZW5P8nC4kv7n xCYMIbdFLeO74jmeC/1ghTkaj11IeBES5Wfxom2SZ/20aP2+0Di1m/T1aeb3jeR3xNx0 E3+9HNSu/VIRjYChbOjIB/Fef0Q4sFUCsBC4hlSi2+j5EBl+zoG5Ls+NBc83tNLjOysz 0qFd5qDSPumpbhYeXc/w20afl9Jj9ZhBtn3QdzZS7xWGJIwP1kYxo7shGV+hKI/gg1ar yViQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FDh0xRrxNKle4pRoEftfiIirEtPOD6rcCJZUiwu3wG8=; b=cogD6Sii3L8SjukgQ6qMoRsxYesfhgFs8kFyF8eKvTbCBC2yriLRYA9O96isJGNd1D puPjK3xTGMLGkNLcBDT0UoNAPtrLvmo/CYU9Shm/s3dsG5ZZxzjvcM29pwjSzJO6rpQ1 tWpXffgovJTTrsgBdaGPBWYSYRQ8h8LLRgsvviUtGUUxg6Q4tB2HQ7f/HpNHvN/4ZE46 MOKtuTGJAndQ4XtSNNw6RIqaOWg8DLaxw7I8zJ2HJnQfHO9MVYf3UQx1OogLsL2MA5UD bZObfeuHBJ7mUcuwSxbrUFxlNUo+FbaOTMvfQzM7kYV6mhnL/YslQ122bvyjYG1bsAlc 9MPg== X-Gm-Message-State: AOAM532pQctddcq/aOV9Cqf+GHz7nbe51NTb317xRL3JuvUZCLLj46lL SXj2pMWER+s8C1zvxiJ26sgP+NpaMaXraQ== X-Google-Smtp-Source: ABdhPJzhdmGZ+mCIDdTuM9qZiKXFVBns2DC0TdWvB3AmkNjnRgoBoCYWE+NSpgrRxVa5tX6x7u1lJQ== X-Received: by 2002:a17:90a:3b49:: with SMTP id t9mr24796794pjf.218.1634271286311; Thu, 14 Oct 2021 21:14:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 66/67] target/hppa: Implement prctl_unalign_sigbus Date: Thu, 14 Oct 2021 21:10:52 -0700 Message-Id: <20211015041053.2769193-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273619423100001 Content-Type: text/plain; charset="utf-8" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- linux-user/hppa/target_prctl.h | 2 +- target/hppa/cpu.h | 5 ++++- target/hppa/translate.c | 19 +++++++++++++++---- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/hppa/target_prctl.h +++ b/linux-user/hppa/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 294fd7297f..45fd338b02 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -259,12 +259,14 @@ static inline target_ulong hppa_form_gva(CPUHPPAState= *env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } =20 -/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. +/* + * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the * same value. */ #define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 +#define TB_FLAG_UNALIGN 0x400 =20 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *p= c, target_ulong *cs_base, @@ -279,6 +281,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, target_ulong *pc, #ifdef CONFIG_USER_ONLY *pc =3D env->iaoq_f & -4; *cs_base =3D env->iaoq_b & -4; + flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c3698cf067..fdaa2b12b8 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -272,8 +272,18 @@ typedef struct DisasContext { int mmu_idx; int privilege; bool psw_n_nonzero; + +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#endif } DisasContext; =20 +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ static int expand_sm_imm(DisasContext *ctx, int val) { @@ -1477,7 +1487,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 de= st, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1495,7 +1505,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 de= st, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1513,7 +1523,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 s= rc, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1531,7 +1541,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 s= rc, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -4110,6 +4120,7 @@ static void hppa_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->mmu_idx =3D MMU_USER_IDX; ctx->iaoq_f =3D ctx->base.pc_first | MMU_USER_IDX; ctx->iaoq_b =3D ctx->base.tb->cs_base | MMU_USER_IDX; + ctx->unalign =3D (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIG= N); #else ctx->privilege =3D (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx =3D (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_ID= X); --=20 2.25.1 From nobody Sun May 19 10:01:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634273359241758.635913771067; Thu, 14 Oct 2021 21:49:19 -0700 (PDT) Received: from localhost ([::1]:59750 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF9i-0005O6-7L for importer@patchew.org; Fri, 15 Oct 2021 00:49:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcN-000755-87 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:51 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:37568) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcK-00033X-Dp for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:50 -0400 Received: by mail-pg1-x52c.google.com with SMTP id s136so4203278pgs.4 for ; Thu, 14 Oct 2021 21:14:47 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QXtWYu3k26efdjnMd2Pt42jkFdW4b3H42VfJHmp983k=; b=SVI14zqg8H1ZYoKK9vlctQyy74N5XzIlUWRI7+DKjp0nRA2cQUhgzSOmwmpOcS3Eng mNbXt5SaK3pyxOcg6KxwCA+90CozRDTihTtY7Qz6+a0C4XWWUpYXGAA5kHEAF37F24OP PBhBf8tt/irlO1Kx9TmJZToUx8wSd6lfHyx60dVRG/D2tBZXpur5pNGYEp8Ic77JnfWv PV8LBWe8UWBvrrDLtlfr3lwzxRPEE+dyzd+BOPX1IIO6gLVen/tn4Bhk/hbzMmIgDraM FmmvsVIwfm/+KWZnXLGw4RfZAOrJTMZWttfPGRu8dqrMxitYNZk+XMq/bgWzCDPuuCcn 0COQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QXtWYu3k26efdjnMd2Pt42jkFdW4b3H42VfJHmp983k=; b=QJghRzqOiDMTX6KajvydeDQbggaa+HUlZoYvuVkV+fKG5G0SsJIP3ZK/BNe3WYyYYS xtTSChoAD9MV3ozGtlPj92NhTEVnc8be0owppJwt5qrYBISJEUuVgK/TBSOVpH8Y7kjw 6HYQv2/fxXv5l5EuMmojKXydK2iCfjyxib5us+hUUWwAJ2pn8VvSvYeAXPldBEgrw6ez ELK+bXsOJEXTN9NcKMuvQ88txFaUTjsWdz2z1oIlAkB2Dpg54PJQHR+QBslSdWXrXNYa KftygeZ8v2NcAtEFTZu3LqvGYWr/4iANDBXCKZIz6HCX+qVJT8R5lfNr0JMdO+pKfihW JWVw== X-Gm-Message-State: AOAM533rQgBzK1d8cHazQCi5DMGR66TSwFqR0s3XMcbgFtTJXUu/eKpZ 1xXCEaG1VXhk7z8/txEirawQFvhOeztLYg== X-Google-Smtp-Source: ABdhPJzQDazkJiPx4jbuFPZscv/J2Vq16L++1RLVRIbftBA2RlBntOuoGFFXCis3Of1B+rduyDzQkQ== X-Received: by 2002:a63:db41:: with SMTP id x1mr7400774pgi.474.1634271286926; Thu, 14 Oct 2021 21:14:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 67/67] target/sh4: Implement prctl_unalign_sigbus Date: Thu, 14 Oct 2021 21:10:53 -0700 Message-Id: <20211015041053.2769193-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634273359668100001 Content-Type: text/plain; charset="utf-8" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. The Linux kernel does not handle all memory operations: no floating-point and no MAC. Signed-off-by: Richard Henderson --- linux-user/sh4/target_prctl.h | 2 +- target/sh4/cpu.h | 4 +++ target/sh4/translate.c | 50 ++++++++++++++++++++++++----------- 3 files changed, 39 insertions(+), 17 deletions(-) diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/sh4/target_prctl.h +++ b/linux-user/sh4/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 4cfb109f56..fb9dd9db2f 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -83,6 +83,7 @@ #define DELAY_SLOT_RTE (1 << 2) =20 #define TB_FLAG_PENDING_MOVCA (1 << 3) +#define TB_FLAG_UNALIGN (1 << 4) =20 #define GUSA_SHIFT 4 #ifdef CONFIG_USER_ONLY @@ -373,6 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *en= v, target_ulong *pc, | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-= 30 */ | (env->sr & (1u << SR_FD)) /* Bit 15 */ | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } =20 #endif /* SH4_CPU_H */ diff --git a/target/sh4/translate.c b/target/sh4/translate.c index d363050272..7965db586f 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -50,8 +50,10 @@ typedef struct DisasContext { =20 #if defined(CONFIG_USER_ONLY) #define IS_USER(ctx) 1 +#define UNALIGN(C) (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : 0) #else #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD))) +#define UNALIGN(C) 0 #endif =20 /* Target-specific values for ctx->base.is_jmp. */ @@ -499,7 +501,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -507,7 +510,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -562,19 +566,23 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB); return; case 0x2001: /* mov.w Rm,@Rn */ - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUW | UNALIGN(ctx)); return; case 0x2002: /* mov.l Rm,@Rn */ - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUL | UNALIGN(ctx)); return; case 0x6000: /* mov.b @Rm,Rn */ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB); return; case 0x6001: /* mov.w @Rm,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESW | UNALIGN(ctx)); return; case 0x6002: /* mov.l @Rm,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESL | UNALIGN(ctx)); return; case 0x2004: /* mov.b Rm,@-Rn */ { @@ -590,7 +598,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 2); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); } @@ -599,7 +608,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); } @@ -610,12 +620,14 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1); return; case 0x6005: /* mov.w @Rm+,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESW | UNALIGN(ctx)); if ( B11_8 !=3D B7_4 ) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); return; case 0x6006: /* mov.l @Rm+,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESL | UNALIGN(ctx)); if ( B11_8 !=3D B7_4 ) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); return; @@ -631,7 +643,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -639,7 +652,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -655,7 +669,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -663,7 +678,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -1257,7 +1273,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); - tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -1273,7 +1290,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); - tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, + MO_TESW | UNALIGN(ctx)); tcg_temp_free(addr); } return; --=20 2.25.1