From nobody Fri Apr 26 23:35:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634161464958679.0136019397993; Wed, 13 Oct 2021 14:44:24 -0700 (PDT) Received: from localhost ([::1]:52030 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mam2x-0007L1-Tv for importer@patchew.org; Wed, 13 Oct 2021 17:44:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46002) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1malzX-0008Ts-Uy for qemu-devel@nongnu.org; Wed, 13 Oct 2021 17:40:51 -0400 Received: from 4.mo552.mail-out.ovh.net ([178.33.43.201]:54453) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1malzT-0004pp-I1 for qemu-devel@nongnu.org; Wed, 13 Oct 2021 17:40:51 -0400 Received: from mxplan5.mail.ovh.net (unknown [10.108.4.102]) by mo552.mail-out.ovh.net (Postfix) with ESMTPS id ED53122172; Wed, 13 Oct 2021 21:40:44 +0000 (UTC) Received: from kaod.org (37.59.142.103) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Wed, 13 Oct 2021 23:40:44 +0200 Authentication-Results: garm.ovh; auth=pass (GARM-103G005fdd12635-370a-4817-bffa-2b5df1e1d27a, ADB6EDD73587FDF9B2583A0B30D51DAD1F8B0393) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson , Greg Kurz Subject: [PATCH 1/3] ppc: Add QOM interface for machine check injection Date: Wed, 13 Oct 2021 23:40:40 +0200 Message-ID: <20211013214042.618918-2-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211013214042.618918-1-clg@kaod.org> References: <20211013214042.618918-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [37.59.142.103] X-ClientProxiedBy: DAG6EX2.mxp5.local (172.16.2.52) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: 6eef0b98-776f-4ead-9041-d344b07f4012 X-Ovh-Tracer-Id: 5934618413139069734 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvtddrvddutddgudeivdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgihesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpeehheefgeejiedtffefteejudevjeeufeeugfdtfeeuleeuteevleeihffhgfdtleenucfkpheptddrtddrtddrtddpfeejrdehledrudegvddruddtfeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehmgihplhgrnhehrdhmrghilhdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtoheptghlgheskhgrohgurdhorhhg Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.33.43.201; envelope-from=clg@kaod.org; helo=4.mo552.mail-out.ovh.net X-Spam_score_int: 0 X-Spam_score: -0.0 X-Spam_bar: / X-Spam_report: (-0.0 / 5.0 requ) RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634161466432100001 From: Nicholas Piggin This implements a machine check injection framework and defines a 'mce' monitor command for ppc. Signed-off-by: Nicholas Piggin [ clg: - moved definition under "hw/ppc/mce.h" - renamed to PPCMceInjection - simplified injection call in hmp_mce - QMP support ] Message-Id: <20200325144147.221875-4-npiggin@gmail.com> Signed-off-by: C=C3=A9dric Le Goater --- qapi/misc-target.json | 26 ++++++++++++++++++++ include/hw/ppc/mce.h | 31 ++++++++++++++++++++++++ target/ppc/monitor.c | 56 +++++++++++++++++++++++++++++++++++++++++++ hmp-commands.hx | 20 +++++++++++++++- 4 files changed, 132 insertions(+), 1 deletion(-) create mode 100644 include/hw/ppc/mce.h diff --git a/qapi/misc-target.json b/qapi/misc-target.json index 594fbd1577fa..b1456901893c 100644 --- a/qapi/misc-target.json +++ b/qapi/misc-target.json @@ -394,3 +394,29 @@ # ## { 'command': 'query-sgx-capabilities', 'returns': 'SGXInfo', 'if': 'TARGET= _I386' } + +## +# @mce: +# +# This command injects a machine check exception +# +# @cpu-index: CPU number on which to inject the machine check exception +# +# @srr1-mask : possible reasons for the exception +# +# @dsisr : more reasons +# +# @dar : effective address of next instruction +# +# @recovered : recoverable exception. Set MSR[RI] +# +# Since: 6.2 +# +## +{ 'command': 'mce', + 'data': { 'cpu-index': 'uint32', + 'srr1-mask': 'uint64', + 'dsisr': 'uint32', + 'dar': 'uint64', + 'recovered': 'bool' }, + 'if': 'TARGET_PPC' } diff --git a/include/hw/ppc/mce.h b/include/hw/ppc/mce.h new file mode 100644 index 000000000000..b2b7dfa3342c --- /dev/null +++ b/include/hw/ppc/mce.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2021, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_PPC_MCE_H +#define HW_PPC_MCE_H + +typedef struct PPCMceInjectionParams { + uint64_t srr1_mask; + uint32_t dsisr; + uint64_t dar; + bool recovered; +} PPCMceInjectionParams; + +typedef struct PPCMceInjection PPCMceInjection; + +#define TYPE_PPC_MCE_INJECTION "ppc-mce-injection" +#define PPC_MCE_INJECTION(obj) \ + INTERFACE_CHECK(PPCMceInjection, (obj), TYPE_PPC_MCE_INJECTION) +typedef struct PPCMceInjectionClass PPCMceInjectionClass; +DECLARE_CLASS_CHECKERS(PPCMceInjectionClass, PPC_MCE_INJECTION, + TYPE_PPC_MCE_INJECTION) + +struct PPCMceInjectionClass { + InterfaceClass parent_class; + void (*inject_mce)(CPUState *cs, PPCMceInjectionParams *p); +}; + +#endif diff --git a/target/ppc/monitor.c b/target/ppc/monitor.c index a475108b2dbc..ae1a047e86de 100644 --- a/target/ppc/monitor.c +++ b/target/ppc/monitor.c @@ -23,11 +23,15 @@ */ =20 #include "qemu/osdep.h" +#include "qapi/error.h" +#include "qapi/qapi-commands-misc-target.h" #include "cpu.h" #include "monitor/monitor.h" #include "qemu/ctype.h" #include "monitor/hmp-target.h" #include "monitor/hmp.h" +#include "qapi/qmp/qdict.h" +#include "hw/ppc/mce.h" =20 static target_long monitor_get_ccr(Monitor *mon, const struct MonitorDef *= md, int val) @@ -76,6 +80,48 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict) dump_mmu(env1); } =20 +void qmp_mce(uint32_t cpu_index, uint64_t srr1_mask, uint32_t dsisr, + uint64_t dar, bool recovered, Error **errp) +{ + PPCMceInjection *mce =3D (PPCMceInjection *) + object_dynamic_cast(qdev_get_machine(), TYPE_PPC_MCE_INJECTION); + CPUState *cs; + + if (!mce) { + error_setg(errp, "MCE injection not supported on this machine"); + return; + } + + cs =3D qemu_get_cpu(cpu_index); + + if (cs !=3D NULL) { + PPCMceInjectionClass *mcec =3D PPC_MCE_INJECTION_GET_CLASS(mce); + PPCMceInjectionParams p =3D { + .srr1_mask =3D srr1_mask, + .dsisr =3D dsisr, + .dar =3D dar, + .recovered =3D recovered, + }; + mcec->inject_mce(cs, &p); + } +} + +void hmp_mce(Monitor *mon, const QDict *qdict) +{ + uint32_t cpu_index =3D qdict_get_int(qdict, "cpu_index"); + uint64_t srr1_mask =3D qdict_get_int(qdict, "srr1_mask"); + uint32_t dsisr =3D qdict_get_int(qdict, "dsisr"); + uint64_t dar =3D qdict_get_int(qdict, "dar"); + bool recovered =3D qdict_get_int(qdict, "recovered"); + Error *err =3D NULL; + + qmp_mce(cpu_index, srr1_mask, dsisr, dar, recovered, &err); + if (err) { + hmp_handle_error(mon, err); + return; + } +} + const MonitorDef monitor_defs[] =3D { { "fpscr", offsetof(CPUPPCState, fpscr) }, /* Next instruction pointer */ @@ -156,3 +202,13 @@ int target_get_monitor_def(CPUState *cs, const char *n= ame, uint64_t *pval) =20 return -EINVAL; } + +static const TypeInfo type_infos[] =3D { + { + .name =3D TYPE_PPC_MCE_INJECTION, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(PPCMceInjectionClass), + }, +}; + +DEFINE_TYPES(type_infos); diff --git a/hmp-commands.hx b/hmp-commands.hx index cf723c69acb7..15d939ae096e 100644 --- a/hmp-commands.hx +++ b/hmp-commands.hx @@ -1461,12 +1461,30 @@ ERST .cmd =3D hmp_mce, }, =20 -#endif SRST ``mce`` *cpu* *bank* *status* *mcgstatus* *addr* *misc* Inject an MCE on the given CPU (x86 only). ERST =20 +#endif + +#if defined(TARGET_PPC) + + { + .name =3D "mce", + .args_type =3D "cpu_index:i,srr1_mask:l,dsisr:i,dar:l,recovered:i= ", + .params =3D "cpu srr1_mask dsisr dar recovered", + .help =3D "inject a MCE on the given CPU", + .cmd =3D hmp_mce, + }, + +SRST +``mce`` *cpu* *srr1_mask* *dsisr* *dar* *recovered* + Inject an MCE on the given CPU (PPC only). +ERST + +#endif + { .name =3D "getfd", .args_type =3D "fdname:s", --=20 2.31.1 From nobody Fri Apr 26 23:35:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634161342737380.6362365159107; Wed, 13 Oct 2021 14:42:22 -0700 (PDT) Received: from localhost ([::1]:45236 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mam0z-0002nq-JV for importer@patchew.org; Wed, 13 Oct 2021 17:42:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1malzY-0008W9-Ld for qemu-devel@nongnu.org; Wed, 13 Oct 2021 17:40:52 -0400 Received: from smtpout2.mo529.mail-out.ovh.net ([79.137.123.220]:42353) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1malzU-0004ql-8A for qemu-devel@nongnu.org; Wed, 13 Oct 2021 17:40:52 -0400 Received: from mxplan5.mail.ovh.net (unknown [10.108.4.25]) by mo529.mail-out.ovh.net (Postfix) with ESMTPS id 97967C48051B; Wed, 13 Oct 2021 23:40:45 +0200 (CEST) Received: from kaod.org (37.59.142.103) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Wed, 13 Oct 2021 23:40:44 +0200 Authentication-Results: garm.ovh; auth=pass (GARM-103G0056b96a2a2-7312-4745-9c13-921adb59834f, ADB6EDD73587FDF9B2583A0B30D51DAD1F8B0393) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson , Greg Kurz Subject: [PATCH 2/3] ppc/spapr: Implement mce injection Date: Wed, 13 Oct 2021 23:40:41 +0200 Message-ID: <20211013214042.618918-3-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211013214042.618918-1-clg@kaod.org> References: <20211013214042.618918-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [37.59.142.103] X-ClientProxiedBy: DAG6EX2.mxp5.local (172.16.2.52) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: 436201db-4069-4e1a-aa7a-1f9adedace79 X-Ovh-Tracer-Id: 5934899884115790630 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvtddrvddutddgudeivdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgihesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpeehheefgeejiedtffefteejudevjeeufeeugfdtfeeuleeuteevleeihffhgfdtleenucfkpheptddrtddrtddrtddpfeejrdehledrudegvddruddtfeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehmgihplhgrnhehrdhmrghilhdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtoheptghlgheskhgrohgurdhorhhg Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=79.137.123.220; envelope-from=clg@kaod.org; helo=smtpout2.mo529.mail-out.ovh.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634161345529100001 From: Nicholas Piggin This implements mce injection for spapr. (qemu) mce 0 0x200000 0x80 0xdeadbeef 1 Disabling lock debugging due to kernel taint MCE: CPU0: machine check (Severe) Host SLB Multihit DAR: 00000000deadbe= ef [Recovered] MCE: CPU0: machine check (Severe) Host SLB Multihit [Recovered] MCE: CPU0: PID: 495 Comm: a NIP: [0000000130ee07c8] MCE: CPU0: Initiator CPU MCE: CPU0: Unknown [ 71.567193] MCE: CPU0: NIP: [c0000000000d7f6c] plpar_hcall_norets+0x1c/0= x28 [ 71.567249] MCE: CPU0: Initiator CPU [ 71.567308] MCE: CPU0: Unknown Signed-off-by: Nicholas Piggin [ clg: - simplified injection and moved code under spapr_cpu_core.c ] Message-Id: <20200325144147.221875-5-npiggin@gmail.com> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/spapr_cpu_core.h | 2 ++ hw/ppc/spapr.c | 4 ++++ hw/ppc/spapr_cpu_core.c | 27 +++++++++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_cor= e.h index dab3dfc76c0a..6734c7a89640 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -9,6 +9,7 @@ #ifndef HW_SPAPR_CPU_CORE_H #define HW_SPAPR_CPU_CORE_H =20 +#include "hw/ppc/mce.h" #include "hw/cpu/core.h" #include "hw/qdev-core.h" #include "target/ppc/cpu-qom.h" @@ -40,6 +41,7 @@ const char *spapr_get_cpu_core_type(const char *cpu_type); void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r1, target_ulong r3, target_ulong r4); +void spapr_cpu_inject_mce(CPUState *cs, PPCMceInjectionParams *p); =20 typedef struct SpaprCpuState { uint64_t vpa_addr; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 087449f93871..c4ff63a79313 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -56,6 +56,7 @@ #include "hw/core/cpu.h" =20 #include "hw/ppc/ppc.h" +#include "hw/ppc/mce.h" #include "hw/loader.h" =20 #include "hw/ppc/fdt.h" @@ -4522,6 +4523,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) InterruptStatsProviderClass *ispc =3D INTERRUPT_STATS_PROVIDER_CLASS(o= c); XiveFabricClass *xfc =3D XIVE_FABRIC_CLASS(oc); VofMachineIfClass *vmc =3D VOF_MACHINE_CLASS(oc); + PPCMceInjectionClass *mcec =3D PPC_MCE_INJECTION_CLASS(oc); =20 mc->desc =3D "pSeries Logical Partition (PAPR compliant)"; mc->ignore_boot_device_suffixes =3D true; @@ -4615,6 +4617,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) vmc->client_architecture_support =3D spapr_vof_client_architecture_sup= port; vmc->quiesce =3D spapr_vof_quiesce; vmc->setprop =3D spapr_vof_setprop; + mcec->inject_mce =3D spapr_cpu_inject_mce; } =20 static const TypeInfo spapr_machine_info =3D { @@ -4635,6 +4638,7 @@ static const TypeInfo spapr_machine_info =3D { { TYPE_INTERRUPT_STATS_PROVIDER }, { TYPE_XIVE_FABRIC }, { TYPE_VOF_MACHINE_IF }, + { TYPE_PPC_MCE_INJECTION }, { } }, }; diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 58e7341cb784..360efc16b1d6 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -9,6 +9,7 @@ =20 #include "qemu/osdep.h" #include "hw/cpu/core.h" +#include "hw/core/cpu.h" #include "hw/ppc/spapr_cpu_core.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -19,12 +20,38 @@ #include "sysemu/kvm.h" #include "target/ppc/kvm_ppc.h" #include "hw/ppc/ppc.h" +#include "hw/ppc/mce.h" #include "target/ppc/mmu-hash64.h" #include "sysemu/numa.h" #include "sysemu/reset.h" #include "sysemu/hw_accel.h" #include "qemu/error-report.h" =20 +static void spapr_cpu_inject_mce_on_cpu(CPUState *cs, run_on_cpu_data data) +{ + PPCMceInjectionParams *params =3D (PPCMceInjectionParams *) data.host_= ptr; + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + uint64_t srr1_mce_bits =3D PPC_BITMASK(42, 45) | PPC_BIT(36); + + cpu_synchronize_state(cs); + + env->spr[SPR_SRR0] =3D env->nip; + env->spr[SPR_SRR1] =3D (env->msr & ~srr1_mce_bits) | + (params->srr1_mask & srr1_mce_bits); + if (params->dsisr) { + env->spr[SPR_DSISR] =3D params->dsisr; + env->spr[SPR_DAR] =3D params->dar; + } + + spapr_mce_req_event(cpu, params->recovered); +} + +void spapr_cpu_inject_mce(CPUState *cs, PPCMceInjectionParams *p) +{ + run_on_cpu(cs, spapr_cpu_inject_mce_on_cpu, RUN_ON_CPU_HOST_PTR(p)); +} + static void spapr_reset_vcpu(PowerPCCPU *cpu) { CPUState *cs =3D CPU(cpu); --=20 2.31.1 From nobody Fri Apr 26 23:35:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634161369043755.1846276134211; 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Wed, 13 Oct 2021 23:40:45 +0200 Authentication-Results: garm.ovh; auth=pass (GARM-103G005dec8fab3-1005-49e0-9718-e20915549239, ADB6EDD73587FDF9B2583A0B30D51DAD1F8B0393) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson , Greg Kurz Subject: [PATCH 3/3] ppc/pnv: Implement mce injection Date: Wed, 13 Oct 2021 23:40:42 +0200 Message-ID: <20211013214042.618918-4-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211013214042.618918-1-clg@kaod.org> References: <20211013214042.618918-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [37.59.142.103] X-ClientProxiedBy: DAG6EX2.mxp5.local (172.16.2.52) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: f81329d9-1043-4d3b-b79c-2e31025cd780 X-Ovh-Tracer-Id: 5934899884953864998 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvtddrvddutddgudeivdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgihesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpeehheefgeejiedtffefteejudevjeeufeeugfdtfeeuleeuteevleeihffhgfdtleenucfkpheptddrtddrtddrtddpfeejrdehledrudegvddruddtfeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehmgihplhgrnhehrdhmrghilhdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtoheptghlgheskhgrohgurdhorhhg Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=46.105.54.81; envelope-from=clg@kaod.org; helo=smtpout3.mo529.mail-out.ovh.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634161371379100005 From: Nicholas Piggin This implements mce injection for pnv. Signed-off-by: Nicholas Piggin [ clg: - simplified injection and moved code under pnv_core.c - removed superfluous cpu_synchronize_state() - clear previous setting in SPR_SRR1 ] Message-Id: <20200325144147.221875-6-npiggin@gmail.com> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv_core.h | 4 ++++ target/ppc/cpu.h | 1 + hw/ppc/pnv.c | 3 +++ hw/ppc/pnv_core.c | 27 +++++++++++++++++++++++++++ target/ppc/excp_helper.c | 12 ++++++++++++ 5 files changed, 47 insertions(+) diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index c22eab2e1f69..7ed7a52077ea 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -23,6 +23,7 @@ #include "hw/cpu/core.h" #include "target/ppc/cpu.h" #include "qom/object.h" +#include "hw/ppc/mce.h" =20 #define TYPE_PNV_CORE "powernv-cpu-core" OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass, @@ -70,4 +71,7 @@ struct PnvQuad { uint32_t quad_id; MemoryRegion xscom_regs; }; + +void pnv_cpu_inject_mce(CPUState *cs, PPCMceInjectionParams *p); + #endif /* PPC_PNV_CORE_H */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index baa4e7c34d30..e0757e287718 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1273,6 +1273,7 @@ int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction = f, CPUState *cs, void ppc_cpu_do_interrupt(CPUState *cpu); bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); void ppc_cpu_do_system_reset(CPUState *cs); +void ppc_cpu_do_machine_check(CPUState *cs); void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector); extern const VMStateDescription vmstate_ppc_cpu; #endif diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 71e45515f136..374f48ea7f1b 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2001,6 +2001,7 @@ static void pnv_machine_class_init(ObjectClass *oc, v= oid *data) MachineClass *mc =3D MACHINE_CLASS(oc); InterruptStatsProviderClass *ispc =3D INTERRUPT_STATS_PROVIDER_CLASS(o= c); NMIClass *nc =3D NMI_CLASS(oc); + PPCMceInjectionClass *mcec =3D PPC_MCE_INJECTION_CLASS(oc); =20 mc->desc =3D "IBM PowerNV (Non-Virtualized)"; mc->init =3D pnv_init; @@ -2018,6 +2019,7 @@ static void pnv_machine_class_init(ObjectClass *oc, v= oid *data) mc->default_ram_id =3D "pnv.ram"; ispc->print_info =3D pnv_pic_print_info; nc->nmi_monitor_handler =3D pnv_nmi; + mcec->inject_mce =3D pnv_cpu_inject_mce; =20 object_class_property_add_bool(oc, "hb-mode", pnv_machine_get_hb, pnv_machine_set_hb); @@ -2080,6 +2082,7 @@ static const TypeInfo types[] =3D { .interfaces =3D (InterfaceInfo[]) { { TYPE_INTERRUPT_STATS_PROVIDER }, { TYPE_NMI }, + { TYPE_PPC_MCE_INJECTION }, { }, }, }, diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 19e8eb885f71..868b361f99e5 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -25,12 +25,39 @@ #include "target/ppc/cpu.h" #include "hw/ppc/ppc.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/mce.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/xics.h" #include "hw/qdev-properties.h" #include "helper_regs.h" =20 +static void pnv_cpu_inject_mce_on_cpu(CPUState *cs, run_on_cpu_data data) +{ + PPCMceInjectionParams *params =3D (PPCMceInjectionParams *) data.host_= ptr; + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + uint64_t srr1_mce_bits =3D PPC_BITMASK(42, 45) | PPC_BIT(36); + + ppc_cpu_do_machine_check(cs); + + env->spr[SPR_SRR1] =3D (env->msr & ~srr1_mce_bits) | + (params->srr1_mask & srr1_mce_bits); + if (params->dsisr) { + env->spr[SPR_DSISR] =3D params->dsisr; + env->spr[SPR_DAR] =3D params->dar; + } + + if (!params->recovered) { + env->msr &=3D ~MSR_RI; + } +} + +void pnv_cpu_inject_mce(CPUState *cs, PPCMceInjectionParams *p) +{ + run_on_cpu(cs, pnv_cpu_inject_mce_on_cpu, RUN_ON_CPU_HOST_PTR(p)); +} + static const char *pnv_core_cpu_typename(PnvCore *pc) { const char *core_type =3D object_class_get_name(object_get_class(OBJEC= T(pc))); diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b7d176792098..f383f1646cc3 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -379,6 +379,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int e= xcp_model, int excp) cs->halted =3D 1; cpu_interrupt_exittb(cs); } + if (msr_pow) { + /* indicate that we resumed from power save mode */ + msr |=3D 0x10000; + } if (env->msr_mask & MSR_HVB) { /* * ISA specifies HV, but can be delivered to guest with HV @@ -1071,6 +1075,14 @@ void ppc_cpu_do_system_reset(CPUState *cs) powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); } =20 +void ppc_cpu_do_machine_check(CPUState *cs) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK); +} + void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); --=20 2.31.1