From nobody Fri Apr 26 15:26:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163415856743494.54638686035855; Wed, 13 Oct 2021 13:56:07 -0700 (PDT) Received: from localhost ([::1]:34426 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1malIE-0006ME-CQ for importer@patchew.org; Wed, 13 Oct 2021 16:56:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35700) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1malDa-0007XG-H2 for qemu-devel@nongnu.org; Wed, 13 Oct 2021 16:51:18 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:42783) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1malDT-00085N-Nt for qemu-devel@nongnu.org; Wed, 13 Oct 2021 16:51:17 -0400 Received: by mail-pg1-x535.google.com with SMTP id 66so3466512pgc.9 for ; Wed, 13 Oct 2021 13:51:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id t71sm383043pgc.29.2021.10.13.13.51.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Oct 2021 13:51:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4Tfk6rOkPFBJ6N3/4OlCjFDtsGaLD4ljr9lrSt09j54=; b=t0s+vv3Nmr+rq13d5cs76Urxj8YeqYAIiVfupQsSBDhTY2ZPvRsp0wglr7xXk4umpn LrdyraL59RyEZ2i8Ha3O19Fv2l+sbuuJOHnYGQqJLDySmwC9p4r0tQw17aBchAAUPWnX XBMv9da/GgN64rUEIFwWcgwZ8CWX+/2lDB/IRpgO78gfux2PRolSNNzIGs5G+q1f87jR C3CuiL2t+s/Vih9UxxnAIOThXe3oPDeR49V6UgpdQ2lR32DPhuhrQAhcljWRp5KQqp5C ij7iOhtta2at/ie7DMp36pF+VCyw5cft2u2kmp+gcUvS1XrjjPFPf85cj85y6nxGzCeA b22g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4Tfk6rOkPFBJ6N3/4OlCjFDtsGaLD4ljr9lrSt09j54=; b=qTp84PjZUbiDYBAp/uGjfBdydiEOMVPCrqqRvLdThr+cHU8I8Icqe5I+uP6/iURU47 ACphimmTAhjWXkau8UXlq1h/N26YOO5xBh8+BOQsJl+qnyJqRy/sZhSGvhVumitenrCs lLLRRAXlX66dP9nsJXFWJw1O48tOWRODn+ztMI5qVW6Kmz6sgIAC2KmEBs4LfKMEXsqA negw3JL2I47PXGB/L7PUAFcN6VHRYNCg5WRbwyj22H6z12joE3CIZR+99xUgUOZ2cZ21 jKvl5CRV2Qkp79rUkFDrdRje/eHOI3XpTCgROU4WB6aURXI1k9WFYu84c0s4lJiLGp3N 9RSQ== X-Gm-Message-State: AOAM532wJmlwqflA735jLhnhzOstHvdlZUA59CYBernOJ2XVzJgsC6O3 L544JxZeJuSltgDZ0rm3N0JQt1By7bRY+A== X-Google-Smtp-Source: ABdhPJxKj5gij5fYoQGeqjewzjAMd1VlIbd+DWLPCJ0Ucnquw6QFtyf/SNTTUcq6NRG6Yd6mnBbl/g== X-Received: by 2002:a65:6a15:: with SMTP id m21mr1109788pgu.415.1634158270210; Wed, 13 Oct 2021 13:51:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Date: Wed, 13 Oct 2021 13:50:55 -0700 Message-Id: <20211013205104.1031679-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013205104.1031679-1-richard.henderson@linaro.org> References: <20211013205104.1031679-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634158568385100003 Content-Type: text/plain; charset="utf-8" Shortly, the set of supported XL will not be just 32 and 64, and representing that properly using the enumeration will be imperative. Two places, booting and gdb, intentionally use misa_mxl_max to emphasize the use of the reset value of misa.mxl, and not the current cpu state. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 9 ++++++++- hw/riscv/boot.c | 2 +- semihosting/arm-compat-semi.c | 2 +- target/riscv/cpu.c | 24 ++++++++++++++---------- target/riscv/cpu_helper.c | 12 ++++++------ target/riscv/csr.c | 24 ++++++++++++------------ target/riscv/gdbstub.c | 2 +- target/riscv/monitor.c | 4 ++-- 8 files changed, 45 insertions(+), 34 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e708fcc168..87248b562a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -396,7 +396,14 @@ FIELD(TB_FLAGS, VILL, 8, 1) FIELD(TB_FLAGS, HLSX, 9, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) =20 -bool riscv_cpu_is_32bit(CPURISCVState *env); +#ifdef CONFIG_RISCV32 +#define riscv_cpu_mxl(env) MXL_RV32 +#else +static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) +{ + return env->misa_mxl; +} +#endif =20 /* * A simplification for VLMAX diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 993bf89064..d1ffc7b56c 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -35,7 +35,7 @@ =20 bool riscv_is_32bit(RISCVHartArrayState *harts) { - return riscv_cpu_is_32bit(&harts->harts[0].env); + return harts->harts[0].env.misa_mxl_max =3D=3D MXL_RV32; } =20 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 01badea99c..37963becae 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -775,7 +775,7 @@ static inline bool is_64bit_semihosting(CPUArchState *e= nv) #if defined(TARGET_ARM) return is_a64(env); #elif defined(TARGET_RISCV) - return !riscv_cpu_is_32bit(env); + return riscv_cpu_mxl(env) !=3D MXL_RV32; #else #error un-handled architecture #endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fdf031a394..1857670a69 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -108,11 +108,6 @@ const char *riscv_cpu_get_trap_name(target_ulong cause= , bool async) } } =20 -bool riscv_cpu_is_32bit(CPURISCVState *env) -{ - return env->misa_mxl =3D=3D MXL_RV32; -} - static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { env->misa_mxl_max =3D env->misa_mxl =3D mxl; @@ -249,7 +244,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)e= nv->mstatus); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", (target_ulong)(env->mstatus >> 32)); } @@ -372,10 +367,16 @@ static void riscv_cpu_reset(DeviceState *dev) static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) { RISCVCPU *cpu =3D RISCV_CPU(s); - if (riscv_cpu_is_32bit(&cpu->env)) { + + switch (riscv_cpu_mxl(&cpu->env)) { + case MXL_RV32: info->print_insn =3D print_insn_riscv32; - } else { + break; + case MXL_RV64: info->print_insn =3D print_insn_riscv64; + break; + default: + g_assert_not_reached(); } } =20 @@ -631,10 +632,13 @@ static gchar *riscv_gdb_arch_name(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; =20 - if (riscv_cpu_is_32bit(env)) { + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: return g_strdup("riscv:rv32"); - } else { + case MXL_RV64: return g_strdup("riscv:rv64"); + default: + g_assert_not_reached(); } } =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 14d1d3cb72..403f54171d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -152,7 +152,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) =20 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - uint64_t sd =3D riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD; + uint64_t sd =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? MSTATUS32_SD : MS= TATUS64_SD; uint64_t mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | MSTATUS64_UXL | sd; @@ -447,7 +447,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, =20 if (first_stage =3D=3D true) { if (use_background) { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { base =3D (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSH= IFT; vm =3D get_field(env->vsatp, SATP32_MODE); } else { @@ -455,7 +455,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, vm =3D get_field(env->vsatp, SATP64_MODE); } } else { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHI= FT; vm =3D get_field(env->satp, SATP32_MODE); } else { @@ -465,7 +465,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } widened =3D 0; } else { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { base =3D (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; vm =3D get_field(env->hgatp, SATP32_MODE); } else { @@ -558,7 +558,7 @@ restart: } =20 target_ulong pte; - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { pte =3D address_space_ldl(cs->as, pte_addr, attrs, &res); } else { pte =3D address_space_ldq(cs->as, pte_addr, attrs, &res); @@ -678,7 +678,7 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, int page_fault_exceptions, vm; uint64_t stap_mode; =20 - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { stap_mode =3D SATP32_MODE; } else { stap_mode =3D SATP64_MODE; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d0c86a300d..9c0753bc8b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -95,7 +95,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { switch (csrno) { case CSR_CYCLEH: if (!get_field(env->hcounteren, COUNTEREN_CY) && @@ -130,7 +130,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) =20 static RISCVException ctr32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -145,7 +145,7 @@ static RISCVException any(CPURISCVState *env, int csrno) =20 static RISCVException any32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -180,7 +180,7 @@ static RISCVException hmode(CPURISCVState *env, int csr= no) =20 static RISCVException hmode32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { if (riscv_cpu_virt_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; } else { @@ -486,7 +486,7 @@ static RISCVException read_mstatus(CPURISCVState *env, = int csrno, =20 static int validate_vm(CPURISCVState *env, target_ulong vm) { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; } else { return valid_vm_1_10_64[vm & 0xf]; @@ -510,7 +510,7 @@ static RISCVException write_mstatus(CPURISCVState *env,= int csrno, MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_TW; =20 - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { /* * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. @@ -522,7 +522,7 @@ static RISCVException write_mstatus(CPURISCVState *env,= int csrno, =20 dirty =3D ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS) | ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { mstatus =3D set_field(mstatus, MSTATUS32_SD, dirty); } else { mstatus =3D set_field(mstatus, MSTATUS64_SD, dirty); @@ -795,7 +795,7 @@ static RISCVException read_sstatus(CPURISCVState *env, = int csrno, { target_ulong mask =3D (sstatus_v1_10_mask); =20 - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { mask |=3D SSTATUS32_SD; } else { mask |=3D SSTATUS64_SD; @@ -1006,7 +1006,7 @@ static RISCVException write_satp(CPURISCVState *env, = int csrno, return RISCV_EXCP_NONE; } =20 - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { vm =3D validate_vm(env, get_field(val, SATP32_MODE)); mask =3D (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_P= PN); asid =3D (val ^ env->satp) & SATP32_ASID; @@ -1034,7 +1034,7 @@ static RISCVException read_hstatus(CPURISCVState *env= , int csrno, target_ulong *val) { *val =3D env->hstatus; - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { /* We only support 64-bit VSXL */ *val =3D set_field(*val, HSTATUS_VSXL, 2); } @@ -1047,7 +1047,7 @@ static RISCVException write_hstatus(CPURISCVState *en= v, int csrno, target_ulong val) { env->hstatus =3D val; - if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) !=3D 2) { + if (riscv_cpu_mxl(env) !=3D MXL_RV32 && get_field(val, HSTATUS_VSXL) != =3D 2) { qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN optio= ns."); } if (get_field(val, HSTATUS_VSBE) !=3D 0) { @@ -1215,7 +1215,7 @@ static RISCVException write_htimedelta(CPURISCVState = *env, int csrno, return RISCV_EXCP_ILLEGAL_INST; } =20 - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { env->htimedelta =3D deposit64(env->htimedelta, 0, 32, (uint64_t)va= l); } else { env->htimedelta =3D val; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 5257df0217..23429179e2 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -161,7 +161,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int = base_reg) CPURISCVState *env =3D &cpu->env; GString *s =3D g_string_new(NULL); riscv_csr_predicate_fn predicate; - int bitsize =3D riscv_cpu_is_32bit(env) ? 32 : 64; + int bitsize =3D 16 << env->misa_mxl_max; int i; =20 g_string_printf(s, ""); diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index f7e6ea72b3..7efb4b62c1 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -150,7 +150,7 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *e= nv) target_ulong last_size; int last_attr; =20 - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; vm =3D get_field(env->satp, SATP32_MODE); } else { @@ -220,7 +220,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } =20 - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { if (!(env->satp & SATP32_MODE)) { monitor_printf(mon, "No translation or protection\n"); return; --=20 2.25.1