From nobody Fri Apr 19 19:01:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634159010796109.31242027601013; Wed, 13 Oct 2021 14:03:30 -0700 (PDT) Received: from localhost ([::1]:51436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1malPN-00016m-I0 for importer@patchew.org; Wed, 13 Oct 2021 17:03:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1malDi-0007ds-E0 for qemu-devel@nongnu.org; Wed, 13 Oct 2021 16:51:27 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:36476) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1malDZ-0008AU-V7 for qemu-devel@nongnu.org; Wed, 13 Oct 2021 16:51:22 -0400 Received: by mail-pg1-x532.google.com with SMTP id 75so3495977pga.3 for ; Wed, 13 Oct 2021 13:51:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id t71sm383043pgc.29.2021.10.13.13.51.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Oct 2021 13:51:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5BmUKj5ZFDfEAmKDg/dVXECTi9BNeky+S0S3T1g9RSg=; b=juH1Z5qsnceT9siUWgFUSnfR0VV6n92dpM2ofAB1buXemzwWhf+K9vA1z/kM3I7Yqk +cXRJundO2PMQgTQQZqwBK41xU2Y9GKuZ92QhbHU+xq3/y+web3efa6ShuXzeyM53tQf DyTonAL7eKcy3KvbIlqYpNr+C2T+GWCk2vw/qY1HUeC0DON8zyJCQBYOOLPJ3tmBUc8s Wxuf3K0mEWdUERec6444adA6uL5SbETcD/UgOuO4K9N2mldq/Q//nbSn9o3Dagdo0SQk wDOmdmaBvBoZ3FED2zdwS+MD2zHEdr95Cv1Uz4A4Da18whEJqoAfEXz2xHFIr3X1FKsY 32tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5BmUKj5ZFDfEAmKDg/dVXECTi9BNeky+S0S3T1g9RSg=; b=J5AdDCztnuBLsyNP+W8WmHNBBq0PR6SG3Xf3u1JYZ0zScY8caRojFIXXPZI8leZn0e swSaNEUJe/Hl/n03NnrilIzYDDN1tGIOssLBjPlVWhSw9viQwsOee5nP2UoqSCJ/pY2f pTNRsoccrwWXxMcKljHxhK8x6sBjgBM+jXpwzy0Qkb58FpmZNfQ1n66LWOTzhc87FjIG KDhjXhHLfcYbtJTZpm08Hd5RvclKzNznKvPWpseUsSJ3McAFHq3ImZWosqUCudY8z5cn o9YtU45ys4gUwfNKcX2cRA3FwVDbfLNGSUlGaa8Zi8qfSYWdivUazg/0yZCAUF3ZKls3 2VXw== X-Gm-Message-State: AOAM533RuYm1EFurrLPG3q3QyiDQjdklZdlVBZ5PaQjFwJrdcbvm0e1s n0HWvTD7D8b5K1g+sfqWMXqxXoSmqm3z3g== X-Google-Smtp-Source: ABdhPJzzLRqHFXBfxrKIz8XFqBrXFHenpH7YPr6eHVlGXtBTaA9YD8W7pzq5GYh5CUrV/bYPCuZFIA== X-Received: by 2002:a63:e613:: with SMTP id g19mr1196812pgh.12.1634158275380; Wed, 13 Oct 2021 13:51:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Date: Wed, 13 Oct 2021 13:51:00 -0700 Message-Id: <20211013205104.1031679-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013205104.1031679-1-richard.henderson@linaro.org> References: <20211013205104.1031679-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634159012704100001 Content-Type: text/plain; charset="utf-8" In preparation for RV128, consider more than just "w" for operand size modification. This will be used for the "d" insns from RV128 as well. Rename oper_len to get_olen to better match get_xlen. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 71 ++++++++++++++++--------- target/riscv/insn_trans/trans_rvb.c.inc | 8 +-- target/riscv/insn_trans/trans_rvi.c.inc | 18 +++---- target/riscv/insn_trans/trans_rvm.c.inc | 10 ++-- 4 files changed, 63 insertions(+), 44 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5724a62bb0..6ab5c6aa58 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,7 +67,7 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; - bool w; + RISCVMXL ol; bool virt_enabled; bool ext_ifencei; bool hlsx; @@ -103,12 +103,17 @@ static inline int get_xlen(DisasContext *ctx) return 16 << get_xl(ctx); } =20 -/* The word size for this operation. */ -static inline int oper_len(DisasContext *ctx) -{ - return ctx->w ? 32 : TARGET_LONG_BITS; -} +/* The operation length, as opposed to the xlen. */ +#ifdef TARGET_RISCV32 +#define get_ol(ctx) MXL_RV32 +#else +#define get_ol(ctx) ((ctx)->ol) +#endif =20 +static inline int get_olen(DisasContext *ctx) +{ + return 16 << get_ol(ctx); +} =20 /* * RISC-V requires NaN-boxing of narrower width floating point values. @@ -221,24 +226,34 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, D= isasExtend ext) return ctx->zero; } =20 - switch (ctx->w ? ext : EXT_NONE) { - case EXT_NONE: - return cpu_gpr[reg_num]; - case EXT_SIGN: - t =3D temp_new(ctx); - tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); - return t; - case EXT_ZERO: - t =3D temp_new(ctx); - tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); - return t; + switch (get_ol(ctx)) { + case MXL_RV32: + switch (ext) { + case EXT_NONE: + break; + case EXT_SIGN: + t =3D temp_new(ctx); + tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); + return t; + case EXT_ZERO: + t =3D temp_new(ctx); + tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); + return t; + default: + g_assert_not_reached(); + } + break; + case MXL_RV64: + break; + default: + g_assert_not_reached(); } - g_assert_not_reached(); + return cpu_gpr[reg_num]; } =20 static TCGv dest_gpr(DisasContext *ctx, int reg_num) { - if (reg_num =3D=3D 0 || ctx->w) { + if (reg_num =3D=3D 0 || get_olen(ctx) < TARGET_LONG_BITS) { return temp_new(ctx); } return cpu_gpr[reg_num]; @@ -247,10 +262,15 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num) static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) { if (reg_num !=3D 0) { - if (ctx->w) { + switch (get_ol(ctx)) { + case MXL_RV32: tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); - } else { + break; + case MXL_RV64: tcg_gen_mov_tl(cpu_gpr[reg_num], t); + break; + default: + g_assert_not_reached(); } } } @@ -411,7 +431,7 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shi= ft *a, DisasExtend ext, void (*func)(TCGv, TCGv, target_long)) { TCGv dest, src1; - int max_len =3D oper_len(ctx); + int max_len =3D get_olen(ctx); =20 if (a->shamt >=3D max_len) { return false; @@ -430,7 +450,7 @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shi= ft *a, DisasExtend ext, void (*func)(TCGv, TCGv, TCGv)) { TCGv dest, src1, src2; - int max_len =3D oper_len(ctx); + int max_len =3D get_olen(ctx); =20 if (a->shamt >=3D max_len) { return false; @@ -454,7 +474,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, Disa= sExtend ext, TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); TCGv ext2 =3D tcg_temp_new(); =20 - tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1); + tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1); func(dest, src1, ext2); =20 gen_set_gpr(ctx, a->rd, dest); @@ -554,7 +574,6 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs =3D cs; - ctx->w =3D false; ctx->ntemp =3D 0; memset(ctx->temp, 0, sizeof(ctx->temp)); =20 @@ -578,9 +597,9 @@ static void riscv_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cpu) CPURISCVState *env =3D cpu->env_ptr; uint16_t opcode16 =3D translator_lduw(env, &ctx->base, ctx->base.pc_ne= xt); =20 + ctx->ol =3D ctx->xl; decode_opc(env, ctx, opcode16); ctx->base.pc_next =3D ctx->pc_succ_insn; - ctx->w =3D false; =20 for (int i =3D ctx->ntemp - 1; i >=3D 0; --i) { tcg_temp_free(ctx->temp[i]); diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 185c3e9a60..66dd51de49 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -341,7 +341,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } =20 @@ -367,7 +367,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_shift(ctx, a, EXT_NONE, gen_rorw); } =20 @@ -375,7 +375,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw); } =20 @@ -401,7 +401,7 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_shift(ctx, a, EXT_NONE, gen_rolw); } =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 920ae0edb3..c0a46d823f 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -333,14 +333,14 @@ static bool trans_and(DisasContext *ctx, arg_and *a) static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { REQUIRE_64BIT(ctx); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl); } =20 static bool trans_slliw(DisasContext *ctx, arg_slliw *a) { REQUIRE_64BIT(ctx); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } =20 @@ -352,7 +352,7 @@ static void gen_srliw(TCGv dst, TCGv src, target_long s= hamt) static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw); } =20 @@ -364,42 +364,42 @@ static void gen_sraiw(TCGv dst, TCGv src, target_long= shamt) static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw); } =20 static bool trans_addw(DisasContext *ctx, arg_addw *a) { REQUIRE_64BIT(ctx); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl); } =20 static bool trans_subw(DisasContext *ctx, arg_subw *a) { REQUIRE_64BIT(ctx); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl); } =20 static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { REQUIRE_64BIT(ctx); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl); } =20 static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { REQUIRE_64BIT(ctx); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl); } =20 static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { REQUIRE_64BIT(ctx); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl); } =20 diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index b89a85ad3a..9a1fe3c799 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -214,7 +214,7 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl); } =20 @@ -222,7 +222,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_arith(ctx, a, EXT_SIGN, gen_div); } =20 @@ -230,7 +230,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_arith(ctx, a, EXT_ZERO, gen_divu); } =20 @@ -238,7 +238,7 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_arith(ctx, a, EXT_SIGN, gen_rem); } =20 @@ -246,6 +246,6 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w =3D true; + ctx->ol =3D MXL_RV32; return gen_arith(ctx, a, EXT_ZERO, gen_remu); } --=20 2.25.1