[PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64

Richard Henderson posted 13 patches 1 month, 2 weeks ago
Maintainers: "Alex Bennée" <alex.bennee@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Laurent Vivier <laurent@vivier.eu>, Palmer Dabbelt <palmer@dabbelt.com>

[PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64

Posted by Richard Henderson 1 month, 2 weeks ago
When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 66dd51de49..c62eea433a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
     return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
 }
 
+static void gen_rev8_32(TCGv ret, TCGv src1)
+{
+    tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
+}
+
 static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
 {
     REQUIRE_32BIT(ctx);
     REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
+    return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
 }
 
 static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
-- 
2.25.1


Re: [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64

Posted by Alistair Francis 1 month, 1 week ago
On Thu, Oct 14, 2021 at 7:08 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> When target_long is 64-bit, we still want a 32-bit bswap for rev8.
> Since this opcode is specific to RV32, we need not conditionalize.
>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 66dd51de49..c62eea433a 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
>      return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
>  }
>
> +static void gen_rev8_32(TCGv ret, TCGv src1)
> +{
> +    tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
> +}
> +
>  static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
>  {
>      REQUIRE_32BIT(ctx);
>      REQUIRE_ZBB(ctx);
> -    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
> +    return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
>  }
>
>  static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
> --
> 2.25.1
>
>