From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634149510002663.206000380632; Wed, 13 Oct 2021 11:25:10 -0700 (PDT) Received: from localhost ([::1]:47390 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maiw8-0006Mh-4s for importer@patchew.org; Wed, 13 Oct 2021 14:25:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36650) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maitq-0003bd-10 for qemu-devel@nongnu.org; Wed, 13 Oct 2021 14:22:46 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:39647) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maito-0002y0-Ea for qemu-devel@nongnu.org; Wed, 13 Oct 2021 14:22:45 -0400 Received: by mail-pj1-x102d.google.com with SMTP id ls18-20020a17090b351200b001a00250584aso5061926pjb.4 for ; Wed, 13 Oct 2021 11:22:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id z2sm177140pfe.210.2021.10.13.11.22.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Oct 2021 11:22:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OcQ/8dg+uyCnQNjoef3iDXLc5D161p75+kxjS6wsxRk=; b=CVuXOrOqNEEerpD7YUjAQB/oP8P7/+YUHVk4TPZD7rGBqIbMRRwYxqkVOhFrKYKTXm 4+dg0QO3G/iGPMlGM7u4KqrOl3oWHvC1mZYXBAu9CG8hh9CQdmAQOu1hP2mBR87IJ2Nk Qp+Hajm1O5XGKBPtNwLGYG/V7NC5vginvA/0Wthjs4fJla/slr2qtcu6Sddim7fL913f Ke5axfKFpWBzSdvwQucU0aWONvrpzVa9sinYy3lJVQq79I96GLmv0WK4cBOFCTP4gYeH tNuT1qUvD+M32HJgr9FGY+kE2Bh57FdMdOTAkh8wRvZ+Zd4t3sxKtHIOJxTgU4JUPk7h iEdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OcQ/8dg+uyCnQNjoef3iDXLc5D161p75+kxjS6wsxRk=; b=4JmJDr2zvf3bgfIflOpTyhFnz4/tOmjdGum5sfaoeXhWaRVBxy6oDjWTXuUgeqAlzB gQpklTF/NYYwflTqsmla7o8SMdwyXqm5dz1GfRgoe2jKVdoOTxP1sA3FQ8zH4IElQFZM B7DMwzCXKpxlQGgNtccdPh8xcmJfd/tRHDz5Jowx1bRO1QbQSg34tgUHAizriEIFrLIv LeNIAR5Y+VAk9fPDA/deRz93VxamBf9aSv6OarnKMXHwGJ5AbCOts42i9DnrJr+0S8kp qhcrPOsTaNzj2YxeL7Mxca9B68P/V0v1XbVg4t9OOKffD0aqePbT9vQo0aLMok12OI5a ycVQ== X-Gm-Message-State: AOAM531EYcfBYblzCnFhWEvxqAqQ4sKFRefvhTmoxptojqMVM5e3nXlb Lk8zwqO2oFmdaiZJsN7RxEX0CfoW9L/3/Q== X-Google-Smtp-Source: ABdhPJxQVeGPgQQHbjX2TQAdkm1QH3pgNI5q4SQY8xEjxOmxH1xz6ix8z4eugwm+UP4FNAVmwqP8Aw== X-Received: by 2002:a17:90b:4ac9:: with SMTP id mh9mr873392pjb.173.1634149362930; Wed, 13 Oct 2021 11:22:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/15] memory: Log access direction for invalid accesses Date: Wed, 13 Oct 2021 11:22:25 -0700 Message-Id: <20211013182239.991127-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013182239.991127-1-richard.henderson@linaro.org> References: <20211013182239.991127-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634149511834100001 Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan In memory_region_access_valid() invalid accesses are logged to help debugging but the log message does not say if it was a read or write. Log that too to better identify the access causing the problem. Reviewed-by: David Hildenbrand Signed-off-by: BALATON Zoltan Message-Id: <20211011173616.F1DE0756022@zero.eik.bme.hu> Signed-off-by: Richard Henderson --- softmmu/memory.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/softmmu/memory.c b/softmmu/memory.c index db182e5d3d..e5826faa0c 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -1378,17 +1378,17 @@ bool memory_region_access_valid(MemoryRegion *mr, { if (mr->ops->valid.accepts && !mr->ops->valid.accepts(mr->opaque, addr, size, is_write, attrs= )) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr " - "0x%" HWADDR_PRIX ", size %u, " - "region '%s', reason: rejected\n", + qemu_log_mask(LOG_GUEST_ERROR, "Invalid %s at addr 0x%" HWADDR_PRIX + ", size %u, region '%s', reason: rejected\n", + is_write ? "write" : "read", addr, size, memory_region_name(mr)); return false; } =20 if (!mr->ops->valid.unaligned && (addr & (size - 1))) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr " - "0x%" HWADDR_PRIX ", size %u, " - "region '%s', reason: unaligned\n", + qemu_log_mask(LOG_GUEST_ERROR, "Invalid %s at addr 0x%" HWADDR_PRIX + ", size %u, region '%s', reason: unaligned\n", + is_write ? "write" : "read", addr, size, memory_region_name(mr)); return false; } @@ -1400,10 +1400,10 @@ bool memory_region_access_valid(MemoryRegion *mr, =20 if (size > mr->ops->valid.max_access_size || size < mr->ops->valid.min_access_size) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr " - "0x%" HWADDR_PRIX ", size %u, " - "region '%s', reason: invalid size " - "(min:%u max:%u)\n", + qemu_log_mask(LOG_GUEST_ERROR, "Invalid %s at addr 0x%" HWADDR_PRIX + ", size %u, region '%s', reason: invalid size " + "(min:%u max:%u)\n", + is_write ? "write" : "read", addr, size, memory_region_name(mr), mr->ops->valid.min_access_size, mr->ops->valid.max_access_size); --=20 2.25.1 From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1634149512; cv=none; d=zohomail.com; s=zohoarc; b=HCsNi3WsK6VExR06rma5ZFJzjJQdQdbIF3xUBd6euNwgLTyyfpQ3THgCACJEH07u/I+vzKKsxQlER06UQqhlgV26gGbEpiz0HxgII5umpJX4RdCIxWULaIEqMScPj5CmoixbatJjQJH63SzDyEgO7hgAFphI7d6UVSafVzYcBhI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634149512; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1634149513904100005 Cc: qemu-arm@nongnu.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index c5af779006..4cafd3c11a 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -560,7 +560,7 @@ uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMSta= te *env, uint64_t addr, assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); =20 cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); newv =3D int128_make128(new_lo, new_hi); @@ -630,7 +630,7 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMSta= te *env, uint64_t addr, assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); + oi =3D make_memop_idx(MO_BE | MO_128 | MO_ALIGN, mem_idx); =20 /* * High and low need to be switched here because this is not actually a @@ -656,7 +656,7 @@ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); =20 cmpv =3D int128_make128(env->xregs[rs], env->xregs[rs + 1]); newv =3D int128_make128(new_lo, new_hi); @@ -677,7 +677,7 @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); =20 cmpv =3D int128_make128(env->xregs[rs + 1], env->xregs[rs]); newv =3D int128_make128(new_lo, new_hi); --=20 2.25.1 From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1634149713; cv=none; d=zohomail.com; s=zohoarc; b=k0EwzNV5tkBTUSZf/yK2USqtR1wn1fsvYc35gt9+cSxNZ3oVfCDSx0NrgmbBF2u85ePorQHswGvzHZZweyc9W+w6vpMedQCrupjo8p1Hzk/VEjPvt6qGNbjIQmdj1W4dCZPRVs0Ny6Htwxinj4OhStxRPByCnJMIQkGvsQzcFLg= ARC-Message-Signature: i=1; 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Wed, 13 Oct 2021 11:22:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 03/15] target/i386: Use MO_128 for 16 byte atomics Date: Wed, 13 Oct 2021 11:22:27 -0700 Message-Id: <20211013182239.991127-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013182239.991127-1-richard.henderson@linaro.org> References: <20211013182239.991127-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1634149715140100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/i386/tcg/mem_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 0fd696f9c1..a207e624cb 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -136,7 +136,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a= 0) Int128 newv =3D int128_make128(env->regs[R_EBX], env->regs[R_ECX]); =20 int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); Int128 oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi= , ra); =20 if (int128_eq(oldv, cmpv)) { --=20 2.25.1 From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1634149898; cv=none; d=zohomail.com; s=zohoarc; b=g5jpfU1F2wvExe1szoh63MfYhW2ox5vkdm96xdst1ZPSmja0Qk4Te9bBd2S3kIMGU8SVX4MPASoFyd/CxC/ab9lsx91tMxWJ8AzTpMN8PpEkKygHodrJUz6/ghWOOiiNbasQKsJ74yBLMsIrHpImIBArn3IKQOJuBc46VkP4lNM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634149898; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1634149898585100001 Cc: qemu-ppc@nongnu.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/ppc/translate.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b985e9e55b..9ca78ee156 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3462,10 +3462,12 @@ static void gen_std(DisasContext *ctx) if (HAVE_ATOMIC128) { TCGv_i32 oi =3D tcg_temp_new_i32(); if (ctx->le_mode) { - tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_i= dx)); + tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128, + ctx->mem_idx)); gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); } else { - tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_i= dx)); + tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128, + ctx->mem_idx)); gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); } tcg_temp_free_i32(oi); @@ -4067,11 +4069,11 @@ static void gen_lqarx(DisasContext *ctx) if (HAVE_ATOMIC128) { TCGv_i32 oi =3D tcg_temp_new_i32(); if (ctx->le_mode) { - tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, + tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_AL= IGN, ctx->mem_idx)); gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); } else { - tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, + tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_AL= IGN, ctx->mem_idx)); gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); } @@ -4122,7 +4124,7 @@ static void gen_stqcx_(DisasContext *ctx) =20 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { if (HAVE_CMPXCHG128) { - TCGv_i32 oi =3D tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); + TCGv_i32 oi =3D tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); if (ctx->le_mode) { gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi); --=20 2.25.1 From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163414951395215.358091211913575; Wed, 13 Oct 2021 11:25:13 -0700 (PDT) Received: from localhost ([::1]:47796 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maiwC-0006cZ-OW for importer@patchew.org; Wed, 13 Oct 2021 14:25:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maitu-0003lb-Md for qemu-devel@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634149516145100001 Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 75f6735545..e64d1bc725 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1811,7 +1811,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64= _t addr, assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); fail =3D !int128_eq(oldv, cmpv); =20 @@ -1940,7 +1940,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra); cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra); } else if (HAVE_CMPXCHG128) { - MemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_i= dx); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, = mem_idx); ov =3D cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra); cc =3D !int128_eq(ov, cv); } else { --=20 2.25.1 From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 13 Oct 2021 11:22:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 06/15] target/hexagon: Implement cpu_mmu_index Date: Wed, 13 Oct 2021 11:22:30 -0700 Message-Id: <20211013182239.991127-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013182239.991127-1-richard.henderson@linaro.org> References: <20211013182239.991127-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Taylor Simpson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1634149710982100001 The function is trivial for user-only, but still must be present. Reviewed-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/hexagon/cpu.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index f7d043865b..f90c187888 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -141,6 +141,15 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonStat= e *env, target_ulong *pc, #endif } =20 +static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else +#error System mode not supported on Hexagon yet +#endif +} + typedef struct CPUHexagonState CPUArchState; typedef HexagonCPU ArchCPU; =20 --=20 2.25.1 From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Wed, 13 Oct 2021 11:22:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 07/15] accel/tcg: Add cpu_{ld,st}*_mmu interfaces Date: Wed, 13 Oct 2021 11:22:31 -0700 Message-Id: <20211013182239.991127-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013182239.991127-1-richard.henderson@linaro.org> References: <20211013182239.991127-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1634150292732100001 Content-Type: text/plain; charset="utf-8" These functions are much closer to the softmmu helper functions, in that they take the complete MemOpIdx, and from that they may enforce required alignment. The previous cpu_ldst.h functions did not have alignment info, and so did not enforce it. Retain this by adding MO_UNALN to the MemOp that we create in calling the new functions. Note that we are not yet enforcing alignment for user-only, but we now have the information with which to do so. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/devel/loads-stores.rst | 52 ++++- include/exec/cpu_ldst.h | 245 ++++++++-------------- accel/tcg/cputlb.c | 392 ++++++++++++------------------------ accel/tcg/user-exec.c | 385 +++++++++++++++-------------------- accel/tcg/ldst_common.c.inc | 307 ++++++++++++++++++++++++++++ 5 files changed, 717 insertions(+), 664 deletions(-) create mode 100644 accel/tcg/ldst_common.c.inc diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst index 568274baec..8f0035c821 100644 --- a/docs/devel/loads-stores.rst +++ b/docs/devel/loads-stores.rst @@ -68,15 +68,19 @@ Regexes for git grep - ``\`` - ``\`` =20 -``cpu_{ld,st}*_mmuidx_ra`` -~~~~~~~~~~~~~~~~~~~~~~~~~~ +``cpu_{ld,st}*_mmu`` +~~~~~~~~~~~~~~~~~~~~ =20 -These functions operate on a guest virtual address plus a context, -known as a "mmu index" or ``mmuidx``, which controls how that virtual -address is translated. The meaning of the indexes are target specific, -but specifying a particular index might be necessary if, for instance, -the helper requires an "always as non-privileged" access rather that -the default access for the current state of the guest CPU. +These functions operate on a guest virtual address, plus a context +known as a "mmu index" which controls how that virtual address is +translated, plus a ``MemOp`` which contains alignment requirements +among other things. The ``MemOp`` and mmu index are combined into +a single argument of type ``MemOpIdx``. + +The meaning of the indexes are target specific, but specifying a +particular index might be necessary if, for instance, the helper +requires a "always as non-privileged" access rather than the +default access for the current state of the guest CPU. =20 These functions may cause a guest CPU exception to be taken (e.g. for an alignment fault or MMU fault) which will result in @@ -99,6 +103,35 @@ function, which is a return address into the generated = code [#gpc]_. =20 Function names follow the pattern: =20 +load: ``cpu_ld{size}{end}_mmu(env, ptr, oi, retaddr)`` + +store: ``cpu_st{size}{end}_mmu(env, ptr, val, oi, retaddr)`` + +``size`` + - ``b`` : 8 bits + - ``w`` : 16 bits + - ``l`` : 32 bits + - ``q`` : 64 bits + +``end`` + - (empty) : for target endian, or 8 bit sizes + - ``_be`` : big endian + - ``_le`` : little endian + +Regexes for git grep: + - ``\`` + - ``\`` + + +``cpu_{ld,st}*_mmuidx_ra`` +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +These functions work like the ``cpu_{ld,st}_mmu`` functions except +that the ``mmuidx`` parameter is not combined with a ``MemOp``, +and therefore there is no required alignment supplied or enforced. + +Function names follow the pattern: + load: ``cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmuidx, retaddr)`` =20 store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)`` @@ -132,7 +165,8 @@ of the guest CPU, as determined by ``cpu_mmu_index(env,= false)``. =20 These are generally the preferred way to do accesses by guest virtual address from helper functions, unless the access should -be performed with a context other than the default. +be performed with a context other than the default, or alignment +should be enforced for the access. =20 Function names follow the pattern: =20 diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ce6ce82618..a4dad0772f 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -28,10 +28,12 @@ * load: cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr) * cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr) * cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr) + * cpu_ld{sign}{size}{end}_mmu(env, ptr, oi, retaddr) * * store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val) * cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr) * cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr) + * cpu_st{size}{end}_mmu(env, ptr, val, oi, retaddr) * * sign is: * (empty): for 32 and 64 bit sizes @@ -53,10 +55,15 @@ * The "mmuidx" suffix carries an extra mmu_idx argument that specifies * the index to use; the "data" and "code" suffixes take the index from * cpu_mmu_index(). + * + * The "mmu" suffix carries the full MemOpIdx, with both mmu_idx and the + * MemOp including alignment requirements. The alignment will be enforced. */ #ifndef CPU_LDST_H #define CPU_LDST_H =20 +#include "exec/memopidx.h" + #if defined(CONFIG_USER_ONLY) /* sparc32plus has 64bit long but 32bit space address * this can make bad result with g2h() and h2g() @@ -118,12 +125,10 @@ typedef target_ulong abi_ptr; =20 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr); int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr); - uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr); int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr); uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr); uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr); - uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr); int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr); uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr); @@ -131,37 +136,31 @@ uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr p= tr); =20 uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); - uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); - uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); =20 void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val); - void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val); - void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val); =20 void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t ra); - void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t ra); void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t ra); void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, uintptr_t ra); - void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t ra); void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, @@ -169,6 +168,71 @@ void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, uintptr_t ra); =20 +uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); + +void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, + int mmu_idx, uintptr_t ra); +void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, + int mmu_idx, uintptr_t ra); + +uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t= ra); +uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); + +void cpu_stb_mmu(CPUArchState *env, abi_ptr ptr, uint8_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stw_be_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stl_be_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stq_be_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stw_le_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stl_le_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stq_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, + MemOpIdx oi, uintptr_t ra); + #if defined(CONFIG_USER_ONLY) =20 extern __thread uintptr_t helper_retaddr; @@ -193,119 +257,6 @@ static inline void clear_helper_retaddr(void) helper_retaddr =3D 0; } =20 -/* - * Provide the same *_mmuidx_ra interface as for softmmu. - * The mmu_idx argument is ignored. - */ - -static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldub_data_ra(env, addr, ra); -} - -static inline int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldsb_data_ra(env, addr, ra); -} - -static inline uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, - int mmu_idx, uintptr_t ra) -{ - return cpu_lduw_be_data_ra(env, addr, ra); -} - -static inline int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldsw_be_data_ra(env, addr, ra); -} - -static inline uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr add= r, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldl_be_data_ra(env, addr, ra); -} - -static inline uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr add= r, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldq_be_data_ra(env, addr, ra); -} - -static inline uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, - int mmu_idx, uintptr_t ra) -{ - return cpu_lduw_le_data_ra(env, addr, ra); -} - -static inline int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldsw_le_data_ra(env, addr, ra); -} - -static inline uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr add= r, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldl_le_data_ra(env, addr, ra); -} - -static inline uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr add= r, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldq_le_data_ra(env, addr, ra); -} - -static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, uintptr_t = ra) -{ - cpu_stb_data_ra(env, addr, val, ra); -} - -static inline void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stw_be_data_ra(env, addr, val, ra); -} - -static inline void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stl_be_data_ra(env, addr, val, ra); -} - -static inline void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint64_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stq_be_data_ra(env, addr, val, ra); -} - -static inline void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stw_le_data_ra(env, addr, val, ra); -} - -static inline void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stl_le_data_ra(env, addr, val, ra); -} - -static inline void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint64_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stq_le_data_ra(env, addr, val, ra); -} - #else =20 /* Needed for TCG_OVERSIZED_GUEST */ @@ -336,46 +287,6 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env= , uintptr_t mmu_idx, return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; } =20 -uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); - -uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); - -uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); - -void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); - -void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); -void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); -void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, - int mmu_idx, uintptr_t retaddr); - -void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); -void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); -void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, - int mmu_idx, uintptr_t retaddr); - #endif /* defined(CONFIG_USER_ONLY) */ =20 #ifdef TARGET_WORDS_BIGENDIAN @@ -391,6 +302,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, uint64_t val, # define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra # define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra # define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra +# define cpu_ldw_mmu cpu_ldw_be_mmu +# define cpu_ldl_mmu cpu_ldl_be_mmu +# define cpu_ldq_mmu cpu_ldq_be_mmu # define cpu_stw_data cpu_stw_be_data # define cpu_stl_data cpu_stl_be_data # define cpu_stq_data cpu_stq_be_data @@ -400,6 +314,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, uint64_t val, # define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra # define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra # define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra +# define cpu_stw_mmu cpu_stw_be_mmu +# define cpu_stl_mmu cpu_stl_be_mmu +# define cpu_stq_mmu cpu_stq_be_mmu #else # define cpu_lduw_data cpu_lduw_le_data # define cpu_ldsw_data cpu_ldsw_le_data @@ -413,6 +330,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, uint64_t val, # define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra # define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra # define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra +# define cpu_ldw_mmu cpu_ldw_le_mmu +# define cpu_ldl_mmu cpu_ldl_le_mmu +# define cpu_ldq_mmu cpu_ldq_le_mmu # define cpu_stw_data cpu_stw_le_data # define cpu_stl_data cpu_stl_le_data # define cpu_stq_data cpu_stq_le_data @@ -422,6 +342,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, uint64_t val, # define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra # define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra # define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra +# define cpu_stw_mmu cpu_stw_le_mmu +# define cpu_stl_mmu cpu_stl_le_mmu +# define cpu_stq_mmu cpu_stq_le_mmu #endif =20 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 46140ccff3..b350cafa3d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1839,6 +1839,25 @@ static void *atomic_mmu_lookup(CPUArchState *env, ta= rget_ulong addr, cpu_loop_exit_atomic(env_cpu(env), retaddr); } =20 +/* + * Verify that we have passed the correct MemOp to the correct function. + * + * In the case of the helper_*_mmu functions, we will have done this by + * using the MemOp to look up the helper during code generation. + * + * In the case of the cpu_*_mmu functions, this is up to the caller. + * We could present one function to target code, and dispatch based on + * the MemOp, but so far we have worked hard to avoid an indirect function + * call along the memory path. + */ +static void validate_memop(MemOpIdx oi, MemOp expected) +{ +#ifdef CONFIG_DEBUG_TCG + MemOp have =3D get_memop(oi) & (MO_SIZE | MO_BSWAP); + assert(have =3D=3D expected); +#endif +} + /* * Load Helpers * @@ -1992,6 +2011,7 @@ load_helper(CPUArchState *env, target_ulong addr, Mem= OpIdx oi, static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_UB); return load_helper(env, addr, oi, retaddr, MO_UB, false, full_ldub_mmu= ); } =20 @@ -2004,6 +2024,7 @@ tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *en= v, target_ulong addr, static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_LEUW); return load_helper(env, addr, oi, retaddr, MO_LEUW, false, full_le_lduw_mmu); } @@ -2017,6 +2038,7 @@ tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env= , target_ulong addr, static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_BEUW); return load_helper(env, addr, oi, retaddr, MO_BEUW, false, full_be_lduw_mmu); } @@ -2030,6 +2052,7 @@ tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env= , target_ulong addr, static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_LEUL); return load_helper(env, addr, oi, retaddr, MO_LEUL, false, full_le_ldul_mmu); } @@ -2043,6 +2066,7 @@ tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env= , target_ulong addr, static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_BEUL); return load_helper(env, addr, oi, retaddr, MO_BEUL, false, full_be_ldul_mmu); } @@ -2056,6 +2080,7 @@ tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env= , target_ulong addr, uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_LEQ); return load_helper(env, addr, oi, retaddr, MO_LEQ, false, helper_le_ldq_mmu); } @@ -2063,6 +2088,7 @@ uint64_t helper_le_ldq_mmu(CPUArchState *env, target_= ulong addr, uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_BEQ); return load_helper(env, addr, oi, retaddr, MO_BEQ, false, helper_be_ldq_mmu); } @@ -2108,186 +2134,56 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *= env, target_ulong addr, */ =20 static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t retaddr, - MemOp op, FullLoadHelper *full_load) + MemOpIdx oi, uintptr_t retaddr, + FullLoadHelper *full_load) { - MemOpIdx oi =3D make_memop_idx(op, mmu_idx); uint64_t ret; =20 trace_guest_ld_before_exec(env_cpu(env), addr, oi); - ret =3D full_load(env, addr, oi, retaddr); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; } =20 -uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_= t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_UB, full_ldub_mmu); + return cpu_load_helper(env, addr, oi, ra, full_ldub_mmu); } =20 -int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra); + return cpu_load_helper(env, addr, oi, ra, full_be_lduw_mmu); } =20 -uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUW, full_be_lduw_m= mu); + return cpu_load_helper(env, addr, oi, ra, full_be_ldul_mmu); } =20 -int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra); + return cpu_load_helper(env, addr, oi, MO_BEQ, helper_be_ldq_mmu); } =20 -uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUL, full_be_ldul_m= mu); + return cpu_load_helper(env, addr, oi, ra, full_le_lduw_mmu); } =20 -uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEQ, helper_be_ldq_m= mu); + return cpu_load_helper(env, addr, oi, ra, full_le_ldul_mmu); } =20 -uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUW, full_le_lduw_m= mu); -} - -int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra); -} - -uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUL, full_le_ldul_m= mu); -} - -uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEQ, helper_le_ldq_m= mu); -} - -uint32_t cpu_ldub_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldub_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr= ); -} - -int cpu_ldsb_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retadd= r) -{ - return cpu_ldsb_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr= ); -} - -uint32_t cpu_lduw_be_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_lduw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), reta= ddr); -} - -int cpu_ldsw_be_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t ret= addr) -{ - return cpu_ldsw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), reta= ddr); -} - -uint32_t cpu_ldl_be_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldl_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retad= dr); -} - -uint64_t cpu_ldq_be_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldq_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retad= dr); -} - -uint32_t cpu_lduw_le_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_lduw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), reta= ddr); -} - -int cpu_ldsw_le_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t ret= addr) -{ - return cpu_ldsw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), reta= ddr); -} - -uint32_t cpu_ldl_le_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldl_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retad= dr); -} - -uint64_t cpu_ldq_le_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldq_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retad= dr); -} - -uint32_t cpu_ldub_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldub_data_ra(env, ptr, 0); -} - -int cpu_ldsb_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldsb_data_ra(env, ptr, 0); -} - -uint32_t cpu_lduw_be_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_lduw_be_data_ra(env, ptr, 0); -} - -int cpu_ldsw_be_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldsw_be_data_ra(env, ptr, 0); -} - -uint32_t cpu_ldl_be_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldl_be_data_ra(env, ptr, 0); -} - -uint64_t cpu_ldq_be_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldq_be_data_ra(env, ptr, 0); -} - -uint32_t cpu_lduw_le_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_lduw_le_data_ra(env, ptr, 0); -} - -int cpu_ldsw_le_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldsw_le_data_ra(env, ptr, 0); -} - -uint32_t cpu_ldl_le_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldl_le_data_ra(env, ptr, 0); -} - -uint64_t cpu_ldq_le_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldq_le_data_ra(env, ptr, 0); + return cpu_load_helper(env, addr, oi, ra, helper_le_ldq_mmu); } =20 /* @@ -2324,6 +2220,9 @@ store_memop(void *haddr, uint64_t val, MemOp op) } } =20 +static void full_stb_mmu(CPUArchState *env, target_ulong addr, uint64_t va= l, + MemOpIdx oi, uintptr_t retaddr); + static void __attribute__((noinline)) store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val, uintptr_t retaddr, size_t size, uintptr_t mmu_idx, @@ -2387,13 +2286,13 @@ store_helper_unaligned(CPUArchState *env, target_ul= ong addr, uint64_t val, for (i =3D 0; i < size; ++i) { /* Big-endian extract. */ uint8_t val8 =3D val >> (((size - 1) * 8) - (i * 8)); - helper_ret_stb_mmu(env, addr + i, val8, oi, retaddr); + full_stb_mmu(env, addr + i, val8, oi, retaddr); } } else { for (i =3D 0; i < size; ++i) { /* Little-endian extract. */ uint8_t val8 =3D val >> (i * 8); - helper_ret_stb_mmu(env, addr + i, val8, oi, retaddr); + full_stb_mmu(env, addr + i, val8, oi, retaddr); } } } @@ -2496,46 +2395,83 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, store_memop(haddr, val, op); } =20 -void __attribute__((noinline)) -helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, - MemOpIdx oi, uintptr_t retaddr) +static void __attribute__((noinline)) +full_stb_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_UB); store_helper(env, addr, val, oi, retaddr, MO_UB); } =20 +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + full_stb_mmu(env, addr, val, oi, retaddr); +} + +static void full_le_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t= val, + MemOpIdx oi, uintptr_t retaddr) +{ + validate_memop(oi, MO_LEUW); + store_helper(env, addr, val, oi, retaddr, MO_LEUW); +} + void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, MemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, MO_LEUW); + full_le_stw_mmu(env, addr, val, oi, retaddr); +} + +static void full_be_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t= val, + MemOpIdx oi, uintptr_t retaddr) +{ + validate_memop(oi, MO_BEUW); + store_helper(env, addr, val, oi, retaddr, MO_BEUW); } =20 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, MemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, MO_BEUW); + full_be_stw_mmu(env, addr, val, oi, retaddr); +} + +static void full_le_stl_mmu(CPUArchState *env, target_ulong addr, uint64_t= val, + MemOpIdx oi, uintptr_t retaddr) +{ + validate_memop(oi, MO_LEUL); + store_helper(env, addr, val, oi, retaddr, MO_LEUL); } =20 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, MO_LEUL); + full_le_stl_mmu(env, addr, val, oi, retaddr); +} + +static void full_be_stl_mmu(CPUArchState *env, target_ulong addr, uint64_t= val, + MemOpIdx oi, uintptr_t retaddr) +{ + validate_memop(oi, MO_BEUL); + store_helper(env, addr, val, oi, retaddr, MO_BEUL); } =20 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, MO_BEUL); + full_be_stl_mmu(env, addr, val, oi, retaddr); } =20 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_LEQ); store_helper(env, addr, val, oi, retaddr, MO_LEQ); } =20 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_BEQ); store_helper(env, addr, val, oi, retaddr, MO_BEQ); } =20 @@ -2543,137 +2479,61 @@ void helper_be_stq_mmu(CPUArchState *env, target_u= long addr, uint64_t val, * Store Helpers for cpu_ldst.h */ =20 -static inline void QEMU_ALWAYS_INLINE -cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val, - int mmu_idx, uintptr_t retaddr, MemOp op) +typedef void FullStoreHelper(CPUArchState *env, target_ulong addr, + uint64_t val, MemOpIdx oi, uintptr_t retaddr); + +static inline void cpu_store_helper(CPUArchState *env, target_ulong addr, + uint64_t val, MemOpIdx oi, uintptr_t r= a, + FullStoreHelper *full_store) { - MemOpIdx oi =3D make_memop_idx(op, mmu_idx); - trace_guest_st_before_exec(env_cpu(env), addr, oi); - - store_helper(env, addr, val, oi, retaddr, op); - + full_store(env, addr, val, oi, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val, - int mmu_idx, uintptr_t retaddr) +void cpu_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_UB); + cpu_store_helper(env, addr, val, oi, retaddr, full_stb_mmu); } =20 -void cpu_stw_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t v= al, - int mmu_idx, uintptr_t retaddr) +void cpu_stw_be_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUW); + cpu_store_helper(env, addr, val, oi, retaddr, full_be_stw_mmu); } =20 -void cpu_stl_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t v= al, - int mmu_idx, uintptr_t retaddr) +void cpu_stl_be_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUL); + cpu_store_helper(env, addr, val, oi, retaddr, full_be_stl_mmu); } =20 -void cpu_stq_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t v= al, - int mmu_idx, uintptr_t retaddr) +void cpu_stq_be_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEQ); + cpu_store_helper(env, addr, val, oi, retaddr, helper_be_stq_mmu); } =20 -void cpu_stw_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t v= al, - int mmu_idx, uintptr_t retaddr) +void cpu_stw_le_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUW); + cpu_store_helper(env, addr, val, oi, retaddr, full_le_stw_mmu); } =20 -void cpu_stl_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t v= al, - int mmu_idx, uintptr_t retaddr) +void cpu_stl_le_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUL); + cpu_store_helper(env, addr, val, oi, retaddr, full_le_stl_mmu); } =20 -void cpu_stq_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t v= al, - int mmu_idx, uintptr_t retaddr) +void cpu_stq_le_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEQ); + cpu_store_helper(env, addr, val, oi, retaddr, helper_le_stq_mmu); } =20 -void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stb_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr); -} - -void cpu_stw_be_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stw_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr= ); -} - -void cpu_stl_be_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stl_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr= ); -} - -void cpu_stq_be_data_ra(CPUArchState *env, target_ulong ptr, - uint64_t val, uintptr_t retaddr) -{ - cpu_stq_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr= ); -} - -void cpu_stw_le_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stw_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr= ); -} - -void cpu_stl_le_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stl_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr= ); -} - -void cpu_stq_le_data_ra(CPUArchState *env, target_ulong ptr, - uint64_t val, uintptr_t retaddr) -{ - cpu_stq_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr= ); -} - -void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stb_data_ra(env, ptr, val, 0); -} - -void cpu_stw_be_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stw_be_data_ra(env, ptr, val, 0); -} - -void cpu_stl_be_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stl_be_data_ra(env, ptr, val, 0); -} - -void cpu_stq_be_data(CPUArchState *env, target_ulong ptr, uint64_t val) -{ - cpu_stq_be_data_ra(env, ptr, val, 0); -} - -void cpu_stw_le_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stw_le_data_ra(env, ptr, val, 0); -} - -void cpu_stl_le_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stl_le_data_ra(env, ptr, val, 0); -} - -void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val) -{ - cpu_stq_le_data_ra(env, ptr, val, 0); -} +#include "ldst_common.c.inc" =20 /* * First set of functions passes in OI and RETADDR. diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 65d3c9b286..e6bb29b42d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -886,300 +886,227 @@ int cpu_signal_handler(int host_signum, void *pinfo, =20 /* The softmmu versions of these helpers are in cputlb.c. */ =20 -uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) +/* + * Verify that we have passed the correct MemOp to the correct function. + * + * We could present one function to target code, and dispatch based on + * the MemOp, but so far we have worked hard to avoid an indirect function + * call along the memory path. + */ +static void validate_memop(MemOpIdx oi, MemOp expected) { - MemOpIdx oi =3D make_memop_idx(MO_UB, MMU_USER_IDX); - uint32_t ret; +#ifdef CONFIG_DEBUG_TCG + MemOp have =3D get_memop(oi) & (MO_SIZE | MO_BSWAP); + assert(have =3D=3D expected); +#endif +} =20 - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D ldub_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); +static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t ra, MMUAccessType type) +{ + void *ret; + + /* TODO: Enforce guest required alignment. */ + + ret =3D g2h(env_cpu(env), addr); + set_helper_retaddr(ra); return ret; } =20 -int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) +uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int8_t)cpu_ldub_data(env, ptr); -} + void *haddr; + uint8_t ret; =20 -uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUW, MMU_USER_IDX); - uint32_t ret; - - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D lduw_be_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_UB); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D ldub_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr) +uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_be_data(env, ptr); -} + void *haddr; + uint16_t ret; =20 -uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUL, MMU_USER_IDX); - uint32_t ret; - - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D ldl_be_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_BEUW); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D lduw_be_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) +uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - MemOpIdx oi =3D make_memop_idx(MO_BEQ, MMU_USER_IDX); + void *haddr; + uint32_t ret; + + validate_memop(oi, MO_BEUL); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D ldl_be_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return ret; +} + +uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; uint64_t ret; =20 - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D ldq_be_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_BEQ); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D ldq_be_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr) +uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - MemOpIdx oi =3D make_memop_idx(MO_LEUW, MMU_USER_IDX); + void *haddr; + uint16_t ret; + + validate_memop(oi, MO_LEUW); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D lduw_le_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return ret; +} + +uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; uint32_t ret; =20 - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D lduw_le_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_LEUL); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D ldl_le_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr) +uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_le_data(env, ptr); -} - -uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEUL, MMU_USER_IDX); - uint32_t ret; - - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D ldl_le_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); - return ret; -} - -uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEQ, MMU_USER_IDX); + void *haddr; uint64_t ret; =20 - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D ldq_le_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_LEQ); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D ldq_le_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retadd= r) +void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, + MemOpIdx oi, uintptr_t ra) { - uint32_t ret; + void *haddr; =20 - set_helper_retaddr(retaddr); - ret =3D cpu_ldub_data(env, ptr); + validate_memop(oi, MO_UB); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stb_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) +void cpu_stw_be_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, + MemOpIdx oi, uintptr_t ra) { - return (int8_t)cpu_ldub_data_ra(env, ptr, retaddr); -} + void *haddr; =20 -uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ret= addr) -{ - uint32_t ret; - - set_helper_retaddr(retaddr); - ret =3D cpu_lduw_be_data(env, ptr); + validate_memop(oi, MO_BEUW); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stw_be_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) +void cpu_stl_be_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_be_data_ra(env, ptr, retaddr); -} + void *haddr; =20 -uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t reta= ddr) -{ - uint32_t ret; - - set_helper_retaddr(retaddr); - ret =3D cpu_ldl_be_data(env, ptr); + validate_memop(oi, MO_BEUL); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stl_be_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t reta= ddr) +void cpu_stq_be_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, + MemOpIdx oi, uintptr_t ra) { - uint64_t ret; + void *haddr; =20 - set_helper_retaddr(retaddr); - ret =3D cpu_ldq_be_data(env, ptr); + validate_memop(oi, MO_BEQ); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stq_be_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ret= addr) +void cpu_stw_le_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, + MemOpIdx oi, uintptr_t ra) { - uint32_t ret; + void *haddr; =20 - set_helper_retaddr(retaddr); - ret =3D cpu_lduw_le_data(env, ptr); + validate_memop(oi, MO_LEUW); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stw_le_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) +void cpu_stl_le_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_le_data_ra(env, ptr, retaddr); -} + void *haddr; =20 -uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t reta= ddr) -{ - uint32_t ret; - - set_helper_retaddr(retaddr); - ret =3D cpu_ldl_le_data(env, ptr); + validate_memop(oi, MO_LEUL); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stl_le_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t reta= ddr) +void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, + MemOpIdx oi, uintptr_t ra) { - uint64_t ret; + void *haddr; =20 - set_helper_retaddr(retaddr); - ret =3D cpu_ldq_le_data(env, ptr); - clear_helper_retaddr(); - return ret; -} - -void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_UB, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stb_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUW, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stw_be_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUL, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stl_be_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEQ, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stq_be_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEUW, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stw_le_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEUL, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stl_le_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEQ, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stq_le_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stb_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stw_be_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stl_be_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr, - uint64_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stq_be_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stw_le_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stl_le_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr, - uint64_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stq_le_data(env, ptr, val); + validate_memop(oi, MO_LEQ); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stq_le_p(haddr, val); clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) @@ -1222,6 +1149,8 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) return ret; } =20 +#include "ldst_common.c.inc" + /* * Do not allow unaligned operations to proceed. Return the host address. * diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc new file mode 100644 index 0000000000..bfefb275e7 --- /dev/null +++ b/accel/tcg/ldst_common.c.inc @@ -0,0 +1,307 @@ +/* + * Routines common to user and system emulation of load/store. + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + return cpu_ldb_mmu(env, addr, oi, ra); +} + +int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra); +} + +uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx); + return cpu_ldw_be_mmu(env, addr, oi, ra); +} + +int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra); +} + +uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx); + return cpu_ldl_be_mmu(env, addr, oi, ra); +} + +uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEQ | MO_UNALN, mmu_idx); + return cpu_ldq_be_mmu(env, addr, oi, ra); +} + +uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx); + return cpu_ldw_le_mmu(env, addr, oi, ra); +} + +int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra); +} + +uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx); + return cpu_ldl_le_mmu(env, addr, oi, ra); +} + +uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEQ | MO_UNALN, mmu_idx); + return cpu_ldq_le_mmu(env, addr, oi, ra); +} + +void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + cpu_stb_mmu(env, addr, val, oi, ra); +} + +void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx); + cpu_stw_be_mmu(env, addr, val, oi, ra); +} + +void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx); + cpu_stl_be_mmu(env, addr, val, oi, ra); +} + +void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEQ | MO_UNALN, mmu_idx); + cpu_stq_be_mmu(env, addr, val, oi, ra); +} + +void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx); + cpu_stw_le_mmu(env, addr, val, oi, ra); +} + +void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx); + cpu_stl_le_mmu(env, addr, val, oi, ra); +} + +void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEQ | MO_UNALN, mmu_idx); + cpu_stq_le_mmu(env, addr, val, oi, ra); +} + +/*--------------------------*/ + +uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldub_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return (int8_t)cpu_ldub_data_ra(env, addr, ra); +} + +uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_lduw_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return (int16_t)cpu_lduw_be_data_ra(env, addr, ra); +} + +uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldl_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldq_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_lduw_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return (int16_t)cpu_lduw_le_data_ra(env, addr, ra); +} + +uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldl_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldq_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +void cpu_stb_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stb_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stw_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stl_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr, + uint64_t val, uintptr_t ra) +{ + cpu_stq_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stw_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stl_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr, + uint64_t val, uintptr_t ra) +{ + cpu_stq_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +/*--------------------------*/ + +uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldub_data_ra(env, addr, 0); +} + +int cpu_ldsb_data(CPUArchState *env, abi_ptr addr) +{ + return (int8_t)cpu_ldub_data(env, addr); +} + +uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_lduw_be_data_ra(env, addr, 0); +} + +int cpu_ldsw_be_data(CPUArchState *env, abi_ptr addr) +{ + return (int16_t)cpu_lduw_be_data(env, addr); +} + +uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldl_be_data_ra(env, addr, 0); +} + +uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldq_be_data_ra(env, addr, 0); +} + +uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_lduw_le_data_ra(env, addr, 0); +} + +int cpu_ldsw_le_data(CPUArchState *env, abi_ptr addr) +{ + return (int16_t)cpu_lduw_le_data(env, addr); +} + +uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldl_le_data_ra(env, addr, 0); +} + +uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldq_le_data_ra(env, addr, 0); +} + +void cpu_stb_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stb_data_ra(env, addr, val, 0); +} + +void cpu_stw_be_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stw_be_data_ra(env, addr, val, 0); +} + +void cpu_stl_be_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stl_be_data_ra(env, addr, val, 0); +} + +void cpu_stq_be_data(CPUArchState *env, abi_ptr addr, uint64_t val) +{ + cpu_stq_be_data_ra(env, addr, val, 0); +} + +void cpu_stw_le_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stw_le_data_ra(env, addr, val, 0); +} + +void cpu_stl_le_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stl_le_data_ra(env, addr, val, 0); +} + +void cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint64_t val) +{ + cpu_stq_le_data_ra(env, addr, val, 0); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1634149746584100001 The previous placement in tcg/tcg.h was not logical. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 87 +++++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 87 ----------------------------------- target/arm/helper-a64.c | 1 - target/m68k/op_helper.c | 1 - target/ppc/mem_helper.c | 1 - target/s390x/tcg/mem_helper.c | 1 - 6 files changed, 87 insertions(+), 91 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index a4dad0772f..a878fd0105 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -63,6 +63,7 @@ #define CPU_LDST_H =20 #include "exec/memopidx.h" +#include "qemu/int128.h" =20 #if defined(CONFIG_USER_ONLY) /* sparc32plus has 64bit long but 32bit space address @@ -233,6 +234,92 @@ void cpu_stl_le_mmu(CPUArchState *env, abi_ptr ptr, ui= nt32_t val, void cpu_stq_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, MemOpIdx oi, uintptr_t ra); =20 +uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, + uint64_t cmpv, uint64_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, + uint64_t cmpv, uint64_t newv, + MemOpIdx oi, uintptr_t retaddr); + +#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ +TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ + (CPUArchState *env, target_ulong addr, TYPE val, \ + MemOpIdx oi, uintptr_t retaddr); + +#ifdef CONFIG_ATOMIC64 +#define GEN_ATOMIC_HELPER_ALL(NAME) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ + GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ + GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) +#else +#define GEN_ATOMIC_HELPER_ALL(NAME) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) +#endif + +GEN_ATOMIC_HELPER_ALL(fetch_add) +GEN_ATOMIC_HELPER_ALL(fetch_sub) +GEN_ATOMIC_HELPER_ALL(fetch_and) +GEN_ATOMIC_HELPER_ALL(fetch_or) +GEN_ATOMIC_HELPER_ALL(fetch_xor) +GEN_ATOMIC_HELPER_ALL(fetch_smin) +GEN_ATOMIC_HELPER_ALL(fetch_umin) +GEN_ATOMIC_HELPER_ALL(fetch_smax) +GEN_ATOMIC_HELPER_ALL(fetch_umax) + +GEN_ATOMIC_HELPER_ALL(add_fetch) +GEN_ATOMIC_HELPER_ALL(sub_fetch) +GEN_ATOMIC_HELPER_ALL(and_fetch) +GEN_ATOMIC_HELPER_ALL(or_fetch) +GEN_ATOMIC_HELPER_ALL(xor_fetch) +GEN_ATOMIC_HELPER_ALL(smin_fetch) +GEN_ATOMIC_HELPER_ALL(umin_fetch) +GEN_ATOMIC_HELPER_ALL(smax_fetch) +GEN_ATOMIC_HELPER_ALL(umax_fetch) + +GEN_ATOMIC_HELPER_ALL(xchg) + +#undef GEN_ATOMIC_HELPER_ALL +#undef GEN_ATOMIC_HELPER + +Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, + MemOpIdx oi, uintptr_t retaddr); +Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, + MemOpIdx oi, uintptr_t retaddr); + +Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, + MemOpIdx oi, uintptr_t retaddr); +void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, + MemOpIdx oi, uintptr_t retaddr); + #if defined(CONFIG_USER_ONLY) =20 extern __thread uintptr_t helper_retaddr; diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 9f398b9afe..83e38487cf 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -33,7 +33,6 @@ #include "qemu/queue.h" #include "tcg/tcg-mo.h" #include "tcg-target.h" -#include "qemu/int128.h" #include "tcg/tcg-cond.h" =20 /* XXX: make safe guess about sizes */ @@ -1312,92 +1311,6 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulo= ng addr, uint64_t val, #endif #endif /* CONFIG_SOFTMMU */ =20 -uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, - uint64_t cmpv, uint64_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, - uint64_t cmpv, uint64_t newv, - MemOpIdx oi, uintptr_t retaddr); - -#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ -TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ - (CPUArchState *env, target_ulong addr, TYPE val, \ - MemOpIdx oi, uintptr_t retaddr); - -#ifdef CONFIG_ATOMIC64 -#define GEN_ATOMIC_HELPER_ALL(NAME) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ - GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ - GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) -#else -#define GEN_ATOMIC_HELPER_ALL(NAME) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) -#endif - -GEN_ATOMIC_HELPER_ALL(fetch_add) -GEN_ATOMIC_HELPER_ALL(fetch_sub) -GEN_ATOMIC_HELPER_ALL(fetch_and) -GEN_ATOMIC_HELPER_ALL(fetch_or) -GEN_ATOMIC_HELPER_ALL(fetch_xor) -GEN_ATOMIC_HELPER_ALL(fetch_smin) -GEN_ATOMIC_HELPER_ALL(fetch_umin) -GEN_ATOMIC_HELPER_ALL(fetch_smax) -GEN_ATOMIC_HELPER_ALL(fetch_umax) - -GEN_ATOMIC_HELPER_ALL(add_fetch) -GEN_ATOMIC_HELPER_ALL(sub_fetch) -GEN_ATOMIC_HELPER_ALL(and_fetch) -GEN_ATOMIC_HELPER_ALL(or_fetch) -GEN_ATOMIC_HELPER_ALL(xor_fetch) -GEN_ATOMIC_HELPER_ALL(smin_fetch) -GEN_ATOMIC_HELPER_ALL(umin_fetch) -GEN_ATOMIC_HELPER_ALL(smax_fetch) -GEN_ATOMIC_HELPER_ALL(umax_fetch) - -GEN_ATOMIC_HELPER_ALL(xchg) - -#undef GEN_ATOMIC_HELPER_ALL -#undef GEN_ATOMIC_HELPER - -Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, - Int128 cmpv, Int128 newv, - MemOpIdx oi, uintptr_t retaddr); -Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, - Int128 cmpv, Int128 newv, - MemOpIdx oi, uintptr_t retaddr); - -Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, - MemOpIdx oi, uintptr_t retaddr); -void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, - MemOpIdx oi, uintptr_t retaddr); - #ifdef CONFIG_DEBUG_TCG void tcg_assert_listed_vecop(TCGOpcode); #else diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 4cafd3c11a..b110c57956 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -32,7 +32,6 @@ #include "exec/cpu_ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" -#include "tcg/tcg.h" #include "fpu/softfloat.h" #include /* For crc32 */ =20 diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index c1bf73b6f9..cfbc987ba6 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -22,7 +22,6 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "semihosting/semihost.h" -#include "tcg/tcg.h" =20 #if !defined(CONFIG_USER_ONLY) =20 diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index e2282baa8d..39945d9ea5 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -25,7 +25,6 @@ #include "exec/helper-proto.h" #include "helper_regs.h" #include "exec/cpu_ldst.h" -#include "tcg/tcg.h" #include "internal.h" #include "qemu/atomic128.h" =20 diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index e64d1bc725..251d4acf55 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -27,7 +27,6 @@ #include "exec/cpu_ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" -#include "tcg/tcg.h" #include "trace.h" =20 #if !defined(CONFIG_USER_ONLY) --=20 2.25.1 From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1634150011206100001 We should not have been using the helper_ret_* set of functions, as they are supposed to be private to tcg. Nor should we have been using the plain cpu_*_data set of functions, as they do not handle unwinding properly. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/tcg/msa_helper.c | 420 +++++++++++------------------------ 1 file changed, 135 insertions(+), 285 deletions(-) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 167d9a591c..a8880ce81c 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8222,79 +8222,42 @@ void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_BYTE) -#if !defined(CONFIG_USER_ONLY) + uintptr_t ra =3D GETPC(); + #if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); - pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); - pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); - pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); - pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); - pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); - pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); - pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); - pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); - pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); - pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); - pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); - pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); - pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); - pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); - pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); + pwd->b[0] =3D cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); + pwd->b[1] =3D cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); + pwd->b[2] =3D cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); + pwd->b[3] =3D cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); + pwd->b[4] =3D cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); + pwd->b[5] =3D cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); + pwd->b[6] =3D cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); + pwd->b[7] =3D cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); + pwd->b[8] =3D cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); + pwd->b[9] =3D cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); + pwd->b[10] =3D cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); + pwd->b[11] =3D cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); + pwd->b[12] =3D cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); + pwd->b[13] =3D cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); + pwd->b[14] =3D cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); + pwd->b[15] =3D cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); #else - pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); - pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); - pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); - pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); - pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); - pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); - pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); - pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); - pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); - pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); - pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); - pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); - pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); - pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); - pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); - pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); - pwd->b[1] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); - pwd->b[2] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); - pwd->b[3] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); - pwd->b[4] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); - pwd->b[5] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); - pwd->b[6] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); - pwd->b[7] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); - pwd->b[8] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); - pwd->b[9] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); - pwd->b[10] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); - pwd->b[11] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); - pwd->b[12] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); - pwd->b[13] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); - pwd->b[14] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); - pwd->b[15] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); -#else - pwd->b[0] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); - pwd->b[1] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); - pwd->b[2] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); - pwd->b[3] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); - pwd->b[4] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); - pwd->b[5] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); - pwd->b[6] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); - pwd->b[7] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); - pwd->b[8] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); - pwd->b[9] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); - pwd->b[10] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); - pwd->b[11] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); - pwd->b[12] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); - pwd->b[13] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); - pwd->b[14] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); - pwd->b[15] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); -#endif + pwd->b[0] =3D cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); + pwd->b[1] =3D cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); + pwd->b[2] =3D cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); + pwd->b[3] =3D cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); + pwd->b[4] =3D cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); + pwd->b[5] =3D cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); + pwd->b[6] =3D cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); + pwd->b[7] =3D cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); + pwd->b[8] =3D cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); + pwd->b[9] =3D cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); + pwd->b[10] =3D cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); + pwd->b[11] =3D cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); + pwd->b[12] =3D cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); + pwd->b[13] =3D cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); + pwd->b[14] =3D cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); + pwd->b[15] =3D cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); #endif } =20 @@ -8302,47 +8265,26 @@ void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_HALF) -#if !defined(CONFIG_USER_ONLY) + uintptr_t ra =3D GETPC(); + #if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); - pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); - pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); - pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); - pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); - pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); - pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); - pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); + pwd->h[0] =3D cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); + pwd->h[1] =3D cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); + pwd->h[2] =3D cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); + pwd->h[3] =3D cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); + pwd->h[4] =3D cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); + pwd->h[5] =3D cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); + pwd->h[6] =3D cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); + pwd->h[7] =3D cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); #else - pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); - pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); - pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); - pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); - pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); - pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); - pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); - pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); - pwd->h[1] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); - pwd->h[2] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); - pwd->h[3] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); - pwd->h[4] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); - pwd->h[5] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); - pwd->h[6] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); - pwd->h[7] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); -#else - pwd->h[0] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); - pwd->h[1] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); - pwd->h[2] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); - pwd->h[3] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); - pwd->h[4] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); - pwd->h[5] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); - pwd->h[6] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); - pwd->h[7] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); -#endif + pwd->h[0] =3D cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); + pwd->h[1] =3D cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); + pwd->h[2] =3D cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); + pwd->h[3] =3D cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); + pwd->h[4] =3D cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); + pwd->h[5] =3D cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); + pwd->h[6] =3D cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); + pwd->h[7] =3D cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); #endif } =20 @@ -8350,31 +8292,18 @@ void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_WORD) -#if !defined(CONFIG_USER_ONLY) + uintptr_t ra =3D GETPC(); + #if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); - pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); - pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); - pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); + pwd->w[0] =3D cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); + pwd->w[1] =3D cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); + pwd->w[2] =3D cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); + pwd->w[3] =3D cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); #else - pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); - pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); - pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); - pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); - pwd->w[1] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); - pwd->w[2] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); - pwd->w[3] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); -#else - pwd->w[0] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); - pwd->w[1] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); - pwd->w[2] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); - pwd->w[3] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); -#endif + pwd->w[0] =3D cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); + pwd->w[1] =3D cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); + pwd->w[2] =3D cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); + pwd->w[3] =3D cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); #endif } =20 @@ -8382,14 +8311,10 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_DOUBLE) -#if !defined(CONFIG_USER_ONLY) - pwd->d[0] =3D helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GET= PC()); - pwd->d[1] =3D helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GET= PC()); -#else - pwd->d[0] =3D cpu_ldq_data(env, addr + (0 << DF_DOUBLE)); - pwd->d[1] =3D cpu_ldq_data(env, addr + (1 << DF_DOUBLE)); -#endif + uintptr_t ra =3D GETPC(); + + pwd->d[0] =3D cpu_ldq_data_ra(env, addr + (0 << DF_DOUBLE), ra); + pwd->d[1] =3D cpu_ldq_data_ra(env, addr + (1 << DF_DOUBLE), ra); } =20 #define MSA_PAGESPAN(x) \ @@ -8415,81 +8340,44 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D cpu_mmu_index(env, false); + uintptr_t ra =3D GETPC(); + + ensure_writable_pages(env, addr, mmu_idx, ra); =20 - MEMOP_IDX(DF_BYTE) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) #if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC(= )); + cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[0], ra); + cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[1], ra); + cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[2], ra); + cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[3], ra); + cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[4], ra); + cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[5], ra); + cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[6], ra); + cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[7], ra); + cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[8], ra); + cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[9], ra); + cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[10], ra); + cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[11], ra); + cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[12], ra); + cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[13], ra); + cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[14], ra); + cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[15], ra); #else - helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC(= )); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]); - cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]); - cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]); - cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]); - cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]); - cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]); - cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]); - cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]); - cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]); - cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]); - cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]); - cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]); - cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]); - cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]); - cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]); - cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]); -#else - cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]); - cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]); - cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]); - cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]); - cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]); - cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]); - cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]); - cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]); - cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]); - cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]); - cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]); - cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]); - cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]); - cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]); - cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]); - cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]); -#endif + cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[0], ra); + cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[1], ra); + cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[2], ra); + cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[3], ra); + cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[4], ra); + cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[5], ra); + cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[6], ra); + cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[7], ra); + cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[8], ra); + cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[9], ra); + cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[10], ra); + cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[11], ra); + cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[12], ra); + cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[13], ra); + cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[14], ra); + cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[15], ra); #endif } =20 @@ -8498,49 +8386,28 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D cpu_mmu_index(env, false); + uintptr_t ra =3D GETPC(); + + ensure_writable_pages(env, addr, mmu_idx, ra); =20 - MEMOP_IDX(DF_HALF) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) #if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC()); + cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[0], ra); + cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[1], ra); + cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[2], ra); + cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[3], ra); + cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[4], ra); + cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[5], ra); + cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[6], ra); + cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[7], ra); #else - helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]); - cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]); - cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]); - cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]); - cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]); - cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]); - cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]); - cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]); -#else - cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]); - cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]); - cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]); - cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]); - cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]); - cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]); - cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]); - cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]); -#endif + cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[0], ra); + cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[1], ra); + cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[2], ra); + cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[3], ra); + cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[4], ra); + cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[5], ra); + cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[6], ra); + cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[7], ra); #endif } =20 @@ -8549,33 +8416,20 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D cpu_mmu_index(env, false); + uintptr_t ra =3D GETPC(); + + ensure_writable_pages(env, addr, mmu_idx, ra); =20 - MEMOP_IDX(DF_WORD) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) #if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC()); + cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[0], ra); + cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[1], ra); + cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[2], ra); + cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[3], ra); #else - helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]); - cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]); - cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]); - cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]); -#else - cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]); - cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]); - cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]); - cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]); -#endif + cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[0], ra); + cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[1], ra); + cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[2], ra); + cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[3], ra); #endif } =20 @@ -8584,14 +8438,10 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D cpu_mmu_index(env, false); + uintptr_t ra =3D GETPC(); =20 - MEMOP_IDX(DF_DOUBLE) ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) - helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC(= )); - helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC(= )); -#else - cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]); - cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); -#endif + + cpu_stq_data_ra(env, addr + (0 << DF_DOUBLE), pwd->d[0], ra); + cpu_stq_data_ra(env, addr + (1 << DF_DOUBLE), pwd->d[1], ra); } --=20 2.25.1 From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1634149726882100005 Rather than use 4-16 separate operations, use 2 operations plus some byte reordering as necessary. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/tcg/msa_helper.c | 201 +++++++++++++---------------------- 1 file changed, 71 insertions(+), 130 deletions(-) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index a8880ce81c..e40c1b7057 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8218,47 +8218,31 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint3= 2_t df, uint32_t wd, #define MEMOP_IDX(DF) #endif =20 +#ifdef TARGET_WORDS_BIGENDIAN +static inline uint64_t bswap16x4(uint64_t x) +{ + uint64_t m =3D 0x00ff00ff00ff00ffull; + return ((x & m) << 8) | ((x >> 8) & m); +} + +static inline uint64_t bswap32x2(uint64_t x) +{ + return ror64(bswap64(x), 32); +} +#endif + void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] =3D cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); - pwd->b[1] =3D cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); - pwd->b[2] =3D cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); - pwd->b[3] =3D cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); - pwd->b[4] =3D cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); - pwd->b[5] =3D cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); - pwd->b[6] =3D cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); - pwd->b[7] =3D cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); - pwd->b[8] =3D cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); - pwd->b[9] =3D cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); - pwd->b[10] =3D cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); - pwd->b[11] =3D cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); - pwd->b[12] =3D cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); - pwd->b[13] =3D cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); - pwd->b[14] =3D cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); - pwd->b[15] =3D cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); -#else - pwd->b[0] =3D cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); - pwd->b[1] =3D cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); - pwd->b[2] =3D cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); - pwd->b[3] =3D cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); - pwd->b[4] =3D cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); - pwd->b[5] =3D cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); - pwd->b[6] =3D cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); - pwd->b[7] =3D cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); - pwd->b[8] =3D cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); - pwd->b[9] =3D cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); - pwd->b[10] =3D cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); - pwd->b[11] =3D cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); - pwd->b[12] =3D cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); - pwd->b[13] =3D cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); - pwd->b[14] =3D cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); - pwd->b[15] =3D cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); -#endif + /* Load 8 bytes at a time. Vector element ordering makes this LE. */ + d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); + pwd->d[0] =3D d0; + pwd->d[1] =3D d1; } =20 void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, @@ -8266,26 +8250,20 @@ void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] =3D cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); - pwd->h[1] =3D cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); - pwd->h[2] =3D cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); - pwd->h[3] =3D cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); - pwd->h[4] =3D cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); - pwd->h[5] =3D cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); - pwd->h[6] =3D cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); - pwd->h[7] =3D cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); -#else - pwd->h[0] =3D cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); - pwd->h[1] =3D cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); - pwd->h[2] =3D cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); - pwd->h[3] =3D cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); - pwd->h[4] =3D cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); - pwd->h[5] =3D cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); - pwd->h[6] =3D cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); - pwd->h[7] =3D cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); + /* + * Load 8 bytes at a time. Use little-endian load, then for + * big-endian target, we must then swap the four halfwords. + */ + d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); +#ifdef TARGET_WORDS_BIGENDIAN + d0 =3D bswap16x4(d0); + d1 =3D bswap16x4(d1); #endif + pwd->d[0] =3D d0; + pwd->d[1] =3D d1; } =20 void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, @@ -8293,18 +8271,20 @@ void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] =3D cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); - pwd->w[1] =3D cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); - pwd->w[2] =3D cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); - pwd->w[3] =3D cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); -#else - pwd->w[0] =3D cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); - pwd->w[1] =3D cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); - pwd->w[2] =3D cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); - pwd->w[3] =3D cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); + /* + * Load 8 bytes at a time. Use little-endian load, then for + * big-endian target, we must then bswap the two words. + */ + d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); +#ifdef TARGET_WORDS_BIGENDIAN + d0 =3D bswap32x2(d0); + d1 =3D bswap32x2(d1); #endif + pwd->d[0] =3D d0; + pwd->d[1] =3D d1; } =20 void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, @@ -8312,9 +8292,12 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 - pwd->d[0] =3D cpu_ldq_data_ra(env, addr + (0 << DF_DOUBLE), ra); - pwd->d[1] =3D cpu_ldq_data_ra(env, addr + (1 << DF_DOUBLE), ra); + d0 =3D cpu_ldq_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_data_ra(env, addr + 8, ra); + pwd->d[0] =3D d0; + pwd->d[1] =3D d1; } =20 #define MSA_PAGESPAN(x) \ @@ -8344,41 +8327,9 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, =20 ensure_writable_pages(env, addr, mmu_idx, ra); =20 -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[0], ra); - cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[1], ra); - cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[2], ra); - cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[3], ra); - cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[4], ra); - cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[5], ra); - cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[6], ra); - cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[7], ra); - cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[8], ra); - cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[9], ra); - cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[10], ra); - cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[11], ra); - cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[12], ra); - cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[13], ra); - cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[14], ra); - cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[15], ra); -#else - cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[0], ra); - cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[1], ra); - cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[2], ra); - cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[3], ra); - cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[4], ra); - cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[5], ra); - cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[6], ra); - cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[7], ra); - cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[8], ra); - cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[9], ra); - cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[10], ra); - cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[11], ra); - cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[12], ra); - cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[13], ra); - cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[14], ra); - cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[15], ra); -#endif + /* Store 8 bytes at a time. Vector element ordering makes this LE. */ + cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra); + cpu_stq_le_data_ra(env, addr + 0, pwd->d[1], ra); } =20 void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, @@ -8387,28 +8338,19 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D cpu_mmu_index(env, false); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 ensure_writable_pages(env, addr, mmu_idx, ra); =20 -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[0], ra); - cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[1], ra); - cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[2], ra); - cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[3], ra); - cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[4], ra); - cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[5], ra); - cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[6], ra); - cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[7], ra); -#else - cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[0], ra); - cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[1], ra); - cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[2], ra); - cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[3], ra); - cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[4], ra); - cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[5], ra); - cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[6], ra); - cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[7], ra); + /* Store 8 bytes at a time. See helper_msa_ld_h. */ + d0 =3D pwd->d[0]; + d1 =3D pwd->d[1]; +#ifdef TARGET_WORDS_BIGENDIAN + d0 =3D bswap16x4(d0); + d1 =3D bswap16x4(d1); #endif + cpu_stq_le_data_ra(env, addr + 0, d0, ra); + cpu_stq_le_data_ra(env, addr + 8, d1, ra); } =20 void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, @@ -8417,20 +8359,19 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D cpu_mmu_index(env, false); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 ensure_writable_pages(env, addr, mmu_idx, ra); =20 -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[0], ra); - cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[1], ra); - cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[2], ra); - cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[3], ra); -#else - cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[0], ra); - cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[1], ra); - cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[2], ra); - cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[3], ra); + /* Store 8 bytes at a time. See helper_msa_ld_w. */ + d0 =3D pwd->d[0]; + d1 =3D pwd->d[1]; +#ifdef TARGET_WORDS_BIGENDIAN + d0 =3D bswap32x2(d0); + d1 =3D bswap32x2(d1); #endif + cpu_stq_le_data_ra(env, addr + 0, d0, ra); + cpu_stq_le_data_ra(env, addr + 8, d1, ra); } =20 void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, @@ -8442,6 +8383,6 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, =20 ensure_writable_pages(env, addr, mmu_idx, GETPC()); =20 - cpu_stq_data_ra(env, addr + (0 << DF_DOUBLE), pwd->d[0], ra); - cpu_stq_data_ra(env, addr + (1 << DF_DOUBLE), pwd->d[1], ra); + cpu_stq_data_ra(env, addr + 0, pwd->d[0], ra); + cpu_stq_data_ra(env, addr + 8, pwd->d[1], ra); } --=20 2.25.1 From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634150274571722.5058432471252; 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Wed, 13 Oct 2021 11:22:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 11/15] target/s390x: Use cpu_*_mmu instead of helper_*_mmu Date: Wed, 13 Oct 2021 11:22:35 -0700 Message-Id: <20211013182239.991127-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013182239.991127-1-richard.henderson@linaro.org> References: <20211013182239.991127-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634150276996100001 The helper_*_mmu functions were the only thing available when this code was written. This could have been adjusted when we added cpu_*_mmuidx_ra, but now we can most easily use the newest set of interfaces. Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 251d4acf55..17e3f83641 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -249,13 +249,13 @@ static void do_access_memset(CPUS390XState *env, vadd= r vaddr, char *haddr, * page. This is especially relevant to speed up TLB_NOTDIRTY. */ g_assert(size > 0); - helper_ret_stb_mmu(env, vaddr, byte, oi, ra); + cpu_stb_mmu(env, vaddr, byte, oi, ra); haddr =3D tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx); if (likely(haddr)) { memset(haddr + 1, byte, size - 1); } else { for (i =3D 1; i < size; i++) { - helper_ret_stb_mmu(env, vaddr + i, byte, oi, ra); + cpu_stb_mmu(env, vaddr + i, byte, oi, ra); } } } @@ -291,7 +291,7 @@ static uint8_t do_access_get_byte(CPUS390XState *env, v= addr vaddr, char **haddr, * Do a single access and test if we can then get access to the * page. This is especially relevant to speed up TLB_NOTDIRTY. */ - byte =3D helper_ret_ldub_mmu(env, vaddr + offset, oi, ra); + byte =3D cpu_ldb_mmu(env, vaddr + offset, oi, ra); *haddr =3D tlb_vaddr_to_host(env, vaddr, MMU_DATA_LOAD, mmu_idx); return byte; #endif @@ -325,7 +325,7 @@ static void do_access_set_byte(CPUS390XState *env, vadd= r vaddr, char **haddr, * Do a single access and test if we can then get access to the * page. This is especially relevant to speed up TLB_NOTDIRTY. */ - helper_ret_stb_mmu(env, vaddr + offset, byte, oi, ra); + cpu_stb_mmu(env, vaddr + offset, byte, oi, ra); *haddr =3D tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx); #endif } --=20 2.25.1 From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1634149891; cv=none; d=zohomail.com; s=zohoarc; b=QRxMSeFQIGFtDeuZwsrm4Vw0V4gf2kdcG8+oGuqBulmT/24baAWj644u19Kxh4wixHo7tl/BR1JEAhKfIv3Ux9pp/DeyCSbgQghT7ic38qJwfFpLvmy2I7OJg2nq+zJMnlaDiiX5TfpHYGbkWAcqpiA0AeA7w1qWAyuzZSTCM+k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634149891; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1634149894447100001 The helper_*_mmu functions were the only thing available when this code was written. This could have been adjusted when we added cpu_*_mmuidx_ra, but now we can most easily use the newest set of interfaces. Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index abe2889d27..bbf3601cb1 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1333,27 +1333,27 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_u= long addr, oi =3D make_memop_idx(memop, idx); switch (size) { case 1: - ret =3D helper_ret_ldub_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldb_mmu(env, addr, oi, GETPC()); break; case 2: if (asi & 8) { - ret =3D helper_le_lduw_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldw_le_mmu(env, addr, oi, GETPC()); } else { - ret =3D helper_be_lduw_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldw_be_mmu(env, addr, oi, GETPC()); } break; case 4: if (asi & 8) { - ret =3D helper_le_ldul_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldl_le_mmu(env, addr, oi, GETPC()); } else { - ret =3D helper_be_ldul_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldl_be_mmu(env, addr, oi, GETPC()); } break; case 8: if (asi & 8) { - ret =3D helper_le_ldq_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldq_le_mmu(env, addr, oi, GETPC()); } else { - ret =3D helper_be_ldq_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldq_be_mmu(env, addr, oi, GETPC()); } break; default: --=20 2.25.1 From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1634150504; cv=none; d=zohomail.com; s=zohoarc; b=JhpjnYfOeYHt5s/Cm8FqIrmXoZBp97oyUDoVD8bw3gL2jLQtoT69xdm9C7wHXLQeHJ7Nr6e5iffyjmw+QJP4+Dqm3fZ5xYJc4O6eqTsRnLbMpq19fBzfzi+Sd6T6VAz+Ogw4hBfsbg/KRYMLyCJH2Cpj95eHaU0gz9P7VscReU4= ARC-Message-Signature: i=1; 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Wed, 13 Oct 2021 11:22:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 13/15] target/arm: Use cpu_*_mmu instead of helper_*_mmu Date: Wed, 13 Oct 2021 11:22:37 -0700 Message-Id: <20211013182239.991127-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013182239.991127-1-richard.henderson@linaro.org> References: <20211013182239.991127-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1634150505777100001 The helper_*_mmu functions were the only thing available when this code was written. This could have been adjusted when we added cpu_*_mmuidx_ra, but now we can most easily use the newest set of interfaces. Cc: qemu-arm@nongnu.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 52 +++++++---------------------------------- target/arm/m_helper.c | 6 ++--- 2 files changed, 11 insertions(+), 47 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index b110c57956..5ae2ecb0f3 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -512,37 +512,19 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env= , uint64_t addr, uintptr_t ra =3D GETPC(); uint64_t o0, o1; bool success; - -#ifdef CONFIG_USER_ONLY - /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(env_cpu(env), addr); - - set_helper_retaddr(ra); - o0 =3D ldq_le_p(haddr + 0); - o1 =3D ldq_le_p(haddr + 1); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - stq_le_p(haddr + 0, int128_getlo(newv)); - stq_le_p(haddr + 1, int128_gethi(newv)); - } - clear_helper_retaddr(); -#else int mem_idx =3D cpu_mmu_index(env, false); MemOpIdx oi0 =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); MemOpIdx oi1 =3D make_memop_idx(MO_LEQ, mem_idx); =20 - o0 =3D helper_le_ldq_mmu(env, addr + 0, oi0, ra); - o1 =3D helper_le_ldq_mmu(env, addr + 8, oi1, ra); + o0 =3D cpu_ldq_le_mmu(env, addr + 0, oi0, ra); + o1 =3D cpu_ldq_le_mmu(env, addr + 8, oi1, ra); oldv =3D int128_make128(o0, o1); =20 success =3D int128_eq(oldv, cmpv); if (success) { - helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); - helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); + cpu_stq_le_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); + cpu_stq_le_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); } -#endif =20 return !success; } @@ -582,37 +564,19 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env= , uint64_t addr, uintptr_t ra =3D GETPC(); uint64_t o0, o1; bool success; - -#ifdef CONFIG_USER_ONLY - /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(env_cpu(env), addr); - - set_helper_retaddr(ra); - o1 =3D ldq_be_p(haddr + 0); - o0 =3D ldq_be_p(haddr + 1); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - stq_be_p(haddr + 0, int128_gethi(newv)); - stq_be_p(haddr + 1, int128_getlo(newv)); - } - clear_helper_retaddr(); -#else int mem_idx =3D cpu_mmu_index(env, false); MemOpIdx oi0 =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); MemOpIdx oi1 =3D make_memop_idx(MO_BEQ, mem_idx); =20 - o1 =3D helper_be_ldq_mmu(env, addr + 0, oi0, ra); - o0 =3D helper_be_ldq_mmu(env, addr + 8, oi1, ra); + o1 =3D cpu_ldq_be_mmu(env, addr + 0, oi0, ra); + o0 =3D cpu_ldq_be_mmu(env, addr + 8, oi1, ra); oldv =3D int128_make128(o0, o1); =20 success =3D int128_eq(oldv, cmpv); if (success) { - helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); - helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); + cpu_stq_be_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); + cpu_stq_be_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); } -#endif =20 return !success; } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 62aa12c9d8..2c9922dc29 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1947,9 +1947,9 @@ static bool do_v7m_function_return(ARMCPU *cpu) * do them as secure, so work out what MMU index that is. */ mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, true); - oi =3D make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx)); - newpc =3D helper_le_ldul_mmu(env, frameptr, oi, 0); - newpsr =3D helper_le_ldul_mmu(env, frameptr + 4, oi, 0); + oi =3D make_memop_idx(MO_LEUL, arm_to_core_mmu_idx(mmu_idx)); + newpc =3D cpu_ldl_le_mmu(env, frameptr, oi, 0); + newpsr =3D cpu_ldl_le_mmu(env, frameptr + 4, oi, 0); =20 /* Consistency checks on new IPSR */ newpsr_exc =3D newpsr & XPSR_EXCP; --=20 2.25.1 From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 13 Oct 2021 11:22:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 14/15] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h Date: Wed, 13 Oct 2021 11:22:38 -0700 Message-Id: <20211013182239.991127-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013182239.991127-1-richard.henderson@linaro.org> References: <20211013182239.991127-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1634149917134100001 These functions have been replaced by cpu_*_mmu as the most proper interface to use from target code. Hide these declarations from code that should not use them. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 74 ++++++++++++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 71 ---------------------------------------- accel/tcg/cputlb.c | 1 + tcg/tcg.c | 1 + tcg/tci.c | 1 + 5 files changed, 77 insertions(+), 71 deletions(-) create mode 100644 include/tcg/tcg-ldst.h diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h new file mode 100644 index 0000000000..8c86365611 --- /dev/null +++ b/include/tcg/tcg-ldst.h @@ -0,0 +1,74 @@ +/* + * Memory helpers that will be used by TCG generated code. + * + * Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef TCG_LDST_H +#define TCG_LDST_H 1 + +#ifdef CONFIG_SOFTMMU + +/* Value zero-extended to tcg register size. */ +tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); + +/* Value sign-extended to tcg register size. */ +tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); + +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr); + +#endif /* CONFIG_SOFTMMU */ +#endif /* TCG_LDST_H */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 83e38487cf..7069a401f1 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1240,77 +1240,6 @@ uint64_t dup_const(unsigned vece, uint64_t c); : (target_long)dup_const(VECE, C)) #endif =20 -/* - * Memory helpers that will be used by TCG generated code. - */ -#ifdef CONFIG_SOFTMMU -/* Value zero-extended to tcg register size. */ -tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); - -/* Value sign-extended to tcg register size. */ -tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); - -void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr); - -/* Temporary aliases until backends are converted. */ -#ifdef TARGET_WORDS_BIGENDIAN -# define helper_ret_ldsw_mmu helper_be_ldsw_mmu -# define helper_ret_lduw_mmu helper_be_lduw_mmu -# define helper_ret_ldsl_mmu helper_be_ldsl_mmu -# define helper_ret_ldul_mmu helper_be_ldul_mmu -# define helper_ret_ldl_mmu helper_be_ldul_mmu -# define helper_ret_ldq_mmu helper_be_ldq_mmu -# define helper_ret_stw_mmu helper_be_stw_mmu -# define helper_ret_stl_mmu helper_be_stl_mmu -# define helper_ret_stq_mmu helper_be_stq_mmu -#else -# define helper_ret_ldsw_mmu helper_le_ldsw_mmu -# define helper_ret_lduw_mmu helper_le_lduw_mmu -# define helper_ret_ldsl_mmu helper_le_ldsl_mmu -# define helper_ret_ldul_mmu helper_le_ldul_mmu -# define helper_ret_ldl_mmu helper_le_ldul_mmu -# define helper_ret_ldq_mmu helper_le_ldq_mmu -# define helper_ret_stw_mmu helper_le_stw_mmu -# define helper_ret_stl_mmu helper_le_stl_mmu -# define helper_ret_stq_mmu helper_le_stq_mmu -#endif -#endif /* CONFIG_SOFTMMU */ - #ifdef CONFIG_DEBUG_TCG void tcg_assert_listed_vecop(TCGOpcode); #else diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b350cafa3d..b69a953447 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -39,6 +39,7 @@ #ifdef CONFIG_PLUGIN #include "qemu/plugin-memory.h" #endif +#include "tcg/tcg-ldst.h" =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 658be0c6b6..024a22cf39 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -58,6 +58,7 @@ =20 #include "elf.h" #include "exec/log.h" +#include "tcg/tcg-ldst.h" #include "tcg-internal.h" =20 #ifdef CONFIG_TCG_INTERPRETER diff --git a/tcg/tci.c b/tcg/tci.c index 5c08dc0a9a..e76087ccac 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -22,6 +22,7 @@ #include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ #include "exec/cpu_ldst.h" #include "tcg/tcg-op.h" +#include "tcg/tcg-ldst.h" #include "qemu/compiler.h" #include =20 --=20 2.25.1 From nobody Sat Apr 20 09:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1634150661009100003 Having observed e.g. al8+leq in dumps, canonicalize to al+leq. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index b1cfd36f29..61b492d89f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2765,7 +2765,12 @@ void tcg_gen_lookup_and_goto_ptr(void) static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) { /* Trigger the asserts within as early as possible. */ - (void)get_alignment_bits(op); + unsigned a_bits =3D get_alignment_bits(op); + + /* Prefer MO_ALIGN+MO_XX over MO_ALIGN_XX+MO_XX */ + if (a_bits =3D=3D (op & MO_SIZE)) { + op =3D (op & ~MO_AMASK) | MO_ALIGN; + } =20 switch (op & MO_SIZE) { case MO_8: --=20 2.25.1