From nobody Thu May 16 19:21:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163388827734653.638203825859364; Sun, 10 Oct 2021 10:51:17 -0700 (PDT) Received: from localhost ([::1]:40262 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mZcyi-0000bP-Bh for importer@patchew.org; Sun, 10 Oct 2021 13:51:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50792) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mZcrq-0000Sj-2n for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:10 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:34755) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mZcro-0005nh-Go for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:09 -0400 Received: by mail-pg1-x534.google.com with SMTP id 133so8632091pgb.1 for ; Sun, 10 Oct 2021 10:44:08 -0700 (PDT) Received: from localhost.localdomain (068-185-026-038.biz.spectrum.com. [68.185.26.38]) by smtp.gmail.com with ESMTPSA id 18sm5095391pfh.115.2021.10.10.10.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Oct 2021 10:44:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M/4DccFejM9tuchtxwnYOK2Yuhc7vks/tEm5XhG4ki0=; b=v4eTKvgUM8STMOEZQu+m6eFugUylSowKOIlCE1ybt2xTgYUOeFtXK0XziZ+7+rEolX 5aluMMEyIyGzpVlEKHespx+QMe6+039Q3Oi4J2zNVHaWvwm5KovTzpQD/rvXEyRElf4n g341nAZ4sL4I2ue+L4jO6MdK+wO4b7T4NxhfcWYiqCXoqZIYKVKfTueS+g3A2NXASxQZ aQ9iN7yl4hZvgs+UgSXfhiRbSTVRu7zVQy3mi4bjttimqOXX3W48KvBjjeOzvf3tCJzO ywO3vt76ccPQNtq9FwahrpIRUIrl8hDf0ORDpnvh9J7jFEdKacKabbP12p6n08Js1krF vFSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M/4DccFejM9tuchtxwnYOK2Yuhc7vks/tEm5XhG4ki0=; b=jEYTiO1yKfu/Xuh7ut52GvXRGJflUhpZ7PCXb9m3/Uqo869AKagDwntcQh8CzO3it2 syi8Vn7sV2cLCyglXr884VYS7qA/sSsXlX4QOCjt5Xtjoi8Zr7qTthDVq9WtEFIFWPKh fXjKy59YjWHnk1FLTxCVjapaHXDOQ98MuSXC/ApDzYl4AFpQX/2cEEjjgYf5ajqfIJ12 yMc6p4u+3e8V8oLUl0iiQH4R07lVgs5fmt4mlTnE1eXThbMXzQpcdjQ/UjIacKnLLdXK ULxNdC98a5YMNslHy63JmoXiIf0XxPeITLR7t/g64+dM0IbDKGKqcldKbzz2+cd6OeUb TTVQ== X-Gm-Message-State: AOAM533BtToIoorCA+CkeX7yzIRvWK6B04UzpeawgsHystTNMbkQMit9 xXe2MtgwN2tdxmS8r+y4wcgvXg/ZAYNFMFln X-Google-Smtp-Source: ABdhPJwPOo99b9WvuoIAQksP0klM40ArXYVD90svM47G1VuYA2vlCZpvlStdffgFYNOrJoTJhu50XQ== X-Received: by 2002:a63:df05:: with SMTP id u5mr14444660pgg.323.1633887847144; Sun, 10 Oct 2021 10:44:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/8] tcg: Add TCG_TARGET_SIGNED_ADDR32 Date: Sun, 10 Oct 2021 10:43:54 -0700 Message-Id: <20211010174401.141339-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211010174401.141339-1-richard.henderson@linaro.org> References: <20211010174401.141339-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, Alistair.Francis@wdc.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633888277675100002 Content-Type: text/plain; charset="utf-8" Define as 0 for all tcg hosts. Put this in a separate header, because we'll want this in places that do not ordinarily have access to all of tcg/tcg.h. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: WANG Xuerui --- tcg/aarch64/tcg-target-sa32.h | 1 + tcg/arm/tcg-target-sa32.h | 1 + tcg/i386/tcg-target-sa32.h | 1 + tcg/mips/tcg-target-sa32.h | 1 + tcg/ppc/tcg-target-sa32.h | 1 + tcg/riscv/tcg-target-sa32.h | 1 + tcg/s390x/tcg-target-sa32.h | 1 + tcg/sparc/tcg-target-sa32.h | 1 + tcg/tci/tcg-target-sa32.h | 1 + 9 files changed, 9 insertions(+) create mode 100644 tcg/aarch64/tcg-target-sa32.h create mode 100644 tcg/arm/tcg-target-sa32.h create mode 100644 tcg/i386/tcg-target-sa32.h create mode 100644 tcg/mips/tcg-target-sa32.h create mode 100644 tcg/ppc/tcg-target-sa32.h create mode 100644 tcg/riscv/tcg-target-sa32.h create mode 100644 tcg/s390x/tcg-target-sa32.h create mode 100644 tcg/sparc/tcg-target-sa32.h create mode 100644 tcg/tci/tcg-target-sa32.h diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/aarch64/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/arm/tcg-target-sa32.h b/tcg/arm/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/arm/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/i386/tcg-target-sa32.h b/tcg/i386/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/i386/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/mips/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/ppc/tcg-target-sa32.h b/tcg/ppc/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/ppc/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/riscv/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/s390x/tcg-target-sa32.h b/tcg/s390x/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/s390x/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/sparc/tcg-target-sa32.h b/tcg/sparc/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/sparc/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/tci/tcg-target-sa32.h b/tcg/tci/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/tci/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 --=20 2.25.1 From nobody Thu May 16 19:21:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633888063810543.810066487821; Sun, 10 Oct 2021 10:47:43 -0700 (PDT) Received: from localhost ([::1]:59960 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mZcvG-0003Mo-K6 for importer@patchew.org; Sun, 10 Oct 2021 13:47:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mZcrt-0000Tu-F9 for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:18 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:46958) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mZcrr-0005o5-Dw for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:13 -0400 Received: by mail-pg1-x531.google.com with SMTP id m21so8603035pgu.13 for ; Sun, 10 Oct 2021 10:44:10 -0700 (PDT) Received: from localhost.localdomain (068-185-026-038.biz.spectrum.com. [68.185.26.38]) by smtp.gmail.com with ESMTPSA id 18sm5095391pfh.115.2021.10.10.10.44.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Oct 2021 10:44:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xCbmEUSl+ecOqyB7Q5IjpUvL5Is3ROPOJlxFtpvTKsc=; b=eCq2A/fiVcwtgmukaGZYFER9X3cG+V6WA7EOZnM7oMm/W7wZvzEumXo5XTrWTGqvVt P7ArcQgV01wWv4l/WKutDmom77hDQ1uUbzKPIFFexvFhhY4GjkQ8wIj0Mt8g4P+uFC5+ 6wfHmsijXzsS+IzyhqRsvi7EGgGbyu5OWdEoz4hpIzceKLtRgmoUkWB5LhpAmUWiqDb+ FwHgLVT5hF5Q/om6rfx+m8VcRRHfxfyy+jkbQmMxXmxOun3Bc1iY0cZ65tj48aOBxAJe SgdjEegqF0vIL0mK/qoooq1ptDo+F1N7WgIBljpZAfuhkRzbO9BAX1J405g5clWF/dES 9cXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xCbmEUSl+ecOqyB7Q5IjpUvL5Is3ROPOJlxFtpvTKsc=; b=C2XDqj3eACvOt66yr3JRytP/GbRqwhn0OS56CcEORaKJO4hrNvx+hoTawjHi8QmEVD g0+abzWijdztTi5rp6eqrbHvC/flJboMxmIW2hb0YRNfrcYM8l5qgH2pcJ5G6J012grY fttPRZkdUCHARBS0GzjdmDEdiFD1P1280ip9iIYpSCEAKIq8lf0y5Dc3dbX8rK4nedbf s8qybxAmYZpzhR0XcHXCF+rRTmh4kSRztNdfGWEvdBpCdDYFDb301kEqiifDqXNzvWwM 7XmTUy1WbiuyXIjV3d741C0bnzV7J+9sZwcPbrUa1Z4OU2zVUtOK4qxLIga5VtZknLjy 1yMw== X-Gm-Message-State: AOAM533BsuiNOXrfdqm0yMH746VSxFYJqoOZte62+C2TdGigPcA4w/X0 uR3VfHVhG//PpTYy2vMCBPtnZQVWjLvyXkXo X-Google-Smtp-Source: ABdhPJxjS1mmHbV97+OerkMm+/QyAsNri4SnwM+XMXcJZWawncLPmh0jlq1PX2e4302XAlnCVd5qXw== X-Received: by 2002:a62:17d3:0:b0:44c:6022:9428 with SMTP id 202-20020a6217d3000000b0044c60229428mr20938600pfx.65.1633887849090; Sun, 10 Oct 2021 10:44:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/8] accel/tcg: Split out g2h_tlbe Date: Sun, 10 Oct 2021 10:43:55 -0700 Message-Id: <20211010174401.141339-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211010174401.141339-1-richard.henderson@linaro.org> References: <20211010174401.141339-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, Alistair.Francis@wdc.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633888065577100005 Content-Type: text/plain; charset="utf-8" Create a new function to combine a CPUTLBEntry addend with the guest address to form a host address. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: WANG Xuerui --- accel/tcg/cputlb.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 46140ccff3..761f726722 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -90,6 +90,11 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast) return fast->mask + (1 << CPU_TLB_ENTRY_BITS); } =20 +static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gadd= r) +{ + return tlb->addend + (uintptr_t)gaddr; +} + static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, size_t max_entries) { @@ -976,8 +981,7 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *t= lb_entry, =20 if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_DISCARD_WRITE | TLB_NOTDIRTY)) =3D=3D 0) { - addr &=3D TARGET_PAGE_MASK; - addr +=3D tlb_entry->addend; + addr =3D g2h_tlbe(tlb_entry, addr & TARGET_PAGE_MASK); if ((addr - start) < length) { #if TCG_OVERSIZED_GUEST tlb_entry->addr_write |=3D TLB_NOTDIRTY; @@ -1527,7 +1531,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState = *env, target_ulong addr, return -1; } =20 - p =3D (void *)((uintptr_t)addr + entry->addend); + p =3D (void *)g2h_tlbe(entry, addr); if (hostp) { *hostp =3D p; } @@ -1619,7 +1623,7 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, } =20 /* Everything else is RAM. */ - *phost =3D (void *)((uintptr_t)addr + entry->addend); + *phost =3D (void *)g2h_tlbe(entry, addr); return flags; } =20 @@ -1727,7 +1731,7 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong ad= dr, int mmu_idx, data->v.io.offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + = addr; } else { data->is_io =3D false; - data->v.ram.hostaddr =3D (void *)((uintptr_t)addr + tlbe->adde= nd); + data->v.ram.hostaddr =3D (void *)g2h_tlbe(tlbe, addr); } return true; } else { @@ -1826,7 +1830,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, goto stop_the_world; } =20 - hostaddr =3D (void *)((uintptr_t)addr + tlbe->addend); + hostaddr =3D (void *)g2h_tlbe(tlbe, addr); =20 if (unlikely(tlb_addr & TLB_NOTDIRTY)) { notdirty_write(env_cpu(env), addr, size, @@ -1938,7 +1942,7 @@ load_helper(CPUArchState *env, target_ulong addr, Mem= OpIdx oi, access_type, op ^ (need_swap * MO_BSWAP)); } =20 - haddr =3D (void *)((uintptr_t)addr + entry->addend); + haddr =3D (void *)g2h_tlbe(entry, addr); =20 /* * Keep these two load_memop separate to ensure that the compiler @@ -1975,7 +1979,7 @@ load_helper(CPUArchState *env, target_ulong addr, Mem= OpIdx oi, return res & MAKE_64BIT_MASK(0, size * 8); } =20 - haddr =3D (void *)((uintptr_t)addr + entry->addend); + haddr =3D (void *)g2h_tlbe(entry, addr); return load_memop(haddr, op); } =20 @@ -2467,7 +2471,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); } =20 - haddr =3D (void *)((uintptr_t)addr + entry->addend); + haddr =3D (void *)g2h_tlbe(entry, addr); =20 /* * Keep these two store_memop separate to ensure that the compiler @@ -2492,7 +2496,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, return; } =20 - haddr =3D (void *)((uintptr_t)addr + entry->addend); + haddr =3D (void *)g2h_tlbe(entry, addr); store_memop(haddr, val, op); } =20 --=20 2.25.1 From nobody Thu May 16 19:21:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633888062559795.1422183735186; Sun, 10 Oct 2021 10:47:42 -0700 (PDT) Received: from localhost ([::1]:59906 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mZcvF-0003Kp-Gy for importer@patchew.org; Sun, 10 Oct 2021 13:47:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mZcru-0000Tz-Jc for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:18 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:39720) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mZcrs-0005p1-9w for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:14 -0400 Received: by mail-pl1-x62e.google.com with SMTP id c4so9685896pls.6 for ; Sun, 10 Oct 2021 10:44:11 -0700 (PDT) Received: from localhost.localdomain (068-185-026-038.biz.spectrum.com. [68.185.26.38]) by smtp.gmail.com with ESMTPSA id 18sm5095391pfh.115.2021.10.10.10.44.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Oct 2021 10:44:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Im+b1+SE02Qv2KjU8guCaDLdxStcEkFqEbgLcsDJx9w=; b=I4ZYoZfOncX7quOp3ibiSVKLECgadO7FAbEwwVFrKHIPLpSAPj5EV8CIYgL4R7BR0L hbzF/FKBEdqeVQ+JHX51Ppezq4SwvmTPJpxD7C52M5VDTpQjpxUD8bhiKzEWPh1ZywpS AWwR2ybocxiJP3pzJsYOCBaNSK2Sli8mLas/vo/8vEsWcTda8bFjaZ7G6M3dWnspUlcM rF272yh6YuYlF2+gDSUlTiqm4nXvTtOXiCfnt9lqFhST5HzkINGAHmJ3fLwrlVaK2q3t 0ZP5O1epQZR2BYDDaasTww6dKsUFVRl7uvw46epJDO4ESxeZhWuFQcNN8UDPs3Ssnl97 39KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Im+b1+SE02Qv2KjU8guCaDLdxStcEkFqEbgLcsDJx9w=; b=VQKmLI9SEJNbqbu34nE68VrqNht5XWc5H8A1po+SH6V0dyxqNBmV9K2ZtwpF1s465r jNDiiolgwV/0peCVFY8ZTpc2ZPTFrOTYTqAbXH1tjlREE7jTWZe7zujV8Am7yzMLI2Zc +2sV2uy2WePJ4uPjgzlCb6hxccBJ8I5GTfK14V/+uzus3NgR4M+6Cr731c5dfLi2ToZn F714LlmXmnwd/2nAIL9TrTsDd53d+tKcyXnCxWgmZ4T/d4OPIlvBbRSKucTPT7eUem4+ n0+QqzNy8ykuGiJIm9YpfLo6vzrJTcIu4r3mXno48pjfRJN1TMXynz2K9yRyo+9z4EOH L4sQ== X-Gm-Message-State: AOAM530A2nJRPiKbwum6qPJhkvpl5pPxEnvE52SGka9pZnhUDuMorhcg wJFRSKcP9ij9McZWarW6VcaWb5s6BGE9bvW4 X-Google-Smtp-Source: ABdhPJykcHPZXyN2ZmTvQ7m9oyMylUWXo5uz5P5q1BmYtf/Tfq1MVE0A0EvUPUlrLrNXCBUfYoiq+g== X-Received: by 2002:a17:90b:4b89:: with SMTP id lr9mr25019163pjb.11.1633887850945; Sun, 10 Oct 2021 10:44:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/8] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu Date: Sun, 10 Oct 2021 10:43:56 -0700 Message-Id: <20211010174401.141339-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211010174401.141339-1-richard.henderson@linaro.org> References: <20211010174401.141339-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, Alistair.Francis@wdc.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633888063505100003 Content-Type: text/plain; charset="utf-8" When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to allow the 32-bit guest address to be sign extended within the 64-bit host register instead of zero extended. This will simplify tcg hosts like MIPS, RISC-V, and LoongArch, which naturally sign-extend 32-bit values, in contrast to x86_64 and AArch64 which zero-extend them. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 761f726722..d12621c60e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -39,6 +39,7 @@ #ifdef CONFIG_PLUGIN #include "qemu/plugin-memory.h" #endif +#include "tcg-target-sa32.h" =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ @@ -92,6 +93,9 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast) =20 static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gadd= r) { + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS =3D=3D 32) { + return tlb->addend + (int32_t)gaddr; + } return tlb->addend + (uintptr_t)gaddr; } =20 @@ -1234,7 +1238,13 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_u= long vaddr, desc->iotlb[index].attrs =3D attrs; =20 /* Now calculate the new entry */ - tn.addend =3D addend - vaddr_page; + + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS < TCG_TARGET_REG_BITS= ) { + tn.addend =3D addend - (int32_t)vaddr_page; + } else { + tn.addend =3D addend - vaddr_page; + } + if (prot & PAGE_READ) { tn.addr_read =3D address; if (wp_flags & BP_MEM_READ) { --=20 2.25.1 From nobody Thu May 16 19:21:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633888445394803.6546389683282; Sun, 10 Oct 2021 10:54:05 -0700 (PDT) Received: from localhost ([::1]:48894 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mZd1Q-0006PN-7u for importer@patchew.org; Sun, 10 Oct 2021 13:54:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50842) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mZcrw-0000U0-0b for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:18 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:37499) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mZcrt-0005pr-Sv for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:15 -0400 Received: by mail-pg1-x533.google.com with SMTP id r201so8619306pgr.4 for ; Sun, 10 Oct 2021 10:44:13 -0700 (PDT) Received: from localhost.localdomain (068-185-026-038.biz.spectrum.com. [68.185.26.38]) by smtp.gmail.com with ESMTPSA id 18sm5095391pfh.115.2021.10.10.10.44.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Oct 2021 10:44:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OA5lVsCVexffj4tJ1okwj2NEN/znxpIAZbVY6q21rhk=; b=yLhsQCd3YmmYfayNnkAeAZUSSqnntpP+6pSpKb1VFfSA6qGFG0d0JftU4Nir+ZUxn/ oPuqPfsNTERSbxFh13LviYPLwLCbteVmP4YQ+kbp1dEKG0AxArn33bKVgD9ta3M/7CWh +xmfX7KJf0wN1PyCS6VlBzqSM3PGnAfoZ6z0eAXlr2SFx+fsaNKH4ZeXk6cURhdAeNt0 fIC2jkKyzNAPyrOID0WuqzsaoAuxUh87njofjU7fgKnjZpLVVMk1/znlLyBlzjcYEdSm YQ9FIuDpN4jO6qgGh7ruo7cUdi5nPyf9e1un1hm4c7zvoZpt2jEbSxfpED/XIc472rIQ slMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OA5lVsCVexffj4tJ1okwj2NEN/znxpIAZbVY6q21rhk=; b=JtsdRnkM10x5RVGzuRjTjmRB+2h/NruL/WB0xFr0x9BINCQeiXXGhcujd091cZy8P9 I81TgcIDiESeZyRh7MC5D4x91Vv29JlvDfdQJ9F4XtaQzKBwDMYWacjgGyJspxSj++3q rhwCiRYXxWEqw97w4vGLHa3I2PuWZt4ebZJSzvZeflTepblnwyVpxAyB9Bs1F/tcoMC2 fVYLtHGpYUKGuSHyTcQhzdw7UKVDyy+WhPEA+O94V2Y4k+eQNV8LOUEz59LqB2YAIgu4 hqO4Il7F4JIotgBjMwGwiEQYvE+mkiY+ZWlK8eyiGgzDYtFTvCyceCiQY41A5l4C1zlN k6iQ== X-Gm-Message-State: AOAM533MaVr3uFv5dCpmDacAkmSvUrjQkkzP5CRQSHfU7enDX3olmXZf QqAgb+SXkSJ0SALbRdaNcFKCzr7hDGjaedp6 X-Google-Smtp-Source: ABdhPJxCTpfU7IxxMd4oxdDLQIu7KQw7Ub2pHrXMNHrMdyjTp+0T9VLtigQpPhBnZh+UbsPK6bKoog== X-Received: by 2002:a62:6206:0:b0:44c:bc1f:aa5a with SMTP id w6-20020a626206000000b0044cbc1faa5amr20852668pfb.5.1633887852598; Sun, 10 Oct 2021 10:44:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 4/8] accel/tcg: Add guest_base_signed_addr32 for user-only Date: Sun, 10 Oct 2021 10:43:57 -0700 Message-Id: <20211010174401.141339-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211010174401.141339-1-richard.henderson@linaro.org> References: <20211010174401.141339-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, Alistair.Francis@wdc.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633888446422100001 Content-Type: text/plain; charset="utf-8" While the host may prefer to treat 32-bit addresses as signed, there are edge cases of guests that cannot be implemented with addresses 0x7fff_ffff and 0x8000_0000 being non-consecutive. Therefore, default to guest_base_signed_addr32 false, and allow probe_guest_base to determine whether it is possible to set it to true. A tcg backend which sets TCG_TARGET_SIGNED_ADDR32 will have to cope with either setting for user-only. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 16 ++++++++++++++++ include/exec/cpu_ldst.h | 3 ++- bsd-user/main.c | 4 ++++ linux-user/main.c | 3 +++ 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 32cfb634c6..80b5e17329 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -146,6 +146,7 @@ static inline void tswap64s(uint64_t *s) =20 #if defined(CONFIG_USER_ONLY) #include "exec/user/abitypes.h" +#include "tcg-target-sa32.h" =20 /* On some host systems the guest address space is reserved on the host. * This allows the guest address space to be offset to a convenient locati= on. @@ -154,6 +155,21 @@ extern uintptr_t guest_base; extern bool have_guest_base; extern unsigned long reserved_va; =20 +#if TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS =3D=3D 32 +extern bool guest_base_signed_addr32; +#else +#define guest_base_signed_addr32 false +#endif + +static inline void set_guest_base_signed_addr32(void) +{ +#ifdef guest_base_signed_addr32 + qemu_build_not_reached(); +#else + guest_base_signed_addr32 =3D true; +#endif +} + /* * Limit the guest addresses as best we can. * diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ce6ce82618..db760ff5c2 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -79,7 +79,8 @@ static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi= _ptr x) /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ static inline void *g2h_untagged(abi_ptr x) { - return (void *)((uintptr_t)(x) + guest_base); + uintptr_t hx =3D guest_base_signed_addr32 ? (int32_t)x : (uintptr_t)x; + return (void *)(guest_base + hx); } =20 static inline void *g2h(CPUState *cs, abi_ptr x) diff --git a/bsd-user/main.c b/bsd-user/main.c index 48643eeabc..4fef0520da 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -54,6 +54,10 @@ int singlestep; uintptr_t guest_base; bool have_guest_base; +#ifndef guest_base_signed_addr32 +bool guest_base_signed_addr32; +#endif + /* * When running 32-on-64 we should make sure we can fit all of the possible * guest address space into a contiguous chunk of virtual host memory. diff --git a/linux-user/main.c b/linux-user/main.c index 16def5215d..ed7a88c195 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -72,6 +72,9 @@ static const char *seed_optarg; unsigned long mmap_min_addr; uintptr_t guest_base; bool have_guest_base; +#ifndef guest_base_signed_addr32 +bool guest_base_signed_addr32; +#endif =20 /* * Used to implement backwards-compatibility for the `-strace`, and --=20 2.25.1 From nobody Thu May 16 19:21:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633888276622748.207562075942; Sun, 10 Oct 2021 10:51:16 -0700 (PDT) Received: from localhost ([::1]:40252 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mZcyh-0000b0-Kx for importer@patchew.org; Sun, 10 Oct 2021 13:51:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mZcry-0000U1-Dw for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:19 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:44980) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mZcrw-0005qB-1v for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:17 -0400 Received: by mail-pg1-x536.google.com with SMTP id s11so8603538pgr.11 for ; Sun, 10 Oct 2021 10:44:15 -0700 (PDT) Received: from localhost.localdomain (068-185-026-038.biz.spectrum.com. [68.185.26.38]) by smtp.gmail.com with ESMTPSA id 18sm5095391pfh.115.2021.10.10.10.44.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Oct 2021 10:44:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+xpwLQQ3G87YSNylwYvHxHVXJT0SSnowXmZR7ncguZ4=; b=AwfA1P+B7oTp7cIicVjutkFHPKGSDxyBdEFpxVl0KBSea831gakU3flL5lRDSkhbd8 fpP2WyhRdrNPG6zlBRMqSx497zlhsiizbJCgf2Vqw06RwX0oZa7HY5SDfAJOe6EhMSt1 ZwE1gpC/XNq8e9eKHfpaiFZg5cIG5xm33UU+GfRwikCBn5Xxwtzq10Gpgz2PqCnJtean MbO9kaqMBeByO4TcF762O1jx7lpBNmZdBI4eZTP2o4Dxynm+PTBndeaxtV0aZg2uPR6f dlgot+Lb5HcALaMvxr0w6C9Su+tehKPapDQBuFLlPwKAj/o9OXPJlBor7H0hWf4cOATi U1kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+xpwLQQ3G87YSNylwYvHxHVXJT0SSnowXmZR7ncguZ4=; b=Ui7DkPzJ/9bh7sgwR62PiGWF3vDtJWZBkicw/8uWy2FCRPJXc+a9d8AjL6MjWKS9nO 2vunsXlnsdH8dcRdhgRDn9g37f5Dbw7lJIIy+igN3WQ1L0+wv+PzfGVlSqUXvgAt9QHh 0IXwLjUO2NwWzPzWtWNO8yvib0ERrObr66XUO6V9p62o0uo7Z5awysFHwAl1fUqNaxC/ 3PeRXoM2KIANLrtwMM4zc37kZNZbQu/5jeLszpDc0agdkZIdsgRLwDB38KvhqyWh29BP UJ3EfY6WKqDx0Qzxz06Dw1U4u4BZut/PQOoZZZpt7hJ50aTW9J4rFMQwU42TLOFYq8Zq OuHQ== X-Gm-Message-State: AOAM530817BrPiMhPCU1F7Eb1w+hjPc0EYkrj6k7M+OHCmQbM6kiS8qh bNgkfxSvwdNPFM3+Egt4CKXPoY1WKg1e2fwb X-Google-Smtp-Source: ABdhPJzA1u19OfZQmUPO415GN0pB6eMcDWarTOmqSQYOtnU42qYGk/xstdn3mCAgzmQr18/70sZqTQ== X-Received: by 2002:a05:6a00:140c:b0:447:96be:2ade with SMTP id l12-20020a056a00140c00b0044796be2ademr21015946pfu.26.1633887854719; Sun, 10 Oct 2021 10:44:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 5/8] linux-user: Support TCG_TARGET_SIGNED_ADDR32 Date: Sun, 10 Oct 2021 10:43:58 -0700 Message-Id: <20211010174401.141339-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211010174401.141339-1-richard.henderson@linaro.org> References: <20211010174401.141339-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, Alistair.Francis@wdc.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633888277671100001 Content-Type: text/plain; charset="utf-8" When using reserved_va, which is the default for a 64-bit host and a 32-bit guest, set guest_base_signed_addr32 if requested by TCG_TARGET_SIGNED_ADDR32, and the executable layout allows. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/exec/cpu-all.h | 4 --- linux-user/elfload.c | 62 ++++++++++++++++++++++++++++++++++-------- 2 files changed, 50 insertions(+), 16 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 80b5e17329..71d8e1de7a 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -278,11 +278,7 @@ extern intptr_t qemu_host_page_mask; #define PAGE_RESET 0x0040 /* For linux-user, indicates that the page is MAP_ANON. */ #define PAGE_ANON 0x0080 - -#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) -/* FIXME: Code that sets/uses this is broken and needs to go away. */ #define PAGE_RESERVED 0x0100 -#endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0200 #define PAGE_TARGET_2 0x0400 diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 2404d482ba..4a3d339cf1 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2422,33 +2422,71 @@ static void pgb_dynamic(const char *image_name, lon= g align) static void pgb_reserved_va(const char *image_name, abi_ulong guest_loaddr, abi_ulong guest_hiaddr, long align) { - int flags =3D MAP_ANONYMOUS | MAP_PRIVATE | MAP_NORESERVE; + int flags =3D (MAP_ANONYMOUS | MAP_PRIVATE | + MAP_NORESERVE | MAP_FIXED_NOREPLACE); + unsigned long local_rva =3D reserved_va; + bool protect_wrap =3D false; void *addr, *test; =20 - if (guest_hiaddr > reserved_va) { + if (guest_hiaddr > local_rva) { error_report("%s: requires more than reserved virtual " "address space (0x%" PRIx64 " > 0x%lx)", - image_name, (uint64_t)guest_hiaddr, reserved_va); + image_name, (uint64_t)guest_hiaddr, local_rva); exit(EXIT_FAILURE); } =20 - /* Widen the "image" to the entire reserved address space. */ - pgb_static(image_name, 0, reserved_va, align); + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS =3D=3D 32) { + if (guest_loaddr < 0x80000000u && guest_hiaddr > 0x80000000u) { + /* + * The executable itself wraps on signed addresses. + * Without per-page translation, we must keep the + * guest address 0x7fff_ffff adjacent to 0x8000_0000 + * consecutive in host memory: unsigned addresses. + */ + } else { + set_guest_base_signed_addr32(); + if (local_rva <=3D 0x80000000u) { + /* No guest addresses are "negative": win! */ + } else { + /* Begin by allocating the entire address space. */ + local_rva =3D 0xfffffffful + 1; + protect_wrap =3D true; + } + } + } =20 - /* osdep.h defines this as 0 if it's missing */ - flags |=3D MAP_FIXED_NOREPLACE; + /* Widen the "image" to the entire reserved address space. */ + pgb_static(image_name, 0, local_rva, align); + assert(guest_base !=3D 0); =20 /* Reserve the memory on the host. */ - assert(guest_base !=3D 0); test =3D g2h_untagged(0); - addr =3D mmap(test, reserved_va, PROT_NONE, flags, -1, 0); + addr =3D mmap(test, local_rva, PROT_NONE, flags, -1, 0); if (addr =3D=3D MAP_FAILED || addr !=3D test) { + /* + * If protect_wrap, we could try again with the original reserved_= va + * setting, but the edge case of low ulimit vm setting on a 64-bit + * host is probably useless. + */ error_report("Unable to reserve 0x%lx bytes of virtual address " - "space at %p (%s) for use as guest address space (che= ck your" - "virtual memory ulimit setting, min_mmap_addr or rese= rve less " - "using -R option)", reserved_va, test, strerror(errno= )); + "space at %p (%s) for use as guest address space " + "(check your virtual memory ulimit setting, " + "min_mmap_addr or reserve less using -R option)", + local_rva, test, strerror(errno)); exit(EXIT_FAILURE); } + + if (protect_wrap) { + /* + * Prevent the page just before 0x80000000 from being allocated. + * This prevents a single guest object/allocation from crossing + * the signed wrap, and thus being discontiguous in host memory. + */ + page_set_flags(0x7fffffff & TARGET_PAGE_MASK, 0x80000000u, + PAGE_RESERVED); + /* Adjust guest_base so that 0 is in the middle of the reservation= . */ + guest_base +=3D 0x80000000ul; + } } =20 void probe_guest_base(const char *image_name, abi_ulong guest_loaddr, --=20 2.25.1 From nobody Thu May 16 19:21:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633888276699715.5393165435897; Sun, 10 Oct 2021 10:51:16 -0700 (PDT) Received: from localhost ([::1]:40276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mZcyh-0000bl-Kh for importer@patchew.org; Sun, 10 Oct 2021 13:51:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50880) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mZcs1-0000UQ-0H for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:22 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:46790) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mZcry-00061C-Of for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:20 -0400 Received: by mail-pf1-x435.google.com with SMTP id z11so441297pfg.13 for ; Sun, 10 Oct 2021 10:44:18 -0700 (PDT) Received: from localhost.localdomain (068-185-026-038.biz.spectrum.com. [68.185.26.38]) by smtp.gmail.com with ESMTPSA id 18sm5095391pfh.115.2021.10.10.10.44.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Oct 2021 10:44:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AE3YCDFcRA2qGK8f6qCGrhsHOd0kXVvkieozwsdgT24=; b=W+rd8dD0+tZHu5G51ya5hoAhHDJDj9KFCIYTp8+Rn+mFRCBZDl1VI3vug5ZuQq2QRV qfyRCd/cih6EBAezKDhc2SdKmoOBtjkY6cY0eredUexigsFUBCeJ5G0j++TzIncFlW3Q evrQRtJN6lt2REKvygVVZAgwRmOsv3XcKfgFg6byYkNGjSTRLg/aNq1kIkdv87c613/d WCjqKjgTsf84eUsJq+b3F2BsbDb29iKZ5dV91eiuDJKxJbbVJSHEpVqZwDx25aCToAi/ RKRMFrBia5ddj4SufrgRXRDJWZkzymPeQ4sYJrcF+0YW+W6M5Di/K8aGpflrqSMq6Uwr d4Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AE3YCDFcRA2qGK8f6qCGrhsHOd0kXVvkieozwsdgT24=; b=cAUYs0UyXJwK0S3NiPZjSVBRU87ARxyxItswzt65djoZQZxIszZQJLqNY1n+ylP+8I rNcRMJVRzgX6mg9nWxURYd9msj77dGDb7hIprCoqBDHLuZTQZqrKQyL4x9kk3pciEnHY iHP+iEMEa2IJnxieHuDz3JlXFPB7T+qfL5boMhqUwSsPlGv4r0zMR6Uym5ZBUdfaOYKC d6ui3osvlegii+YGJvttRHdAiqBDR/fTpUXmdYH0tWQWnrNWbK6H3pj940wpi/4btuWN MTEZJePDF1rrios82j4mD0i0L+glm4QIhf08xQLECTAHaFIfWcZl0lhfz6REWvZ4IJuG X85Q== X-Gm-Message-State: AOAM531vY4PWrqvodOuBvhROt7gf8xGpsYJhKVJMhQ5fpGyzXT4dsO0q IzoijAvkdKwGL2LX107s3qflA9njABYamBtR X-Google-Smtp-Source: ABdhPJwcSf1+7Us+yV9cDfOP0MFu4wPn194dsGHRKrb6NP0z9ZiSDYaZXgDb02/GlKKUpAI+5OAeaw== X-Received: by 2002:a62:1683:0:b0:3f3:814f:4367 with SMTP id 125-20020a621683000000b003f3814f4367mr21322951pfw.68.1633887856716; Sun, 10 Oct 2021 10:44:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 6/8] tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32 Date: Sun, 10 Oct 2021 10:43:59 -0700 Message-Id: <20211010174401.141339-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211010174401.141339-1-richard.henderson@linaro.org> References: <20211010174401.141339-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, Alistair.Francis@wdc.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633888277684100003 Content-Type: text/plain; charset="utf-8" AArch64 has both sign and zero-extending addressing modes, which means that either treatment of guest addresses is equally efficient. Enabling this for AArch64 gives us testing of the feature in CI. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-sa32.h | 8 ++++- tcg/aarch64/tcg-target.c.inc | 68 ++++++++++++++++++++++------------- 2 files changed, 51 insertions(+), 25 deletions(-) diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h index cb185b1526..c99e502e4c 100644 --- a/tcg/aarch64/tcg-target-sa32.h +++ b/tcg/aarch64/tcg-target-sa32.h @@ -1 +1,7 @@ -#define TCG_TARGET_SIGNED_ADDR32 0 +/* + * AArch64 has both SXTW and UXTW addressing modes, which means that + * it is agnostic to how guest addresses should be represented. + * Because aarch64 is more common than the other hosts that will + * want to use this feature, enable it for continuous testing. + */ +#define TCG_TARGET_SIGNED_ADDR32 1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 5edca8d44d..88b2963f9d 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -12,6 +12,7 @@ =20 #include "../tcg-pool.c.inc" #include "qemu/bitops.h" +#include "tcg-target-sa32.h" =20 /* We're going to re-use TCGType in setting of the SF bit, which controls the size of the operation performed. If we know the values match, it @@ -804,12 +805,12 @@ static void tcg_out_insn_3617(TCGContext *s, AArch64I= nsn insn, bool q, } =20 static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn, - TCGReg rd, TCGReg base, TCGType ext, + TCGReg rd, TCGReg base, int option, TCGReg regoff) { /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 | - 0x4000 | ext << 13 | base << 5 | (rd & 0x1f)); + option << 13 | base << 5 | (rd & 0x1f)); } =20 static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn, @@ -1124,7 +1125,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn i= nsn, TCGReg rd, =20 /* Worst-case scenario, move offset to temp register, use reg offset. = */ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset); - tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP); + tcg_out_ldst_r(s, insn, rd, rn, 3 /* LSL #0 */, TCG_REG_TMP); } =20 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) @@ -1718,34 +1719,34 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg = addr_reg, MemOp opc, =20 static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, TCGReg data_r, TCGReg addr_r, - TCGType otype, TCGReg off_r) + int option, TCGReg off_r) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); =20 switch (memop & MO_SSIZE) { case MO_UB: - tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, option, off_r); break; case MO_SB: tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW, - data_r, addr_r, otype, off_r); + data_r, addr_r, option, off_r); break; case MO_UW: - tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, option, off_r); break; case MO_SW: tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), - data_r, addr_r, otype, off_r); + data_r, addr_r, option, off_r); break; case MO_UL: - tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, option, off_r); break; case MO_SL: - tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, option, off_r); break; case MO_Q: - tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, option, off_r); break; default: tcg_abort(); @@ -1754,50 +1755,68 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, M= emOp memop, TCGType ext, =20 static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop, TCGReg data_r, TCGReg addr_r, - TCGType otype, TCGReg off_r) + int option, TCGReg off_r) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); =20 switch (memop & MO_SIZE) { case MO_8: - tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, option, off_r); break; case MO_16: - tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, option, off_r); break; case MO_32: - tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, option, off_r); break; case MO_64: - tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, option, off_r); break; default: tcg_abort(); } } =20 +static int guest_ext_option(void) +{ +#ifdef CONFIG_USER_ONLY + bool signed_addr32 =3D guest_base_signed_addr32; +#else + bool signed_addr32 =3D TCG_TARGET_SIGNED_ADDR32; +#endif + + if (TARGET_LONG_BITS =3D=3D 64) { + return 3; /* LSL #0 */ + } else if (signed_addr32) { + return 6; /* SXTW */ + } else { + return 2; /* UXTW */ + } +} + static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType ext) { MemOp memop =3D get_memop(oi); - const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + int option =3D guest_ext_option(); + #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; =20 tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1); tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_X1, otype, addr_reg); + TCG_REG_X1, option, addr_reg); add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ if (USE_GUEST_BASE) { tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_GUEST_BASE, otype, addr_reg); + TCG_REG_GUEST_BASE, option, addr_reg); } else { tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - addr_reg, TCG_TYPE_I64, TCG_REG_XZR); + addr_reg, option, TCG_REG_XZR); } #endif /* CONFIG_SOFTMMU */ } @@ -1806,23 +1825,24 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, MemOpIdx oi) { MemOp memop =3D get_memop(oi); - const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + int option =3D guest_ext_option(); + #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; =20 tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0); tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_X1, otype, addr_reg); + TCG_REG_X1, option, addr_reg); add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)=3D=3D MO_64, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ if (USE_GUEST_BASE) { tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_GUEST_BASE, otype, addr_reg); + TCG_REG_GUEST_BASE, option, addr_reg); } else { tcg_out_qemu_st_direct(s, memop, data_reg, - addr_reg, TCG_TYPE_I64, TCG_REG_XZR); + addr_reg, option, TCG_REG_XZR); } #endif /* CONFIG_SOFTMMU */ } --=20 2.25.1 From nobody Thu May 16 19:21:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633888183710970.8359552441472; Sun, 10 Oct 2021 10:49:43 -0700 (PDT) Received: from localhost ([::1]:36046 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mZcxC-0006EL-DO for importer@patchew.org; Sun, 10 Oct 2021 13:49:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50926) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mZcs9-0000aC-RV for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:30 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:37755) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mZcs2-0006Ay-1t for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:29 -0400 Received: by mail-pj1-x1033.google.com with SMTP id oa6-20020a17090b1bc600b0019ffc4b9c51so12957389pjb.2 for ; Sun, 10 Oct 2021 10:44:20 -0700 (PDT) Received: from localhost.localdomain (068-185-026-038.biz.spectrum.com. [68.185.26.38]) by smtp.gmail.com with ESMTPSA id 18sm5095391pfh.115.2021.10.10.10.44.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Oct 2021 10:44:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SlW+IUqmPo07UfsLUjSBetG4k12I6tcttGhU4k9emPg=; b=M89zMZ5mN6x1x8O+7HfSa7VatIQ7T4b4DKRP3Z59lPTc9OK8F9692vFF01YtJgODQ7 r0ytrzf6u4yFWdbvAnlU4GkdHcKD4RCzRqraZtix7kGLBPn+Hy4mQxzkIgxbdNF7UQRR dDDcJq1BmNgKQr5Uglk48oet2hFAFCYsmEDbp2R5lLjbd0GINt/a6E+GzjYnBO+H1mql KApP4EcVZegvyYKfDEBvVJbchTeMOlqeMGyuiidjGoqwTVu7W9gkbEeNeDT/rh2q5AP/ nt+1xkuTlpE/hX41VaFyqcUC2e//zoQf5JYKC7zpdFjsbph6tJLJobqHjkPghHA2S9iu xejA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SlW+IUqmPo07UfsLUjSBetG4k12I6tcttGhU4k9emPg=; b=GHlXjfMh/WL9vcIdb96l5xet0lBKTamDUOkezANW2ugmnPZvFM5BzmEq6TP9oEz39L PKq34+GTPKx0L8KS0YzDh1pNuLQOlufdxulWQVremEiwgs8SjAbnz49bwE6HMGWTokVa kzZef86cYlW9VpKFrnLm2jBjKAR9uMQfCngjGTjbAYR6uHs/EHodxqIMciabKIwN35Qg clbgG8A9Ta+bd34AyFnFcNJ0an5bxPmiJiSDED7xNQLa6FzSda/A/XQDkiGWmK13JscL sKFrl34nIPAacb8nj23P5gQ/re3MZaNT/kXnnLb4sXnTrfeTr9kRY/CwwXfBrgKnw9A7 mfIg== X-Gm-Message-State: AOAM532Vq0ufmYRCAexxpwiijBsXHfggeChUhm07yOgl+OCzSPYzcFvd scvFFfi6U0GT7iXepsvOF+Qbtc+Wi+SnfgNf X-Google-Smtp-Source: ABdhPJyz10noCkViOt84QDANrYVo2Nn9p7V6WLnWPmat3Cl4yzm/1er6oTnVf5xkx9+RiV7Z/fVsAA== X-Received: by 2002:a17:903:41d0:b0:13f:1bbf:1535 with SMTP id u16-20020a17090341d000b0013f1bbf1535mr11379365ple.52.1633887859637; Sun, 10 Oct 2021 10:44:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 7/8] target/mips: Support TCG_TARGET_SIGNED_ADDR32 Date: Sun, 10 Oct 2021 10:44:00 -0700 Message-Id: <20211010174401.141339-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211010174401.141339-1-richard.henderson@linaro.org> References: <20211010174401.141339-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, Alistair.Francis@wdc.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633888184740100001 Content-Type: text/plain; charset="utf-8" All 32-bit mips operations sign-extend the output, so we are easily able to keep TCG_TYPE_I32 values sign-extended in host registers. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-sa32.h | 8 ++++++++ tcg/mips/tcg-target.c.inc | 13 +++---------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h index cb185b1526..51255e7cba 100644 --- a/tcg/mips/tcg-target-sa32.h +++ b/tcg/mips/tcg-target-sa32.h @@ -1 +1,9 @@ +/* + * Do not set TCG_TARGET_SIGNED_ADDR32 for mips32; + * TCG expects this to only be set for 64-bit hosts. + */ +#ifdef __mips64 +#define TCG_TARGET_SIGNED_ADDR32 1 +#else #define TCG_TARGET_SIGNED_ADDR32 0 +#endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index d8f6914f03..cc3b4d5b90 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1161,20 +1161,13 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg = base, TCGReg addrl, tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask); } else { - tcg_out_ldst(s, (TARGET_LONG_BITS =3D=3D 64 ? OPC_LD - : TCG_TARGET_REG_BITS =3D=3D 64 ? OPC_LWU : OPC_L= W), - TCG_TMP0, TCG_TMP3, cmp_off); + tcg_out_ld(s, TCG_TYPE_TL, TCG_TMP0, TCG_TMP3, cmp_off); tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask); /* No second compare is required here; load the tlb addend for the fast path. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); } =20 - /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addrl); - addrl =3D base; - } tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); =20 label_ptr[0] =3D s->code_ptr; @@ -1456,7 +1449,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr3= 2) { tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } @@ -1559,7 +1552,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) s->code_ptr, label_ptr); #else base =3D TCG_REG_A0; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr3= 2) { tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } --=20 2.25.1 From nobody Thu May 16 19:21:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633888346052240.33544526571404; Sun, 10 Oct 2021 10:52:26 -0700 (PDT) Received: from localhost ([::1]:44572 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mZczo-0003XX-SM for importer@patchew.org; Sun, 10 Oct 2021 13:52:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mZcsA-0000ag-8z for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:30 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:55002) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mZcs4-0006Na-1x for qemu-devel@nongnu.org; Sun, 10 Oct 2021 13:44:29 -0400 Received: by mail-pj1-x1029.google.com with SMTP id np13so11435421pjb.4 for ; Sun, 10 Oct 2021 10:44:23 -0700 (PDT) Received: from localhost.localdomain (068-185-026-038.biz.spectrum.com. [68.185.26.38]) by smtp.gmail.com with ESMTPSA id 18sm5095391pfh.115.2021.10.10.10.44.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Oct 2021 10:44:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=igFIr5w2dB50Bl4A1K1Rsq9n6Q+Zz9Bk0DkYG9Us5K0=; b=I/s6malkYD455gnUFy6pdeBm41Dnn6a10SzidnrjlqAMu4TfM5+GYJHEomHHocL21T GYej1LMJ4vv2qOEt3lO+Tf53YnydW9R843Ugu9IT2+ncNtCqBucggAOWIz10W+6SJ+0s /H0CPfhFiO8z/EiCr+1P9yhXrGanr0SoRImo/4cEkaPD8HrtwbDSfX3NvsVPIBEAK1pq GOMLYt450b729radFmXFmind5q9jRpFLBM9Le0oWEwRL1/EfOkrechMiigdaqFWWfSbr 3pVyNNrunmXQWrvZLW5cfIe+qsX2VWsgmGN9KKCr5fqjmEwlX16mOsYYycw4w7ekeV/A ZzJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=igFIr5w2dB50Bl4A1K1Rsq9n6Q+Zz9Bk0DkYG9Us5K0=; b=eQjwKpnM1cyn1TXLlKbacketODUAdwDNm4i8LLeGf8/qXHZZJR2b74TcE4F6Gf77Qf D6EypY4aW4FY/D0QATYOWwwaUfMD86KmMF8UXWBKCA29FkV7BqJnCRGlK50KBYAVx3or 818j1MVCWel1u9qDs9tyZ6uvsRi1r/OEhYXAIRb92zWtXb/KC7VoXAnBffDreR5iXx6c 0V5oA5tPzEhtlYU6SEGIcfA6J7HqAIf66FZWC6qGPJMQ4uL+zaAKDCFkpT3T02BRHO+/ 0sh6FWuxljUVqSjTNqpJm5I6+BCNzgPByCrIKuV2zIhdWeY+6b0n6PtSlhI3DlA5vMqF wNVg== X-Gm-Message-State: AOAM532AUg3mO9Cdz9CbLvKFEwk2fjgovBLIwNuPtDymcCMFcIEJkcew U3vsIxt+OPm9hZ2TZqTx0JZY79KvIOkqaNmP X-Google-Smtp-Source: ABdhPJy90eqhQoQHPVhJJTFAmBgeYFENdVxp5iNfEvGHQsLjGzXaPmab9UKX+Q3rbVZT5GpCIDcS1g== X-Received: by 2002:a17:902:9a83:b0:13e:5b1e:aa40 with SMTP id w3-20020a1709029a8300b0013e5b1eaa40mr20352400plp.41.1633887861781; Sun, 10 Oct 2021 10:44:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 8/8] target/riscv: Support TCG_TARGET_SIGNED_ADDR32 Date: Sun, 10 Oct 2021 10:44:01 -0700 Message-Id: <20211010174401.141339-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211010174401.141339-1-richard.henderson@linaro.org> References: <20211010174401.141339-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, Alistair.Francis@wdc.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633888346760100001 Content-Type: text/plain; charset="utf-8" All RV64 32-bit operations sign-extend the output, so we are easily able to keep TCG_TYPE_I32 values sign-extended in host registers. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/riscv/tcg-target-sa32.h | 6 +++++- tcg/riscv/tcg-target.c.inc | 8 ++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h index cb185b1526..703467b37a 100644 --- a/tcg/riscv/tcg-target-sa32.h +++ b/tcg/riscv/tcg-target-sa32.h @@ -1 +1,5 @@ -#define TCG_TARGET_SIGNED_ADDR32 0 +/* + * Do not set TCG_TARGET_SIGNED_ADDR32 for RV32; + * TCG expects this to only be set for 64-bit hosts. + */ +#define TCG_TARGET_SIGNED_ADDR32 (__riscv_xlen =3D=3D 64) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 9b13a46fb4..9426ef8926 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -952,10 +952,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg add= rl, tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); =20 /* TLB Hit - translate address using addend. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP0, addrl); - addrl =3D TCG_REG_TMP0; - } tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); } =20 @@ -1126,7 +1122,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr3= 2) { tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } @@ -1192,7 +1188,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr3= 2) { tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } --=20 2.25.1