From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633627285285925.4931488540815; Thu, 7 Oct 2021 10:21:25 -0700 (PDT) Received: from localhost ([::1]:46652 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYX5A-0004le-7g for importer@patchew.org; Thu, 07 Oct 2021 13:21:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWKv-000721-5P; Thu, 07 Oct 2021 12:33:37 -0400 Received: from mga06.intel.com ([134.134.136.31]:50270) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWKs-0002V0-V8; Thu, 07 Oct 2021 12:33:36 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:25:48 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:25:46 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="287184271" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="287184271" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325693" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 01/15] pcie: Set default and supported MaxReadReq to 512 Date: Thu, 7 Oct 2021 18:23:52 +0200 Message-Id: <20211007162406.1920374-2-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=lukasz.maniak@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-block@nongnu.org, "Michael S. Tsirkin" , =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Knut Omang , Lukasz Maniak , Knut Omang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633627287500100003 Content-Type: text/plain; charset="utf-8" From: Knut Omang Make the default PCI Express Capability for PCIe devices set MaxReadReq to 512. Tyipcal modern devices people would want to emulate or simulate would want this. The previous value would cause warnings from the root port driver on some kernels. Signed-off-by: Knut Omang --- hw/pci/pcie.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 6e95d82903..c1a12f3744 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -62,8 +62,9 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t ty= pe, uint8_t version) * Functions conforming to the ECN, PCI Express Base * Specification, Revision 1.1., or subsequent PCI Express Base * Specification revisions. + * + set max payload size to 256, which seems to be a common value */ - pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); + pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER | (0x1 & PC= I_EXP_DEVCAP_PAYLOAD)); =20 pci_set_long(exp_cap + PCI_EXP_LNKCAP, (port << PCI_EXP_LNKCAP_PN_SHIFT) | @@ -179,6 +180,8 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, pci_set_long(exp_cap + PCI_EXP_DEVCAP2, PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); =20 + pci_set_word(exp_cap + PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_READRQ_256B); + pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLP= PB); =20 if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) { --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633626869531739.0427298032655; Thu, 7 Oct 2021 10:14:29 -0700 (PDT) Received: from localhost ([::1]:54228 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYWyS-0007hJ-Df for importer@patchew.org; Thu, 07 Oct 2021 13:14:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWL1-0007A3-PM; Thu, 07 Oct 2021 12:33:43 -0400 Received: from mga06.intel.com ([134.134.136.31]:50281) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWKy-0002as-O0; Thu, 07 Oct 2021 12:33:43 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:25:51 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:25:48 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="287184305" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="287184305" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325724" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 02/15] pcie: Add support for Single Root I/O Virtualization (SR/IOV) Date: Thu, 7 Oct 2021 18:23:53 +0200 Message-Id: <20211007162406.1920374-3-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=lukasz.maniak@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-block@nongnu.org, "Michael S. Tsirkin" , =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Knut Omang , Lukasz Maniak , Knut Omang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633626871089100008 Content-Type: text/plain; charset="utf-8" From: Knut Omang This patch provides the building blocks for creating an SR/IOV PCIe Extended Capability header and register/unregister SR/IOV Virtual Functions. Signed-off-by: Knut Omang --- hw/pci/meson.build | 1 + hw/pci/pci.c | 97 +++++++++--- hw/pci/pcie.c | 5 + hw/pci/pcie_sriov.c | 287 ++++++++++++++++++++++++++++++++++++ hw/pci/trace-events | 5 + include/hw/pci/pci.h | 12 +- include/hw/pci/pcie.h | 6 + include/hw/pci/pcie_sriov.h | 67 +++++++++ include/qemu/typedefs.h | 2 + 9 files changed, 456 insertions(+), 26 deletions(-) create mode 100644 hw/pci/pcie_sriov.c create mode 100644 include/hw/pci/pcie_sriov.h diff --git a/hw/pci/meson.build b/hw/pci/meson.build index 5c4bbac817..bcc9c75919 100644 --- a/hw/pci/meson.build +++ b/hw/pci/meson.build @@ -5,6 +5,7 @@ pci_ss.add(files( 'pci.c', 'pci_bridge.c', 'pci_host.c', + 'pcie_sriov.c', 'shpc.c', 'slotid_cap.c' )) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 186758ee11..1ad647f78e 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -239,6 +239,9 @@ int pci_bar(PCIDevice *d, int reg) { uint8_t type; =20 + /* PCIe virtual functions do not have their own BARs */ + assert(!pci_is_vf(d)); + if (reg !=3D PCI_ROM_SLOT) return PCI_BASE_ADDRESS_0 + reg * 4; =20 @@ -304,10 +307,30 @@ void pci_device_deassert_intx(PCIDevice *dev) } } =20 -static void pci_do_device_reset(PCIDevice *dev) +static void pci_reset_regions(PCIDevice *dev) { int r; + if (pci_is_vf(dev)) { + return; + } + + for (r =3D 0; r < PCI_NUM_REGIONS; ++r) { + PCIIORegion *region =3D &dev->io_regions[r]; + if (!region->size) { + continue; + } + + if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && + region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { + pci_set_quad(dev->config + pci_bar(dev, r), region->type); + } else { + pci_set_long(dev->config + pci_bar(dev, r), region->type); + } + } +} =20 +static void pci_do_device_reset(PCIDevice *dev) +{ pci_device_deassert_intx(dev); assert(dev->irq_state =3D=3D 0); =20 @@ -323,19 +346,7 @@ static void pci_do_device_reset(PCIDevice *dev) pci_get_word(dev->wmask + PCI_INTERRUPT_LINE= ) | pci_get_word(dev->w1cmask + PCI_INTERRUPT_LI= NE)); dev->config[PCI_CACHE_LINE_SIZE] =3D 0x0; - for (r =3D 0; r < PCI_NUM_REGIONS; ++r) { - PCIIORegion *region =3D &dev->io_regions[r]; - if (!region->size) { - continue; - } - - if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && - region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { - pci_set_quad(dev->config + pci_bar(dev, r), region->type); - } else { - pci_set_long(dev->config + pci_bar(dev, r), region->type); - } - } + pci_reset_regions(dev); pci_update_mappings(dev); =20 msi_reset(dev); @@ -884,6 +895,15 @@ static void pci_init_multifunction(PCIBus *bus, PCIDev= ice *dev, Error **errp) dev->config[PCI_HEADER_TYPE] |=3D PCI_HEADER_TYPE_MULTI_FUNCTION; } =20 + /* With SR/IOV and ARI, a device at function 0 need not be a multifunc= tion + * device, as it may just be a VF that ended up with function 0 in + * the legacy PCI interpretation. Avoid failing in such cases: + */ + if (pci_is_vf(dev) && + dev->exp.sriov_vf.pf->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { + return; + } + /* * multifunction bit is interpreted in two ways as follows. * - all functions must set the bit to 1. @@ -1083,6 +1103,7 @@ static PCIDevice *do_pci_register_device(PCIDevice *p= ci_dev, bus->devices[devfn]->name); return NULL; } else if (dev->hotplugged && + !pci_is_vf(pci_dev) && pci_get_function_0(pci_dev)) { error_setg(errp, "PCI: slot %d function 0 already occupied by %s," " new func %s cannot be exposed to guest.", @@ -1191,6 +1212,7 @@ void pci_register_bar(PCIDevice *pci_dev, int region_= num, pcibus_t size =3D memory_region_size(memory); uint8_t hdr_type; =20 + assert(!pci_is_vf(pci_dev)); /* VFs must use pcie_sriov_vf_register_ba= r */ assert(region_num >=3D 0); assert(region_num < PCI_NUM_REGIONS); assert(is_power_of_2(size)); @@ -1294,11 +1316,43 @@ pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int r= egion_num) return pci_dev->io_regions[region_num].addr; } =20 -static pcibus_t pci_bar_address(PCIDevice *d, - int reg, uint8_t type, pcibus_t size) +static pcibus_t pci_config_get_bar_addr(PCIDevice *d, int reg, + uint8_t type, pcibus_t size) +{ + pcibus_t new_addr; + if (!pci_is_vf(d)) { + int bar =3D pci_bar(d, reg); + if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { + new_addr =3D pci_get_quad(d->config + bar); + } else { + new_addr =3D pci_get_long(d->config + bar); + } + } else { + PCIDevice *pf =3D d->exp.sriov_vf.pf; + uint16_t sriov_cap =3D pf->exp.sriov_cap; + int bar =3D sriov_cap + PCI_SRIOV_BAR + reg * 4; + uint16_t vf_offset =3D pci_get_word(pf->config + sriov_cap + PCI_S= RIOV_VF_OFFSET); + uint16_t vf_stride =3D pci_get_word(pf->config + sriov_cap + PCI_S= RIOV_VF_STRIDE); + uint32_t vf_num =3D (d->devfn - (pf->devfn + vf_offset)) / vf_stri= de; + + if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { + new_addr =3D pci_get_quad(pf->config + bar); + } else { + new_addr =3D pci_get_long(pf->config + bar); + } + new_addr +=3D vf_num * size; + } + if (reg !=3D PCI_ROM_SLOT) { + /* Preserve the rom enable bit */ + new_addr &=3D ~(size - 1); + } + return new_addr; +} + +pcibus_t pci_bar_address(PCIDevice *d, + int reg, uint8_t type, pcibus_t size) { pcibus_t new_addr, last_addr; - int bar =3D pci_bar(d, reg); uint16_t cmd =3D pci_get_word(d->config + PCI_COMMAND); Object *machine =3D qdev_get_machine(); ObjectClass *oc =3D object_get_class(machine); @@ -1309,7 +1363,7 @@ static pcibus_t pci_bar_address(PCIDevice *d, if (!(cmd & PCI_COMMAND_IO)) { return PCI_BAR_UNMAPPED; } - new_addr =3D pci_get_long(d->config + bar) & ~(size - 1); + new_addr =3D pci_config_get_bar_addr(d, reg, type, size); last_addr =3D new_addr + size - 1; /* Check if 32 bit BAR wraps around explicitly. * TODO: make priorities correct and remove this work around. @@ -1324,11 +1378,7 @@ static pcibus_t pci_bar_address(PCIDevice *d, if (!(cmd & PCI_COMMAND_MEMORY)) { return PCI_BAR_UNMAPPED; } - if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { - new_addr =3D pci_get_quad(d->config + bar); - } else { - new_addr =3D pci_get_long(d->config + bar); - } + new_addr =3D pci_config_get_bar_addr(d, reg, type, size); /* the ROM slot has a specific enable bit */ if (reg =3D=3D PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { return PCI_BAR_UNMAPPED; @@ -1470,6 +1520,7 @@ void pci_default_write_config(PCIDevice *d, uint32_t = addr, uint32_t val_in, int =20 msi_write_config(d, addr, val_in, l); msix_write_config(d, addr, val_in, l); + pcie_sriov_config_write(d, addr, val_in, l); } =20 /***********************************************************/ diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index c1a12f3744..8c6982d03c 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -426,6 +426,11 @@ void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev= , DeviceState *dev, PCIDevice *pci_dev =3D PCI_DEVICE(dev); uint32_t lnkcap =3D pci_get_long(exp_cap + PCI_EXP_LNKCAP); =20 + if(pci_is_vf(pci_dev)) { + /* We don't want to change any state in hotplug_dev for SR/IOV vir= tual functions */ + return; + } + /* Don't send event when device is enabled during qemu machine creatio= n: * it is present on boot, no hotplug event is necessary. We do send an * event when the device is disabled later. */ diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c new file mode 100644 index 0000000000..501a1ff433 --- /dev/null +++ b/hw/pci/pcie_sriov.c @@ -0,0 +1,287 @@ +/* + * pcie_sriov.c: + * + * Implementation of SR/IOV emulation support. + * + * Copyright (c) 2015-2017 Knut Omang + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci.h" +#include "hw/pci/pcie.h" +#include "hw/pci/pci_bus.h" +#include "hw/qdev-properties.h" +#include "qemu/error-report.h" +#include "qemu/range.h" +#include "qapi/error.h" +#include "trace.h" + +#define SRIOV_ID(dev) \ + (dev)->name, PCI_SLOT((dev)->devfn), PCI_FUNC((dev)->devfn) + +static PCIDevice *register_vf(PCIDevice *pf, int devfn, + const char *name, uint16_t vf_num); +static void unregister_vfs(PCIDevice *dev); + +void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, + const char *vfname, uint16_t vf_dev_id, + uint16_t init_vfs, uint16_t total_vfs, + uint16_t vf_offset, uint16_t vf_stride) +{ + uint8_t *cfg =3D dev->config + offset; + uint8_t *wmask; + + pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1, + offset, PCI_EXT_CAP_SRIOV_SIZEOF); + dev->exp.sriov_cap =3D offset; + dev->exp.sriov_pf.num_vfs =3D 0; + dev->exp.sriov_pf.vfname =3D g_strdup(vfname); + dev->exp.sriov_pf.vf =3D NULL; + + pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset); + pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride); + + /* Mandatory page sizes to support. + * Device implementations can call pcie_sriov_pf_add_sup_pgsize() + * to set more bits: + */ + pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ); + + /* Default is to use 4K pages, software can modify it + * to any of the supported bits + */ + pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1); + + /* Set up device ID and initial/total number of VFs available */ + pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id); + pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs); + pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs); + pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0); + + /* Write enable control bits */ + wmask =3D dev->wmask + offset; + pci_set_word(wmask + PCI_SRIOV_CTRL, + PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_= ARI); + pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff); + pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553); + + qdev_prop_set_bit(&dev->qdev, "multifunction", true); +} + +void pcie_sriov_pf_exit(PCIDevice *dev) +{ + unregister_vfs(dev); + g_free((char *)dev->exp.sriov_pf.vfname); + dev->exp.sriov_pf.vfname =3D NULL; +} + +void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, + uint8_t type, dma_addr_t size) +{ + uint32_t addr; + uint64_t wmask; + uint16_t sriov_cap =3D dev->exp.sriov_cap; + + assert(sriov_cap > 0); + assert(region_num >=3D 0); + assert(region_num < PCI_NUM_REGIONS); + assert(region_num !=3D PCI_ROM_SLOT); + + wmask =3D ~(size - 1); + addr =3D sriov_cap + PCI_SRIOV_BAR + region_num * 4; + + pci_set_long(dev->config + addr, type); + if (!(type & PCI_BASE_ADDRESS_SPACE_IO) && + type & PCI_BASE_ADDRESS_MEM_TYPE_64) { + pci_set_quad(dev->wmask + addr, wmask); + pci_set_quad(dev->cmask + addr, ~0ULL); + } else { + pci_set_long(dev->wmask + addr, wmask & 0xffffffff); + pci_set_long(dev->cmask + addr, 0xffffffff); + } + dev->exp.sriov_pf.vf_bar_type[region_num] =3D type; +} + +void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num, + MemoryRegion *memory) +{ + PCIIORegion *r; + PCIBus *bus =3D pci_get_bus(dev); + uint8_t type; + pcibus_t size =3D memory_region_size(memory); + + assert(pci_is_vf(dev)); /* PFs must use pci_register_bar */ + assert(region_num >=3D 0); + assert(region_num < PCI_NUM_REGIONS); + type =3D dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num]; + + if (!is_power_of_2(size)) { + error_report("%s: PCI region size must be a power" + " of two - type=3D0x%x, size=3D0x%"FMT_PCIBUS, + __func__, type, size); + exit(1); + } + + r =3D &dev->io_regions[region_num]; + r->memory =3D memory; + r->address_space =3D + type & PCI_BASE_ADDRESS_SPACE_IO + ? bus->address_space_io + : bus->address_space_mem; + r->size =3D size; + r->type =3D type; + + r->addr =3D pci_bar_address(dev, region_num, r->type, r->size); + if (r->addr !=3D PCI_BAR_UNMAPPED) { + memory_region_add_subregion_overlap(r->address_space, + r->addr, r->memory, 1); + } +} + +static PCIDevice *register_vf(PCIDevice *pf, int devfn, const char *name, + uint16_t vf_num) +{ + PCIDevice *dev =3D pci_new(devfn, name); + dev->exp.sriov_vf.pf =3D pf; + dev->exp.sriov_vf.vf_number =3D vf_num; + PCIBus* bus =3D pci_get_bus(pf); + Error *local_err =3D NULL; + + qdev_realize(&dev->qdev, &bus->qbus, &local_err); + if (local_err) { + error_report_err(local_err); + return NULL; + } + + /* set vid/did according to sr/iov spec - they are not used */ + pci_config_set_vendor_id(dev->config, 0xffff); + pci_config_set_device_id(dev->config, 0xffff); + + return dev; +} + +static void register_vfs(PCIDevice *dev) +{ + uint16_t num_vfs; + uint16_t i; + uint16_t sriov_cap =3D dev->exp.sriov_cap; + uint16_t vf_offset =3D pci_get_word(dev->config + sriov_cap + PCI_SRIO= V_VF_OFFSET); + uint16_t vf_stride =3D pci_get_word(dev->config + sriov_cap + PCI_SRIO= V_VF_STRIDE); + int32_t devfn =3D dev->devfn + vf_offset; + + assert(sriov_cap > 0); + num_vfs =3D pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); + + dev->exp.sriov_pf.vf =3D g_malloc(sizeof(PCIDevice *) * num_vfs); + assert(dev->exp.sriov_pf.vf); + + trace_sriov_register_vfs(SRIOV_ID(dev), num_vfs); + for (i =3D 0; i < num_vfs; i++) { + dev->exp.sriov_pf.vf[i] =3D register_vf(dev, devfn, dev->exp.sriov= _pf.vfname, i); + if (!dev->exp.sriov_pf.vf[i]) { + num_vfs =3D i; + break; + } + devfn +=3D vf_stride; + } + dev->exp.sriov_pf.num_vfs =3D num_vfs; +} + +static void unregister_vfs(PCIDevice *dev) +{ + Error *local_err =3D NULL; + uint16_t num_vfs =3D dev->exp.sriov_pf.num_vfs; + uint16_t i; + + trace_sriov_unregister_vfs(SRIOV_ID(dev), num_vfs); + for (i =3D 0; i < num_vfs; i++) { + PCIDevice *vf =3D dev->exp.sriov_pf.vf[i]; + object_property_set_bool(OBJECT(vf), "realized", false, &local_err= ); + if (local_err) { + fprintf(stderr, "Failed to unplug: %s\n", + error_get_pretty(local_err)); + error_free(local_err); + } + object_unparent(OBJECT(vf)); + } + g_free(dev->exp.sriov_pf.vf); + dev->exp.sriov_pf.vf =3D NULL; + dev->exp.sriov_pf.num_vfs =3D 0; + pci_set_word(dev->config + dev->exp.sriov_cap + PCI_SRIOV_NUM_VF, 0); +} + +void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, uint32_t va= l, int len) +{ + uint32_t off; + uint16_t sriov_cap =3D dev->exp.sriov_cap; + + if (!sriov_cap || address < sriov_cap) { + return; + } + off =3D address - sriov_cap; + if (off >=3D PCI_EXT_CAP_SRIOV_SIZEOF) { + return; + } + + trace_sriov_config_write(SRIOV_ID(dev), off, val, len); + + if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) { + if (dev->exp.sriov_pf.num_vfs) { + if (!(val & PCI_SRIOV_CTRL_VFE)) { + unregister_vfs(dev); + } + } else { + if (val & PCI_SRIOV_CTRL_VFE) { + register_vfs(dev); + } + } + } +} + + +/* Reset SR/IOV VF Enable bit to trigger an unregister of all VFs */ +void pcie_sriov_pf_disable_vfs(PCIDevice *dev) +{ + uint16_t sriov_cap =3D dev->exp.sriov_cap; + if (sriov_cap) { + uint32_t val =3D pci_get_byte(dev->config + sriov_cap + PCI_SRIOV_= CTRL); + if (val & PCI_SRIOV_CTRL_VFE) { + val &=3D ~PCI_SRIOV_CTRL_VFE; + pcie_sriov_config_write(dev, sriov_cap + PCI_SRIOV_CTRL, val, = 1); + } + } +} + +/* Add optional supported page sizes to the mask of supported page sizes */ +void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize) +{ + uint8_t *cfg =3D dev->config + dev->exp.sriov_cap; + uint8_t *wmask =3D dev->wmask + dev->exp.sriov_cap; + + uint16_t sup_pgsize =3D pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE); + + sup_pgsize |=3D opt_sup_pgsize; + + /* Make sure the new bits are set, and that system page size + * also can be set to any of the new values according to spec: + */ + pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize); + pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize); +} + + +uint16_t pcie_sriov_vf_number(PCIDevice *dev) +{ + assert(pci_is_vf(dev)); + return dev->exp.sriov_vf.vf_number; +} + + +PCIDevice *pcie_sriov_get_pf(PCIDevice *dev) +{ + return dev->exp.sriov_vf.pf; +} diff --git a/hw/pci/trace-events b/hw/pci/trace-events index fc777d0b5e..bd92cf4a25 100644 --- a/hw/pci/trace-events +++ b/hw/pci/trace-events @@ -10,3 +10,8 @@ pci_cfg_write(const char *dev, unsigned devid, unsigned f= nid, unsigned offs, uns =20 # msix.c msix_write_config(char *name, bool enabled, bool masked) "dev %s enabled %= d masked %d" + +# hw/pci/pcie_sriov.c +sriov_register_vfs(const char *name, int slot, int function, int num_vfs) = "%s %02x:%x: creating %d vf devs" +sriov_unregister_vfs(const char *name, int slot, int function, int num_vfs= ) "%s %02x:%x: Unregistering %d vf devs" +sriov_config_write(const char *name, int slot, int fun, uint32_t offset, u= int32_t val, uint32_t len) "%s %02x:%x: sriov offset 0x%x val 0x%x len %d" diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 7fc90132cf..d1d242c93a 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -7,9 +7,6 @@ /* PCI includes legacy ISA access. */ #include "hw/isa/isa.h" =20 -#include "hw/pci/pcie.h" -#include "qom/object.h" - extern bool pci_available; =20 /* PCI bus */ @@ -156,6 +153,7 @@ enum { #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 =20 #include "hw/pci/pci_regs.h" +#include "hw/pci/pcie.h" =20 /* PCI HEADER_TYPE */ #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 @@ -493,6 +491,9 @@ typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *,= int); AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); =20 +pcibus_t pci_bar_address(PCIDevice *d, + int reg, uint8_t type, pcibus_t size); + static inline void pci_set_byte(uint8_t *config, uint8_t val) { @@ -768,6 +769,11 @@ static inline int pci_is_express_downstream_port(const= PCIDevice *d) return type =3D=3D PCI_EXP_TYPE_DOWNSTREAM || type =3D=3D PCI_EXP_TYPE= _ROOT_PORT; } =20 +static inline int pci_is_vf(const PCIDevice *d) +{ + return d->exp.sriov_vf.pf !=3D NULL; +} + static inline uint32_t pci_config_size(const PCIDevice *d) { return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_S= IZE; diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 6063bee0ec..168950a83b 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -24,6 +24,7 @@ #include "hw/pci/pci_regs.h" #include "hw/pci/pcie_regs.h" #include "hw/pci/pcie_aer.h" +#include "hw/pci/pcie_sriov.h" #include "hw/hotplug.h" =20 typedef enum { @@ -81,6 +82,11 @@ struct PCIExpressDevice { =20 /* ACS */ uint16_t acs_cap; + + /* SR/IOV */ + uint16_t sriov_cap; + PCIESriovPF sriov_pf; + PCIESriovVF sriov_vf; }; =20 #define COMPAT_PROP_PCP "power_controller_present" diff --git a/include/hw/pci/pcie_sriov.h b/include/hw/pci/pcie_sriov.h new file mode 100644 index 0000000000..0974f00054 --- /dev/null +++ b/include/hw/pci/pcie_sriov.h @@ -0,0 +1,67 @@ +/* + * pcie_sriov.h: + * + * Implementation of SR/IOV emulation support. + * + * Copyright (c) 2015 Knut Omang + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef QEMU_PCIE_SRIOV_H +#define QEMU_PCIE_SRIOV_H + +struct PCIESriovPF { + uint16_t num_vfs; /* Number of virtual functions created */ + uint8_t vf_bar_type[PCI_NUM_REGIONS]; /* Store type for each VF bar */ + const char *vfname; /* Reference to the device type used for t= he VFs */ + PCIDevice **vf; /* Pointer to an array of num_vfs VF devic= es */ +}; + +struct PCIESriovVF { + PCIDevice *pf; /* Pointer back to owner physical function= */ + uint16_t vf_number; /* Logical VF number of this function */ +}; + +void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, + const char *vfname, uint16_t vf_dev_id, + uint16_t init_vfs, uint16_t total_vfs, + uint16_t vf_offset, uint16_t vf_stride); +void pcie_sriov_pf_exit(PCIDevice *dev); + +/* Set up a VF bar in the SR/IOV bar area */ +void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, + uint8_t type, dma_addr_t size); + +/* Instantiate a bar for a VF */ +void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num, + MemoryRegion *memory); + +/* Default (minimal) page size support values as required by the SR/IOV st= andard: + * 0x553 << 12 =3D 0x553000 =3D 4K + 8K + 64K + 256K + 1M + 4M + */ +#define SRIOV_SUP_PGSIZE_MINREQ 0x553 + +/* Optionally add supported page sizes to the mask of supported page sizes + * Page size values are interpreted as opt_sup_pgsize << 12. + */ +void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize); + +/* SR/IOV capability config write handler */ +void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, + uint32_t val, int len); + +/* Reset SR/IOV VF Enable bit to unregister all VFs */ +void pcie_sriov_pf_disable_vfs(PCIDevice *dev); + +/* Get logical VF number of a VF - only valid for VFs */ +uint16_t pcie_sriov_vf_number(PCIDevice *dev); + +/* Get the physical function that owns this VF. + * Returns NULL if dev is not a virtual function + */ +PCIDevice *pcie_sriov_get_pf(PCIDevice *dev); + +#endif /* QEMU_PCIE_SRIOV_H */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index ee60eb3de4..5b302cb214 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -86,6 +86,8 @@ typedef struct PCIDevice PCIDevice; typedef struct PCIEAERErr PCIEAERErr; typedef struct PCIEAERLog PCIEAERLog; typedef struct PCIEAERMsg PCIEAERMsg; +typedef struct PCIESriovPF PCIESriovPF; +typedef struct PCIESriovVF PCIESriovVF; typedef struct PCIEPort PCIEPort; typedef struct PCIESlot PCIESlot; typedef struct PCIExpressDevice PCIExpressDevice; --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633627208325284.2155841861444; Thu, 7 Oct 2021 10:20:08 -0700 (PDT) Received: from localhost ([::1]:43610 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYX3u-0002ds-Tz for importer@patchew.org; Thu, 07 Oct 2021 13:20:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWL4-0007F8-UF; Thu, 07 Oct 2021 12:33:46 -0400 Received: from mga06.intel.com ([134.134.136.31]:50281) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWL3-0002as-60; Thu, 07 Oct 2021 12:33:46 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:25:53 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:25:51 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="287184344" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="287184344" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325746" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 03/15] pcie: Add some SR/IOV API documentation in docs/pcie_sriov.txt Date: Thu, 7 Oct 2021 18:23:54 +0200 Message-Id: <20211007162406.1920374-4-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=lukasz.maniak@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-block@nongnu.org, "Michael S. Tsirkin" , =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Knut Omang , Lukasz Maniak , Knut Omang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633627209347100001 Content-Type: text/plain; charset="utf-8" From: Knut Omang Add a small intro + minimal documentation for how to implement SR/IOV support for an emulated device. Signed-off-by: Knut Omang --- docs/pcie_sriov.txt | 115 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 docs/pcie_sriov.txt diff --git a/docs/pcie_sriov.txt b/docs/pcie_sriov.txt new file mode 100644 index 0000000000..f5e891e1d4 --- /dev/null +++ b/docs/pcie_sriov.txt @@ -0,0 +1,115 @@ +PCI SR/IOV EMULATION SUPPORT +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + +Description +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +SR/IOV (Single Root I/O Virtualization) is an optional extended capability +of a PCI Express device. It allows a single physical function (PF) to appe= ar as multiple +virtual functions (VFs) for the main purpose of eliminating software +overhead in I/O from virtual machines. + +Qemu now implements the basic common functionality to enable an emulated d= evice +to support SR/IOV. Yet no fully implemented devices exists in Qemu, but a +proof-of-concept hack of the Intel igb can be found here: + +git://github.com/knuto/qemu.git sriov_patches_v5 + +Implementation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Implementing emulation of an SR/IOV capable device typically consists of +implementing support for two types of device classes; the "normal" physica= l device +(PF) and the virtual device (VF). From Qemu's perspective, the VFs are just +like other devices, except that some of their properties are derived from +the PF. + +A virtual function is different from a physical function in that the BAR +space for all VFs are defined by the BAR registers in the PFs SR/IOV +capability. All VFs have the same BARs and BAR sizes. + +Accesses to these virtual BARs then is computed as + + + * + + +From our emulation perspective this means that there is a separate call for +setting up a BAR for a VF. + +1) To enable SR/IOV support in the PF, it must be a PCI Express device so + you would need to add a PCI Express capability in the normal PCI + capability list. You might also want to add an ARI (Alternative + Routing-ID Interpretation) capability to indicate that your device + supports functions beyond it's "own" function space (0-7), + which is necessary to support more than 7 functions, or + if functions extends beyond offset 7 because they are placed at an + offset > 1 or have stride > 1. + + ... + #include "hw/pci/pcie.h" + #include "hw/pci/pcie_sriov.h" + + pci_your_pf_dev_realize( ... ) + { + ... + int ret =3D pcie_endpoint_cap_init(d, 0x70); + ... + pcie_ari_init(d, 0x100, 1); + ... + + /* Add and initialize the SR/IOV capability */ + pcie_sriov_pf_init(d, 0x200, "your_virtual_dev", + vf_devid, initial_vfs, total_vfs, + fun_offset, stride); + + /* Set up individual VF BARs (parameters as for normal BARs) */ + pcie_sriov_pf_init_vf_bar( ... ) + ... + } + + For cleanup, you simply call: + + pcie_sriov_pf_exit(device); + + which will delete all the virtual functions and associated resources. + +2) Similarly in the implementation of the virtual function, you need to + make it a PCI Express device and add a similar set of capabilities + except for the SR/IOV capability. Then you need to set up the VF BARs as + subregions of the PFs SR/IOV VF BARs by calling + pcie_sriov_vf_register_bar() instead of the normal pci_register_bar() c= all: + + pci_your_vf_dev_realize( ... ) + { + ... + int ret =3D pcie_endpoint_cap_init(d, 0x60); + ... + pcie_ari_init(d, 0x100, 1); + ... + memory_region_init(mr, ... ) + pcie_sriov_vf_register_bar(d, bar_nr, mr); + ... + } + +Testing on Linux guest +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The easiest is if your device driver supports sysfs based SR/IOV +enabling. Support for this was added in kernel v.3.8, so not all drivers +support it yet. + +To enable 4 VFs for a device at 01:00.0: + + modprobe yourdriver + echo 4 > /sys/bus/pci/devices/0000:01:00.0/sriov_numvfs + +You should now see 4 VFs with lspci. +To turn SR/IOV off again - the standard requires you to turn it off before= you can enable +another VF count, and the emulation enforces this: + + echo 0 > /sys/bus/pci/devices/0000:01:00.0/sriov_numvfs + +Older drivers typically provide a max_vfs module parameter +to enable it at load time: + + modprobe yourdriver max_vfs=3D4 + +To disable the VFs again then, you simply have to unload the driver: + + rmmod yourdriver --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633627344436466.29825942782827; Thu, 7 Oct 2021 10:22:24 -0700 (PDT) Received: from localhost ([::1]:52108 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYX67-0008LJ-F5 for importer@patchew.org; Thu, 07 Oct 2021 13:22:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWL7-0007LX-96; Thu, 07 Oct 2021 12:33:49 -0400 Received: from mga06.intel.com ([134.134.136.31]:50288) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWL4-0002eE-S6; Thu, 07 Oct 2021 12:33:49 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:25:55 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:25:53 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="287184368" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="287184368" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325771" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 04/15] pcie: Add callback preceding SR-IOV VFs update Date: Thu, 7 Oct 2021 18:23:55 +0200 Message-Id: <20211007162406.1920374-5-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=lukasz.maniak@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Lukasz Maniak , qemu-block@nongnu.org, "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633627345750100001 Content-Type: text/plain; charset="utf-8" PCIe devices implementing SR-IOV may need to perform certain actions before the VFs are unrealized or vice versa. Signed-off-by: Lukasz Maniak --- docs/pcie_sriov.txt | 2 +- hw/pci/pcie_sriov.c | 14 +++++++++++++- include/hw/pci/pcie_sriov.h | 8 +++++++- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/docs/pcie_sriov.txt b/docs/pcie_sriov.txt index f5e891e1d4..63ca1a7b8e 100644 --- a/docs/pcie_sriov.txt +++ b/docs/pcie_sriov.txt @@ -57,7 +57,7 @@ setting up a BAR for a VF. /* Add and initialize the SR/IOV capability */ pcie_sriov_pf_init(d, 0x200, "your_virtual_dev", vf_devid, initial_vfs, total_vfs, - fun_offset, stride); + fun_offset, stride, pre_vfs_update_cb); =20 /* Set up individual VF BARs (parameters as for normal BARs) */ pcie_sriov_pf_init_vf_bar( ... ) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index 501a1ff433..cac2aee061 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_sriov.c @@ -30,7 +30,8 @@ static void unregister_vfs(PCIDevice *dev); void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, const char *vfname, uint16_t vf_dev_id, uint16_t init_vfs, uint16_t total_vfs, - uint16_t vf_offset, uint16_t vf_stride) + uint16_t vf_offset, uint16_t vf_stride, + SriovVfsUpdate pre_vfs_update) { uint8_t *cfg =3D dev->config + offset; uint8_t *wmask; @@ -41,6 +42,7 @@ void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, dev->exp.sriov_pf.num_vfs =3D 0; dev->exp.sriov_pf.vfname =3D g_strdup(vfname); dev->exp.sriov_pf.vf =3D NULL; + dev->exp.sriov_pf.pre_vfs_update =3D pre_vfs_update; =20 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset); pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride); @@ -180,6 +182,11 @@ static void register_vfs(PCIDevice *dev) assert(dev->exp.sriov_pf.vf); =20 trace_sriov_register_vfs(SRIOV_ID(dev), num_vfs); + + if (dev->exp.sriov_pf.pre_vfs_update) { + dev->exp.sriov_pf.pre_vfs_update(dev, dev->exp.sriov_pf.num_vfs, n= um_vfs); + } + for (i =3D 0; i < num_vfs; i++) { dev->exp.sriov_pf.vf[i] =3D register_vf(dev, devfn, dev->exp.sriov= _pf.vfname, i); if (!dev->exp.sriov_pf.vf[i]) { @@ -198,6 +205,11 @@ static void unregister_vfs(PCIDevice *dev) uint16_t i; =20 trace_sriov_unregister_vfs(SRIOV_ID(dev), num_vfs); + + if (dev->exp.sriov_pf.pre_vfs_update) { + dev->exp.sriov_pf.pre_vfs_update(dev, dev->exp.sriov_pf.num_vfs, 0= ); + } + for (i =3D 0; i < num_vfs; i++) { PCIDevice *vf =3D dev->exp.sriov_pf.vf[i]; object_property_set_bool(OBJECT(vf), "realized", false, &local_err= ); diff --git a/include/hw/pci/pcie_sriov.h b/include/hw/pci/pcie_sriov.h index 0974f00054..9ab48b79c0 100644 --- a/include/hw/pci/pcie_sriov.h +++ b/include/hw/pci/pcie_sriov.h @@ -13,11 +13,16 @@ #ifndef QEMU_PCIE_SRIOV_H #define QEMU_PCIE_SRIOV_H =20 +typedef void (*SriovVfsUpdate)(PCIDevice *dev, uint16_t prev_num_vfs, + uint16_t num_vfs); + struct PCIESriovPF { uint16_t num_vfs; /* Number of virtual functions created */ uint8_t vf_bar_type[PCI_NUM_REGIONS]; /* Store type for each VF bar */ const char *vfname; /* Reference to the device type used for t= he VFs */ PCIDevice **vf; /* Pointer to an array of num_vfs VF devic= es */ + + SriovVfsUpdate pre_vfs_update; /* Callback preceding VFs count change= */ }; =20 struct PCIESriovVF { @@ -28,7 +33,8 @@ struct PCIESriovVF { void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, const char *vfname, uint16_t vf_dev_id, uint16_t init_vfs, uint16_t total_vfs, - uint16_t vf_offset, uint16_t vf_stride); + uint16_t vf_offset, uint16_t vf_stride, + SriovVfsUpdate pre_vfs_update); void pcie_sriov_pf_exit(PCIDevice *dev); =20 /* Set up a VF bar in the SR/IOV bar area */ --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633627086893580.6500270169197; Thu, 7 Oct 2021 10:18:06 -0700 (PDT) Received: from localhost ([::1]:36178 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYX1x-00069E-Qb for importer@patchew.org; Thu, 07 Oct 2021 13:18:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWLF-0007ZE-LV; Thu, 07 Oct 2021 12:33:57 -0400 Received: from mga06.intel.com ([134.134.136.31]:50306) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWLC-0002mP-EN; Thu, 07 Oct 2021 12:33:57 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:25:57 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:25:55 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="287184408" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="287184408" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325800" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 05/15] hw/nvme: Add support for SR-IOV Date: Thu, 7 Oct 2021 18:23:56 +0200 Message-Id: <20211007162406.1920374-6-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=lukasz.maniak@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-block@nongnu.org, "Michael S. Tsirkin" , =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Lukasz Maniak , Klaus Jensen , Keith Busch Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633627088294100001 Content-Type: text/plain; charset="utf-8" This patch implements initial support for Single Root I/O Virtualization on an NVMe device. Essentially, it allows to define the maximum number of virtual functions supported by the NVMe controller via sriov_max_vfs parameter. Passing a non-zero value to sriov_max_vfs triggers reporting of SR-IOV capability by a physical controller and ARI capability by both the physical and virtual function devices. NVMe controllers created via virtual functions mirror functionally the physical controller, which may not entirely be the case, thus consideration would be needed on the way to limit the capabilities of the VF. NVMe subsystem is required for the use of SR-IOV. Signed-off-by: Lukasz Maniak --- hw/nvme/ctrl.c | 74 ++++++++++++++++++++++++++++++++++++++-- hw/nvme/nvme.h | 1 + include/hw/pci/pci_ids.h | 1 + 3 files changed, 73 insertions(+), 3 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 6a571d18cf..ad79ff0c00 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -35,6 +35,7 @@ * mdts=3D,vsl=3D, \ * zoned.zasl=3D, \ * zoned.auto_transition=3D, \ + * sriov_max_vfs=3D \ * subsys=3D * -device nvme-ns,drive=3D,bus=3D,nsid=3D,\ * zoned=3D, \ @@ -106,6 +107,12 @@ * transitioned to zone state closed for resource management purposes. * Defaults to 'on'. * + * - `sriov_max_vfs` + * Indicates the maximum number of PCIe virtual functions supported + * by the controller. The default value is 0. Specifying a non-zero value + * enables reporting of both SR-IOV and ARI capabilities by the NVMe dev= ice. + * Virtual function controllers will not report SR-IOV capability. + * * nvme namespace device parameters * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * - `shared` @@ -160,6 +167,7 @@ #include "sysemu/block-backend.h" #include "sysemu/hostmem.h" #include "hw/pci/msix.h" +#include "hw/pci/pcie_sriov.h" #include "migration/vmstate.h" =20 #include "nvme.h" @@ -175,6 +183,9 @@ #define NVME_TEMPERATURE_CRITICAL 0x175 #define NVME_NUM_FW_SLOTS 1 #define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB) +#define NVME_MAX_VFS 127 +#define NVME_VF_OFFSET 0x1 +#define NVME_VF_STRIDE 1 =20 #define NVME_GUEST_ERR(trace, fmt, ...) \ do { \ @@ -5583,6 +5594,10 @@ static void nvme_ctrl_reset(NvmeCtrl *n) g_free(event); } =20 + if (!pci_is_vf(&n->parent_obj) && n->params.sriov_max_vfs) { + pcie_sriov_pf_disable_vfs(&n->parent_obj); + } + n->aer_queued =3D 0; n->outstanding_aers =3D 0; n->qs_created =3D false; @@ -6264,6 +6279,19 @@ static void nvme_check_constraints(NvmeCtrl *n, Erro= r **errp) error_setg(errp, "vsl must be non-zero"); return; } + + if (params->sriov_max_vfs) { + if (!n->subsys) { + error_setg(errp, "subsystem is required for the use of SR-IOV"= ); + return; + } + + if (params->sriov_max_vfs > NVME_MAX_VFS) { + error_setg(errp, "sriov_max_vfs must be between 0 and %d", + NVME_MAX_VFS); + return; + } + } } =20 static void nvme_init_state(NvmeCtrl *n) @@ -6321,6 +6349,20 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pc= i_dev) memory_region_set_enabled(&n->pmr.dev->mr, false); } =20 +static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offs= et, + uint64_t bar_size) +{ + uint16_t vf_dev_id =3D n->params.use_intel_id ? + PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_N= VME; + + pcie_sriov_pf_init(pci_dev, offset, "nvme", vf_dev_id, + n->params.sriov_max_vfs, n->params.sriov_max_vfs, + NVME_VF_OFFSET, NVME_VF_STRIDE, NULL); + + pcie_sriov_pf_init_vf_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, bar_size); +} + static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) { uint8_t *pci_conf =3D pci_dev->config; @@ -6335,7 +6377,7 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_= dev, Error **errp) =20 if (n->params.use_intel_id) { pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); - pci_config_set_device_id(pci_conf, 0x5845); + pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_NVME); } else { pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REDHAT); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REDHAT_NVME); @@ -6343,6 +6385,9 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_= dev, Error **errp) =20 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS); pcie_endpoint_cap_init(pci_dev, 0x80); + if (n->params.sriov_max_vfs) { + pcie_ari_init(pci_dev, 0x100, 1); + } =20 bar_size =3D QEMU_ALIGN_UP(n->reg_size, 4 * KiB); msix_table_offset =3D bar_size; @@ -6361,8 +6406,12 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci= _dev, Error **errp) n->reg_size); memory_region_add_subregion(&n->bar0, 0, &n->iomem); =20 - pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | - PCI_BASE_ADDRESS_MEM_TYPE_64, &n->bar0); + if (pci_is_vf(pci_dev)) { + pcie_sriov_vf_register_bar(pci_dev, 0, &n->bar0); + } else { + pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, &n->bar0); + } ret =3D msix_init(pci_dev, n->params.msix_qsize, &n->bar0, 0, msix_table_offset, &n->bar0, 0, msix_pba_offset, 0, &err); @@ -6383,6 +6432,10 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci= _dev, Error **errp) nvme_init_pmr(n, pci_dev); } =20 + if (!pci_is_vf(pci_dev) && n->params.sriov_max_vfs) { + nvme_init_sriov(n, pci_dev, 0x120, bar_size); + } + return 0; } =20 @@ -6532,6 +6585,15 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) NvmeCtrl *n =3D NVME(pci_dev); NvmeNamespace *ns; Error *local_err =3D NULL; + NvmeCtrl *pn =3D NVME(pcie_sriov_get_pf(pci_dev)); + + if (pci_is_vf(pci_dev)) { + /* VFs derive settings from the parent. PF's lifespan exceeds + * that of VF's, so it's safe to share params.serial. + */ + memcpy(&n->params, &pn->params, sizeof(NvmeParams)); + n->subsys =3D pn->subsys; + } =20 nvme_check_constraints(n, &local_err); if (local_err) { @@ -6596,6 +6658,11 @@ static void nvme_exit(PCIDevice *pci_dev) if (n->pmr.dev) { host_memory_backend_set_mapped(n->pmr.dev, false); } + + if (!pci_is_vf(pci_dev) && n->params.sriov_max_vfs) { + pcie_sriov_pf_exit(pci_dev); + } + msix_uninit(pci_dev, &n->bar0, &n->bar0); memory_region_del_subregion(&n->bar0, &n->iomem); } @@ -6620,6 +6687,7 @@ static Property nvme_props[] =3D { DEFINE_PROP_UINT8("zoned.zasl", NvmeCtrl, params.zasl, 0), DEFINE_PROP_BOOL("zoned.auto_transition", NvmeCtrl, params.auto_transition_zones, true), + DEFINE_PROP_UINT8("sriov_max_vfs", NvmeCtrl, params.sriov_max_vfs, 0), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index 83ffabade4..4331f5da1f 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -391,6 +391,7 @@ typedef struct NvmeParams { uint8_t zasl; bool auto_transition_zones; bool legacy_cmb; + uint8_t sriov_max_vfs; } NvmeParams; =20 typedef struct NvmeCtrl { diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index 11abe22d46..992426768e 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -237,6 +237,7 @@ #define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e #define PCI_DEVICE_ID_INTEL_82801D 0x24CD #define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab +#define PCI_DEVICE_ID_INTEL_NVME 0x5845 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 #define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633626868541265.3900220518366; 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a="225072986" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="225072986" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325822" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 06/15] hw/nvme: Add support for Primary Controller Capabilities Date: Thu, 7 Oct 2021 18:23:57 +0200 Message-Id: <20211007162406.1920374-7-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.120; envelope-from=lukasz.maniak@linux.intel.com; helo=mga04.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_NONE=0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Lukasz Maniak , Klaus Jensen , Hanna Reitz , Stefan Hajnoczi , Keith Busch , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633626869583100003 Content-Type: text/plain; charset="utf-8" Implementation of Primary Controller Capabilities data structure (Identify command with CNS value of 14h). Currently, the command returns only ID of a primary controller. Handling of remaining fields are added in subsequent patches implementing virtualization enhancements. Signed-off-by: Lukasz Maniak Reviewed-by: Klaus Jensen --- hw/nvme/ctrl.c | 22 +++++++++++++++++----- hw/nvme/nvme.h | 2 ++ hw/nvme/trace-events | 1 + include/block/nvme.h | 23 +++++++++++++++++++++++ 4 files changed, 43 insertions(+), 5 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index ad79ff0c00..d2fde3dd07 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -4538,6 +4538,13 @@ static uint16_t nvme_identify_ctrl_list(NvmeCtrl *n,= NvmeRequest *req, return nvme_c2h(n, (uint8_t *)list, sizeof(list), req); } =20 +static uint16_t nvme_identify_pri_ctrl_cap(NvmeCtrl *n, NvmeRequest *req) +{ + trace_pci_nvme_identify_pri_ctrl_cap(le16_to_cpu(n->pri_ctrl_cap.cntli= d)); + + return nvme_c2h(n, (uint8_t *)&n->pri_ctrl_cap, sizeof(NvmePriCtrlCap)= , req); +} + static uint16_t nvme_identify_ns_csi(NvmeCtrl *n, NvmeRequest *req, bool active) { @@ -4756,6 +4763,8 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeReques= t *req) return nvme_identify_ctrl_list(n, req, true); case NVME_ID_CNS_CTRL_LIST: return nvme_identify_ctrl_list(n, req, false); + case NVME_ID_CNS_PRIMARY_CTRL_CAP: + return nvme_identify_pri_ctrl_cap(n, req); case NVME_ID_CNS_CS_NS: return nvme_identify_ns_csi(n, req, true); case NVME_ID_CNS_CS_NS_PRESENT: @@ -6296,6 +6305,8 @@ static void nvme_check_constraints(NvmeCtrl *n, Error= **errp) =20 static void nvme_init_state(NvmeCtrl *n) { + NvmePriCtrlCap *cap =3D &n->pri_ctrl_cap; + /* add one to max_ioqpairs to account for the admin queue pair */ n->reg_size =3D pow2ceil(sizeof(NvmeBar) + 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); @@ -6305,6 +6316,8 @@ static void nvme_init_state(NvmeCtrl *n) n->features.temp_thresh_hi =3D NVME_TEMPERATURE_WARNING; n->starttime_ms =3D qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); n->aer_reqs =3D g_new0(NvmeRequest *, n->params.aerl + 1); + + cap->cntlid =3D cpu_to_le16(n->cntlid); } =20 static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev) @@ -6604,15 +6617,14 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) qbus_init(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS, &pci_dev->qdev, n->parent_obj.qdev.id); =20 - nvme_init_state(n); - if (nvme_init_pci(n, pci_dev, errp)) { - return; - } - if (nvme_init_subsys(n, errp)) { error_propagate(errp, local_err); return; } + nvme_init_state(n); + if (nvme_init_pci(n, pci_dev, errp)) { + return; + } nvme_init_ctrl(n, pci_dev); =20 /* setup a namespace if the controller drive property was given */ diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index 4331f5da1f..479817f66e 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -461,6 +461,8 @@ typedef struct NvmeCtrl { }; uint32_t async_config; } features; + + NvmePriCtrlCap pri_ctrl_cap; } NvmeCtrl; =20 static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid) diff --git a/hw/nvme/trace-events b/hw/nvme/trace-events index ff6cafd520..1014ebceb6 100644 --- a/hw/nvme/trace-events +++ b/hw/nvme/trace-events @@ -52,6 +52,7 @@ pci_nvme_identify_ctrl(void) "identify controller" pci_nvme_identify_ctrl_csi(uint8_t csi) "identify controller, csi=3D0x%"PR= Ix8"" pci_nvme_identify_ns(uint32_t ns) "nsid %"PRIu32"" pci_nvme_identify_ctrl_list(uint8_t cns, uint16_t cntid) "cns 0x%"PRIx8" c= ntid %"PRIu16"" +pci_nvme_identify_pri_ctrl_cap(uint16_t cntlid) "identify primary controll= er capabilities cntlid=3D%"PRIu16"" pci_nvme_identify_ns_csi(uint32_t ns, uint8_t csi) "nsid=3D%"PRIu32", csi= =3D0x%"PRIx8"" pci_nvme_identify_nslist(uint32_t ns) "nsid %"PRIu32"" pci_nvme_identify_nslist_csi(uint16_t ns, uint8_t csi) "nsid=3D%"PRIu16", = csi=3D0x%"PRIx8"" diff --git a/include/block/nvme.h b/include/block/nvme.h index e3bd47bf76..f69bd1d14f 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -1017,6 +1017,7 @@ enum NvmeIdCns { NVME_ID_CNS_NS_PRESENT =3D 0x11, NVME_ID_CNS_NS_ATTACHED_CTRL_LIST =3D 0x12, NVME_ID_CNS_CTRL_LIST =3D 0x13, + NVME_ID_CNS_PRIMARY_CTRL_CAP =3D 0x14, NVME_ID_CNS_CS_NS_PRESENT_LIST =3D 0x1a, NVME_ID_CNS_CS_NS_PRESENT =3D 0x1b, NVME_ID_CNS_IO_COMMAND_SET =3D 0x1c, @@ -1465,6 +1466,27 @@ typedef enum NvmeZoneState { NVME_ZONE_STATE_OFFLINE =3D 0x0f, } NvmeZoneState; =20 +typedef struct QEMU_PACKED NvmePriCtrlCap { + uint16_t cntlid; + uint16_t portid; + uint8_t crt; + uint8_t rsvd5[27]; + uint32_t vqfrt; + uint32_t vqrfa; + uint16_t vqrfap; + uint16_t vqprt; + uint16_t vqfrsm; + uint16_t vqgran; + uint8_t rsvd48[16]; + uint32_t vifrt; + uint32_t virfa; + uint16_t virfap; + uint16_t viprt; + uint16_t vifrsm; + uint16_t vigran; + uint8_t rsvd80[4016]; +} NvmePriCtrlCap; + static inline void _nvme_check_size(void) { QEMU_BUILD_BUG_ON(sizeof(NvmeBar) !=3D 4096); @@ -1497,5 +1519,6 @@ static inline void _nvme_check_size(void) QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) !=3D 4); QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) !=3D 64); QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) !=3D 8); + QEMU_BUILD_BUG_ON(sizeof(NvmePriCtrlCap) !=3D 4096); } #endif --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633626869124882.6255004056802; Thu, 7 Oct 2021 10:14:29 -0700 (PDT) Received: from localhost ([::1]:54226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYWyR-0007hB-TE for importer@patchew.org; Thu, 07 Oct 2021 13:14:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50854) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQM-00017c-1K; Thu, 07 Oct 2021 12:39:14 -0400 Received: from mga04.intel.com ([192.55.52.120]:55444) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQI-00007p-Rd; Thu, 07 Oct 2021 12:39:13 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:05 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:00 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="225072987" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="225072987" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325848" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 07/15] hw/nvme: Add support for Secondary Controller List Date: Thu, 7 Oct 2021 18:23:58 +0200 Message-Id: <20211007162406.1920374-8-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.120; envelope-from=lukasz.maniak@linux.intel.com; helo=mga04.intel.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Lukasz Maniak , Klaus Jensen , Hanna Reitz , Stefan Hajnoczi , Keith Busch , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633626871063100007 Content-Type: text/plain; charset="utf-8" Introduce handling for Secondary Controller List (Identify command with CNS value of 15h). Secondary controller ids are unique in the subsystem, hence they are reserved by it upon initialization of the primary controller to the number of sriov_max_vfs. ID reservation requires the addition of an intermediate controller slot state, so the reserved controller has the address 0xFFFF. A secondary controller is in the reserved state when it has no virtual function assigned, but its primary controller is realized. Secondary controller reservations are released to NULL when its primary controller is unregistered. Signed-off-by: Lukasz Maniak --- hw/nvme/ctrl.c | 42 ++++++++++++++++++++++++- hw/nvme/ns.c | 2 +- hw/nvme/nvme.h | 16 +++++++++- hw/nvme/subsys.c | 74 ++++++++++++++++++++++++++++++++++++++------ hw/nvme/trace-events | 1 + include/block/nvme.h | 20 ++++++++++++ 6 files changed, 143 insertions(+), 12 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index d2fde3dd07..9687a7322c 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -4545,6 +4545,14 @@ static uint16_t nvme_identify_pri_ctrl_cap(NvmeCtrl = *n, NvmeRequest *req) return nvme_c2h(n, (uint8_t *)&n->pri_ctrl_cap, sizeof(NvmePriCtrlCap)= , req); } =20 +static uint16_t nvme_identify_sec_ctrl_list(NvmeCtrl *n, NvmeRequest *req) +{ + trace_pci_nvme_identify_sec_ctrl_list(le16_to_cpu(n->pri_ctrl_cap.cntl= id), + n->sec_ctrl_list.numcntl); + + return nvme_c2h(n, (uint8_t *)&n->sec_ctrl_list, sizeof(NvmeSecCtrlLis= t), req); +} + static uint16_t nvme_identify_ns_csi(NvmeCtrl *n, NvmeRequest *req, bool active) { @@ -4765,6 +4773,8 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeReques= t *req) return nvme_identify_ctrl_list(n, req, false); case NVME_ID_CNS_PRIMARY_CTRL_CAP: return nvme_identify_pri_ctrl_cap(n, req); + case NVME_ID_CNS_SECONDARY_CTRL_LIST: + return nvme_identify_sec_ctrl_list(n, req); case NVME_ID_CNS_CS_NS: return nvme_identify_ns_csi(n, req, true); case NVME_ID_CNS_CS_NS_PRESENT: @@ -6306,6 +6316,9 @@ static void nvme_check_constraints(NvmeCtrl *n, Error= **errp) static void nvme_init_state(NvmeCtrl *n) { NvmePriCtrlCap *cap =3D &n->pri_ctrl_cap; + NvmeSecCtrlList *list =3D &n->sec_ctrl_list; + NvmeSecCtrlEntry *sctrl; + int i; =20 /* add one to max_ioqpairs to account for the admin queue pair */ n->reg_size =3D pow2ceil(sizeof(NvmeBar) + @@ -6317,6 +6330,12 @@ static void nvme_init_state(NvmeCtrl *n) n->starttime_ms =3D qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); n->aer_reqs =3D g_new0(NvmeRequest *, n->params.aerl + 1); =20 + list->numcntl =3D cpu_to_le16(n->params.sriov_max_vfs); + for (i =3D 0; i < n->params.sriov_max_vfs; i++) { + sctrl =3D &list->sec[i]; + sctrl->pcid =3D cpu_to_le16(n->cntlid); + } + cap->cntlid =3D cpu_to_le16(n->cntlid); } =20 @@ -6362,6 +6381,27 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pc= i_dev) memory_region_set_enabled(&n->pmr.dev->mr, false); } =20 +static void nvme_update_vfs(PCIDevice *pci_dev, uint16_t prev_num_vfs, + uint16_t num_vfs) +{ + NvmeCtrl *n =3D NVME(pci_dev); + uint16_t num_active_vfs =3D MAX(prev_num_vfs, num_vfs); + bool vf_enable =3D (prev_num_vfs < num_vfs); + uint16_t i; + + /* + * As per SR-IOV design, + * VF count can only go from 0 to a set value and vice versa. + */ + for (i =3D 0; i < num_active_vfs; i++) { + if (vf_enable) { + n->sec_ctrl_list.sec[i].vfn =3D cpu_to_le16(i + 1); + } else { + n->sec_ctrl_list.sec[i].vfn =3D 0; + } + } +} + static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offs= et, uint64_t bar_size) { @@ -6370,7 +6410,7 @@ static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *p= ci_dev, uint16_t offset, =20 pcie_sriov_pf_init(pci_dev, offset, "nvme", vf_dev_id, n->params.sriov_max_vfs, n->params.sriov_max_vfs, - NVME_VF_OFFSET, NVME_VF_STRIDE, NULL); + NVME_VF_OFFSET, NVME_VF_STRIDE, nvme_update_vfs); =20 pcie_sriov_pf_init_vf_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, bar_size); diff --git a/hw/nvme/ns.c b/hw/nvme/ns.c index b7cf1494e7..c70aed8c66 100644 --- a/hw/nvme/ns.c +++ b/hw/nvme/ns.c @@ -517,7 +517,7 @@ static void nvme_ns_realize(DeviceState *dev, Error **e= rrp) for (i =3D 0; i < ARRAY_SIZE(subsys->ctrls); i++) { NvmeCtrl *ctrl =3D subsys->ctrls[i]; =20 - if (ctrl) { + if (ctrl && ctrl !=3D SUBSYS_SLOT_RSVD) { nvme_attach_ns(ctrl, ns); } } diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index 479817f66e..fd229f06f0 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -24,7 +24,7 @@ =20 #include "block/nvme.h" =20 -#define NVME_MAX_CONTROLLERS 32 +#define NVME_MAX_CONTROLLERS 256 #define NVME_MAX_NAMESPACES 256 #define NVME_EUI64_DEFAULT ((uint64_t)0x5254000000000000) =20 @@ -43,6 +43,7 @@ typedef struct NvmeBus { #define TYPE_NVME_SUBSYS "nvme-subsys" #define NVME_SUBSYS(obj) \ OBJECT_CHECK(NvmeSubsystem, (obj), TYPE_NVME_SUBSYS) +#define SUBSYS_SLOT_RSVD (void *)0xFFFF =20 typedef struct NvmeSubsystem { DeviceState parent_obj; @@ -463,6 +464,7 @@ typedef struct NvmeCtrl { } features; =20 NvmePriCtrlCap pri_ctrl_cap; + NvmeSecCtrlList sec_ctrl_list; } NvmeCtrl; =20 static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid) @@ -497,6 +499,18 @@ static inline uint16_t nvme_cid(NvmeRequest *req) return le16_to_cpu(req->cqe.cid); } =20 +static inline NvmeSecCtrlEntry *nvme_sctrl(NvmeCtrl *n) +{ + PCIDevice *pci_dev =3D &n->parent_obj; + NvmeCtrl *pf =3D NVME(pcie_sriov_get_pf(pci_dev)); + + if (pci_is_vf(pci_dev)) { + return &pf->sec_ctrl_list.sec[pcie_sriov_vf_number(pci_dev)]; + } + + return NULL; +} + void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns); uint16_t nvme_bounce_data(NvmeCtrl *n, uint8_t *ptr, uint32_t len, NvmeTxDirection dir, NvmeRequest *req); diff --git a/hw/nvme/subsys.c b/hw/nvme/subsys.c index 495dcff5eb..43c295056f 100644 --- a/hw/nvme/subsys.c +++ b/hw/nvme/subsys.c @@ -11,20 +11,71 @@ =20 #include "nvme.h" =20 -int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp) +static int nvme_subsys_reserve_cntlids(NvmeCtrl *n, int start, int num) { NvmeSubsystem *subsys =3D n->subsys; - int cntlid; + NvmeSecCtrlList *list =3D &n->sec_ctrl_list; + NvmeSecCtrlEntry *sctrl; + int i, cnt =3D 0; + + for (i =3D start; i < ARRAY_SIZE(subsys->ctrls) && cnt < num; i++) { + if (!subsys->ctrls[i]) { + sctrl =3D &list->sec[cnt]; + sctrl->scid =3D cpu_to_le16(i); + subsys->ctrls[i] =3D SUBSYS_SLOT_RSVD; + cnt++; + } + } + + return cnt; +} =20 - for (cntlid =3D 0; cntlid < ARRAY_SIZE(subsys->ctrls); cntlid++) { - if (!subsys->ctrls[cntlid]) { - break; +static void nvme_subsys_unreserve_cntlids(NvmeCtrl *n) +{ + NvmeSubsystem *subsys =3D n->subsys; + NvmeSecCtrlList *list =3D &n->sec_ctrl_list; + NvmeSecCtrlEntry *sctrl; + int i, cntlid; + + for (i =3D 0; i < n->params.sriov_max_vfs; i++) { + sctrl =3D &list->sec[i]; + cntlid =3D le16_to_cpu(sctrl->scid); + + if (cntlid) { + assert(subsys->ctrls[cntlid] =3D=3D SUBSYS_SLOT_RSVD); + subsys->ctrls[cntlid] =3D NULL; + sctrl->scid =3D 0; } } +} =20 - if (cntlid =3D=3D ARRAY_SIZE(subsys->ctrls)) { - error_setg(errp, "no more free controller id"); - return -1; +int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp) +{ + NvmeSubsystem *subsys =3D n->subsys; + NvmeSecCtrlEntry *sctrl =3D nvme_sctrl(n); + int cntlid, num_rsvd, num_vfs =3D n->params.sriov_max_vfs; + + if (pci_is_vf(&n->parent_obj)) { + cntlid =3D le16_to_cpu(sctrl->scid); + } else { + for (cntlid =3D 0; cntlid < ARRAY_SIZE(subsys->ctrls); cntlid++) { + if (!subsys->ctrls[cntlid]) { + break; + } + } + + if (cntlid =3D=3D ARRAY_SIZE(subsys->ctrls)) { + error_setg(errp, "no more free controller id"); + return -1; + } + + num_rsvd =3D nvme_subsys_reserve_cntlids(n, cntlid + 1, num_vfs); + if (num_rsvd !=3D num_vfs) { + nvme_subsys_unreserve_cntlids(n); + error_setg(errp, + "no more free controller ids for secondary controll= ers"); + return -1; + } } =20 subsys->ctrls[cntlid] =3D n; @@ -34,7 +85,12 @@ int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp) =20 void nvme_subsys_unregister_ctrl(NvmeSubsystem *subsys, NvmeCtrl *n) { - subsys->ctrls[n->cntlid] =3D NULL; + if (pci_is_vf(&n->parent_obj)) { + subsys->ctrls[n->cntlid] =3D SUBSYS_SLOT_RSVD; + } else { + subsys->ctrls[n->cntlid] =3D NULL; + nvme_subsys_unreserve_cntlids(n); + } } =20 static void nvme_subsys_setup(NvmeSubsystem *subsys) diff --git a/hw/nvme/trace-events b/hw/nvme/trace-events index 1014ebceb6..dd2aac3418 100644 --- a/hw/nvme/trace-events +++ b/hw/nvme/trace-events @@ -53,6 +53,7 @@ pci_nvme_identify_ctrl_csi(uint8_t csi) "identify control= ler, csi=3D0x%"PRIx8"" pci_nvme_identify_ns(uint32_t ns) "nsid %"PRIu32"" pci_nvme_identify_ctrl_list(uint8_t cns, uint16_t cntid) "cns 0x%"PRIx8" c= ntid %"PRIu16"" pci_nvme_identify_pri_ctrl_cap(uint16_t cntlid) "identify primary controll= er capabilities cntlid=3D%"PRIu16"" +pci_nvme_identify_sec_ctrl_list(uint16_t cntlid, uint8_t numcntl) "identif= y secondary controller list cntlid=3D%"PRIu16" numcntl=3D%"PRIu8"" pci_nvme_identify_ns_csi(uint32_t ns, uint8_t csi) "nsid=3D%"PRIu32", csi= =3D0x%"PRIx8"" pci_nvme_identify_nslist(uint32_t ns) "nsid %"PRIu32"" pci_nvme_identify_nslist_csi(uint16_t ns, uint8_t csi) "nsid=3D%"PRIu16", = csi=3D0x%"PRIx8"" diff --git a/include/block/nvme.h b/include/block/nvme.h index f69bd1d14f..96595ea8f1 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -1018,6 +1018,7 @@ enum NvmeIdCns { NVME_ID_CNS_NS_ATTACHED_CTRL_LIST =3D 0x12, NVME_ID_CNS_CTRL_LIST =3D 0x13, NVME_ID_CNS_PRIMARY_CTRL_CAP =3D 0x14, + NVME_ID_CNS_SECONDARY_CTRL_LIST =3D 0x15, NVME_ID_CNS_CS_NS_PRESENT_LIST =3D 0x1a, NVME_ID_CNS_CS_NS_PRESENT =3D 0x1b, NVME_ID_CNS_IO_COMMAND_SET =3D 0x1c, @@ -1487,6 +1488,23 @@ typedef struct QEMU_PACKED NvmePriCtrlCap { uint8_t rsvd80[4016]; } NvmePriCtrlCap; =20 +typedef struct QEMU_PACKED NvmeSecCtrlEntry { + uint16_t scid; + uint16_t pcid; + uint8_t scs; + uint8_t rsvd5[3]; + uint16_t vfn; + uint16_t nvq; + uint16_t nvi; + uint8_t rsvd14[18]; +} NvmeSecCtrlEntry; + +typedef struct QEMU_PACKED NvmeSecCtrlList { + uint8_t numcntl; + uint8_t rsvd1[31]; + NvmeSecCtrlEntry sec[127]; +} NvmeSecCtrlList; + static inline void _nvme_check_size(void) { QEMU_BUILD_BUG_ON(sizeof(NvmeBar) !=3D 4096); @@ -1520,5 +1538,7 @@ static inline void _nvme_check_size(void) QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) !=3D 64); QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) !=3D 8); QEMU_BUILD_BUG_ON(sizeof(NvmePriCtrlCap) !=3D 4096); + QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlEntry) !=3D 32); + QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlList) !=3D 4096); } #endif --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16336275034011012.0726525860837; Thu, 7 Oct 2021 10:25:03 -0700 (PDT) Received: from localhost ([::1]:60148 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYX8g-0005GA-Dt for importer@patchew.org; Thu, 07 Oct 2021 13:25:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQN-0001D0-Mz; Thu, 07 Oct 2021 12:39:15 -0400 Received: from mga04.intel.com ([192.55.52.120]:55434) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQM-0008BP-0p; Thu, 07 Oct 2021 12:39:15 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:05 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:03 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="225072992" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="225072992" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325877" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 08/15] pcie: Add 1.2 version token for the Power Management Capability Date: Thu, 7 Oct 2021 18:23:59 +0200 Message-Id: <20211007162406.1920374-9-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.120; envelope-from=lukasz.maniak@linux.intel.com; helo=mga04.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Lukasz Maniak , qemu-block@nongnu.org, "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633627503996100001 From: =C5=81ukasz Gieryk Signed-off-by: =C5=81ukasz Gieryk --- include/hw/pci/pci_regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/pci/pci_regs.h b/include/hw/pci/pci_regs.h index 77ba64b931..a590140962 100644 --- a/include/hw/pci/pci_regs.h +++ b/include/hw/pci/pci_regs.h @@ -4,5 +4,6 @@ #include "standard-headers/linux/pci_regs.h" =20 #define PCI_PM_CAP_VER_1_1 0x0002 /* PCI PM spec ver. 1.1 */ +#define PCI_PM_CAP_VER_1_2 0x0003 /* PCI PM spec ver. 1.2 */ =20 #endif --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633626869013178.2778573617628; Thu, 7 Oct 2021 10:14:29 -0700 (PDT) Received: from localhost ([::1]:54158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYWyR-0007f0-Lh for importer@patchew.org; Thu, 07 Oct 2021 13:14:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQP-0001Id-Fw; Thu, 07 Oct 2021 12:39:17 -0400 Received: from mga04.intel.com ([192.55.52.120]:55446) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQM-0000On-1h; Thu, 07 Oct 2021 12:39:17 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:06 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:05 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="225073011" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="225073011" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325895" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 09/15] hw/nvme: Implement the Function Level Reset Date: Thu, 7 Oct 2021 18:24:00 +0200 Message-Id: <20211007162406.1920374-10-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.120; envelope-from=lukasz.maniak@linux.intel.com; helo=mga04.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Keith Busch , =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Klaus Jensen , Lukasz Maniak , qemu-block@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633626870898100005 From: =C5=81ukasz Gieryk This patch implements the FLR, a feature currently not implemented for the Nvme device, while listed as a mandatory ("shall") in the 1.4 spec. The implementation reuses FLR-related building blocks defined for the pci-bridge module, and follows the same logic: - FLR capability is advertised in the PCIE config, - custom pci_write_config callback detects a write to the trigger register and performs the PCI reset, - which, eventually, calls the custom dc->reset handler. Depending on reset type, parts of the state should (or should not) be cleared. To distinguish the type of reset, an additional parameter is passed to the reset function. This patch also enables advertisement of the Power Management PCI capability. The main reason behind it is to announce the no_soft_reset=3D1 bit, to signal SR/IOV support where each VF can be reset individually. The implementation purposedly ignores writes to the PMCS.PS register, as even such na=C3=AFve behavior is enough to correctly handle the D3->D0 transition. It=E2=80=99s worth to note, that the power state transition back to to D3, = with all the corresponding side effects, wasn't and stil isn't handled properly. Signed-off-by: =C5=81ukasz Gieryk Reviewed-by: Klaus Jensen --- hw/nvme/ctrl.c | 52 ++++++++++++++++++++++++++++++++++++++++---- hw/nvme/nvme.h | 5 +++++ hw/nvme/trace-events | 1 + 3 files changed, 54 insertions(+), 4 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 9687a7322c..b04cf5eae9 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -5582,7 +5582,7 @@ static void nvme_process_sq(void *opaque) } } =20 -static void nvme_ctrl_reset(NvmeCtrl *n) +static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst) { NvmeNamespace *ns; int i; @@ -5614,7 +5614,9 @@ static void nvme_ctrl_reset(NvmeCtrl *n) } =20 if (!pci_is_vf(&n->parent_obj) && n->params.sriov_max_vfs) { - pcie_sriov_pf_disable_vfs(&n->parent_obj); + if (rst !=3D NVME_RESET_CONTROLLER) { + pcie_sriov_pf_disable_vfs(&n->parent_obj); + } } =20 n->aer_queued =3D 0; @@ -5848,7 +5850,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset= , uint64_t data, } } else if (!NVME_CC_EN(data) && NVME_CC_EN(cc)) { trace_pci_nvme_mmio_stopped(); - nvme_ctrl_reset(n); + nvme_ctrl_reset(n, NVME_RESET_CONTROLLER); cc =3D 0; csts &=3D ~NVME_CSTS_READY; } @@ -6416,6 +6418,28 @@ static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *= pci_dev, uint16_t offset, PCI_BASE_ADDRESS_MEM_TYPE_64, bar_size); } =20 +static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) +{ + Error *err =3D NULL; + int ret; + + ret =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset, + PCI_PM_SIZEOF, &err); + if (err) { + error_report_err(err); + return ret; + } + + pci_set_word(pci_dev->config + offset + PCI_PM_PMC, + PCI_PM_CAP_VER_1_2); + pci_set_word(pci_dev->config + offset + PCI_PM_CTRL, + PCI_PM_CTRL_NO_SOFT_RESET); + pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL, + PCI_PM_CTRL_STATE_MASK); + + return 0; +} + static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) { uint8_t *pci_conf =3D pci_dev->config; @@ -6437,7 +6461,9 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_= dev, Error **errp) } =20 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS); + nvme_add_pm_capability(pci_dev, 0x60); pcie_endpoint_cap_init(pci_dev, 0x80); + pcie_cap_flr_init(pci_dev); if (n->params.sriov_max_vfs) { pcie_ari_init(pci_dev, 0x100, 1); } @@ -6686,7 +6712,7 @@ static void nvme_exit(PCIDevice *pci_dev) NvmeNamespace *ns; int i; =20 - nvme_ctrl_reset(n); + nvme_ctrl_reset(n, NVME_RESET_FUNCTION); =20 if (n->subsys) { for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { @@ -6785,6 +6811,22 @@ static void nvme_set_smart_warning(Object *obj, Visi= tor *v, const char *name, } } =20 +static void nvme_pci_reset(DeviceState *qdev) +{ + PCIDevice *pci_dev =3D PCI_DEVICE(qdev); + NvmeCtrl *n =3D NVME(pci_dev); + + trace_pci_nvme_pci_reset(); + nvme_ctrl_reset(n, NVME_RESET_FUNCTION); +} + +static void nvme_pci_write_config(PCIDevice *dev, uint32_t address, + uint32_t val, int len) +{ + pci_default_write_config(dev, address, val, len); + pcie_cap_flr_write_config(dev, address, val, len); +} + static const VMStateDescription nvme_vmstate =3D { .name =3D "nvme", .unmigratable =3D 1, @@ -6796,6 +6838,7 @@ static void nvme_class_init(ObjectClass *oc, void *da= ta) PCIDeviceClass *pc =3D PCI_DEVICE_CLASS(oc); =20 pc->realize =3D nvme_realize; + pc->config_write =3D nvme_pci_write_config; pc->exit =3D nvme_exit; pc->class_id =3D PCI_CLASS_STORAGE_EXPRESS; pc->revision =3D 2; @@ -6804,6 +6847,7 @@ static void nvme_class_init(ObjectClass *oc, void *da= ta) dc->desc =3D "Non-Volatile Memory Express"; device_class_set_props(dc, nvme_props); dc->vmsd =3D &nvme_vmstate; + dc->reset =3D nvme_pci_reset; } =20 static void nvme_instance_init(Object *obj) diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index fd229f06f0..9fbb0a70b5 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -467,6 +467,11 @@ typedef struct NvmeCtrl { NvmeSecCtrlList sec_ctrl_list; } NvmeCtrl; =20 +typedef enum NvmeResetType { + NVME_RESET_FUNCTION =3D 0, + NVME_RESET_CONTROLLER =3D 1, +} NvmeResetType; + static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid) { if (!nsid || nsid > NVME_MAX_NAMESPACES) { diff --git a/hw/nvme/trace-events b/hw/nvme/trace-events index dd2aac3418..88678fc21e 100644 --- a/hw/nvme/trace-events +++ b/hw/nvme/trace-events @@ -105,6 +105,7 @@ pci_nvme_set_descriptor_extension(uint64_t slba, uint32= _t zone_idx) "set zone de pci_nvme_zd_extension_set(uint32_t zone_idx) "set descriptor extension for= zone_idx=3D%"PRIu32"" pci_nvme_clear_ns_close(uint32_t state, uint64_t slba) "zone state=3D%"PRI= u32", slba=3D%"PRIu64" transitioned to Closed state" pci_nvme_clear_ns_reset(uint32_t state, uint64_t slba) "zone state=3D%"PRI= u32", slba=3D%"PRIu64" transitioned to Empty state" +pci_nvme_pci_reset(void) "PCI Function Level Reset" =20 # error conditions pci_nvme_err_mdts(size_t len) "len %zu" --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633627273441569.3721330115945; Thu, 7 Oct 2021 10:21:13 -0700 (PDT) Received: from localhost ([::1]:45546 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYX4y-0003vt-As for importer@patchew.org; Thu, 07 Oct 2021 13:21:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50942) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQP-0001JB-Mv; Thu, 07 Oct 2021 12:39:17 -0400 Received: from mga04.intel.com ([192.55.52.120]:55444) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQN-00007p-2i; Thu, 07 Oct 2021 12:39:17 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:08 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:07 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="225073031" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="225073031" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325909" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 10/15] hw/nvme: Make max_ioqpairs and msix_qsize configurable in runtime Date: Thu, 7 Oct 2021 18:24:01 +0200 Message-Id: <20211007162406.1920374-11-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.120; envelope-from=lukasz.maniak@linux.intel.com; helo=mga04.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Keith Busch , =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Klaus Jensen , Lukasz Maniak , qemu-block@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633627275690100003 From: =C5=81ukasz Gieryk The Nvme device defines two properties: max_ioqpairs, msix_qsize. Having them as constants is problematic for SR-IOV support. The SR-IOV feature introduces virtual resources (queues, interrupts) that can be assigned to PF and its dependent VFs. Each device, following a reset, should work with the configured number of queues. A single constant is no longer sufficient to hold the whole state. This patch tries to solve the problem by introducing additional variables in NvmeCtrl=E2=80=99s state. The variables for, e.g., managing qu= eues are therefore organized as: - n->params.max_ioqpairs =E2=80=93 no changes, constant set by the user. - n->max_ioqpairs - (new) value derived from n->params.* in realize(); constant through device=E2=80=99s lifetime. - n->(mutable_state) =E2=80=93 (not a part of this patch) user-configurabl= e, specifies number of queues available _after_ reset. - n->conf_ioqpairs - (new) used in all the places instead of the =E2=80=98= old=E2=80=99 n->params.max_ioqpairs; initialized in realize() and updated during reset() to reflect user=E2=80=99s changes to the mutable state. Since the number of available i/o queues and interrupts can change in runtime, buffers for sq/cqs and the MSIX-related structures are allocated big enough to handle the limits, to completely avoid the complicated reallocation. A helper function (nvme_update_msixcap_ts) updates the corresponding capability register, to signal configuration changes. Signed-off-by: =C5=81ukasz Gieryk --- hw/nvme/ctrl.c | 62 +++++++++++++++++++++++++++++++++----------------- hw/nvme/nvme.h | 4 ++++ 2 files changed, 45 insertions(+), 21 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index b04cf5eae9..5d9166d66f 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -416,12 +416,12 @@ static bool nvme_nsid_valid(NvmeCtrl *n, uint32_t nsi= d) =20 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) { - return sqid < n->params.max_ioqpairs + 1 && n->sq[sqid] !=3D NULL ? 0 = : -1; + return sqid < n->conf_ioqpairs + 1 && n->sq[sqid] !=3D NULL ? 0 : -1; } =20 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid) { - return cqid < n->params.max_ioqpairs + 1 && n->cq[cqid] !=3D NULL ? 0 = : -1; + return cqid < n->conf_ioqpairs + 1 && n->cq[cqid] !=3D NULL ? 0 : -1; } =20 static void nvme_inc_cq_tail(NvmeCQueue *cq) @@ -4034,8 +4034,7 @@ static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeReque= st *req) trace_pci_nvme_err_invalid_create_sq_cqid(cqid); return NVME_INVALID_CQID | NVME_DNR; } - if (unlikely(!sqid || sqid > n->params.max_ioqpairs || - n->sq[sqid] !=3D NULL)) { + if (unlikely(!sqid || sqid > n->conf_ioqpairs || n->sq[sqid] !=3D NULL= )) { trace_pci_nvme_err_invalid_create_sq_sqid(sqid); return NVME_INVALID_QID | NVME_DNR; } @@ -4382,8 +4381,7 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeReque= st *req) trace_pci_nvme_create_cq(prp1, cqid, vector, qsize, qflags, NVME_CQ_FLAGS_IEN(qflags) !=3D 0); =20 - if (unlikely(!cqid || cqid > n->params.max_ioqpairs || - n->cq[cqid] !=3D NULL)) { + if (unlikely(!cqid || cqid > n->conf_ioqpairs || n->cq[cqid] !=3D NULL= )) { trace_pci_nvme_err_invalid_create_cq_cqid(cqid); return NVME_INVALID_QID | NVME_DNR; } @@ -4399,7 +4397,7 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeReque= st *req) trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } - if (unlikely(vector >=3D n->params.msix_qsize)) { + if (unlikely(vector >=3D n->conf_msix_qsize)) { trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } @@ -4980,13 +4978,12 @@ defaults: =20 break; case NVME_NUMBER_OF_QUEUES: - result =3D (n->params.max_ioqpairs - 1) | - ((n->params.max_ioqpairs - 1) << 16); + result =3D (n->conf_ioqpairs - 1) | ((n->conf_ioqpairs - 1) << 16); trace_pci_nvme_getfeat_numq(result); break; case NVME_INTERRUPT_VECTOR_CONF: iv =3D dw11 & 0xffff; - if (iv >=3D n->params.max_ioqpairs + 1) { + if (iv >=3D n->conf_ioqpairs + 1) { return NVME_INVALID_FIELD | NVME_DNR; } =20 @@ -5141,10 +5138,10 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeR= equest *req) =20 trace_pci_nvme_setfeat_numq((dw11 & 0xffff) + 1, ((dw11 >> 16) & 0xffff) + 1, - n->params.max_ioqpairs, - n->params.max_ioqpairs); - req->cqe.result =3D cpu_to_le32((n->params.max_ioqpairs - 1) | - ((n->params.max_ioqpairs - 1) << 16)= ); + n->conf_ioqpairs, + n->conf_ioqpairs); + req->cqe.result =3D cpu_to_le32((n->conf_ioqpairs - 1) | + ((n->conf_ioqpairs - 1) << 16)); break; case NVME_ASYNCHRONOUS_EVENT_CONF: n->features.async_config =3D dw11; @@ -5582,8 +5579,21 @@ static void nvme_process_sq(void *opaque) } } =20 +static void nvme_update_msixcap_ts(PCIDevice *pci_dev, uint32_t table_size) +{ + uint8_t *config; + + assert(pci_dev->msix_cap); + assert(table_size <=3D pci_dev->msix_entries_nr); + + config =3D pci_dev->config + pci_dev->msix_cap; + pci_set_word_by_mask(config + PCI_MSIX_FLAGS, PCI_MSIX_FLAGS_QSIZE, + table_size - 1); +} + static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst) { + PCIDevice *pci_dev =3D &n->parent_obj; NvmeNamespace *ns; int i; =20 @@ -5596,12 +5606,12 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetT= ype rst) nvme_ns_drain(ns); } =20 - for (i =3D 0; i < n->params.max_ioqpairs + 1; i++) { + for (i =3D 0; i < n->max_ioqpairs + 1; i++) { if (n->sq[i] !=3D NULL) { nvme_free_sq(n->sq[i], n); } } - for (i =3D 0; i < n->params.max_ioqpairs + 1; i++) { + for (i =3D 0; i < n->max_ioqpairs + 1; i++) { if (n->cq[i] !=3D NULL) { nvme_free_cq(n->cq[i], n); } @@ -5613,15 +5623,17 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetT= ype rst) g_free(event); } =20 - if (!pci_is_vf(&n->parent_obj) && n->params.sriov_max_vfs) { + if (!pci_is_vf(pci_dev) && n->params.sriov_max_vfs) { if (rst !=3D NVME_RESET_CONTROLLER) { - pcie_sriov_pf_disable_vfs(&n->parent_obj); + pcie_sriov_pf_disable_vfs(pci_dev); } } =20 n->aer_queued =3D 0; n->outstanding_aers =3D 0; n->qs_created =3D false; + + nvme_update_msixcap_ts(pci_dev, n->conf_msix_qsize); } =20 static void nvme_ctrl_shutdown(NvmeCtrl *n) @@ -6322,11 +6334,17 @@ static void nvme_init_state(NvmeCtrl *n) NvmeSecCtrlEntry *sctrl; int i; =20 + n->max_ioqpairs =3D n->params.max_ioqpairs; + n->conf_ioqpairs =3D n->max_ioqpairs; + + n->max_msix_qsize =3D n->params.msix_qsize; + n->conf_msix_qsize =3D n->max_msix_qsize; + /* add one to max_ioqpairs to account for the admin queue pair */ n->reg_size =3D pow2ceil(sizeof(NvmeBar) + 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); - n->sq =3D g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); - n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); + n->sq =3D g_new0(NvmeSQueue *, n->max_ioqpairs + 1); + n->cq =3D g_new0(NvmeCQueue *, n->max_ioqpairs + 1); n->temperature =3D NVME_TEMPERATURE; n->features.temp_thresh_hi =3D NVME_TEMPERATURE_WARNING; n->starttime_ms =3D qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); @@ -6491,7 +6509,7 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_= dev, Error **errp) pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &n->bar0); } - ret =3D msix_init(pci_dev, n->params.msix_qsize, + ret =3D msix_init(pci_dev, n->max_msix_qsize, &n->bar0, 0, msix_table_offset, &n->bar0, 0, msix_pba_offset, 0, &err); if (ret < 0) { @@ -6503,6 +6521,8 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_= dev, Error **errp) } } =20 + nvme_update_msixcap_ts(pci_dev, n->conf_msix_qsize); + if (n->params.cmb_size_mb) { nvme_init_cmb(n, pci_dev); } diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index 9fbb0a70b5..65383e495c 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -420,6 +420,10 @@ typedef struct NvmeCtrl { uint64_t starttime_ms; uint16_t temperature; uint8_t smart_critical_warning; + uint32_t max_msix_qsize; /* Derived from params.msi= x.qsize */ + uint32_t conf_msix_qsize; /* Configured limit */ + uint32_t max_ioqpairs; /* Derived from params.max= _ioqpairs */ + uint32_t conf_ioqpairs; /* Configured limit */ =20 struct { MemoryRegion mem; --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633627069278571.8104991316623; Thu, 7 Oct 2021 10:17:49 -0700 (PDT) Received: from localhost ([::1]:34678 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYX1g-0005AW-7W for importer@patchew.org; Thu, 07 Oct 2021 13:17:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50962) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQQ-0001NI-Vl; Thu, 07 Oct 2021 12:39:19 -0400 Received: from mga04.intel.com ([192.55.52.120]:55434) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQO-0008BP-ON; Thu, 07 Oct 2021 12:39:18 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:10 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:08 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="225073055" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="225073055" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325927" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 11/15] hw/nvme: Calculate BAR atributes in a function Date: Thu, 7 Oct 2021 18:24:02 +0200 Message-Id: <20211007162406.1920374-12-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.120; envelope-from=lukasz.maniak@linux.intel.com; helo=mga04.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Keith Busch , =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Klaus Jensen , Lukasz Maniak , qemu-block@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633627071579100003 From: =C5=81ukasz Gieryk An Nvme device with SR-IOV capability calculates the BAR size differently for PF and VF, so it makes sense to extract the common code to a separate function. Also: it seems the n->reg_size parameter unnecessarily splits the BAR size calculation in two phases; removed to simplify the code. Signed-off-by: =C5=81ukasz Gieryk --- hw/nvme/ctrl.c | 52 +++++++++++++++++++++++++++++++++----------------- hw/nvme/nvme.h | 1 - 2 files changed, 35 insertions(+), 18 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 5d9166d66f..425fbf2c73 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -6339,10 +6339,6 @@ static void nvme_init_state(NvmeCtrl *n) =20 n->max_msix_qsize =3D n->params.msix_qsize; n->conf_msix_qsize =3D n->max_msix_qsize; - - /* add one to max_ioqpairs to account for the admin queue pair */ - n->reg_size =3D pow2ceil(sizeof(NvmeBar) + - 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); n->sq =3D g_new0(NvmeSQueue *, n->max_ioqpairs + 1); n->cq =3D g_new0(NvmeCQueue *, n->max_ioqpairs + 1); n->temperature =3D NVME_TEMPERATURE; @@ -6401,6 +6397,36 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pc= i_dev) memory_region_set_enabled(&n->pmr.dev->mr, false); } =20 +static uint64_t nvme_bar_size(unsigned total_queues, unsigned total_irqs, + unsigned *msix_table_offset, + unsigned *msix_pba_offset) +{ + uint64_t bar_size, msix_table_size, msix_pba_size; + + bar_size =3D sizeof(NvmeBar); + bar_size +=3D 2 * total_queues * NVME_DB_SIZE; + bar_size =3D pow2ceil(bar_size); + bar_size =3D QEMU_ALIGN_UP(bar_size, 4 * KiB); + + if (msix_table_offset) { + *msix_table_offset =3D bar_size; + } + + msix_table_size =3D PCI_MSIX_ENTRY_SIZE * total_irqs; + bar_size +=3D msix_table_size; + bar_size =3D QEMU_ALIGN_UP(bar_size, 4 * KiB); + + if (msix_pba_offset) { + *msix_pba_offset =3D bar_size; + } + + msix_pba_size =3D QEMU_ALIGN_UP(total_irqs, 64) / 8; + bar_size +=3D msix_pba_size; + + bar_size =3D pow2ceil(bar_size); + return bar_size; +} + static void nvme_update_vfs(PCIDevice *pci_dev, uint16_t prev_num_vfs, uint16_t num_vfs) { @@ -6461,7 +6487,7 @@ static int nvme_add_pm_capability(PCIDevice *pci_dev,= uint8_t offset) static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) { uint8_t *pci_conf =3D pci_dev->config; - uint64_t bar_size, msix_table_size, msix_pba_size; + uint64_t bar_size; unsigned msix_table_offset, msix_pba_offset; int ret; =20 @@ -6486,21 +6512,13 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pc= i_dev, Error **errp) pcie_ari_init(pci_dev, 0x100, 1); } =20 - bar_size =3D QEMU_ALIGN_UP(n->reg_size, 4 * KiB); - msix_table_offset =3D bar_size; - msix_table_size =3D PCI_MSIX_ENTRY_SIZE * n->params.msix_qsize; - - bar_size +=3D msix_table_size; - bar_size =3D QEMU_ALIGN_UP(bar_size, 4 * KiB); - msix_pba_offset =3D bar_size; - msix_pba_size =3D QEMU_ALIGN_UP(n->params.msix_qsize, 64) / 8; - - bar_size +=3D msix_pba_size; - bar_size =3D pow2ceil(bar_size); + /* add one to max_ioqpairs to account for the admin queue pair */ + bar_size =3D nvme_bar_size(n->max_ioqpairs + 1, n->max_msix_qsize, + &msix_table_offset, &msix_pba_offset); =20 memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size); memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", - n->reg_size); + msix_table_offset); memory_region_add_subregion(&n->bar0, 0, &n->iomem); =20 if (pci_is_vf(pci_dev)) { diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index 65383e495c..a8eded4713 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -410,7 +410,6 @@ typedef struct NvmeCtrl { uint16_t max_prp_ents; uint16_t cqe_size; uint16_t sqe_size; - uint32_t reg_size; uint32_t max_q_ents; uint8_t outstanding_aers; uint32_t irq_status; --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633627454265443.9340552557494; Thu, 7 Oct 2021 10:24:14 -0700 (PDT) Received: from localhost ([::1]:56998 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYX7t-0003Co-2U for importer@patchew.org; Thu, 07 Oct 2021 13:24:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQW-0001bm-Ly; Thu, 07 Oct 2021 12:39:24 -0400 Received: from mga04.intel.com ([192.55.52.120]:55434) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQT-0008BP-Dn; Thu, 07 Oct 2021 12:39:24 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:13 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:10 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="225073098" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="225073098" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325943" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 12/15] hw/nvme: Initialize capability structures for primary/secondary controllers Date: Thu, 7 Oct 2021 18:24:03 +0200 Message-Id: <20211007162406.1920374-13-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.120; envelope-from=lukasz.maniak@linux.intel.com; helo=mga04.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Lukasz Maniak , Klaus Jensen , Hanna Reitz , Stefan Hajnoczi , Keith Busch , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633627455661100001 From: =C5=81ukasz Gieryk With two new properties (sriov_max_vi_per_vf, sriov_max_vq_per_vf) one can configure the maximum number of virtual queues and interrupts assignable to a single virtual device. The primary and secondary controller capability structures are initialized accordingly. Since the number of available queues (interrupts) now varies between VF/PF, BAR size calculation is also adjusted. Signed-off-by: =C5=81ukasz Gieryk --- hw/nvme/ctrl.c | 110 +++++++++++++++++++++++++++++++++++++++---- hw/nvme/nvme.h | 2 + include/block/nvme.h | 5 ++ 3 files changed, 108 insertions(+), 9 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 425fbf2c73..67c7210d7e 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -36,6 +36,8 @@ * zoned.zasl=3D, \ * zoned.auto_transition=3D, \ * sriov_max_vfs=3D \ + * sriov_max_vi_per_vf=3D \ + * sriov_max_vq_per_vf=3D \ * subsys=3D * -device nvme-ns,drive=3D,bus=3D,nsid=3D,\ * zoned=3D, \ @@ -113,6 +115,18 @@ * enables reporting of both SR-IOV and ARI capabilities by the NVMe dev= ice. * Virtual function controllers will not report SR-IOV capability. * + * - `sriov_max_vi_per_vf` + * Indicates the maximum number of virtual interrupt resources assignable + * to a secondary controller. Must be explicitly set if sriov_max_vfs != =3D 0. + * The parameter affect VFs similarly to how msix_qsize affects PF, i.e., + * determines the number of interrupts available to all queues (admin, i= o). + * + * - `sriov_max_vq_per_vf` + * Indicates the maximum number of virtual queue resources assignable to + * a secondary controller. Must be explicitly set if sriov_max_vfs !=3D = 0. + * The parameter affect VFs similarly to how max_ioqpairs affects PF, + * except the number of flexible queues includes the admin queue. + * * nvme namespace device parameters * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * - `shared` @@ -184,6 +198,7 @@ #define NVME_NUM_FW_SLOTS 1 #define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB) #define NVME_MAX_VFS 127 +#define NVME_VF_RES_GRANULARITY 1 #define NVME_VF_OFFSET 0x1 #define NVME_VF_STRIDE 1 =20 @@ -6254,6 +6269,7 @@ static const MemoryRegionOps nvme_cmb_ops =3D { static void nvme_check_constraints(NvmeCtrl *n, Error **errp) { NvmeParams *params =3D &n->params; + int msix_total; =20 if (params->num_queues) { warn_report("num_queues is deprecated; please use max_ioqpairs " @@ -6324,6 +6340,30 @@ static void nvme_check_constraints(NvmeCtrl *n, Erro= r **errp) NVME_MAX_VFS); return; } + + if (params->sriov_max_vi_per_vf < 1 || + (params->sriov_max_vi_per_vf - 1) % NVME_VF_RES_GRANULARITY) { + error_setg(errp, "sriov_max_vi_per_vf must meet:" + " (X - 1) %% %d =3D=3D 0 and X >=3D 1", + NVME_VF_RES_GRANULARITY); + return; + } + + if (params->sriov_max_vq_per_vf < 2 || + (params->sriov_max_vq_per_vf - 1) % NVME_VF_RES_GRANULARITY) { + error_setg(errp, "sriov_max_vq_per_vf must meet:" + " (X - 1) %% %d =3D=3D 0 and X >=3D 2", + NVME_VF_RES_GRANULARITY); + return; + } + + msix_total =3D params->msix_qsize + + params->sriov_max_vfs * params->sriov_max_vi_per_vf; + if (msix_total > PCI_MSIX_FLAGS_QSIZE + 1) { + error_setg(errp, "sriov_max_vi_per_vf is too big for max_vfs= =3D%d", + params->sriov_max_vfs); + return; + } } } =20 @@ -6332,13 +6372,35 @@ static void nvme_init_state(NvmeCtrl *n) NvmePriCtrlCap *cap =3D &n->pri_ctrl_cap; NvmeSecCtrlList *list =3D &n->sec_ctrl_list; NvmeSecCtrlEntry *sctrl; + uint8_t max_vfs; + uint32_t total_vq, total_vi; int i; =20 - n->max_ioqpairs =3D n->params.max_ioqpairs; - n->conf_ioqpairs =3D n->max_ioqpairs; + if (pci_is_vf(&n->parent_obj)) { + sctrl =3D nvme_sctrl(n); + + max_vfs =3D 0; + + n->max_ioqpairs =3D n->params.sriov_max_vq_per_vf - 1; + n->conf_ioqpairs =3D sctrl->nvq ? le16_to_cpu(sctrl->nvq) - 1 : 0; + + n->max_msix_qsize =3D n->params.sriov_max_vi_per_vf; + n->conf_msix_qsize =3D sctrl->nvi ? le16_to_cpu(sctrl->nvi) : 1; + } else { + max_vfs =3D n->params.sriov_max_vfs; + + n->max_ioqpairs =3D n->params.max_ioqpairs + + max_vfs * n->params.sriov_max_vq_per_vf; + n->conf_ioqpairs =3D n->max_ioqpairs; + + n->max_msix_qsize =3D n->params.msix_qsize + + max_vfs * n->params.sriov_max_vi_per_vf; + n->conf_msix_qsize =3D n->max_msix_qsize; + } + + total_vq =3D n->params.sriov_max_vq_per_vf * max_vfs; + total_vi =3D n->params.sriov_max_vi_per_vf * max_vfs; =20 - n->max_msix_qsize =3D n->params.msix_qsize; - n->conf_msix_qsize =3D n->max_msix_qsize; n->sq =3D g_new0(NvmeSQueue *, n->max_ioqpairs + 1); n->cq =3D g_new0(NvmeCQueue *, n->max_ioqpairs + 1); n->temperature =3D NVME_TEMPERATURE; @@ -6346,13 +6408,34 @@ static void nvme_init_state(NvmeCtrl *n) n->starttime_ms =3D qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); n->aer_reqs =3D g_new0(NvmeRequest *, n->params.aerl + 1); =20 - list->numcntl =3D cpu_to_le16(n->params.sriov_max_vfs); - for (i =3D 0; i < n->params.sriov_max_vfs; i++) { + list->numcntl =3D cpu_to_le16(max_vfs); + for (i =3D 0; i < max_vfs; i++) { sctrl =3D &list->sec[i]; sctrl->pcid =3D cpu_to_le16(n->cntlid); } =20 cap->cntlid =3D cpu_to_le16(n->cntlid); + cap->crt =3D NVME_CRT_VQ | NVME_CRT_VI; + + cap->vqfrt =3D cpu_to_le32(total_vq); + cap->vqrfap =3D cpu_to_le32(total_vq); + if (pci_is_vf(&n->parent_obj)) { + cap->vqprt =3D cpu_to_le16(n->conf_ioqpairs + 1); + } else { + cap->vqprt =3D cpu_to_le16(n->params.max_ioqpairs + 1); + cap->vqfrsm =3D cpu_to_le16(n->params.sriov_max_vq_per_vf); + cap->vqgran =3D cpu_to_le16(NVME_VF_RES_GRANULARITY); + } + + cap->vifrt =3D cpu_to_le32(total_vi); + cap->virfap =3D cpu_to_le32(total_vi); + if (pci_is_vf(&n->parent_obj)) { + cap->viprt =3D cpu_to_le16(n->conf_msix_qsize); + } else { + cap->viprt =3D cpu_to_le16(n->params.msix_qsize); + cap->vifrsm =3D cpu_to_le16(n->params.sriov_max_vi_per_vf); + cap->vigran =3D cpu_to_le16(NVME_VF_RES_GRANULARITY); + } } =20 static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev) @@ -6448,11 +6531,13 @@ static void nvme_update_vfs(PCIDevice *pci_dev, uin= t16_t prev_num_vfs, } } =20 -static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offs= et, - uint64_t bar_size) +static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offs= et) { uint16_t vf_dev_id =3D n->params.use_intel_id ? PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_N= VME; + uint64_t bar_size =3D nvme_bar_size(n->params.sriov_max_vq_per_vf, + n->params.sriov_max_vi_per_vf, + NULL, NULL); =20 pcie_sriov_pf_init(pci_dev, offset, "nvme", vf_dev_id, n->params.sriov_max_vfs, n->params.sriov_max_vfs, @@ -6550,7 +6635,7 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_= dev, Error **errp) } =20 if (!pci_is_vf(pci_dev) && n->params.sriov_max_vfs) { - nvme_init_sriov(n, pci_dev, 0x120, bar_size); + nvme_init_sriov(n, pci_dev, 0x120); } =20 return 0; @@ -6574,6 +6659,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pc= i_dev) NvmeIdCtrl *id =3D &n->id_ctrl; uint8_t *pci_conf =3D pci_dev->config; uint64_t cap =3D ldq_le_p(&n->bar.cap); + NvmeSecCtrlEntry *sctrl =3D nvme_sctrl(n); =20 id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); @@ -6665,6 +6751,10 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *p= ci_dev) =20 stl_le_p(&n->bar.vs, NVME_SPEC_VER); n->bar.intmc =3D n->bar.intms =3D 0; + + if (pci_is_vf(&n->parent_obj) && !sctrl->scs) { + stl_le_p(&n->bar.csts, NVME_CSTS_FAILED); + } } =20 static int nvme_init_subsys(NvmeCtrl *n, Error **errp) @@ -6804,6 +6894,8 @@ static Property nvme_props[] =3D { DEFINE_PROP_BOOL("zoned.auto_transition", NvmeCtrl, params.auto_transition_zones, true), DEFINE_PROP_UINT8("sriov_max_vfs", NvmeCtrl, params.sriov_max_vfs, 0), + DEFINE_PROP_UINT8("sriov_max_vi_per_vf", NvmeCtrl, params.sriov_max_vi= _per_vf, 0), + DEFINE_PROP_UINT8("sriov_max_vq_per_vf", NvmeCtrl, params.sriov_max_vq= _per_vf, 0), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index a8eded4713..43609c979a 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -393,6 +393,8 @@ typedef struct NvmeParams { bool auto_transition_zones; bool legacy_cmb; uint8_t sriov_max_vfs; + uint8_t sriov_max_vq_per_vf; + uint8_t sriov_max_vi_per_vf; } NvmeParams; =20 typedef struct NvmeCtrl { diff --git a/include/block/nvme.h b/include/block/nvme.h index 96595ea8f1..26672d0a31 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -1488,6 +1488,11 @@ typedef struct QEMU_PACKED NvmePriCtrlCap { uint8_t rsvd80[4016]; } NvmePriCtrlCap; =20 +typedef enum NvmePriCtrlCapCrt { + NVME_CRT_VQ =3D 1 << 0, + NVME_CRT_VI =3D 1 << 1, +} NvmePriCtrlCapCrt; + typedef struct QEMU_PACKED NvmeSecCtrlEntry { uint16_t scid; uint16_t pcid; --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163362764456499.44404669864127; Thu, 7 Oct 2021 10:27:24 -0700 (PDT) Received: from localhost ([::1]:40670 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXAx-0002jm-Ce for importer@patchew.org; Thu, 07 Oct 2021 13:27:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51026) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQb-0001rJ-AJ; Thu, 07 Oct 2021 12:39:29 -0400 Received: from mga04.intel.com ([192.55.52.120]:55434) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQZ-0008BP-G7; Thu, 07 Oct 2021 12:39:29 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:15 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:13 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="225073121" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="225073121" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325955" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 13/15] pcie: Add helpers to the SR/IOV API Date: Thu, 7 Oct 2021 18:24:04 +0200 Message-Id: <20211007162406.1920374-14-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.120; envelope-from=lukasz.maniak@linux.intel.com; helo=mga04.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Lukasz Maniak , qemu-block@nongnu.org, "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633627645463100001 From: =C5=81ukasz Gieryk Two convenience functions for retrieving: - the total number of VFs, - the PCIDevice object of the N-th VF. Signed-off-by: =C5=81ukasz Gieryk Reviewed-by: Knut Omang --- hw/pci/pcie_sriov.c | 14 ++++++++++++++ include/hw/pci/pcie_sriov.h | 8 ++++++++ 2 files changed, 22 insertions(+) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index cac2aee061..5a8e92d5ab 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_sriov.c @@ -292,8 +292,22 @@ uint16_t pcie_sriov_vf_number(PCIDevice *dev) return dev->exp.sriov_vf.vf_number; } =20 +uint16_t pcie_sriov_vf_number_total(PCIDevice *dev) +{ + assert(!pci_is_vf(dev)); + return dev->exp.sriov_pf.num_vfs; +} =20 PCIDevice *pcie_sriov_get_pf(PCIDevice *dev) { return dev->exp.sriov_vf.pf; } + +PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n) +{ + assert(!pci_is_vf(dev)); + if (n < dev->exp.sriov_pf.num_vfs) { + return dev->exp.sriov_pf.vf[n]; + } + return NULL; +} diff --git a/include/hw/pci/pcie_sriov.h b/include/hw/pci/pcie_sriov.h index 9ab48b79c0..d1f39b7223 100644 --- a/include/hw/pci/pcie_sriov.h +++ b/include/hw/pci/pcie_sriov.h @@ -65,9 +65,17 @@ void pcie_sriov_pf_disable_vfs(PCIDevice *dev); /* Get logical VF number of a VF - only valid for VFs */ uint16_t pcie_sriov_vf_number(PCIDevice *dev); =20 +/* Get the total number of VFs - only valid for PF */ +uint16_t pcie_sriov_vf_number_total(PCIDevice *dev); + /* Get the physical function that owns this VF. * Returns NULL if dev is not a virtual function */ PCIDevice *pcie_sriov_get_pf(PCIDevice *dev); =20 +/* Get the n-th VF of this physical function - only valid for PF. + * Returns NULL if index is invalid + */ +PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n); + #endif /* QEMU_PCIE_SRIOV_H */ --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633627272269619.3451944945202; Thu, 7 Oct 2021 10:21:12 -0700 (PDT) Received: from localhost ([::1]:45578 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYX4w-0003x5-Vc for importer@patchew.org; Thu, 07 Oct 2021 13:21:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51090) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQj-0002JR-C1; Thu, 07 Oct 2021 12:39:37 -0400 Received: from mga04.intel.com ([192.55.52.120]:55434) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQf-0008BP-BY; Thu, 07 Oct 2021 12:39:37 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:18 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:15 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="225073152" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="225073152" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325959" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 14/15] hw/nvme: Add support for the Virtualization Management command Date: Thu, 7 Oct 2021 18:24:05 +0200 Message-Id: <20211007162406.1920374-15-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.120; envelope-from=lukasz.maniak@linux.intel.com; helo=mga04.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Lukasz Maniak , Klaus Jensen , Hanna Reitz , Stefan Hajnoczi , Keith Busch , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633627273972100001 From: =C5=81ukasz Gieryk With the new command one can: - assign flexible resources (queues, interrupts) to primary and secondary controllers, - toggle the online/offline state of given controller. Signed-off-by: =C5=81ukasz Gieryk --- hw/nvme/ctrl.c | 207 ++++++++++++++++++++++++++++++++++++++++++- hw/nvme/nvme.h | 16 ++++ hw/nvme/trace-events | 3 + include/block/nvme.h | 17 ++++ 4 files changed, 241 insertions(+), 2 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 67c7210d7e..0c44d9b23a 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -246,6 +246,7 @@ static const uint32_t nvme_cse_acs[256] =3D { [NVME_ADM_CMD_GET_FEATURES] =3D NVME_CMD_EFF_CSUPP, [NVME_ADM_CMD_ASYNC_EV_REQ] =3D NVME_CMD_EFF_CSUPP, [NVME_ADM_CMD_NS_ATTACHMENT] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= NIC, + [NVME_ADM_CMD_VIRT_MNGMT] =3D NVME_CMD_EFF_CSUPP, [NVME_ADM_CMD_FORMAT_NVM] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, }; =20 @@ -277,6 +278,7 @@ static const uint32_t nvme_cse_iocs_zoned[256] =3D { }; =20 static void nvme_process_sq(void *opaque); +static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst); =20 static uint16_t nvme_sqid(NvmeRequest *req) { @@ -5506,6 +5508,163 @@ out: return status; } =20 +static void nvme_get_virt_res_num(NvmeCtrl *n, uint8_t rt, int *num_total, + int *num_prim, int *num_sec) +{ + *num_total =3D le32_to_cpu(rt ? n->pri_ctrl_cap.vifrt : n->pri_ctrl_ca= p.vqfrt); + *num_prim =3D le16_to_cpu(rt ? n->pri_ctrl_cap.virfap : n->pri_ctrl_ca= p.vqrfap); + *num_sec =3D le16_to_cpu(rt ? n->pri_ctrl_cap.virfa : n->pri_ctrl_cap.= vqrfa); +} + +static uint16_t nvme_assign_virt_res_to_prim(NvmeCtrl *n, NvmeRequest *req, + uint16_t cntlid, uint8_t rt, = int nr) +{ + int num_total, num_prim, num_sec; + + if (cntlid !=3D n->cntlid) { + return NVME_INVALID_CTRL_ID; + } + + nvme_get_virt_res_num(n, rt, &num_total, &num_prim, &num_sec); + + if (nr > num_total) { + return NVME_INVALID_NUM_RESOURCES; + } + + if (nr > num_total - num_sec) { + return NVME_INVALID_RESOURCE_ID; + } + + if (rt) { + n->pri_ctrl_cap.virfap =3D cpu_to_le16(nr); + } else { + n->pri_ctrl_cap.vqrfap =3D cpu_to_le16(nr); + } + + req->cqe.result =3D cpu_to_le32(nr); + return req->status; +} + +static void nvme_update_virt_res(NvmeCtrl *n, NvmeSecCtrlEntry *sctrl, + uint8_t rt, int nr) +{ + int prev_nr, prev_total; + + if (rt) { + prev_nr =3D le16_to_cpu(sctrl->nvi); + prev_total =3D le32_to_cpu(n->pri_ctrl_cap.virfa); + sctrl->nvi =3D cpu_to_le16(nr); + n->pri_ctrl_cap.virfa =3D cpu_to_le32(prev_total + nr - prev_nr); + } else { + prev_nr =3D le16_to_cpu(sctrl->nvq); + prev_total =3D le32_to_cpu(n->pri_ctrl_cap.vqrfa); + sctrl->nvq =3D cpu_to_le16(nr); + n->pri_ctrl_cap.vqrfa =3D cpu_to_le32(prev_total + nr - prev_nr); + } +} + +static uint16_t nvme_assign_virt_res_to_sec(NvmeCtrl *n, NvmeRequest *req, + uint16_t cntlid, uint8_t rt, i= nt nr) +{ + int limit =3D rt ? n->params.sriov_max_vi_per_vf : + n->params.sriov_max_vq_per_vf; + int num_total, num_prim, num_sec, num_free, diff; + NvmeSecCtrlEntry *sctrl; + + sctrl =3D nvme_sctrl_for_cntlid(n, cntlid); + if (!sctrl) { + return NVME_INVALID_CTRL_ID; + } + + if (sctrl->scs) { + return NVME_INVALID_SEC_CTRL_STATE; + } + + if (nr > limit) { + return NVME_INVALID_NUM_RESOURCES; + } + + nvme_get_virt_res_num(n, rt, &num_total, &num_prim, &num_sec); + num_free =3D num_total - num_prim - num_sec; + diff =3D nr - le16_to_cpu(rt ? sctrl->nvi : sctrl->nvq); + + if (diff > num_free) { + return NVME_INVALID_RESOURCE_ID; + } + + nvme_update_virt_res(n, sctrl, rt, nr); + req->cqe.result =3D cpu_to_le32(nr); + + return req->status; +} + +static uint16_t nvme_virt_set_state(NvmeCtrl *n, uint16_t cntlid, bool onl= ine) +{ + NvmeCtrl *sn =3D NULL; + NvmeSecCtrlEntry *sctrl; + + sctrl =3D nvme_sctrl_for_cntlid(n, cntlid); + if (!sctrl) { + return NVME_INVALID_CTRL_ID; + } + + if (sctrl->vfn) { + sn =3D NVME(pcie_sriov_get_vf_at_index(&n->parent_obj, + le16_to_cpu(sctrl->vfn) - 1)); + } + + if (online) { + if (!NVME_CC_EN(ldl_le_p(&n->bar.cc)) || !sctrl->nvi || + (le16_to_cpu(sctrl->nvq) < 2)) { + return NVME_INVALID_SEC_CTRL_STATE; + } + + if (!sctrl->scs) { + sctrl->scs =3D 0x1; + if (sn) { + nvme_ctrl_reset(sn, NVME_RESET_CONTROLLER); + } + } + } else { + if (sctrl->scs) { + sctrl->scs =3D 0x0; + if (sn) { + nvme_ctrl_reset(sn, NVME_RESET_CONTROLLER); + } + } + + nvme_update_virt_res(n, sctrl, NVME_VIRT_RES_INTERRUPT, 0); + nvme_update_virt_res(n, sctrl, NVME_VIRT_RES_QUEUE, 0); + } + + return NVME_SUCCESS; +} + +static uint16_t nvme_virt_mngmt(NvmeCtrl *n, NvmeRequest *req) +{ + uint32_t dw10 =3D le32_to_cpu(req->cmd.cdw10); + uint32_t dw11 =3D le32_to_cpu(req->cmd.cdw11); + uint8_t act =3D dw10 & 0xf; + uint8_t rt =3D (dw10 >> 8) & 0x7; + uint16_t cntlid =3D (dw10 >> 16) & 0xffff; + int nr =3D dw11 & 0xffff; + + trace_pci_nvme_virt_mngmt(nvme_cid(req), act, cntlid, rt ? "VI" : "VQ"= , nr); + + switch (act) { + case NVME_VIRT_MNGMT_ACTION_SEC_ASSIGN: + return nvme_assign_virt_res_to_sec(n, req, cntlid, rt, nr); + case NVME_VIRT_MNGMT_ACTION_PRM_ALLOC: + return nvme_assign_virt_res_to_prim(n, req, cntlid, rt, nr); + case NVME_VIRT_MNGMT_ACTION_SEC_ONLINE: + return nvme_virt_set_state(n, cntlid, true); + case NVME_VIRT_MNGMT_ACTION_SEC_OFFLINE: + return nvme_virt_set_state(n, cntlid, false); + default: + return NVME_INVALID_FIELD; + } +} + static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req) { trace_pci_nvme_admin_cmd(nvme_cid(req), nvme_sqid(req), req->cmd.opcod= e, @@ -5548,6 +5707,8 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeReque= st *req) return nvme_aer(n, req); case NVME_ADM_CMD_NS_ATTACHMENT: return nvme_ns_attachment(n, req); + case NVME_ADM_CMD_VIRT_MNGMT: + return nvme_virt_mngmt(n, req); case NVME_ADM_CMD_FORMAT_NVM: return nvme_format(n, req); default: @@ -5609,6 +5770,7 @@ static void nvme_update_msixcap_ts(PCIDevice *pci_dev= , uint32_t table_size) static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst) { PCIDevice *pci_dev =3D &n->parent_obj; + NvmeSecCtrlEntry *sctrl; NvmeNamespace *ns; int i; =20 @@ -5639,6 +5801,11 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetTy= pe rst) } =20 if (!pci_is_vf(pci_dev) && n->params.sriov_max_vfs) { + for (i =3D 0; i < n->sec_ctrl_list.numcntl; i++) { + sctrl =3D &n->sec_ctrl_list.sec[i]; + nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false); + } + if (rst !=3D NVME_RESET_CONTROLLER) { pcie_sriov_pf_disable_vfs(pci_dev); } @@ -5648,6 +5815,19 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetTy= pe rst) n->outstanding_aers =3D 0; n->qs_created =3D false; =20 + if (pci_is_vf(pci_dev)) { + sctrl =3D nvme_sctrl(n); + n->conf_ioqpairs =3D sctrl->nvq ? le16_to_cpu(sctrl->nvq) - 1 : 0; + n->conf_msix_qsize =3D sctrl->nvi ? le16_to_cpu(sctrl->nvi) : 1; + stl_le_p(&n->bar.csts, sctrl->scs ? 0 : NVME_CSTS_FAILED); + } else { + n->conf_ioqpairs =3D n->params.max_ioqpairs + + le16_to_cpu(n->pri_ctrl_cap.vqrfap); + n->conf_msix_qsize =3D n->params.msix_qsize + + le16_to_cpu(n->pri_ctrl_cap.virfap); + stl_le_p(&n->bar.csts, 0); + } + nvme_update_msixcap_ts(pci_dev, n->conf_msix_qsize); } =20 @@ -5694,7 +5874,14 @@ static int nvme_start_ctrl(NvmeCtrl *n) uint64_t acq =3D ldq_le_p(&n->bar.acq); uint32_t page_bits =3D NVME_CC_MPS(cc) + 12; uint32_t page_size =3D 1 << page_bits; + NvmeSecCtrlEntry *sctrl =3D nvme_sctrl(n); =20 + if (pci_is_vf(&n->parent_obj) && !sctrl->scs) { + trace_pci_nvme_err_startfail_virt_state(le16_to_cpu(sctrl->nvi), + le16_to_cpu(sctrl->nvq), + sctrl->scs ? "ONLINE" : "O= FFLINE"); + return -1; + } if (unlikely(n->cq[0])) { trace_pci_nvme_err_startfail_cq(); return -1; @@ -6077,6 +6264,12 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr = addr, unsigned size) return 0; } =20 + if (pci_is_vf(&n->parent_obj) && !nvme_sctrl(n)->scs && + addr !=3D NVME_REG_CSTS) { + trace_pci_nvme_err_ignored_mmio_vf_offline(addr, size); + return 0; + } + /* * When PMRWBM bit 1 is set then read from * from PMRSTS should ensure prior writes @@ -6226,6 +6419,12 @@ static void nvme_mmio_write(void *opaque, hwaddr add= r, uint64_t data, =20 trace_pci_nvme_mmio_write(addr, data, size); =20 + if (pci_is_vf(&n->parent_obj) && !nvme_sctrl(n)->scs && + addr !=3D NVME_REG_CSTS) { + trace_pci_nvme_err_ignored_mmio_vf_offline(addr, size); + return; + } + if (addr < sizeof(n->bar)) { nvme_write_bar(n, addr, data, size); } else { @@ -6516,6 +6715,7 @@ static void nvme_update_vfs(PCIDevice *pci_dev, uint1= 6_t prev_num_vfs, NvmeCtrl *n =3D NVME(pci_dev); uint16_t num_active_vfs =3D MAX(prev_num_vfs, num_vfs); bool vf_enable =3D (prev_num_vfs < num_vfs); + NvmeSecCtrlEntry *sctrl; uint16_t i; =20 /* @@ -6523,10 +6723,13 @@ static void nvme_update_vfs(PCIDevice *pci_dev, uin= t16_t prev_num_vfs, * VF count can only go from 0 to a set value and vice versa. */ for (i =3D 0; i < num_active_vfs; i++) { + sctrl =3D &n->sec_ctrl_list.sec[i]; + if (vf_enable) { - n->sec_ctrl_list.sec[i].vfn =3D cpu_to_le16(i + 1); + sctrl->vfn =3D cpu_to_le16(i + 1); } else { - n->sec_ctrl_list.sec[i].vfn =3D 0; + sctrl->vfn =3D 0; + nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false); } } } diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index 43609c979a..79667af635 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -321,6 +321,7 @@ static inline const char *nvme_adm_opc_str(uint8_t opc) case NVME_ADM_CMD_GET_FEATURES: return "NVME_ADM_CMD_GET_FEATURES"; case NVME_ADM_CMD_ASYNC_EV_REQ: return "NVME_ADM_CMD_ASYNC_EV_REQ"; case NVME_ADM_CMD_NS_ATTACHMENT: return "NVME_ADM_CMD_NS_ATTACHMENT= "; + case NVME_ADM_CMD_VIRT_MNGMT: return "NVME_ADM_CMD_VIRT_MNGMT"; case NVME_ADM_CMD_FORMAT_NVM: return "NVME_ADM_CMD_FORMAT_NVM"; default: return "NVME_ADM_CMD_UNKNOWN"; } @@ -521,6 +522,21 @@ static inline NvmeSecCtrlEntry *nvme_sctrl(NvmeCtrl *n) return NULL; } =20 +static inline NvmeSecCtrlEntry *nvme_sctrl_for_cntlid(NvmeCtrl *n, + uint16_t cntlid) +{ + NvmeSecCtrlList *list =3D &n->sec_ctrl_list; + uint8_t i; + + for (i =3D 0; i < list->numcntl; i++) { + if (le16_to_cpu(list->sec[i].scid) =3D=3D cntlid) { + return &list->sec[i]; + } + } + + return NULL; +} + void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns); uint16_t nvme_bounce_data(NvmeCtrl *n, uint8_t *ptr, uint32_t len, NvmeTxDirection dir, NvmeRequest *req); diff --git a/hw/nvme/trace-events b/hw/nvme/trace-events index 88678fc21e..aab70cc5bd 100644 --- a/hw/nvme/trace-events +++ b/hw/nvme/trace-events @@ -106,6 +106,7 @@ pci_nvme_zd_extension_set(uint32_t zone_idx) "set descr= iptor extension for zone_ pci_nvme_clear_ns_close(uint32_t state, uint64_t slba) "zone state=3D%"PRI= u32", slba=3D%"PRIu64" transitioned to Closed state" pci_nvme_clear_ns_reset(uint32_t state, uint64_t slba) "zone state=3D%"PRI= u32", slba=3D%"PRIu64" transitioned to Empty state" pci_nvme_pci_reset(void) "PCI Function Level Reset" +pci_nvme_virt_mngmt(uint16_t cid, uint16_t act, uint16_t cntlid, const cha= r* rt, uint16_t nr) "cid %"PRIu16", act=3D0x%"PRIx16", ctrlid=3D%"PRIu16" %= s nr=3D%"PRIu16"" =20 # error conditions pci_nvme_err_mdts(size_t len) "len %zu" @@ -175,7 +176,9 @@ pci_nvme_err_startfail_asqent_sz_zero(void) "nvme_start= _ctrl failed because the pci_nvme_err_startfail_acqent_sz_zero(void) "nvme_start_ctrl failed becaus= e the admin completion queue size is zero" pci_nvme_err_startfail_zasl_too_small(uint32_t zasl, uint32_t pagesz) "nvm= e_start_ctrl failed because zone append size limit %"PRIu32" is too small, = needs to be >=3D %"PRIu32"" pci_nvme_err_startfail(void) "setting controller enable bit failed" +pci_nvme_err_startfail_virt_state(uint16_t vq, uint16_t vi, const char *st= ate) "nvme_start_ctrl failed due to ctrl state: vi=3D%u vq=3D%u %s" pci_nvme_err_invalid_mgmt_action(uint8_t action) "action=3D0x%"PRIx8"" +pci_nvme_err_ignored_mmio_vf_offline(uint64_t addr, unsigned size) "addr 0= x%"PRIx64" size %d" =20 # undefined behavior pci_nvme_ub_mmiowr_misaligned32(uint64_t offset) "MMIO write not 32-bit al= igned, offset=3D0x%"PRIx64"" diff --git a/include/block/nvme.h b/include/block/nvme.h index 26672d0a31..320f43d186 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -595,6 +595,7 @@ enum NvmeAdminCommands { NVME_ADM_CMD_ACTIVATE_FW =3D 0x10, NVME_ADM_CMD_DOWNLOAD_FW =3D 0x11, NVME_ADM_CMD_NS_ATTACHMENT =3D 0x15, + NVME_ADM_CMD_VIRT_MNGMT =3D 0x1c, NVME_ADM_CMD_FORMAT_NVM =3D 0x80, NVME_ADM_CMD_SECURITY_SEND =3D 0x81, NVME_ADM_CMD_SECURITY_RECV =3D 0x82, @@ -886,6 +887,10 @@ enum NvmeStatusCodes { NVME_NS_PRIVATE =3D 0x0119, NVME_NS_NOT_ATTACHED =3D 0x011a, NVME_NS_CTRL_LIST_INVALID =3D 0x011c, + NVME_INVALID_CTRL_ID =3D 0x011f, + NVME_INVALID_SEC_CTRL_STATE =3D 0x0120, + NVME_INVALID_NUM_RESOURCES =3D 0x0121, + NVME_INVALID_RESOURCE_ID =3D 0x0122, NVME_CONFLICTING_ATTRS =3D 0x0180, NVME_INVALID_PROT_INFO =3D 0x0181, NVME_WRITE_TO_RO =3D 0x0182, @@ -1510,6 +1515,18 @@ typedef struct QEMU_PACKED NvmeSecCtrlList { NvmeSecCtrlEntry sec[127]; } NvmeSecCtrlList; =20 +typedef enum NvmeVirtMngmtAction { + NVME_VIRT_MNGMT_ACTION_PRM_ALLOC =3D 0x01, + NVME_VIRT_MNGMT_ACTION_SEC_OFFLINE =3D 0x07, + NVME_VIRT_MNGMT_ACTION_SEC_ASSIGN =3D 0x08, + NVME_VIRT_MNGMT_ACTION_SEC_ONLINE =3D 0x09, +} NvmeVirtMngmtAct; + +typedef enum NvmeVirtResType { + NVME_VIRT_RES_QUEUE =3D 0x00, + NVME_VIRT_RES_INTERRUPT =3D 0x01, +} NvmeVirtualResourceType; + static inline void _nvme_check_size(void) { QEMU_BUILD_BUG_ON(sizeof(NvmeBar) !=3D 4096); --=20 2.25.1 From nobody Sun Feb 8 14:34:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633627068860767.8682590055108; Thu, 7 Oct 2021 10:17:48 -0700 (PDT) Received: from localhost ([::1]:34688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYX1f-0005An-Ra for importer@patchew.org; Thu, 07 Oct 2021 13:17:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51086) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQh-0002EI-Tv; Thu, 07 Oct 2021 12:39:35 -0400 Received: from mga04.intel.com ([192.55.52.120]:55463) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYWQg-0000fL-6t; Thu, 07 Oct 2021 12:39:35 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:19 -0700 Received: from lmaniak-dev.igk.intel.com ([10.55.248.48]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 09:26:17 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="225073155" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="225073155" X-IronPort-AV: E=Sophos;i="5.85,355,1624345200"; d="scan'208";a="624325966" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH 15/15] docs: Add documentation for SR-IOV and Virtualization Enhancements Date: Thu, 7 Oct 2021 18:24:06 +0200 Message-Id: <20211007162406.1920374-16-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.120; envelope-from=lukasz.maniak@linux.intel.com; helo=mga04.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 07 Oct 2021 13:12:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Lukasz Maniak , qemu-block@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633627069509100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Lukasz Maniak --- docs/system/devices/nvme.rst | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/docs/system/devices/nvme.rst b/docs/system/devices/nvme.rst index bff72d1c24..904fd7290c 100644 --- a/docs/system/devices/nvme.rst +++ b/docs/system/devices/nvme.rst @@ -235,3 +235,30 @@ The virtual namespace device supports DIF- and DIX-bas= ed protection information to ``1`` to transfer protection information as the first eight bytes of metadata. Otherwise, the protection information is transferred as the la= st eight bytes. + +Virtualization Enhancements and SR-IOV +-------------------------------------- + +The ``nvme`` device supports Single Root I/O Virtualization and Sharing +along with Virtualization Enhancements. The controller has to be linked to +an NVM Subsystem device (``nvme-subsys``) for use with SR-IOV. + +A number of parameters are present: + +``sriov_max_vfs`` (default: ``0``) + Indicates the maximum number of PCIe virtual functions supported + by the controller. Specifying a non-zero value enables reporting of both + SR-IOV and ARI (Alternative Routing-ID Interpretation) capabilities + by the NVMe device. Virtual function controllers will not report SR-IOV. + +``sriov_max_vi_per_vf`` + Indicates the maximum number of virtual interrupt resources assignable + to a secondary controller. Must be explicitly set if ``sriov_max_vfs`` != =3D 0. + The parameter affect VFs similarly to how ``msix_qsize`` affects PF, i.e= ., + determines the number of interrupts available to all queues (admin, io). + +``sriov_max_vq_per_vf`` + Indicates the maximum number of virtual queue resources assignable to + a secondary controller. Must be explicitly set if ``sriov_max_vfs`` !=3D= 0. + The parameter affect VFs similarly to how ``max_ioqpairs`` affects PF, + except the number of flexible queues includes the admin queue. --=20 2.25.1