From nobody Wed May 8 20:56:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633603664455399.8969447322521; Thu, 7 Oct 2021 03:47:44 -0700 (PDT) Received: from localhost ([::1]:50028 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYQwB-0003bC-Bl for importer@patchew.org; Thu, 07 Oct 2021 06:47:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYQsQ-0005ui-Ou for qemu-devel@nongnu.org; Thu, 07 Oct 2021 06:43:51 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:2821) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYQsN-0002Rv-J7 for qemu-devel@nongnu.org; Thu, 07 Oct 2021 06:43:50 -0400 Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.54]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4HQ79L02YszYdgL; Thu, 7 Oct 2021 18:39:18 +0800 (CST) Received: from dggpemm500023.china.huawei.com (7.185.36.83) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Thu, 7 Oct 2021 18:43:41 +0800 Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Thu, 7 Oct 2021 18:43:40 +0800 From: Yanan Wang To: Subject: [RFC PATCH 1/3] qemu-options: Improve scalability of the -smp documentation Date: Thu, 7 Oct 2021 18:43:35 +0800 Message-ID: <20211007104337.10232-2-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20211007104337.10232-1-wangyanan55@huawei.com> References: <20211007104337.10232-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.188; envelope-from=wangyanan55@huawei.com; helo=szxga02-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eduardo Habkost , Pierre Morel , Markus Armbruster , Yanan Wang , wanghaibin.wang@huawei.com, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633603666795100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rewrite part of the -smp documentation in qemu-option.hx, so that we can easily/clearly extend it with more target specific CPU topology members introduced in the future. Signed-off-by: Yanan Wang --- qemu-options.hx | 90 +++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 73 insertions(+), 17 deletions(-) diff --git a/qemu-options.hx b/qemu-options.hx index 5f375bbfa6..212657d689 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -207,14 +207,29 @@ ERST =20 DEF("smp", HAS_ARG, QEMU_OPTION_smp, "-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,sockets=3Dsockets][,dies=3Ddie= s][,cores=3Dcores][,threads=3Dthreads]\n" - " set the number of CPUs to 'n' [default=3D1]\n" + " set the number of initial CPUs to 'n' [default=3D1]\n" " maxcpus=3D maximum number of total CPUs, including\n" " offline CPUs for hotplug, etc\n" - " sockets=3D number of discrete sockets in the system\n" - " dies=3D number of CPU dies on one socket (for PC only= )\n" - " cores=3D number of CPU cores on one socket (for PC, i= t's on one die)\n" - " threads=3D number of threads on one CPU core\n", - QEMU_ARCH_ALL) + " sockets=3D number of sockets per upper layer containe= r\n" + " dies=3D number of dies per upper layer container\n" + " cores=3D number of cores per upper layer container\n" + " threads=3D number of threads per upper layer containe= r\n" + "Note: Different machines may have different subsets of the CPU topolo= gy\n" + " parameters supported, so the description of the supported param= eters\n" + " will vary accordingly. For example, for a machine that supports= a\n" + " CPU hierarchy of sockets/cores/threads, the parameters will seq= uentially\n" + " mean as below:\n" + " sockets=3D the total number of sockets on the machine= board\n" + " which is the upper layer container of socket\n" + " cores=3D the number of cores per socket\n" + " which is the upper layer container of core\n" + " threads=3D the number of threads per core\n" + " which is the upper layer container of thread\n" + " For a particular machine type board, an expected CPU topology h= ierarchy\n" + " can be defined through the supported sub-option. Unsupported pa= rameters\n" + " can also be provided in addition to the sub-option, but their v= alues\n" + " must be set as 1 in the purpose of correct parsing.\n", + QEMU_ARCH_ALL) SRST ``-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,sockets=3Dsockets][,dies=3Ddies][= ,cores=3Dcores][,threads=3Dthreads]`` Simulate a SMP system with '\ ``n``\ ' CPUs initially present on @@ -225,27 +240,68 @@ SRST initial CPU count will match the maximum number. When only one of them is given then the omitted one will be set to its counterpart's value. Both parameters may be specified, but the maximum number of CPUs must - be equal to or greater than the initial CPU count. Both parameters are - subject to an upper limit that is determined by the specific machine - type chosen. - - To control reporting of CPU topology information, the number of socket= s, - dies per socket, cores per die, and threads per core can be specified. - The sum `` sockets * cores * dies * threads `` must be equal to the - maximum CPU count. CPU targets may only support a subset of the topolo= gy - parameters. Where a CPU target does not support use of a particular - topology parameter, its value should be assumed to be 1 for the purpose - of computing the CPU maximum count. + be equal to or greater than the initial CPU count. Product of the + CPU topology hierarchy must be equal to the maximum number of CPUs. + Both parameters are subject to an upper limit that is determined by + the specific machine type chosen. + + To control reporting of CPU topology information, values of the topolo= gy + parameters can be specified. Machines may only support a subset of the + parameters and different machines may have different subsets supported + which vary depending on capacity of the corresponding CPU targets. So + for a particular machine type board, an expected topology hierarchy can + be defined through the supported sub-option. Unsupported parameters can + also be provided in addition to the sub-option, but their values must = be + set as 1 in the purpose of correct parsing. =20 Either the initial CPU count, or at least one of the topology paramete= rs must be specified. The specified parameters must be greater than zero, explicit configuration like "cpus=3D0" is not allowed. Values for any omitted parameters will be computed from those which are given. + + For example, the following sub-option defines a CPU topology hierarchy + (2 sockets totally on the machine, 2 cores per socket, 2 threads per + core) for a machine that only supports sockets/cores/threads. + Some members of the option can be omitted but their values will be + automatically computed: + + :: + + -smp 8,sockets=3D2,cores=3D2,threads=3D2,maxcpus=3D8 + + The following sub-option defines a CPU topology hierarchy (2 sockets + totally on the machine, 2 dies per socket, 2 cores per die, 2 threads + per core) for the PC machine which supports sockets/dies/cores/threads. + Some members of the option can be omitted but their values will be + automatically computed: + + :: + + -smp 16,sockets=3D2,dies=3D2,cores=3D2,threads=3D2,maxcpus=3D16 + + The following option provides all the CPU topology parameters for a + machine that only support sockets/cores/threads, but values of the + unsupported parameters are set as 1. The defined hierarchy for the + machine will be 2 sockets totally, 2 cores per socket, 2 threads per + core. Some members of the option can be omitted but their values will + be automatically computed: + + :: + + -smp 8,sockets=3D2,dies=3D1,cores=3D2,threads=3D2,maxcpus=3D8 + Historically preference was given to the coarsest topology parameters when computing missing values (ie sockets preferred over cores, which were preferred over threads), however, this behaviour is considered liable to change. Prior to 6.2 the preference was sockets over cores over threads. Since 6.2 the preference is cores over sockets over thre= ads. + + For example, the following option defines a machine board with 2 socke= ts + of 1 core before 6.2 and 1 socket of 2 cores after 6.2: + + :: + + -smp 2 ERST =20 DEF("numa", HAS_ARG, QEMU_OPTION_numa, --=20 2.19.1 From nobody Wed May 8 20:56:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633603546483541.2276032609717; Thu, 7 Oct 2021 03:45:46 -0700 (PDT) Received: from localhost ([::1]:44172 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYQuG-0007xr-PT for importer@patchew.org; Thu, 07 Oct 2021 06:45:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51256) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYQsO-0005tz-MQ for qemu-devel@nongnu.org; Thu, 07 Oct 2021 06:43:48 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:2822) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYQsL-0002SU-Q1 for qemu-devel@nongnu.org; Thu, 07 Oct 2021 06:43:48 -0400 Received: from dggemv704-chm.china.huawei.com (unknown [172.30.72.54]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4HQ79L6GdbzYfKW; Thu, 7 Oct 2021 18:39:18 +0800 (CST) Received: from dggpemm500023.china.huawei.com (7.185.36.83) by dggemv704-chm.china.huawei.com (10.3.19.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Thu, 7 Oct 2021 18:43:42 +0800 Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Thu, 7 Oct 2021 18:43:41 +0800 From: Yanan Wang To: Subject: [RFC PATCH 2/3] include/hw/boards: Improve scalability of the CpuTopology comment Date: Thu, 7 Oct 2021 18:43:36 +0800 Message-ID: <20211007104337.10232-3-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20211007104337.10232-1-wangyanan55@huawei.com> References: <20211007104337.10232-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.188; envelope-from=wangyanan55@huawei.com; helo=szxga02-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eduardo Habkost , Pierre Morel , Markus Armbruster , Yanan Wang , wanghaibin.wang@huawei.com, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633603548239100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rewrite the comment of struct CpuTopology in include/hw/boards.h, so that we can easily/clearly extend it with more target specific CPU topology members introduced in the future. Signed-off-by: Yanan Wang --- include/hw/boards.h | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 5adbcbb99b..19c5419174 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -280,11 +280,29 @@ typedef struct DeviceMemoryState { /** * CpuTopology: * @cpus: the number of present logical processors on the machine - * @sockets: the number of sockets on the machine - * @dies: the number of dies in one socket - * @cores: the number of cores in one die - * @threads: the number of threads in one core + * @sockets: the number of sockets per upper layer container + * @dies: the number of dies per upper layer container + * @cores: the number of cores per upper layer container + * @threads: the number of threads per upper layer container * @max_cpus: the maximum number of logical processors on the machine + * + * Different machines may have different subsets of the CPU topology + * parameters supported, so the description of the supported parameters + * will vary accordingly. For example, for a machine that supports a + * CPU hierarchy of sockets/cores/threads, the members will sequentially + * mean as below: + * -sockets: the total number of sockets on the machine + * which is the upper layer container of socket + * -cores: the number of cores per socket + * which is the upper layer container of core + * -threads: the number of threads per core + * which is the upper layer container of thread + * + * The currently supported CPU topology subsets are listed here: + * For PC machines, a 4-level CPU hierarchy is supported: + * -sockets/dies/cores/threads + * For the other machines, a 3-level CPU hierarchy is supported: + * -sockets/cores/threads */ typedef struct CpuTopology { unsigned int cpus; --=20 2.19.1 From nobody Wed May 8 20:56:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633603546492366.0017347242573; Thu, 7 Oct 2021 03:45:46 -0700 (PDT) Received: from localhost ([::1]:44162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYQuH-0007xW-9o for importer@patchew.org; Thu, 07 Oct 2021 06:45:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51264) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYQsP-0005u7-31 for qemu-devel@nongnu.org; Thu, 07 Oct 2021 06:43:49 -0400 Received: from szxga08-in.huawei.com ([45.249.212.255]:2876) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYQsM-0002T9-NR for qemu-devel@nongnu.org; Thu, 07 Oct 2021 06:43:48 -0400 Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.53]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4HQ7Dj60CRz1DHZP; Thu, 7 Oct 2021 18:42:13 +0800 (CST) Received: from dggpemm500023.china.huawei.com (7.185.36.83) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Thu, 7 Oct 2021 18:43:43 +0800 Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Thu, 7 Oct 2021 18:43:42 +0800 From: Yanan Wang To: Subject: [RFC PATCH 3/3] qapi/machine.json: Improve scalability of the SMP related comments Date: Thu, 7 Oct 2021 18:43:37 +0800 Message-ID: <20211007104337.10232-4-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20211007104337.10232-1-wangyanan55@huawei.com> References: <20211007104337.10232-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.255; envelope-from=wangyanan55@huawei.com; helo=szxga08-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eduardo Habkost , Pierre Morel , Markus Armbruster , Yanan Wang , wanghaibin.wang@huawei.com, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633603548246100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rewrite the comments related to SMP in qapi/machine.json, so that we can easily/clearly extend it with more target specific CPU topology members introduced in the future. Signed-off-by: Yanan Wang --- qapi/machine.json | 47 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 38 insertions(+), 9 deletions(-) diff --git a/qapi/machine.json b/qapi/machine.json index 5db54df298..2eda8e996e 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -866,10 +866,15 @@ # a CPU is being hotplugged. # # @node-id: NUMA node ID the CPU belongs to -# @socket-id: socket number within node/board the CPU belongs to -# @die-id: die number within node/board the CPU belongs to (Since 4.1) -# @core-id: core number within die the CPU belongs to -# @thread-id: thread number within core the CPU belongs to +# +# @socket-id: socket number within the upper layer container the CPU belon= gs to +# +# @die-id: die number within the upper layer container the CPU belongs to +# (since 4.1) +# +# @core-id: core number within the upper layer container the CPU belongs to +# +# @thread-id: thread number within the upper layer container the CPU belon= gs to # # Note: currently there are 5 properties that could be present # but management should be prepared to pass through other @@ -877,6 +882,15 @@ # interface extension. This also requires the filed names to be kept= in # sync with the properties passed to -device/device_add. # +# Different machines may have different subsets of the CPU topology +# parameters supported, so the description of the supported paramete= rs +# in this struct will vary accordingly. For example, for a machine t= hat +# supports a CPU hierarchy of sockets/cores/threads, the description= of +# the supported members will be: @socket-id means socket number with= in +# node/board the CPU belongs to, @core-id means core number within s= ocket +# the CPU belongs to, @thread-id means thread number within core the= CPU +# belongs to. +# # Since: 2.7 ## { 'struct': 'CpuInstanceProperties', @@ -1390,19 +1404,34 @@ # Schema for CPU topology configuration. A missing value lets # QEMU figure out a suitable value based on the ones that are provided. # -# @cpus: number of virtual CPUs in the virtual machine +# @cpus: number of present virtual CPUs in the virtual machine # -# @sockets: number of sockets in the CPU topology +# @sockets: number of sockets per upper layer container in the CPU topology # -# @dies: number of dies per socket in the CPU topology +# @dies: number of dies per upper layer container in the CPU topology +# (since 4.1) # -# @cores: number of cores per die in the CPU topology +# @cores: number of cores per upper layer container in the CPU topology # -# @threads: number of threads per core in the CPU topology +# @threads: number of threads per upper layer container in the CPU topology # # @maxcpus: maximum number of hotpluggable virtual CPUs in the virtual mac= hine # +# Notes: Different machines may have different subsets of the CPU topology +# parameters supported, so the description of the supported paramet= ers +# in this struct will vary accordingly. For example, for a machine +# that supports a CPU hierarchy of sockets/cores/threads, the +# description of the supported members will be: @sockets means the +# total number of sockets on the machine which is the upper layer +# container of socket, @cores means the number of cores per socket +# which is the upper layer container of core, @threads means the nu= mber +# of threads per core which is the upper layer container of thread. +# +# Unsupported parameters can also be provided in this struct, but t= heir +# values must be set as 1 in the purpose of correct parsing. +# # Since: 6.1 +# ## { 'struct': 'SMPConfiguration', 'data': { '*cpus': 'int', --=20 2.19.1