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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1633589303; x=1636181304; bh=oq5STqUMFTm/KaHyE5 nsTqZMqG6dIzG9MDoOLPn4Nw4=; b=Y8/yR3w5lsihs/Zz4hguqiL9GCEpV7Kn86 5Kqktam3SJ0Dr4Vw4VWgXwbHU1uCkZ/VLQxCiXqVW3KT/eCklCpUYs+kCSLE6/bl oALWiSMw8jZNS6wSzbkmF0DL/8lWHOamJiwqh3Y66EQ+h3HHFbcaiIpcZIECxE/A G+YC8KZeoX7pAwwS58IJGO15hDQf4bzr2PKorkL6bJmGZpfFVat6kaSJr5ezlL9H l35Qu8TzwwLJSCUnKEgWGMbn61qGHXr8uVCBaKqjelb7jkC0sIdHzBWvYHWjd6A8 ojhhCw+9xVnNa+hFbG3UfTDzXmBujEqV9/sbnc3vgNUzXUzyks5w== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Philipp Tomsich , LIU Zhiwei , Alistair Francis Subject: [PULL 03/26] target/riscv: clwz must ignore high bits (use shift-left & changed logic) Date: Thu, 7 Oct 2021 16:47:28 +1000 Message-Id: <20211007064751.608580-4-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211007064751.608580-1-alistair.francis@opensource.wdc.com> References: <20211007064751.608580-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=907902f29=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1633589908155100001 Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich Assume clzw being executed on a register that is not sign-extended, such as for the following sequence that uses (1ULL << 63) | 392 as the operand to clzw: bseti a2, zero, 63 addi a2, a2, 392 clzw a3, a2 The correct result of clzw would be 23, but the current implementation returns -32 (as it performs a 64bit clz, which results in 0 leading zero bits, and then subtracts 32). Fix this by changing the implementation to: 1. shift the original register up by 32 2. performs a target-length (64bit) clz 3. return 32 if no bits are set Marking this instruction as 'w-form' (i.e., setting ctx->w) would not correctly model the behaviour, as the instruction should not perform a zero-extensions on the input (after all, it is not a .uw instruction) and the result is always in the range 0..32 (so neither a sign-extension nor a zero-extension on the result will ever be needed). Consequently, we do not set ctx->w and mark the instruction as EXT_NONE. Signed-off-by: Philipp Tomsich Reviewed-by: LIU Zhiwei Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvb.c.inc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 6c85c89f6d..73d1e45026 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -349,15 +349,17 @@ GEN_TRANS_SHADD(3) =20 static void gen_clzw(TCGv ret, TCGv arg1) { - tcg_gen_clzi_tl(ret, arg1, 64); - tcg_gen_subi_tl(ret, ret, 32); + TCGv t =3D tcg_temp_new(); + tcg_gen_shli_tl(t, arg1, 32); + tcg_gen_clzi_tl(ret, t, 32); + tcg_temp_free(t); } =20 static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, EXT_ZERO, gen_clzw); + return gen_unary(ctx, a, EXT_NONE, gen_clzw); } =20 static void gen_ctzw(TCGv ret, TCGv arg1) --=20 2.31.1