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Tsirkin" To: qemu-devel@nongnu.org Subject: [PULL 43/57] acpi: arm/virt: convert build_iort() to endian agnostic build_append_FOO() API Message-ID: <20211005155946.513818-44-mst@redhat.com> References: <20211005155946.513818-1-mst@redhat.com> MIME-Version: 1.0 In-Reply-To: <20211005155946.513818-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mst@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eric Auger , Shannon Zhao , qemu-arm@nongnu.org, Ani Sinha , Igor Mammedov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633453706933100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Igor Mammedov Drop usage of packed structures and explicit endian conversions when building IORT table use endian agnostic build_append_int_noprefix() API to build it. Signed-off-by: Igor Mammedov Message-Id: <20210924122802.1455362-30-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Eric Auger Tested-by: Eric Auger --- include/hw/acpi/acpi-defs.h | 71 ---------------- hw/arm/virt-acpi-build.c | 156 ++++++++++++++++++++---------------- 2 files changed, 89 insertions(+), 138 deletions(-) diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 195f90caf6..6f2f08a9de 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -188,75 +188,4 @@ struct AcpiGenericTimerTable { } QEMU_PACKED; typedef struct AcpiGenericTimerTable AcpiGenericTimerTable; =20 -/* - * IORT node types - */ - -#define ACPI_IORT_NODE_HEADER_DEF /* Node format common fields */ \ - uint8_t type; \ - uint16_t length; \ - uint8_t revision; \ - uint32_t reserved; \ - uint32_t mapping_count; \ - uint32_t mapping_offset; - -/* Values for node Type above */ -enum { - ACPI_IORT_NODE_ITS_GROUP =3D 0x00, - ACPI_IORT_NODE_NAMED_COMPONENT =3D 0x01, - ACPI_IORT_NODE_PCI_ROOT_COMPLEX =3D 0x02, - ACPI_IORT_NODE_SMMU =3D 0x03, - ACPI_IORT_NODE_SMMU_V3 =3D 0x04 -}; - -struct AcpiIortIdMapping { - uint32_t input_base; - uint32_t id_count; - uint32_t output_base; - uint32_t output_reference; - uint32_t flags; -} QEMU_PACKED; -typedef struct AcpiIortIdMapping AcpiIortIdMapping; - -struct AcpiIortMemoryAccess { - uint32_t cache_coherency; - uint8_t hints; - uint16_t reserved; - uint8_t memory_flags; -} QEMU_PACKED; -typedef struct AcpiIortMemoryAccess AcpiIortMemoryAccess; - -struct AcpiIortItsGroup { - ACPI_IORT_NODE_HEADER_DEF - uint32_t its_count; - uint32_t identifiers[]; -} QEMU_PACKED; -typedef struct AcpiIortItsGroup AcpiIortItsGroup; - -#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE 1 - -struct AcpiIortSmmu3 { - ACPI_IORT_NODE_HEADER_DEF - uint64_t base_address; - uint32_t flags; - uint32_t reserved2; - uint64_t vatos_address; - uint32_t model; - uint32_t event_gsiv; - uint32_t pri_gsiv; - uint32_t gerr_gsiv; - uint32_t sync_gsiv; - AcpiIortIdMapping id_mapping_array[]; -} QEMU_PACKED; -typedef struct AcpiIortSmmu3 AcpiIortSmmu3; - -struct AcpiIortRC { - ACPI_IORT_NODE_HEADER_DEF - AcpiIortMemoryAccess memory_properties; - uint32_t ats_attribute; - uint32_t pci_segment_number; - AcpiIortIdMapping id_mapping_array[]; -} QEMU_PACKED; -typedef struct AcpiIortRC AcpiIortRC; - #endif diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 42ea460313..8c382915a9 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -240,6 +240,28 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineS= tate *vms) } #endif =20 +#define ID_MAPPING_ENTRY_SIZE 20 +#define SMMU_V3_ENTRY_SIZE 60 +#define ROOT_COMPLEX_ENTRY_SIZE 32 +#define IORT_NODE_OFFSET 48 + +static void build_iort_id_mapping(GArray *table_data, uint32_t input_base, + uint32_t id_count, uint32_t out_ref) +{ + /* Identity RID mapping covering the whole input RID range */ + build_append_int_noprefix(table_data, input_base, 4); /* Input base */ + build_append_int_noprefix(table_data, id_count, 4); /* Number of IDs */ + build_append_int_noprefix(table_data, input_base, 4); /* Output base */ + build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference= */ + build_append_int_noprefix(table_data, 0, 4); /* Flags */ +} + +struct AcpiIortIdMapping { + uint32_t input_base; + uint32_t id_count; +}; +typedef struct AcpiIortIdMapping AcpiIortIdMapping; + /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */ static int iort_host_bridges(Object *obj, void *opaque) @@ -282,17 +304,16 @@ static void build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { int i, nb_nodes, rc_mapping_count; - AcpiIortIdMapping *idmap; - AcpiIortItsGroup *its; - AcpiIortSmmu3 *smmu; - AcpiIortRC *rc; - const uint32_t iort_node_offset =3D 48; + const uint32_t iort_node_offset =3D IORT_NODE_OFFSET; size_t node_size, smmu_offset =3D 0; + AcpiIortIdMapping *idmap; GArray *smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); GArray *its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMappi= ng)); =20 AcpiTable table =3D { .sig =3D "IORT", .rev =3D 0, .oem_id =3D vms->oe= m_id, .oem_table_id =3D vms->oem_table_id }; + /* Table 2 The IORT */ + acpi_table_begin(&table, table_data); =20 if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { AcpiIortIdMapping next_range =3D {0}; @@ -330,100 +351,101 @@ build_iort(GArray *table_data, BIOSLinker *linker, = VirtMachineState *vms) nb_nodes =3D 2; /* RC, ITS */ rc_mapping_count =3D 1; } - - /* Table 2 The IORT */ - acpi_table_begin(&table, table_data); /* Number of IORT Nodes */ build_append_int_noprefix(table_data, nb_nodes, 4); + /* Offset to Array of IORT Nodes */ - build_append_int_noprefix(table_data, iort_node_offset, 4); + build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ =20 - /* ITS group node */ - node_size =3D sizeof(*its) + sizeof(uint32_t); - its =3D acpi_data_push(table_data, node_size); - - its->type =3D ACPI_IORT_NODE_ITS_GROUP; - its->length =3D cpu_to_le16(node_size); - its->its_count =3D cpu_to_le32(1); - its->identifiers[0] =3D 0; /* MADT translation_id */ + /* 3.1.1.3 ITS group node */ + build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ + node_size =3D 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier = */; + build_append_int_noprefix(table_data, node_size, 2); /* Length */ + build_append_int_noprefix(table_data, 0, 1); /* Revision */ + build_append_int_noprefix(table_data, 0, 4); /* Reserved */ + build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings = */ + build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array = */ + build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ + /* GIC ITS Identifier Array */ + build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); =20 if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { int irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; =20 - /* SMMUv3 node */ - smmu_offset =3D iort_node_offset + node_size; - node_size =3D sizeof(*smmu) + sizeof(*idmap); - smmu =3D acpi_data_push(table_data, node_size); + smmu_offset =3D table_data->len - table.table_offset; + /* 3.1.1.2 SMMUv3 */ + build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type = */ + node_size =3D SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; + build_append_int_noprefix(table_data, node_size, 2); /* Length */ + build_append_int_noprefix(table_data, 0, 1); /* Revision */ + build_append_int_noprefix(table_data, 0, 4); /* Reserved */ + build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappi= ngs */ + /* Reference to ID Array */ + build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); + /* Base address */ + build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base,= 8); + /* Flags */ + build_append_int_noprefix(table_data, 1 /* COHACC OverrideNote */,= 4); + build_append_int_noprefix(table_data, 0, 4); /* Reserved */ + build_append_int_noprefix(table_data, 0, 8); /* VATOS address */ + /* Model */ + build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4); + build_append_int_noprefix(table_data, irq, 4); /* Event */ + build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */ + build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */ + build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */ =20 - smmu->type =3D ACPI_IORT_NODE_SMMU_V3; - smmu->length =3D cpu_to_le16(node_size); - smmu->mapping_count =3D cpu_to_le32(1); - smmu->mapping_offset =3D cpu_to_le32(sizeof(*smmu)); - smmu->base_address =3D cpu_to_le64(vms->memmap[VIRT_SMMU].base); - smmu->flags =3D cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); - smmu->event_gsiv =3D cpu_to_le32(irq); - smmu->pri_gsiv =3D cpu_to_le32(irq + 1); - smmu->sync_gsiv =3D cpu_to_le32(irq + 2); - smmu->gerr_gsiv =3D cpu_to_le32(irq + 3); - - /* Identity RID mapping covering the whole input RID range */ - idmap =3D &smmu->id_mapping_array[0]; - idmap->input_base =3D 0; - idmap->id_count =3D cpu_to_le32(0xFFFF); - idmap->output_base =3D 0; /* output IORT node is the ITS group node (the first node) */ - idmap->output_reference =3D cpu_to_le32(iort_node_offset); + build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); } =20 - /* Root Complex Node */ - node_size =3D sizeof(*rc) + sizeof(*idmap) * rc_mapping_count; - rc =3D acpi_data_push(table_data, node_size); + /* Table 16 Root Complex Node */ + build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Typ= e */ + node_size =3D ROOT_COMPLEX_ENTRY_SIZE + + ID_MAPPING_ENTRY_SIZE * rc_mapping_count; + build_append_int_noprefix(table_data, node_size, 2); /* Length */ + build_append_int_noprefix(table_data, 0, 1); /* Revision */ + build_append_int_noprefix(table_data, 0, 4); /* Reserved */ + /* Number of ID mappings */ + build_append_int_noprefix(table_data, rc_mapping_count, 4); + /* Reference to ID Array */ + build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4); =20 - rc->type =3D ACPI_IORT_NODE_PCI_ROOT_COMPLEX; - rc->length =3D cpu_to_le16(node_size); - rc->mapping_count =3D cpu_to_le32(rc_mapping_count); - rc->mapping_offset =3D cpu_to_le32(sizeof(*rc)); + /* Table 13 Memory access properties */ + /* CCA: Cache Coherent Attribute */ + build_append_int_noprefix(table_data, 1 /* fully coherent */, 4); + build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hi= nts */ + build_append_int_noprefix(table_data, 0, 2); /* Reserved */ + /* MAF: Note Memory Access Flags */ + build_append_int_noprefix(table_data, 0x3 /* CCA =3D CPM =3D DCAS =3D = 1 */, 1); =20 - /* fully coherent device */ - rc->memory_properties.cache_coherency =3D cpu_to_le32(1); - rc->memory_properties.memory_flags =3D 0x3; /* CCA =3D CPM =3D DCAS = =3D 1 */ - rc->pci_segment_number =3D 0; /* MCFG pci_segment */ + build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */ + /* MCFG pci_segment */ + build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */ =20 + /* Output Reference */ if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { AcpiIortIdMapping *range; =20 /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ for (i =3D 0; i < smmu_idmaps->len; i++) { - idmap =3D &rc->id_mapping_array[i]; range =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); - - idmap->input_base =3D cpu_to_le32(range->input_base); - idmap->id_count =3D cpu_to_le32(range->id_count); - idmap->output_base =3D cpu_to_le32(range->input_base); /* output IORT node is the smmuv3 node */ - idmap->output_reference =3D cpu_to_le32(smmu_offset); + build_iort_id_mapping(table_data, range->input_base, + range->id_count, smmu_offset); } =20 /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ for (i =3D 0; i < its_idmaps->len; i++) { - idmap =3D &rc->id_mapping_array[smmu_idmaps->len + i]; range =3D &g_array_index(its_idmaps, AcpiIortIdMapping, i); - - idmap->input_base =3D cpu_to_le32(range->input_base); - idmap->id_count =3D cpu_to_le32(range->id_count); - idmap->output_base =3D cpu_to_le32(range->input_base); /* output IORT node is the ITS group node (the first node) */ - idmap->output_reference =3D cpu_to_le32(iort_node_offset); + build_iort_id_mapping(table_data, range->input_base, + range->id_count, iort_node_offset); } } else { - /* Identity RID mapping covering the whole input RID range */ - idmap =3D &rc->id_mapping_array[0]; - idmap->input_base =3D cpu_to_le32(0); - idmap->id_count =3D cpu_to_le32(0xFFFF); - idmap->output_base =3D cpu_to_le32(0); /* output IORT node is the ITS group node (the first node) */ - idmap->output_reference =3D cpu_to_le32(iort_node_offset); + build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); } =20 acpi_table_end(linker, &table); --=20 MST