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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id i27sm10807171wmb.40.2021.10.02.06.37.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Oct 2021 06:37:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=xestjMyTU7oTS0aNWwsb1degxoOmHdnc4pP8SK5HjqQ=; b=VAFh6x2ykob7+dXJPU3qAQMesSaOsOyrKChdePdyp5K7/f1mFN+00+x60XWNgQTjA7 PiJW8NQe5MvRKJieyrrqyw3OcdKI0BppadRUANp1fQsSkSKHhwnOPfpgCJBDI+GJzQMw dkGXN2skzkZc/Eji60C1MLojVyN111ZPHWzJR/xVOv7i9zVZkkx0Fc/AiKooZgfIVuxo dkUYaULBZxDqA7yNET3uqQRRjYWYZXS8TP2gJeh0UCZUxuth7g7zLaFGjzQwev6wIwkm J+I0nAOz7gCOEdy5EzqhARsMwbJfMaoWnLp9eDslseQFwaeqCoEnCx/sFJ+XUnXsZJBO G8dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=xestjMyTU7oTS0aNWwsb1degxoOmHdnc4pP8SK5HjqQ=; b=xTHqz5eYQsxatL9jWq0byjzrtLVwXJJyn31c3uNvngpuKqfsvFE6cQtxUjzzozD8kz s9A8t7LufhKZRDwKDanpmQmlqa1PksDWkf91mKU/skHypAZKs0KR368BbejstrzWhxLB JIiQegeO2J4UikUaGpmeJrw+nXHpKLh9O3I9oK8JLaPqFhZBz/Q7T4y+5LD+q59P/Gvy AuiBsRlgn2FQHyLwftganl1eqRjek4cHCL86wQKzcfvl6Uwqi/7rXpV+CrKtvXGZrW9m LAL4SWs/CCVVxC+pO5FuQ/E+3SetP5a7cMynr4AYFve4aoPg7ItytVThdz9yeI9FUSce s5qw== X-Gm-Message-State: AOAM530J+5MHNXKPXsSPaN6Hj7d4plJyLbSkk4/tLtCR1d7p/k6H+JlL IccL5fxfRlkSiwp2IEdRoWYmv7Xunvc= X-Google-Smtp-Source: ABdhPJze7YGVi8pTY3Mo+g/xn7EVaqWCJpycZGKFze2HnfZu/ko0k6E3tunKIm17r99kjOYqrPe0qg== X-Received: by 2002:a7b:c7ce:: with SMTP id z14mr9871999wmk.91.1633181874865; Sat, 02 Oct 2021 06:37:54 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Richard Henderson , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Leon Alrae Subject: [PATCH] target/mips: remove gen_mfc0_load64() and use tcg_gen_ld32s_tl() Date: Sat, 2 Oct 2021 15:37:53 +0200 Message-Id: <20211002133753.3432668-1-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1633181877635100001 From: Leon Alrae Remove misleading gen_mfc0_load64() which actually loads 32 or 64 bits depending whether MIPS32 or MIPS64 and also replace the pair of tcg_gen_ld_tl() + tcg_gen_ext32s_tl() with single tcg_gen_ld32s_tl(). Patch partly generated using the following spatch script: @@ expression reg, env, ofs; @@ -tcg_gen_ld_tl(reg, env, ofs); -tcg_gen_ext32s_tl(reg, reg); +tcg_gen_ld32s_tl(reg, env, ofs); Signed-off-by: Leon Alrae [PMD: Rebased and used Coccinelle spatch to complete] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson --- target/mips/tcg/translate.c | 68 ++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 39 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 148afec9dc0..40b350d6e17 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -5382,12 +5382,6 @@ static inline void gen_mfc0_load32(TCGv arg, target_= ulong off) tcg_temp_free_i32(t0); } =20 -static inline void gen_mfc0_load64(TCGv arg, target_ulong off) -{ - tcg_gen_ld_tl(arg, cpu_env, off); - tcg_gen_ext32s_tl(arg, arg); -} - static inline void gen_mtc0_store32(TCGv arg, target_ulong off) { TCGv_i32 t0 =3D tcg_temp_new_i32(); @@ -5679,17 +5673,19 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REG01__YQMASK: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask)); + tcg_gen_ld32s_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMa= sk)); register_name =3D "YQMask"; break; case CP0_REG01__VPESCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule)); + tcg_gen_ld32s_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPESchedule)); register_name =3D "VPESchedule"; break; case CP0_REG01__VPESCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack)); + tcg_gen_ld32s_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPEScheFBack)); register_name =3D "VPEScheFBack"; break; case CP0_REG01__VPEOPT: @@ -5790,8 +5786,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_04: switch (sel) { case CP0_REG04__CONTEXT: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context= )); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Cont= ext)); register_name =3D "Context"; break; case CP0_REG04__CONTEXTCONFIG: @@ -5801,9 +5796,8 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; case CP0_REG04__USERLOCAL: CP0_CHECK(ctx->ulri); - tcg_gen_ld_tl(arg, cpu_env, - offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, + offsetof(CPUMIPSState, active_tc.CP0_UserLoca= l)); register_name =3D "UserLocal"; break; case CP0_REG04__MMID: @@ -5828,20 +5822,20 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REG05__SEGCTL0: CP0_CHECK(ctx->sc); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0= )); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_SegCtl0)); register_name =3D "SegCtl0"; break; case CP0_REG05__SEGCTL1: CP0_CHECK(ctx->sc); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1= )); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_SegCtl1)); register_name =3D "SegCtl1"; break; case CP0_REG05__SEGCTL2: CP0_CHECK(ctx->sc); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2= )); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_SegCtl2)); register_name =3D "SegCtl2"; break; case CP0_REG05__PWBASE: @@ -5917,8 +5911,8 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_08: switch (sel) { case CP0_REG08__BADVADDR: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAdd= r)); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_BadVAddr)); register_name =3D "BadVAddr"; break; case CP0_REG08__BADINSTR: @@ -5975,8 +5969,8 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_10: switch (sel) { case CP0_REG10__ENTRYHI: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi= )); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_EntryHi)); register_name =3D "EntryHi"; break; default: @@ -6032,8 +6026,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_14: switch (sel) { case CP0_REG14__EPC: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)= ); register_name =3D "EPC"; break; default: @@ -6048,15 +6041,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REG15__EBASE: check_insn(ctx, ISA_MIPS_R2); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBas= e)); register_name =3D "EBase"; break; case CP0_REG15__CMGCRBASE: check_insn(ctx, ISA_MIPS_R2); CP0_CHECK(ctx->cmgcr); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_CMGCRBase)); register_name =3D "CMGCRBase"; break; default: @@ -6163,8 +6155,8 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REG20__XCONTEXT: #if defined(TARGET_MIPS64) check_insn(ctx, ISA_MIPS3); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContex= t)); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_XContext)); register_name =3D "XContext"; break; #endif @@ -6227,8 +6219,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) switch (sel) { case CP0_REG24__DEPC: /* EJTAG support */ - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC= )); register_name =3D "DEPC"; break; default: @@ -6341,8 +6332,8 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_30: switch (sel) { case CP0_REG30__ERROREPC: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_ErrorEPC)); register_name =3D "ErrorEPC"; break; default: @@ -6363,9 +6354,8 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REG31__KSCRATCH5: case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); - tcg_gen_ld_tl(arg, cpu_env, - offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); - tcg_gen_ext32s_tl(arg, arg); + tcg_gen_ld32s_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_KScratch[sel - 2])= ); register_name =3D "KScratch"; break; default: --=20 2.31.1