From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633108900847342.44352903006995; Fri, 1 Oct 2021 10:21:40 -0700 (PDT) Received: from localhost ([::1]:41514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWME7-0002Bh-MV for importer@patchew.org; Fri, 01 Oct 2021 13:21:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54520) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM4k-0004Yz-A9 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:11:58 -0400 Received: from mail-qt1-x835.google.com ([2607:f8b0:4864:20::835]:35654) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4i-0004v0-Dr for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:11:58 -0400 Received: by mail-qt1-x835.google.com with SMTP id c20so9632927qtb.2 for ; Fri, 01 Oct 2021 10:11:56 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MwSLIpZg3SBDOkqorWI9RwSF0cto2aAplNrO4o3oH4g=; b=oS226YFKN/UABBQtiQ2wJ1eX89Oobv6W4nIEnL5Oe1vYlRfVSmXbWkRs0eYir/7kBJ T0kGZuD0tedQMhlVdlIO+FCEW96v74WXPdAlfg6SnycVcH1/WD0ierhqaLOEmXy1DOoD KaTSBY4owfZxOuSYKmtP+DMOpqZ7r84WEVGysZ6aB7ysOJMiDtlZi4Q1FRHrFLCOFZKS l3qTgsq0QLvlFw2DNH/+oWuXLbFV43w7F6RV4Zi5p37o2kURV9q4B0vF5umfuZNA78mL X4T542mAhNoibSZDYL3a2JaRLrqVnqDy1aQj8QaYLr3BOBlIT2igFew03rfK+GmnhTGg fQOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MwSLIpZg3SBDOkqorWI9RwSF0cto2aAplNrO4o3oH4g=; b=1AlBPlvW7YnJHpsCU4AugbPXQ5nJkcrrpY/p//ePw/fzs0fzX1qEUJKDSngtu5tN0f 6R4+XsAL+gDhQCrEdDsULhyA6GFDWHDvgZ4wRuheLgSf8a3KTuFdcYwydznBZEbzxnu2 m1ud9n9KojbaeRELwJe8Nk/JPi22sMOur5FFH32r84kxAgy3p3VLVhd74AfIKaccyvVe 6x6huQAU0ST11jQKxsTckvwHktVjnsGuiob5Ph9fqAl6PKJ4y0GGbCSSVTVxVvUBlGb1 LkanI+O3qrbYvipbL63NRrJgo+WV3EiCtu1TZbu3wCMjt2D9TYNrNmKXNWuZDJ0BdjNx a0+g== X-Gm-Message-State: AOAM532OWIxopPo+ZznUNorETmkpbOx/8Ny5mqcW3fnL3d0bYKw2Mshw l9zMxO2tTuTgUm6npGDS5OKWYad5+z1Ekg== X-Google-Smtp-Source: ABdhPJxmvzShcYblgEycr+CAibPIbbjyyS0K4E7ozcgsqiBpofcIOx+UjrbG0LmaxUve+FCNaBOBNA== X-Received: by 2002:ac8:724b:: with SMTP id l11mr14103408qtp.109.1633108313940; Fri, 01 Oct 2021 10:11:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 01/41] accel/tcg: Split out adjust_signal_pc Date: Fri, 1 Oct 2021 13:11:11 -0400 Message-Id: <20211001171151.1739472-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633108901998100001 Split out a function to adjust the raw signal pc into a value that could be passed to cpu_restore_state. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- v2: Adjust pc in place; return MMUAccessType. --- include/exec/exec-all.h | 10 ++++++++++ accel/tcg/user-exec.c | 41 +++++++++++++++++++++++++---------------- 2 files changed, 35 insertions(+), 16 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 9d5987ba04..e54f8e5d65 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -663,6 +663,16 @@ static inline tb_page_addr_t get_page_addr_code_hostp(= CPUArchState *env, return addr; } =20 +/** + * adjust_signal_pc: + * @pc: raw pc from the host signal ucontext_t. + * @is_write: host memory operation was write, or read-modify-write. + * + * Alter @pc as required for unwinding. Return the type of the + * guest memory access -- host reads may be for guest execution. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8fed542622..cef025d001 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -57,18 +57,11 @@ static void QEMU_NORETURN cpu_exit_tb_from_sighandler(C= PUState *cpu, cpu_loop_exit_noexc(cpu); } =20 -/* 'pc' is the host PC at which the exception was raised. 'address' is - the effective address of the memory exception. 'is_write' is 1 if a - write caused the exception and otherwise 0'. 'old_set' is the - signal set which should be restored */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) +/* + * Adjust the pc to pass to cpu_restore_state; return the memop type. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write) { - CPUState *cpu =3D current_cpu; - CPUClass *cc; - unsigned long address =3D (unsigned long)info->si_addr; - MMUAccessType access_type =3D is_write ? MMU_DATA_STORE : MMU_DATA_LOA= D; - switch (helper_retaddr) { default: /* @@ -77,7 +70,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo= _t *info, * pointer into the generated code that will unwind to the * correct guest pc. */ - pc =3D helper_retaddr; + *pc =3D helper_retaddr; break; =20 case 0: @@ -97,7 +90,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo= _t *info, * Therefore, adjust to compensate for what will be done later * by cpu_restore_state_from_tb. */ - pc +=3D GETPC_ADJ; + *pc +=3D GETPC_ADJ; break; =20 case 1: @@ -113,12 +106,28 @@ static inline int handle_cpu_signal(uintptr_t pc, sig= info_t *info, * * Like tb_gen_code, release the memory lock before cpu_loop_exit. */ - pc =3D 0; - access_type =3D MMU_INST_FETCH; mmap_unlock(); - break; + *pc =3D 0; + return MMU_INST_FETCH; } =20 + return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; +} + +/* + * 'pc' is the host PC at which the exception was raised. + * 'address' is the effective address of the memory exception. + * 'is_write' is 1 if a write caused the exception and otherwise 0. + * 'old_set' is the signal set which should be restored. + */ +static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, + int is_write, sigset_t *old_set) +{ + CPUState *cpu =3D current_cpu; + CPUClass *cc; + unsigned long address =3D (unsigned long)info->si_addr; + MMUAccessType access_type =3D adjust_signal_pc(&pc, is_write); + /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running * code or during translation which can fault as we cross pages. --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633108696063968.7092577409787; Fri, 1 Oct 2021 10:18:16 -0700 (PDT) Received: from localhost ([::1]:33128 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMAo-0004jQ-LC for importer@patchew.org; Fri, 01 Oct 2021 13:18:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM4j-0004YE-Lc for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:11:57 -0400 Received: from mail-qt1-x834.google.com ([2607:f8b0:4864:20::834]:35653) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4i-0004ua-0t for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:11:57 -0400 Received: by mail-qt1-x834.google.com with SMTP id c20so9632902qtb.2 for ; Fri, 01 Oct 2021 10:11:55 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=icrti6lDQPvhEiIgagWnJKzt2C7OPefDuKffLMhjklY=; b=CQDbL3aJacG3T3nXBRaG1TerIp6vyzVIsNa9bhxIPFtdMO1PeLU40zhTJb+mSlRXbs uqY33GSATT64PSG6ZGKvtUxCuyQVuYA54AQuypJFkyC8qlkN75BlKmHhyp8F/QBAZ6iL VmeHPeC+PLlxxW6O6uEaJ2X6cvYfUcsb6Q9n65xHnT27MkZvf8ODlOIRF5R6ZQMma7lh q3e1fvTJ0r676LaQmt/++X4J7rGfMXWmvRISLWsKikoczWSwFTbvlGv2lAmPXxO7vMkJ En7OWUfSTwrEHtvshpk+1GZWeZHZgaJAGJWduiCTLbgP4kcTy6ykYyFPGYnbsliIjNIy yCJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=icrti6lDQPvhEiIgagWnJKzt2C7OPefDuKffLMhjklY=; b=Q9yzEYjT8U2xI9It8LljGt5QJiIDp2B6E1YmwRnpRPleIfcODFoPweXmmP/JdX5nSH nPjiKUyDWbwvyNQKhqG/7wa9EWZ559pWnDNCycXEEUpqSttuevpTg/zEzY9DzK5lryFC psJfkZt/AFCeCDj4FekZHBdN+JqZkW+waqPYd5Qe3xAY2nRG2BBt0twadH71XNArzlya kKiZIm9i3xaREKFEST6jOIaKAtwJ1+RMCrjcU7zA4BGjeQxduyknf3Cv7aG5zptasBzk mMx2gWhSNXKVQMMAMmPdDuxR/Q3EIxrqtm3qiTGfVJmT7mSoNo4wpl3SHqC2EGi9y5jW sMkg== X-Gm-Message-State: AOAM533JjRlbdivmUtBeaXxOoZqHklrlNxnQggPbRrMF1ZWYOXL4g/ZA PMoPNbK2WrshS8SDU8R6fGm2up65dNTKvw== X-Google-Smtp-Source: ABdhPJzbgPDrDYWWg1xJCnXQ5S3KV7fqUnZe2WwUJRuJYnBJ8c9AQuMS0t8CtYPsde+w3WV1zvkQVg== X-Received: by 2002:ac8:5752:: with SMTP id 18mr14961646qtx.203.1633108314910; Fri, 01 Oct 2021 10:11:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 02/41] accel/tcg: Move clear_helper_retaddr to cpu loop Date: Fri, 1 Oct 2021 13:11:12 -0400 Message-Id: <20211001171151.1739472-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633108700230100001 Content-Type: text/plain; charset="utf-8" Currently there are only two places that require we reset this value before exiting to the main loop, but that will change. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 3 ++- accel/tcg/user-exec.c | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5fd1ed3422..410588d08a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -451,6 +451,7 @@ void cpu_exec_step_atomic(CPUState *cpu) * memory. */ #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { @@ -460,7 +461,6 @@ void cpu_exec_step_atomic(CPUState *cpu) qemu_plugin_disable_mem_helpers(cpu); } =20 - /* * As we start the exclusive region before codegen we must still * be in the region if we longjump out of either the codegen or @@ -905,6 +905,7 @@ int cpu_exec(CPUState *cpu) #endif =20 #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index cef025d001..e94f1fed00 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -175,7 +175,6 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, * currently executing TB was modified and must be exited * immediately. Clear helper_retaddr for next execution. */ - clear_helper_retaddr(); cpu_exit_tb_from_sighandler(cpu, old_set); /* NORETURN */ =20 @@ -193,7 +192,6 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, * an exception. Undo signal and retaddr state prior to longjmp. */ sigprocmask(SIG_SETMASK, old_set, NULL); - clear_helper_retaddr(); =20 cc =3D CPU_GET_CLASS(cpu); cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633108496606717.4191545050708; Fri, 1 Oct 2021 10:14:56 -0700 (PDT) Received: from localhost ([::1]:53098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWM7Y-0007U5-1q for importer@patchew.org; Fri, 01 Oct 2021 13:14:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54522) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM4k-0004ZD-EV for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:11:58 -0400 Received: from mail-qt1-x834.google.com ([2607:f8b0:4864:20::834]:34803) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4i-0004vc-Jc for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:11:58 -0400 Received: by mail-qt1-x834.google.com with SMTP id m26so9644595qtn.1 for ; Fri, 01 Oct 2021 10:11:56 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d0XAyTZlMLuZKO7GS2lQ57aRasECVtACHoF9DI2hSaY=; b=SRB5ZbVBwBzLwCA2baGf0vx8izxpHAOS6ayxVYSYwLa702fbToaFah08vQNvJRjQXj Lb7xCpXOh86erkFLuFj9OYCLG9loPmVcPYFsVNBMN+/FarFbTFNHDbWrSz6jiMjEO410 OSoTO1iW2KOKxt+BwlSgqA84DbazpVRDHWIZNOK/EwWBiylqb+mBqdq3ImdWaL6XDA6I CXfd8FVZGMTOexXPWGQOkN9kSRURWMC1o/YH9IpTqGKA8WfwjKHhIkqaJEyugGTNlYbv fc5qv5mlxn+ozH3rZO1Q35MZYc4NnUtvmZ6L89wVAW/Hcz+0msMBFzmuZXGqf8co7ehu tEkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d0XAyTZlMLuZKO7GS2lQ57aRasECVtACHoF9DI2hSaY=; b=cBfAWs/QhmCvaKMIG0/2o604i4qWiEfFsc4Gd3MTQ+SBTDy9XRWKMXJkjiRd1Ivn9p AzOh37ybwwaZTQtcibvNpOo0TmHPam1UNlPBggYzw6hkdiaKYudCFTdJUHNAAKDxdrrY /pHyZvcZGC9bGt8va1P7rS3bFkZuvQz+v6T0ZqURunudc9ZhOwIrOBOKgyvud+hBa1Zq 1m3JG4AwoeRjBH9GycLIRhdylsjjFfRapbIrSH3mGZfTd29yO7QUdWoOqEhY7mm2jKCp Wwq51uj/crOam+U187l9t26TbHFfGLwU9/aAdB4YCMgdI+mcEOzbcuGEIlOUgp4uAO92 bVQA== X-Gm-Message-State: AOAM532JaszVie58rojI6eUTYknHZ/FGtssNQLf2xejgRsWatI/LVJxJ N9sEzz261JE5otumYFNf+p7WIZoktPOz5g== X-Google-Smtp-Source: ABdhPJwliMIplpNgfertU89maX3OdRe4K9Un10yB55nWglP2UIvylqzsuNZSUsHZ8lAKRCYmzboIpQ== X-Received: by 2002:ac8:429a:: with SMTP id o26mr14380184qtl.317.1633108315751; Fri, 01 Oct 2021 10:11:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 03/41] accel/tcg: Split out handle_sigsegv_accerr_write Date: Fri, 1 Oct 2021 13:11:13 -0400 Message-Id: <20211001171151.1739472-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633108498755100001 This is the major portion of handle_cpu_signal which is specific to tcg, handling the page protections for the translations. Most of the rest will migrate to linux-user/ shortly. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- v2: Pass guest address to handle_sigsegv_accerr_write. --- include/exec/exec-all.h | 12 +++++ accel/tcg/user-exec.c | 103 ++++++++++++++++++++++++---------------- 2 files changed, 74 insertions(+), 41 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index e54f8e5d65..5f94d799aa 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -673,6 +673,18 @@ static inline tb_page_addr_t get_page_addr_code_hostp(= CPUArchState *env, */ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); =20 +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @host_addr: the host address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e94f1fed00..6f4fc01b60 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -114,6 +114,54 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_= write) return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; } =20 +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @guest_addr: the guest address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + * + * Note that it is important that we don't call page_unprotect() unless + * this is really a "write to nonwriteable page" fault, because + * page_unprotect() assumes that if it is called for an access to + * a page that's writeable this means we had two threads racing and + * another thread got there first and already made the page writeable; + * so we will retry the access. If we were to call page_unprotect() + * for some other kind of fault that should really be passed to the + * guest, we'd end up in an infinite loop of retrying the faulting access. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr) +{ + switch (page_unprotect(guest_addr, host_pc)) { + case 0: + /* + * Fault not caused by a page marked unwritable to protect + * cached translations, must be the guest binary's problem. + */ + return false; + case 1: + /* + * Fault caused by protection of cached translation; TBs + * invalidated, so resume execution. Retain helper_retaddr + * for a possible second fault. + */ + return true; + case 2: + /* + * Fault caused by protection of cached translation, and the + * currently executing TB was modified and must be exited + * immediately. Clear helper_retaddr for next execution. + */ + cpu_exit_tb_from_sighandler(cpu, old_set); + /* NORETURN */ + default: + g_assert_not_reached(); + } +} + /* * 'pc' is the host PC at which the exception was raised. * 'address' is the effective address of the memory exception. @@ -125,8 +173,9 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, { CPUState *cpu =3D current_cpu; CPUClass *cc; - unsigned long address =3D (unsigned long)info->si_addr; + unsigned long host_addr =3D (unsigned long)info->si_addr; MMUAccessType access_type =3D adjust_signal_pc(&pc, is_write); + abi_ptr guest_addr; =20 /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running @@ -143,49 +192,21 @@ static inline int handle_cpu_signal(uintptr_t pc, sig= info_t *info, =20 #if defined(DEBUG_SIGNAL) printf("qemu: SIGSEGV pc=3D0x%08lx address=3D%08lx w=3D%d oldset=3D0x%= 08lx\n", - pc, address, is_write, *(unsigned long *)old_set); + pc, host_addr, is_write, *(unsigned long *)old_set); #endif - /* XXX: locking issue */ - /* Note that it is important that we don't call page_unprotect() unless - * this is really a "write to nonwriteable page" fault, because - * page_unprotect() assumes that if it is called for an access to - * a page that's writeable this means we had two threads racing and - * another thread got there first and already made the page writeable; - * so we will retry the access. If we were to call page_unprotect() - * for some other kind of fault that should really be passed to the - * guest, we'd end up in an infinite loop of retrying the faulting - * access. - */ - if (is_write && info->si_signo =3D=3D SIGSEGV && info->si_code =3D=3D = SEGV_ACCERR && - h2g_valid(address)) { - switch (page_unprotect(h2g(address), pc)) { - case 0: - /* Fault not caused by a page marked unwritable to protect - * cached translations, must be the guest binary's problem. - */ - break; - case 1: - /* Fault caused by protection of cached translation; TBs - * invalidated, so resume execution. Retain helper_retaddr - * for a possible second fault. - */ - return 1; - case 2: - /* Fault caused by protection of cached translation, and the - * currently executing TB was modified and must be exited - * immediately. Clear helper_retaddr for next execution. - */ - cpu_exit_tb_from_sighandler(cpu, old_set); - /* NORETURN */ - - default: - g_assert_not_reached(); - } - } =20 /* Convert forcefully to guest address space, invalid addresses are still valid segv ones */ - address =3D h2g_nocheck(address); + guest_addr =3D h2g_nocheck(host_addr); + + /* XXX: locking issue */ + if (is_write && + info->si_signo =3D=3D SIGSEGV && + info->si_code =3D=3D SEGV_ACCERR && + h2g_valid(host_addr) && + handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { + return 1; + } =20 /* * There is no way the target can handle this other than raising @@ -194,7 +215,7 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, sigprocmask(SIG_SETMASK, old_set, NULL); =20 cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, + cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, MMU_USER_IDX, false, pc); g_assert_not_reached(); } --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109074668915.041531018987; Fri, 1 Oct 2021 10:24:34 -0700 (PDT) Received: from localhost ([::1]:49890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMGv-0007rW-Gi for importer@patchew.org; Fri, 01 Oct 2021 13:24:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54524) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM4k-0004a6-QY for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:02 -0400 Received: from mail-qv1-xf36.google.com ([2607:f8b0:4864:20::f36]:46641) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4j-0004wv-DH for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:11:58 -0400 Received: by mail-qv1-xf36.google.com with SMTP id gs10so5959590qvb.13 for ; Fri, 01 Oct 2021 10:11:57 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lQDDeP4KrE59xBXWzR54VwCb3z15HLMlRMki+IJBEEo=; b=VXoI1wrngFfI/1y3jprxxdASxBCUI+A3c6wnpzEoNctfl2zsM5nYZmmSygKzZSvYv1 N8kcVkftZgXJxzmx9JYoiIDW0bipKiaT/eUQQi0cysu6Zr0Yk7OTm3pYskiSPzerrt48 3rKbQoViDZc6g8h9wfMQRuNH7CgBRdwjZTk+Ua0/EvirI54/xZJ1cTQ4Djs6/Yvk462r sMyFMxATIPI0TVRaduFJhNhI5Dn0GQtcvMafW9wsXwCdlW1bsrYtc9sDfqjTybi+2wuH LYxbYzYvyZpYGIZ+RLPHvzBsjVNrUbl15FXa0La39bqnOFAD8iXrDT5S1Vw4K0vgCor3 Z4cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lQDDeP4KrE59xBXWzR54VwCb3z15HLMlRMki+IJBEEo=; b=qIMMjj48Nb+Q372VKOyfSL12PJzuoir+8cVJzimE1kw9bMn3p4x63LY3HQkMwnhJPg R6WWSM4ioyjoAnqqu7qco+N7YqOI+reIdSBYvuivYcQECwyr9UVuHrmvlNnCBRh8LBCG QkA+B+aNpdD1esKaKyhz5cF9DB9XE+2BH1bFho69PsbmsyUP/A47C469eqt8rjOvL8bH AmweNkdgn+6X5M/qEbGGrvltnrg5iY/7lr5ZGgGIxrlf8RQL7TM5e6t57opeAEix8RFJ xIm+0Fcp8e9Qp5d+oudDqZeiSAgT6vXQjK0NVrxojvdhPnT3PTL2/1gbT7L9Neay8PdB cyAQ== X-Gm-Message-State: AOAM532w39DaaRrFLw0vvFTI3Adfd05PHwMbDu1aF0Xn5v5ImyPKFkzD Lv/4DnrJjyHQCW8ED+po3kY99dC7QFlp5w== X-Google-Smtp-Source: ABdhPJzgpr5AQIIv5VOOHCXNZJYKeXaD+oZD4aDwIhza/bDsmTquJWuUNVwwNraQrGdOWTmlAJZ+CA== X-Received: by 2002:a05:6214:1269:: with SMTP id r9mr10196117qvv.35.1633108316552; Fri, 01 Oct 2021 10:11:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 04/41] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Date: Fri, 1 Oct 2021 13:11:14 -0400 Message-Id: <20211001171151.1739472-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f36; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109076445100001 Content-Type: text/plain; charset="utf-8" Remove the comment about siglongjmp. We do use sigsetjmp in the main cpu loop, but we do not save the signal mask as most exits from the cpu loop do not require them. Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 6f4fc01b60..de4565f13e 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -46,17 +46,6 @@ __thread uintptr_t helper_retaddr; =20 //#define DEBUG_SIGNAL =20 -/* exit the current TB from a signal handler. The host registers are - restored in a state compatible with the CPU emulator - */ -static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, - sigset_t *old_set) -{ - /* XXX: use siglongjmp ? */ - sigprocmask(SIG_SETMASK, old_set, NULL); - cpu_loop_exit_noexc(cpu); -} - /* * Adjust the pc to pass to cpu_restore_state; return the memop type. */ @@ -155,7 +144,8 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_= t *old_set, * currently executing TB was modified and must be exited * immediately. Clear helper_retaddr for next execution. */ - cpu_exit_tb_from_sighandler(cpu, old_set); + sigprocmask(SIG_SETMASK, old_set, NULL); + cpu_loop_exit_noexc(cpu); /* NORETURN */ default: g_assert_not_reached(); --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633108701193460.5601485025561; Fri, 1 Oct 2021 10:18:21 -0700 (PDT) Received: from localhost ([::1]:33316 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMAu-0004rF-41 for importer@patchew.org; Fri, 01 Oct 2021 13:18:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54596) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM4s-0004dD-5n for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:06 -0400 Received: from mail-qt1-x829.google.com ([2607:f8b0:4864:20::829]:44981) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4p-0004yk-VM for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:05 -0400 Received: by mail-qt1-x829.google.com with SMTP id r16so9588673qtw.11 for ; Fri, 01 Oct 2021 10:11:59 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nXiWOopBLOLRsE3QCVjUHoJD6t3B8cBROMNMjuCuDVo=; b=X3O4gEzGg1mctSpI3dZ6269FnKmFbcvGRc+uVudRl7jOU5d361v4MgkDB6OkYrNEfJ KJ1wdDlAT9WONdescOBnOmT7cusKEzTnB/Fc0ZHgsF1H3b07uJ/mC9Q05SL7mhSWLYoN Z+6uX1N82UFFROma29kXPJbiwr3Pq7BSJZqVeqQGvkABUBMEOO8qguZbuQMY5gJtxfRn hE/3WurCYWzJpGxr3Ak03kt3SPCaYh5M20huvLtVXX84Y1qgLTbMexdwcbTdvZLtnnL9 JA6XdCrAq3fvfDjyvSVSLOhKno5/W1/0m9YzCA/EE+zITqEcTwebFyqog1L6KLiyW12m 3D7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nXiWOopBLOLRsE3QCVjUHoJD6t3B8cBROMNMjuCuDVo=; b=mW9syXIygv6jEt4YILePCueFDo9exV70sFYcsrVMwEJSWDlPbhypQChJlY3tkf9VxG uyvR65KauLFkqosGl3TaskgkirBZdQXb6X9EiRFPDBAY/wUlCLW5UNmq2JlF827G2O6L 9S/hD28sXLcM5xAC590DyPnrfaDzpXTyuNow2eBlzl/pOCb/B44Fwhnbzo+dqHvyRsvT VGuEawCBjOA7uHkqKwSSCd/W7harqU9bE/E5VsNZFBe/p2SkTmCOAcHRUUktS0sjRue+ mbtce4Juep+yc2RRVImN5mbO7z07rI5EXH72bz8f0zemXO15F5AxGUPgEk39LKu5Zmyh Xjkw== X-Gm-Message-State: AOAM533/fvRMZSLrjqZ//cCQHeQmgLDJKg13w0oPTrEjTn8dsnd/O2Ry khZ64xZs9yZnBDoxaSh/jUR9j+jGUWVy/Q== X-Google-Smtp-Source: ABdhPJzRxe84bmpxl/XMJY3aiezDfpAciwVqDUR0awPEwGQXPcxVxEHFnDWSSkyB8nUneHDZIDSnhQ== X-Received: by 2002:ac8:7143:: with SMTP id h3mr14624556qtp.242.1633108317952; Fri, 01 Oct 2021 10:11:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 05/41] configure: Merge riscv32 and riscv64 host architectures Date: Fri, 1 Oct 2021 13:11:15 -0400 Message-Id: <20211001171151.1739472-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::829; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x829.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633108703992100001 The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- configure | 8 ++------ meson.build | 4 +--- linux-user/host/{riscv64 =3D> riscv}/hostdep.h | 4 ++-- linux-user/host/riscv32/hostdep.h | 11 ----------- linux-user/host/{riscv64 =3D> riscv}/safe-syscall.inc.S | 0 5 files changed, 5 insertions(+), 22 deletions(-) rename linux-user/host/{riscv64 =3D> riscv}/hostdep.h (94%) delete mode 100644 linux-user/host/riscv32/hostdep.h rename linux-user/host/{riscv64 =3D> riscv}/safe-syscall.inc.S (100%) diff --git a/configure b/configure index 1043ccce4f..23ede08582 100755 --- a/configure +++ b/configure @@ -650,11 +650,7 @@ elif check_define __s390__ ; then cpu=3D"s390" fi elif check_define __riscv ; then - if check_define _LP64 ; then - cpu=3D"riscv64" - else - cpu=3D"riscv32" - fi + cpu=3D"riscv" elif check_define __arm__ ; then cpu=3D"arm" elif check_define __aarch64__ ; then @@ -667,7 +663,7 @@ ARCH=3D # Normalise host CPU name and set ARCH. # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64) + ppc|ppc64|s390x|sparc64|x32|riscv) ;; ppc64le) ARCH=3D"ppc64" diff --git a/meson.build b/meson.build index 7bdbbbdf02..30cb165b3b 100644 --- a/meson.build +++ b/meson.build @@ -56,7 +56,7 @@ have_block =3D have_system or have_tools python =3D import('python').find_installation() =20 supported_oses =3D ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', '= sunos', 'linux'] -supported_cpus =3D ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', = 'x86_64', +supported_cpus =3D ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] =20 cpu =3D host_machine.cpu_family() @@ -278,8 +278,6 @@ if not get_option('tcg').disabled() tcg_arch =3D 'i386' elif config_host['ARCH'] =3D=3D 'ppc64' tcg_arch =3D 'ppc' - elif config_host['ARCH'] in ['riscv32', 'riscv64'] - tcg_arch =3D 'riscv' endif add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tc= g_arch, language: ['c', 'cpp', 'objc']) diff --git a/linux-user/host/riscv64/hostdep.h b/linux-user/host/riscv/host= dep.h similarity index 94% rename from linux-user/host/riscv64/hostdep.h rename to linux-user/host/riscv/hostdep.h index 865f0fb9ff..2ba07456ae 100644 --- a/linux-user/host/riscv64/hostdep.h +++ b/linux-user/host/riscv/hostdep.h @@ -5,8 +5,8 @@ * See the COPYING file in the top-level directory. */ =20 -#ifndef RISCV64_HOSTDEP_H -#define RISCV64_HOSTDEP_H +#ifndef RISCV_HOSTDEP_H +#define RISCV_HOSTDEP_H =20 /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL diff --git a/linux-user/host/riscv32/hostdep.h b/linux-user/host/riscv32/ho= stdep.h deleted file mode 100644 index adf9edbf2d..0000000000 --- a/linux-user/host/riscv32/hostdep.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef RISCV32_HOSTDEP_H -#define RISCV32_HOSTDEP_H - -#endif diff --git a/linux-user/host/riscv64/safe-syscall.inc.S b/linux-user/host/r= iscv/safe-syscall.inc.S similarity index 100% rename from linux-user/host/riscv64/safe-syscall.inc.S rename to linux-user/host/riscv/safe-syscall.inc.S --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633108509742696.777987824096; Fri, 1 Oct 2021 10:15:09 -0700 (PDT) Received: from localhost ([::1]:54158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWM7o-0008AO-IO for importer@patchew.org; Fri, 01 Oct 2021 13:15:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54602) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM4s-0004dq-M7 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:06 -0400 Received: from mail-qt1-x82c.google.com ([2607:f8b0:4864:20::82c]:41503) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4q-0004yW-DW for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:06 -0400 Received: by mail-qt1-x82c.google.com with SMTP id t2so9609202qtx.8 for ; Fri, 01 Oct 2021 10:11:59 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xW7+Rb4faIKYtOPfsr6ReaDQx6qIs3ejiVFfi8A5QPg=; b=lKlYQstf0MPWhjErJCSowEy376pGtrYFlrklpO2HEO5zTaOnAuSCqNR9nswWf1YKsV I7fCRtAWkJnlKA+kYqfgjoykPfCUYIaEE4yGvmFmTTL/RgTsuj31g6NJ5k4l97Ywe2eQ MZivjVAYRClZII1y+miWGRUCyLrojIEVEPf3X1O14bNCjEHY1XlubklzU4h7dHMJDsxn wNzmQrvo+WFKydV8xi2B23snGQ4ejveEyDX1kMPaYlvY6sF/7BKk17xn618yYfNXO0dU btnOjnl1KRzDbTqsiiI0ULsEE8iVdDyuioQRNsDPySHNg1WkqmCIF7exB9ac17q74acp faBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xW7+Rb4faIKYtOPfsr6ReaDQx6qIs3ejiVFfi8A5QPg=; b=O5R0ozpddpd540CwczQCgKjiGdNlRncgas+v2x0xnXC5TZLkEfktTqS8pA9IZYxEjK 6GVi2C6TaoJd6ShFM3wjl6798u55Aoso1Zs8OxZSpMkzq4li1BAAmyeDRGlQU3bwn6ZV +wHBEDYDHAL/UE4HWvyu5O6oH8xz2U1fMN4MiClRv2+wVdIU3n8bQiZiD+JnuA86IMRZ Z6JgfIqYYx4JX5UUfOym0eZNCyo/YiF8OVsoMDCdsPWsCg3lU1IDunMtPC4ocaPaLAgh OkiecWnu34wccSkEwmWTAkyoMBhMkbaO3LCvv3iycvMVjaf6KTErbeFlLz0A8kYsUFqT 5aBQ== X-Gm-Message-State: AOAM530rbY9iWTnYzsRviieOCnbbYcVA18CizGz4177FR53CwxOsU6Kc JrgUEGJtAMHwPEOcsN8e9LHJ22MPaPLT5A== X-Google-Smtp-Source: ABdhPJyIMXXBKGz0h8zeZ8neOsvTlrkVZfbBm9tx+Ryacpl4e2FIfAeIox57Tq5FM67Q7hWj7UUwTw== X-Received: by 2002:ac8:5d91:: with SMTP id d17mr14445824qtx.18.1633108318902; Fri, 01 Oct 2021 10:11:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 06/41] linux-user: Reorg handling for SIGSEGV Date: Fri, 1 Oct 2021 13:11:16 -0400 Message-Id: <20211001171151.1739472-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82c; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, Warner Losh , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633108511148100005 Add stub host-signal.h for all linux-user hosts. Add new code replacing cpu_signal_handler. Full migration will happen one host at a time. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 1 + linux-user/host/arm/host-signal.h | 1 + linux-user/host/i386/host-signal.h | 1 + linux-user/host/mips/host-signal.h | 1 + linux-user/host/ppc/host-signal.h | 1 + linux-user/host/ppc64/host-signal.h | 1 + linux-user/host/riscv/host-signal.h | 1 + linux-user/host/s390/host-signal.h | 1 + linux-user/host/s390x/host-signal.h | 1 + linux-user/host/sparc/host-signal.h | 1 + linux-user/host/sparc64/host-signal.h | 1 + linux-user/host/x32/host-signal.h | 1 + linux-user/host/x86_64/host-signal.h | 1 + linux-user/signal.c | 109 ++++++++++++++++++++++---- 14 files changed, 106 insertions(+), 16 deletions(-) create mode 100644 linux-user/host/aarch64/host-signal.h create mode 100644 linux-user/host/arm/host-signal.h create mode 100644 linux-user/host/i386/host-signal.h create mode 100644 linux-user/host/mips/host-signal.h create mode 100644 linux-user/host/ppc/host-signal.h create mode 100644 linux-user/host/ppc64/host-signal.h create mode 100644 linux-user/host/riscv/host-signal.h create mode 100644 linux-user/host/s390/host-signal.h create mode 100644 linux-user/host/s390x/host-signal.h create mode 100644 linux-user/host/sparc/host-signal.h create mode 100644 linux-user/host/sparc64/host-signal.h create mode 100644 linux-user/host/x32/host-signal.h create mode 100644 linux-user/host/x86_64/host-signal.h diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch6= 4/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/aarch64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-s= ignal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/arm/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host= -signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/i386/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host= -signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/mips/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-s= ignal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/ho= st-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/ho= st-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/riscv/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host= -signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/ho= st-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390x/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/ho= st-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc6= 4/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-s= ignal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x32/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/= host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x86_64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/signal.c b/linux-user/signal.c index 2038216455..bab47a6962 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/bitops.h" #include "exec/gdbstub.h" +#include "hw/core/tcg-cpu-ops.h" =20 #include #include @@ -29,6 +30,7 @@ #include "loader.h" #include "trace.h" #include "signal-common.h" +#include "host-signal.h" =20 static struct target_sigaction sigact_table[TARGET_NSIG]; =20 @@ -766,41 +768,116 @@ static inline void rewind_if_in_safe_syscall(void *p= uc) } #endif =20 -static void host_signal_handler(int host_signum, siginfo_t *info, - void *puc) +static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) { CPUArchState *env =3D thread_cpu->env_ptr; CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; - - int sig; target_siginfo_t tinfo; ucontext_t *uc =3D puc; struct emulated_sigtable *k; + int guest_sig; =20 +#ifdef HOST_SIGNAL_PLACEHOLDER /* the CPU emulator uses some host signals to detect exceptions, we forward to it some signals */ - if ((host_signum =3D=3D SIGSEGV || host_signum =3D=3D SIGBUS) + if ((host_sig =3D=3D SIGSEGV || host_sig =3D=3D SIGBUS) && info->si_code > 0) { - if (cpu_signal_handler(host_signum, info, puc)) + if (cpu_signal_handler(host_sig, info, puc)) { return; + } } +#else + uintptr_t pc =3D 0; + bool sync_sig =3D false; + + /* + * Non-spoofed SIGSEGV and SIGBUS are synchronous, and need special + * handling wrt signal blocking and unwinding. + */ + if ((host_sig =3D=3D SIGSEGV || host_sig =3D=3D SIGBUS) && info->si_co= de > 0) { + MMUAccessType access_type; + uintptr_t host_addr; + abi_ptr guest_addr; + bool is_write; + + host_addr =3D (uintptr_t)info->si_addr; + + /* + * Convert forcefully to guest address space: addresses outside + * reserved_va are still valid to report via SEGV_MAPERR. + */ + guest_addr =3D h2g_nocheck(host_addr); + + pc =3D host_signal_pc(uc); + is_write =3D host_signal_write(info, uc); + access_type =3D adjust_signal_pc(&pc, is_write); + + if (host_sig =3D=3D SIGSEGV) { + const struct TCGCPUOps *tcg_ops; + + if (info->si_code =3D=3D SEGV_ACCERR && h2g_valid(host_addr)) { + /* If this was a write to a TB protected page, restart. */ + if (is_write && + handle_sigsegv_accerr_write(cpu, &uc->uc_sigmask, + pc, guest_addr)) { + return; + } + + /* + * With reserved_va, the whole address space is PROT_NONE, + * which means that we may get ACCERR when we want MAPERR. + */ + if (page_get_flags(guest_addr) & PAGE_VALID) { + /* maperr =3D false; */ + } else { + info->si_code =3D SEGV_MAPERR; + } + } + + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + + tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, + MMU_USER_IDX, false, pc); + g_assert_not_reached(); + } else { + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + } + + sync_sig =3D true; + } +#endif =20 /* get target signal number */ - sig =3D host_to_target_signal(host_signum); - if (sig < 1 || sig > TARGET_NSIG) + guest_sig =3D host_to_target_signal(host_sig); + if (guest_sig < 1 || guest_sig > TARGET_NSIG) { return; - trace_user_host_signal(env, host_signum, sig); + } + trace_user_host_signal(env, host_sig, guest_sig); + + host_to_target_siginfo_noswap(&tinfo, info); + k =3D &ts->sigtab[guest_sig - 1]; + k->info =3D tinfo; + k->pending =3D guest_sig; + ts->signal_pending =3D 1; + +#ifndef HOST_SIGNAL_PLACEHOLDER + /* + * For synchronous signals, unwind the cpu state to the faulting + * insn and then exit back to the main loop so that the signal + * is delivered immediately. + */ + if (sync_sig) { + cpu->exception_index =3D EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, pc); + } +#endif =20 rewind_if_in_safe_syscall(puc); =20 - host_to_target_siginfo_noswap(&tinfo, info); - k =3D &ts->sigtab[sig - 1]; - k->info =3D tinfo; - k->pending =3D sig; - ts->signal_pending =3D 1; - - /* Block host signals until target signal handler entered. We + /* + * Block host signals until target signal handler entered. We * can't block SIGSEGV or SIGBUS while we're executing guest * code in case the guest code provokes one in the window between * now and it getting out to the main loop. Signals will be --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633108502482997.3977758589286; Fri, 1 Oct 2021 10:15:02 -0700 (PDT) Received: from localhost ([::1]:53646 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWM7h-0007pn-80 for importer@patchew.org; Fri, 01 Oct 2021 13:15:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM4u-0004kb-VE for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:09 -0400 Received: from mail-qt1-x830.google.com ([2607:f8b0:4864:20::830]:42565) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4q-0004zU-GX for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:08 -0400 Received: by mail-qt1-x830.google.com with SMTP id f15so9620249qtv.9 for ; Fri, 01 Oct 2021 10:12:00 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eo69a6qpbSWMyVxfRxEgkjHG9EovPVD2b2o16GmRH3A=; b=XRgiJ10Ug34xSTcmUFKiRO3yy79GDGINSCTIYpW+7TMC8e/dIspBS2bX21aHKxy9Ta lkXg016F0vBrAWZtc+E+0BAb6TL5an2ESSNFiaoXjrd1w2/dKylGd/aZd1y7MhcRBMuD H/OFw9qLL+lch4y3JRGM2UrP4l6MRIlpZ9hPiHSK0pBXPDmIj7X/pPSW5WR4Q1ynydW9 d+zTbuXcpPLjJUZCeSZEi6yGAub8XLt9FeQ/g04dia35OeOnrPDS5Pod7tOiwsSMn539 1nhytwrv3LpyGWCt17Q8zNgXSNY6/TBsfqRaY+JJlWlsBvaOjxmis+YGUCwbAOM3zjAx xydA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eo69a6qpbSWMyVxfRxEgkjHG9EovPVD2b2o16GmRH3A=; b=cHgCyfSFvJHhSHtOp6zt2z5bZ/+p1aZTOjas8xTbAN9Ee+X8b6MTOBmWOEZq1XSOTf 1BUzWT7dYy7xl8imnEzOVeBwLgFCVN4pq2JNB2W4GrbbyN+TiNDG3raJFeYgp9McZFFy EE8skfbZXkFfLOKAgo6DY5qDPjvSc7vbhDWcii6XgBjnCFNC19vgq4heE1lF9XpCmSBK WUlFixGFU5Z6qzA0YB1T/j2Zry71lsyHbTyoS5AeuQH5sLIzd10puUQRYne0imArx9fy SfnXlXGuD1UFbi3sD0vxKui5a/mgs8WgozOnmrH/zEsku0k6tDpe1WE5h+YB0uexjH/R SufQ== X-Gm-Message-State: AOAM531R+JGiO+0/vuvYf3L9xd06NW3p9vlOWR4oA8vKTXfLiBUyekct R5pHP8bDZTtbEngBMF14wfiEU5oH2+RVpg== X-Google-Smtp-Source: ABdhPJyJn5YoLWokhg49Z40gIqfG1YSuS8DOXmYbIw4vE1TiJ8HJUjzedDF7Ski/n0xVW73x5DUtLA== X-Received: by 2002:ac8:5f13:: with SMTP id x19mr14548782qta.305.1633108319686; Fri, 01 Oct 2021 10:11:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 07/41] linux-user/host/x86: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:17 -0400 Message-Id: <20211001171151.1739472-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::830; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x830.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633108503673100001 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/i386/host-signal.h | 25 ++++- linux-user/host/x32/host-signal.h | 2 +- linux-user/host/x86_64/host-signal.h | 25 ++++- accel/tcg/user-exec.c | 136 +-------------------------- 4 files changed, 50 insertions(+), 138 deletions(-) diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host= -signal.h index f4b4d65031..ccbbee5082 100644 --- a/linux-user/host/i386/host-signal.h +++ b/linux-user/host/i386/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef I386_HOST_SIGNAL_H +#define I386_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_EIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] =3D=3D 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-s= ignal.h index f4b4d65031..26800591d3 100644 --- a/linux-user/host/x32/host-signal.h +++ b/linux-user/host/x32/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../x86_64/host-signal.h" diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/= host-signal.h index f4b4d65031..883d2fcf65 100644 --- a/linux-user/host/x86_64/host-signal.h +++ b/linux-user/host/x86_64/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef X86_64_HOST_SIGNAL_H +#define X86_64_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_RIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] =3D=3D 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index de4565f13e..b5d06183db 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -29,19 +29,6 @@ #include "trace/trace-root.h" #include "trace/mem.h" =20 -#undef EAX -#undef ECX -#undef EDX -#undef EBX -#undef ESP -#undef EBP -#undef ESI -#undef EDI -#undef EIP -#ifdef __linux__ -#include -#endif - __thread uintptr_t helper_retaddr; =20 //#define DEBUG_SIGNAL @@ -268,123 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong ad= dr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__i386__) - -#if defined(__NetBSD__) -#include -#include - -#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_e= ip)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define EIP_sig(context) ((context)->sc_eip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc =3D puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc =3D puc; -#else - ucontext_t *uc =3D puc; -#endif - unsigned long pc; - int trapno; - -#ifndef REG_EIP -/* for glibc 2.1 */ -#define REG_EIP EIP -#define REG_ERR ERR -#define REG_TRAPNO TRAPNO -#endif - pc =3D EIP_sig(uc); - trapno =3D TRAP_sig(uc); - return handle_cpu_signal(pc, info, - trapno =3D=3D PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(__x86_64__) - -#ifdef __NetBSD__ -#include -#define PC_sig(context) _UC_MACHINE_PC(context) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define PC_sig(context) ((context)->sc_rip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_ri= p)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - unsigned long pc; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc =3D puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc =3D puc; -#else - ucontext_t *uc =3D puc; -#endif - - pc =3D PC_sig(uc); - return handle_cpu_signal(pc, info, - TRAP_sig(uc) =3D=3D PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(_ARCH_PPC) +#if defined(_ARCH_PPC) =20 /*********************************************************************** * signal context platform-specific definitions @@ -895,11 +766,6 @@ int cpu_signal_handler(int host_signum, void *pinfo, =20 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } - -#else - -#error host CPU specific signal handler needed - #endif =20 /* The softmmu versions of these helpers are in cputlb.c. */ --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633108715036630.0102108500382; Fri, 1 Oct 2021 10:18:35 -0700 (PDT) Received: from localhost ([::1]:34478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMB8-0005ec-1T for importer@patchew.org; Fri, 01 Oct 2021 13:18:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54658) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM4u-0004hq-2t for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:08 -0400 Received: from mail-qv1-xf2d.google.com ([2607:f8b0:4864:20::f2d]:35683) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4q-00050O-IA for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:07 -0400 Received: by mail-qv1-xf2d.google.com with SMTP id dk4so5994502qvb.2 for ; Fri, 01 Oct 2021 10:12:01 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6fVjVy4AkVzaH6Z0yyaREpJWIPed0v0p7SS/ifUGXt0=; b=WD6ib4KHXSeGBc+f2/sASNKNA/iL4eFr5Acjq9YfznAiJj3B1FfHxUPa6DFtMjYfeD XzMVM9xL63I9xREhoQffnYbXw++MzEMqI9JBl5zz8vgpGVHNq6mMrvnIf0zg0E0qLUgw hn3j9wz6KJgPS1THOrLIC5W/W+thPgOKE9HDC9vPHRZSacvHx5Z4JpVYe2kb6QCjV36T ArxdGyuQ4TX+ugFFxywVSUpLcIEJDH331hYBzLFEMsCFLj/RvxN9gTAnRc+nhXz7VQG5 ROGFa0z2A8mUPtosbqfVYuVwNhMLnRbBTWUfajCDysLebw99xBUXlDybCXyGcCbTF49p s8LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6fVjVy4AkVzaH6Z0yyaREpJWIPed0v0p7SS/ifUGXt0=; b=Ls3K5LwLanoYrLOJL9i7AgaHz5H7Lq6ccYdShbxeRznRco2dhvYTe0y/Z69Ypc9YKc PBe2HeHMOUaGvJDhmPT5inWWvSvacaYFlnIhdIBc/Cw9NXOOUqHbXXpCkQ5cNQkq94zT 1G8VLHjcORbnMflmnU020ptY2TD46/YdtZG1+Osp2vbteXhOSL6HccRaH00yuCJJocnI 6TavSivxPvoLvbCZdhEhaEECSVq6EEMhC6kolIKk8KopTF6gdNodhdKU3G5q32hrIa27 GcNlPkbFyPc0EpSQT2lRhw+OeoCHauc614pN/6mvkvrPzJIGIziTGR6Hms8XKQ9fK2jA nBKg== X-Gm-Message-State: AOAM532EPY48aB/OQZLwWuK6o3MsRMpmSxEXGKZ8vsCwp1iFYQYaHZBp R8PMwlgqg7RtR9jxuFv7nlEilQA5QlWwRw== X-Google-Smtp-Source: ABdhPJxu3Amet1SY+/glSQyLcFuu98TEaODhIC1HRfkrP1y/K292n4hP/twEC13SDbyzeC9aas3JGQ== X-Received: by 2002:a0c:c2c4:: with SMTP id c4mr10374993qvi.18.1633108320518; Fri, 01 Oct 2021 10:12:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 08/41] linux-user/host/ppc: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:18 -0400 Message-Id: <20211001171151.1739472-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2d; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633108716604100003 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/ppc/host-signal.h | 25 ++++++++- linux-user/host/ppc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 79 +---------------------------- 3 files changed, 26 insertions(+), 80 deletions(-) diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-s= ignal.h index f4b4d65031..e09756c691 100644 --- a/linux-user/host/ppc/host-signal.h +++ b/linux-user/host/ppc/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef PPC_HOST_SIGNAL_H +#define PPC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.regs->nip; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.regs->trap !=3D 0x400 + && (uc->uc_mcontext.regs->dsisr & 0x02000000); +} + +#endif diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/ho= st-signal.h index f4b4d65031..a353c22a90 100644 --- a/linux-user/host/ppc64/host-signal.h +++ b/linux-user/host/ppc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../ppc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b5d06183db..e9e530e2e1 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,84 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(_ARCH_PPC) - -/*********************************************************************** - * signal context platform-specific definitions - * From Wine - */ -#ifdef linux -/* All Registers access - only for local access */ -#define REG_sig(reg_name, context) \ - ((context)->uc_mcontext.regs->reg_name) -/* Gpr Registers access */ -#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], conte= xt) -/* Program counter */ -#define IAR_sig(context) REG_sig(nip, context) -/* Machine State Register (Supervisor) */ -#define MSR_sig(context) REG_sig(msr, context) -/* Count register */ -#define CTR_sig(context) REG_sig(ctr, context) -/* User's integer exception register */ -#define XER_sig(context) REG_sig(xer, context) -/* Link register */ -#define LR_sig(context) REG_sig(link, context) -/* Condition register */ -#define CR_sig(context) REG_sig(ccr, context) - -/* Float Registers access */ -#define FLOAT_sig(reg_num, context) \ - (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) -#define FPSCR_sig(context) \ - (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) -/* Exception Registers access */ -#define DAR_sig(context) REG_sig(dar, context) -#define DSISR_sig(context) REG_sig(dsisr, context) -#define TRAP_sig(context) REG_sig(trap, context) -#endif /* linux */ - -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) -#include -#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) -#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) -#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) -#define XER_sig(context) ((context)->uc_mcontext.mc_xer) -#define LR_sig(context) ((context)->uc_mcontext.mc_lr) -#define CR_sig(context) ((context)->uc_mcontext.mc_cr) -/* Exception Registers access */ -#define DAR_sig(context) ((context)->uc_mcontext.mc_dar) -#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) -#endif /* __FreeBSD__|| __FreeBSD_kernel__ */ - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) - ucontext_t *uc =3D puc; -#else - ucontext_t *uc =3D puc; -#endif - unsigned long pc; - int is_write; - - pc =3D IAR_sig(uc); - is_write =3D 0; -#if 0 - /* ppc 4xx case */ - if (DSISR_sig(uc) & 0x00800000) { - is_write =3D 1; - } -#else - if (TRAP_sig(uc) !=3D 0x400 && (DSISR_sig(uc) & 0x02000000)) { - is_write =3D 1; - } -#endif - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__alpha__) +#if defined(__alpha__) =20 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109315113326.1591524482428; Fri, 1 Oct 2021 10:28:35 -0700 (PDT) Received: from localhost ([::1]:60364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMKo-0006XR-36 for importer@patchew.org; Fri, 01 Oct 2021 13:28:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54652) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM4t-0004gu-Px for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:07 -0400 Received: from mail-qt1-x82f.google.com ([2607:f8b0:4864:20::82f]:44987) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4q-00050S-H1 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:07 -0400 Received: by mail-qt1-x82f.google.com with SMTP id r16so9588788qtw.11 for ; Fri, 01 Oct 2021 10:12:01 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lavEGkgqky/ZtxbH6vUwcfGBAKCbGr33b9BznRGO5aU=; b=zARl9BpORiMdLKBoL9tIxF920e/AQULOqqM9vtZqXgmsIurF6AA/as5mLLVXlJ9yHg eTKuhftoW4epbDwDINPGSCndyrV31PM+URBPDeMmYV51pT9b1avsHkfeqCXIozUa8bd0 +GJShsRrzuKpTknwmZW9KtiGeUUDQ3D1yN5Aa/AfX6472qzgqK14DJruB7nN18yNSUz7 Nsgq2GIOal8MxIfScptaHQm/HPj6uZbNz4f1AHWlyIaz9rWXya6EgEEiaHSXx+ymZk7O SR9yUqo6nEzQ7bhK1fSqwhavoRhNfhhIG3VHA4zsPq9Dt0RdfBnFpHHQeeLW+bmwVSgt EXsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lavEGkgqky/ZtxbH6vUwcfGBAKCbGr33b9BznRGO5aU=; b=Jxxtxlp8keWfT+4YKYr5rmwxlVYYx2QSQkFULT8pqET+4bVCtUZhXSgfa7CKoloqAL An4oHSZWHCo6A+7x9ygt4CHpswFsbbzRNKb8r5gwyGpbXKmhBBHGpP/sevawy1KpOUJi BRziomtmvbx+7/RgkQPBY7adoqY2n/ZQQlQrCQyoH6aa8iGUcSIMATokojbqBgGqMqVq 6SaNt+9ksmn9iC13vtmL74ymyWv1XTu+dAiv97QbQzw4vz3RjPBHqKH1lXIC4FCFvCGB BDRBspO6nWf4rEUYYqLddNBhIAf03MvtAojJFzqC3pjeqwvCKPVZbgM40/8lwu9pHRQo duMA== X-Gm-Message-State: AOAM532ss27jGt0Llzllg2ZpXI0VS2+cM4/ejWAERZLNCCE+bGJOlaJE HouLHMK409i8g7NywFgPHQtBh/nN9go8zQ== X-Google-Smtp-Source: ABdhPJw62XuAkRyWBp5HmHG8Ga7OZi5soKt+KMF6UhB9M0+B0/e8oQWseAktDpSeoCnU9YBT6tlxqw== X-Received: by 2002:a05:622a:130c:: with SMTP id v12mr14129936qtk.315.1633108321361; Fri, 01 Oct 2021 10:12:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 09/41] linux-user/host/alpha: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:19 -0400 Message-Id: <20211001171151.1739472-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82f; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109316606100003 Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/host/alpha/host-signal.h | 41 +++++++++++++++++++++++++++++ accel/tcg/user-exec.c | 31 +--------------------- 2 files changed, 42 insertions(+), 30 deletions(-) create mode 100644 linux-user/host/alpha/host-signal.h diff --git a/linux-user/host/alpha/host-signal.h b/linux-user/host/alpha/ho= st-signal.h new file mode 100644 index 0000000000..e27704d832 --- /dev/null +++ b/linux-user/host/alpha/host-signal.h @@ -0,0 +1,41 @@ +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ALPHA_HOST_SIGNAL_H +#define ALPHA_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.sc_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t *pc =3D (uint32_t *)host_signal_pc(uc); + uint32_t insn =3D *pc; + + /* XXX: need kernel patch to get write flag faster */ + switch (insn >> 26) { + case 0x0d: /* stw */ + case 0x0e: /* stb */ + case 0x0f: /* stq_u */ + case 0x24: /* stf */ + case 0x25: /* stg */ + case 0x26: /* sts */ + case 0x27: /* stt */ + case 0x2c: /* stl */ + case 0x2d: /* stq */ + case 0x2e: /* stl_c */ + case 0x2f: /* stq_c */ + return true; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e9e530e2e1..b895b5c8bd 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,36 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__alpha__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - uint32_t *pc =3D uc->uc_mcontext.sc_pc; - uint32_t insn =3D *pc; - int is_write =3D 0; - - /* XXX: need kernel patch to get write flag faster */ - switch (insn >> 26) { - case 0x0d: /* stw */ - case 0x0e: /* stb */ - case 0x0f: /* stq_u */ - case 0x24: /* stf */ - case 0x25: /* stg */ - case 0x26: /* sts */ - case 0x27: /* stt */ - case 0x2c: /* stl */ - case 0x2d: /* stq */ - case 0x2e: /* stl_c */ - case 0x2f: /* stq_c */ - is_write =3D 1; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#elif defined(__sparc__) +#if defined(__sparc__) =20 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109543201551.1620981533987; Fri, 1 Oct 2021 10:32:23 -0700 (PDT) Received: from localhost ([::1]:40740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMOT-00041T-RD for importer@patchew.org; Fri, 01 Oct 2021 13:32:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM4u-0004hd-1x for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:08 -0400 Received: from mail-qt1-x833.google.com ([2607:f8b0:4864:20::833]:42568) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4q-00050Y-It for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:07 -0400 Received: by mail-qt1-x833.google.com with SMTP id f15so9620389qtv.9 for ; Fri, 01 Oct 2021 10:12:02 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SHk0L4QVJKHbdhHw2ZILrKhqMEpfB7Y/GR3loPVJEL4=; b=VOPV7a5MvSPeLhFRK8afKO3t56mNUPUFEr+jD7M/hGI3C0q3tMq/+xu/rWBxJn14YF BFwREGkMLdVjiliew4nP2P7vtFci730rPX7C7Fo5a3jarVUy4wzsqU+uzREHdWk2VSeN T3+9M9N0CZkKP1aFjo9myPJ9RV8fcyCDaDoB+UoiQWMZS26MWDTvX1/FGMY+iSjHnULH Ge96sJJ/LU2qLz2TZ7X6soZzqCgEqI+qfphvVHswVTJ9842wKPld22aXkmkVLjpLg7iK esF1OhWG5lyFyAwYBtvbSmUt/Ktu0YHzLf+thFR3kR9amdUhKF3fZu7lo8EdSQ1vXi0l PlGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SHk0L4QVJKHbdhHw2ZILrKhqMEpfB7Y/GR3loPVJEL4=; b=Pc1OMqsLPei3YPEHcrIH6EvUummCVXTtH08HSCTuYKQqEWdskIxAKyFyKBmAkuee5z VIXDvQYdGK3L2C7eCwg0IKNzsuLet85ERvqvcNUJ0dBwJNm1eHz1lzByVM4NPnqiK2dr 6EJEpkcp6XlEdALM72rVNwBYFpunJJsLOcFdAFSVE68Jl25q/xZKuGWghr3yNJBP19jv c7EINpdJkDXtp6Ww0XK/yzL0kk8p5RkU8ROOgCRA1DEIHIIG4Vji7i9XGC0M7CAlGrcs FPxfu4T4X9+QOzfIFcfxkpJp2EOVgMDftzQaO37yep3VcxwgQdwR4mXr8Jf22lM3DHjP GvjQ== X-Gm-Message-State: AOAM532xeuiCO2vXA4tVc3wAW00XIBpamQJT1UteE0nX3ql3sQMQFml1 KuxDH2z1RmNF5zv2SrJ+Gd1P9jYlQ+dQcg== X-Google-Smtp-Source: ABdhPJyhfq8W5ZdAnRgTyiVbsFX1cPvi5cxmPHejFPBEoBl5HjVrT1/o4c93uIcU5RggTNMxUTkfnw== X-Received: by 2002:ac8:4e30:: with SMTP id d16mr14370068qtw.309.1633108322194; Fri, 01 Oct 2021 10:12:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 10/41] linux-user/host/sparc: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:20 -0400 Message-Id: <20211001171151.1739472-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::833; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x833.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109544650100001 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Drop the Solais code as completely unused. Signed-off-by: Richard Henderson --- linux-user/host/sparc/host-signal.h | 54 ++++++++++++++++++++++- linux-user/host/sparc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 62 +-------------------------- 3 files changed, 55 insertions(+), 63 deletions(-) diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/ho= st-signal.h index f4b4d65031..232943a1db 100644 --- a/linux-user/host/sparc/host-signal.h +++ b/linux-user/host/sparc/host-signal.h @@ -1 +1,53 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef SPARC_HOST_SIGNAL_H +#define SPARC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ +#ifdef __arch64__ + return uc->uc_mcontext.mc_gregs[MC_PC]; +#else + return uc->uc_mcontext.gregs[REG_PC]; +#endif +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn =3D *(uint32_t *)host_signal_pc(uc); + + if ((insn >> 30) =3D=3D 3) { + switch ((insn >> 19) & 0x3f) { + case 0x05: /* stb */ + case 0x15: /* stba */ + case 0x06: /* sth */ + case 0x16: /* stha */ + case 0x04: /* st */ + case 0x14: /* sta */ + case 0x07: /* std */ + case 0x17: /* stda */ + case 0x0e: /* stx */ + case 0x1e: /* stxa */ + case 0x24: /* stf */ + case 0x34: /* stfa */ + case 0x27: /* stdf */ + case 0x37: /* stdfa */ + case 0x26: /* stqf */ + case 0x36: /* stqfa */ + case 0x25: /* stfsr */ + case 0x3c: /* casa */ + case 0x3e: /* casxa */ + return true; + } + } + return false; +} + +#endif diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc6= 4/host-signal.h index f4b4d65031..1191fe2d40 100644 --- a/linux-user/host/sparc64/host-signal.h +++ b/linux-user/host/sparc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../sparc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b895b5c8bd..c7d083db92 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,67 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__sparc__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - int is_write; - uint32_t insn; -#if !defined(__arch64__) || defined(CONFIG_SOLARIS) - uint32_t *regs =3D (uint32_t *)(info + 1); - void *sigmask =3D (regs + 20); - /* XXX: is there a standard glibc define ? */ - unsigned long pc =3D regs[1]; -#else -#ifdef __linux__ - struct sigcontext *sc =3D puc; - unsigned long pc =3D sc->sigc_regs.tpc; - void *sigmask =3D (void *)sc->sigc_mask; -#elif defined(__OpenBSD__) - struct sigcontext *uc =3D puc; - unsigned long pc =3D uc->sc_pc; - void *sigmask =3D (void *)(long)uc->sc_mask; -#elif defined(__NetBSD__) - ucontext_t *uc =3D puc; - unsigned long pc =3D _UC_MACHINE_PC(uc); - void *sigmask =3D (void *)&uc->uc_sigmask; -#endif -#endif - - /* XXX: need kernel patch to get write flag faster */ - is_write =3D 0; - insn =3D *(uint32_t *)pc; - if ((insn >> 30) =3D=3D 3) { - switch ((insn >> 19) & 0x3f) { - case 0x05: /* stb */ - case 0x15: /* stba */ - case 0x06: /* sth */ - case 0x16: /* stha */ - case 0x04: /* st */ - case 0x14: /* sta */ - case 0x07: /* std */ - case 0x17: /* stda */ - case 0x0e: /* stx */ - case 0x1e: /* stxa */ - case 0x24: /* stf */ - case 0x34: /* stfa */ - case 0x27: /* stdf */ - case 0x37: /* stdfa */ - case 0x26: /* stqf */ - case 0x36: /* stqfa */ - case 0x25: /* stfsr */ - case 0x3c: /* casa */ - case 0x3e: /* casxa */ - is_write =3D 1; - break; - } - } - return handle_cpu_signal(pc, info, is_write, sigmask); -} - -#elif defined(__arm__) +#if defined(__arm__) =20 #if defined(__NetBSD__) #include --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633108918488670.3597783440146; Fri, 1 Oct 2021 10:21:58 -0700 (PDT) Received: from localhost ([::1]:41718 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMEP-0002PU-8y for importer@patchew.org; Fri, 01 Oct 2021 13:21:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM4u-0004iH-8S for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:08 -0400 Received: from mail-qt1-x836.google.com ([2607:f8b0:4864:20::836]:42571) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4q-00050g-Ig for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:07 -0400 Received: by mail-qt1-x836.google.com with SMTP id f15so9620428qtv.9 for ; Fri, 01 Oct 2021 10:12:03 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sCS25t/S/07LT/4q9hu7ybFQaqd9aKvTlaQnlQkDGSw=; b=ZDOIDG7Yi83QTz10VWbJF1K4VnoBvpRKSgfl4FKywfx0tla/8d8lgz7p63wlJNMymt OxDfCV/oYibpMQA8VLqdWcWJ2Z1ODVEce+uBn3CVqZF0UmOgnk45twLifgnEo09ro9BQ KvTvXXfyN32g91ok0mg1N/qkow2QjuQyLH+ohdJL6m4lEwf5rVjyubYR6PK+3nhHC6kR GBFBCOTQihKrXUzja+y6mHr5BC6gNQ8Iw1D+lh/UYFd4saO2NAxxShK+r/hzvba7sozx hDvlQxza/YaUX0SNpMWmiLCEbWMyPmihhuythvB8XQOk7UsUCJKxcWd9l8k2Yc2Zm4Uf zSzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sCS25t/S/07LT/4q9hu7ybFQaqd9aKvTlaQnlQkDGSw=; b=K8Y2NLb3jfLhDMfQOUhKZ7fqAtYoZm5KG3S2tZveB3PbT9Gqyp1bviKki+f9Fhf1xh x5W/MkzmvLyqtoelD2f9jpPTzc6XnpXPAYZkprbBHt6TZ9PqGSA4AFrT9Owju9zqtrmQ 0y/BTb0mbyDG+tCZuDm8x0Lm3bHmfvQJ1fakfj2Juc8jXQT2PZJsqOWfzIPTy3FlHd0n K0BEGYNguT74ytGXM/Sk0HSgHvOYDWAqgqxgccPBiVm6xTJP5q24QOG+10QonhVdZHLp 7KSvBp592as7fnG21k0Yg6XxVrzftuzZ9ZK6UpPLZ2iXth+Q0Ouw/WC5lNl33dPP+SMH fsdQ== X-Gm-Message-State: AOAM532ObxHjuq7+jVu7PvpclxrRogXX5w7Q/3eH632h3QpF7/63RQ1Q RWJoc2YsSAXWrchJ17CETd2EtmfXLNy/Bw== X-Google-Smtp-Source: ABdhPJxzaCpCV6cseXNcY4Gg0tDXXm8gb0UvW2zUFwDnmIRSVD2HPtdH7hxeuLXiuOwy+TE98Mm26Q== X-Received: by 2002:ac8:4e8d:: with SMTP id 13mr14026136qtp.2.1633108322998; Fri, 01 Oct 2021 10:12:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 11/41] linux-user/host/arm: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:21 -0400 Message-Id: <20211001171151.1739472-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::836; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x836.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633108920166100001 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- linux-user/host/arm/host-signal.h | 30 ++++++++++++++++++++- accel/tcg/user-exec.c | 45 +------------------------------ 2 files changed, 30 insertions(+), 45 deletions(-) diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-s= ignal.h index f4b4d65031..6932224c1c 100644 --- a/linux-user/host/arm/host-signal.h +++ b/linux-user/host/arm/host-signal.h @@ -1 +1,29 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ARM_HOST_SIGNAL_H +#define ARM_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.arm_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + /* + * In the FSR, bit 11 is WnR, assuming a v6 or + * later processor. On v5 we will always report + * this as a read, which will fail later. + */ + uint32_t fsr =3D uc->uc_mcontext.error_code; + return extract32(fsr, 11, 1); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index c7d083db92..e9c29f917d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,50 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__arm__) - -#if defined(__NetBSD__) -#include -#include -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; -#if defined(__NetBSD__) - ucontext_t *uc =3D puc; - siginfo_t *si =3D pinfo; -#else - ucontext_t *uc =3D puc; -#endif - unsigned long pc; - uint32_t fsr; - int is_write; - -#if defined(__NetBSD__) - pc =3D uc->uc_mcontext.__gregs[_REG_R15]; -#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ =3D=3D 2 && __GLI= BC_MINOR__ <=3D 3)) - pc =3D uc->uc_mcontext.gregs[R15]; -#else - pc =3D uc->uc_mcontext.arm_pc; -#endif - -#ifdef __NetBSD__ - fsr =3D si->si_trap; -#else - fsr =3D uc->uc_mcontext.error_code; -#endif - /* - * In the FSR, bit 11 is WnR, assuming a v6 or - * later processor. On v5 we will always report - * this as a read, which will fail later. - */ - is_write =3D extract32(fsr, 11, 1); - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__aarch64__) +#if defined(__aarch64__) =20 #if defined(__NetBSD__) =20 --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16331087091951020.7645108656512; Fri, 1 Oct 2021 10:18:29 -0700 (PDT) Received: from localhost ([::1]:34008 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMB2-0005Jy-3o for importer@patchew.org; Fri, 01 Oct 2021 13:18:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54736) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM4w-0004mh-1c for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:13 -0400 Received: from mail-qt1-x82f.google.com ([2607:f8b0:4864:20::82f]:38795) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4q-00052Z-Nb for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:09 -0400 Received: by mail-qt1-x82f.google.com with SMTP id d8so9626441qtd.5 for ; Fri, 01 Oct 2021 10:12:04 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xfI870gEd9IvWUORblCHYU3iuTigO27Yz4cJ6DbnRFo=; b=T89kgkluOu5eA4RO18gJKtaAT24McqbklZSPn49CuJdrAAXNwOdI9lzEZFwbiMEWwL nQNiCFLHrb0eE6ompkBsfsCe3uJmP7nEXgn5Rn+1mF+5IXrKYhFl9YI1RC9ChzdRXmOc HxNH3BFovS4CIsJVZXXjqCtjUu5ExiKfEYint8sZouN4L4BHr8yZhfjwOkBJNj1gT0lq 6N5ITBrqQ0MzoDXIgDtRDzAE0nedWmwadktSpAIkr2xz9TzHNmwjrV0NpJ0Z4567JxZj u6TJBe/yRL0WBlWqACEPJDrDgEkawvECa/pgH5kdH+2RB2sdAFeM8uwfzcORDuKMJHne 4dUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xfI870gEd9IvWUORblCHYU3iuTigO27Yz4cJ6DbnRFo=; b=gX+8vj9VCLFCP69+mn/XQTzo1lx0I163LUOQErBRBx88763/pcPyyLSHBiht1uzqgL r+QwpKXFT4DjaRhZKZDDjusdUTOlVvMN+8wNEf1pSVGrY7E/HgZ4LUiMlfyatnLoDHLd YgT9KdeZwMQFTttgrR9SAcwcRt7s199scPisaoBjc3Rl2AH8C2t2rQIcFxwF+JrJ3HWZ NrnLATiLsWAdB76vnj/2e2QZVne31hiNb7/afWvHGC+VysVlQXrbuQMdxRI13VKHqXd7 V7gEuKf2jLpzirTgz4AKozm37TFBThObgXXu4UnviKGBJmOLkMeSidLU3VnPv1wZn/mH 8svA== X-Gm-Message-State: AOAM5336Kn2p5QmFbqwrhIP14eoQ+E+Yln4rDoO9fbrvFIbLu7SgNGDW hHnOGnaEdqt9lTtJerVhQ+pg87HD8kc9cg== X-Google-Smtp-Source: ABdhPJyZJUnnSWk2zXXHXQKzQMonr6CdjC7gxQ1i0gNmcPImPN69rBKOU8dyrYEabLtvlsCIcekPyg== X-Received: by 2002:ac8:138b:: with SMTP id h11mr14355519qtj.163.1633108323737; Fri, 01 Oct 2021 10:12:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 12/41] linux-user/host/aarch64: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:22 -0400 Message-Id: <20211001171151.1739472-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82f; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633108710145100001 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 74 ++++++++++++++++++++- accel/tcg/user-exec.c | 94 +-------------------------- 2 files changed, 74 insertions(+), 94 deletions(-) diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch6= 4/host-signal.h index f4b4d65031..02a55c3372 100644 --- a/linux-user/host/aarch64/host-signal.h +++ b/linux-user/host/aarch64/host-signal.h @@ -1 +1,73 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef AARCH64_HOST_SIGNAL_H +#define AARCH64_HOST_SIGNAL_H + +/* Pre-3.16 kernel headers don't have these, so provide fallback definitio= ns */ +#ifndef ESR_MAGIC +#define ESR_MAGIC 0x45535201 +struct esr_context { + struct _aarch64_ctx head; + uint64_t esr; +}; +#endif + +static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) +{ + return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; +} + +static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) +{ + return (struct _aarch64_ctx *)((char *)hdr + hdr->size); +} + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + struct _aarch64_ctx *hdr; + uint32_t insn; + + /* Find the esr_context, which has the WnR bit in it */ + for (hdr =3D first_ctx(uc); hdr->magic; hdr =3D next_ctx(hdr)) { + if (hdr->magic =3D=3D ESR_MAGIC) { + struct esr_context const *ec =3D (struct esr_context const *)h= dr; + uint64_t esr =3D ec->esr; + + /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR b= it */ + return extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6, = 1) =3D=3D 1; + } + } + + /* + * Fall back to parsing instructions; will only be needed + * for really ancient (pre-3.16) kernels. + */ + insn =3D *(uint32_t *)host_signal_pc(uc); + + return (insn & 0xbfff0000) =3D=3D 0x0c000000 /* C3.3.1 */ + || (insn & 0xbfe00000) =3D=3D 0x0c800000 /* C3.3.2 */ + || (insn & 0xbfdf0000) =3D=3D 0x0d000000 /* C3.3.3 */ + || (insn & 0xbfc00000) =3D=3D 0x0d800000 /* C3.3.4 */ + || (insn & 0x3f400000) =3D=3D 0x08000000 /* C3.3.6 */ + || (insn & 0x3bc00000) =3D=3D 0x39000000 /* C3.3.13 */ + || (insn & 0x3fc00000) =3D=3D 0x3d800000 /* ... 128bit */ + /* Ignore bits 10, 11 & 21, controlling indexing. */ + || (insn & 0x3bc00000) =3D=3D 0x38000000 /* C3.3.8-12 */ + || (insn & 0x3fe00000) =3D=3D 0x3c800000 /* ... 128bit */ + /* Ignore bits 23 & 24, controlling indexing. */ + || (insn & 0x3a400000) =3D=3D 0x28000000; /* C3.3.7,14-16 */ +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e9c29f917d..8f4e788304 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,99 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__aarch64__) - -#if defined(__NetBSD__) - -#include -#include - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - ucontext_t *uc =3D puc; - siginfo_t *si =3D pinfo; - unsigned long pc; - int is_write; - uint32_t esr; - - pc =3D uc->uc_mcontext.__gregs[_REG_PC]; - esr =3D si->si_trap; - - /* - * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC - * is 0b10010x: then bit 6 is the WnR bit - */ - is_write =3D extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6, 1)= =3D=3D 1; - return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask); -} - -#else - -#ifndef ESR_MAGIC -/* Pre-3.16 kernel headers don't have these, so provide fallback definitio= ns */ -#define ESR_MAGIC 0x45535201 -struct esr_context { - struct _aarch64_ctx head; - uint64_t esr; -}; -#endif - -static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) -{ - return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; -} - -static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) -{ - return (struct _aarch64_ctx *)((char *)hdr + hdr->size); -} - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - uintptr_t pc =3D uc->uc_mcontext.pc; - bool is_write; - struct _aarch64_ctx *hdr; - struct esr_context const *esrctx =3D NULL; - - /* Find the esr_context, which has the WnR bit in it */ - for (hdr =3D first_ctx(uc); hdr->magic; hdr =3D next_ctx(hdr)) { - if (hdr->magic =3D=3D ESR_MAGIC) { - esrctx =3D (struct esr_context const *)hdr; - break; - } - } - - if (esrctx) { - /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ - uint64_t esr =3D esrctx->esr; - is_write =3D extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6= , 1) =3D=3D 1; - } else { - /* - * Fall back to parsing instructions; will only be needed - * for really ancient (pre-3.16) kernels. - */ - uint32_t insn =3D *(uint32_t *)pc; - - is_write =3D ((insn & 0xbfff0000) =3D=3D 0x0c000000 /* C3.3.1 */ - || (insn & 0xbfe00000) =3D=3D 0x0c800000 /* C3.3.2 */ - || (insn & 0xbfdf0000) =3D=3D 0x0d000000 /* C3.3.3 */ - || (insn & 0xbfc00000) =3D=3D 0x0d800000 /* C3.3.4 */ - || (insn & 0x3f400000) =3D=3D 0x08000000 /* C3.3.6 */ - || (insn & 0x3bc00000) =3D=3D 0x39000000 /* C3.3.13 = */ - || (insn & 0x3fc00000) =3D=3D 0x3d800000 /* ... 128b= it */ - /* Ignore bits 10, 11 & 21, controlling indexing. */ - || (insn & 0x3bc00000) =3D=3D 0x38000000 /* C3.3.8-1= 2 */ - || (insn & 0x3fe00000) =3D=3D 0x3c800000 /* ... 128b= it */ - /* Ignore bits 23 & 24, controlling indexing. */ - || (insn & 0x3a400000) =3D=3D 0x28000000); /* C3.3.7,1= 4-16 */ - } - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - -#elif defined(__s390__) +#if defined(__s390__) =20 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109724014668.9271079924406; Fri, 1 Oct 2021 10:35:24 -0700 (PDT) Received: from localhost ([::1]:49350 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMRM-0001QG-J4 for importer@patchew.org; Fri, 01 Oct 2021 13:35:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54716) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM4v-0004mc-OW for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:13 -0400 Received: from mail-qt1-x82c.google.com ([2607:f8b0:4864:20::82c]:46969) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4r-00053R-FE for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:09 -0400 Received: by mail-qt1-x82c.google.com with SMTP id e16so9583283qte.13 for ; Fri, 01 Oct 2021 10:12:05 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FVBR6xN38KGZK6ffFbaN/UMF6D1nBrL7MvtjajehkgQ=; b=AZobUYr0FYsgQEaOhTGsqGtRBIfXL8+DbygH7pFcxTP86tCCWj1Vn/+xoftPdMZktS 8lu2ALTgk34xo3vNninbhFKRaiotGdoY6xaYIOp8lV095Liv/P1MlU2lMsnQJLJIF1on 8YcpUXBxuU+tVbxuMergunyQa9vNKvJlG8LUvsHyyBLQKJB1xpo8y1SFs5BhQZuEJwAU VnEAbKvQzzaF4t4ARAoUv/VlCjMMOE4F33x2v9xopUz6DPrenBsaQIRl5WpWhSjg/H4w 7/etayHJuP6CgilQEttfZyXvEUMEQ0EeoH9YbpJstTUoOMUK00DYNWRy4gYXyUKqOasw 5b+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FVBR6xN38KGZK6ffFbaN/UMF6D1nBrL7MvtjajehkgQ=; b=J8irkwBu1ya8uPzlUlqZNR8t3y/jAtylSrMmZKhhhTb0vCdzafRa8ubBkjtaWd4ov8 LTHARiLEJgxSIf94O5o8GJZVqx+Eqicpgf3tjfFquovYnxNP2OIqyNz+n9UJLD3tAV2H GFseyM6ntvogUcQBCVaUIjufs//Re5fwSN0lkpK0r9EI2I+XvcoOtE7m6thgxCawy2pe wC3/+TmW7eju5pCKFP4xicWaMvZbqK9OHkZAtu2QWOR9LNv/unApg4maVThDYbHveIWF A2yJGtZV3bHRKc0m07cG6mb8Fs3xTJmE9cCYSbzzcNZRNSwr2D1Q7pUeNy70RVFjAdgZ qGbA== X-Gm-Message-State: AOAM532AgFFBEtNg000pMGLbh5SnvvJ7xfeJ5m6ebJmYySvOa0FRFcp4 rOTMsAkzbAYAzOQyEIvh1/dlO2VUSlik/w== X-Google-Smtp-Source: ABdhPJwHI+y+v/scZLVpucfoll3ytl1MGRjmjZa+cI6y6wMoGArQE4Dmkxki5Rbd8U2Wqa4QI8OBOg== X-Received: by 2002:ac8:740d:: with SMTP id p13mr14105669qtq.35.1633108324591; Fri, 01 Oct 2021 10:12:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 13/41] linux-user/host/s390: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:23 -0400 Message-Id: <20211001171151.1739472-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82c; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109725645100001 Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/host/s390/host-signal.h | 93 ++++++++++++++++++++++++++++- linux-user/host/s390x/host-signal.h | 2 +- accel/tcg/user-exec.c | 88 +-------------------------- 3 files changed, 94 insertions(+), 89 deletions(-) diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host= -signal.h index f4b4d65031..21f59b612a 100644 --- a/linux-user/host/s390/host-signal.h +++ b/linux-user/host/s390/host-signal.h @@ -1 +1,92 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef S390_HOST_SIGNAL_H +#define S390_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.psw.addr; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint16_t *pinsn =3D (uint16_t *)host_signal_pc(uc); + + /* + * ??? On linux, the non-rt signal handler has 4 (!) arguments instead + * of the normal 2 arguments. The 4th argument contains the "Translat= ion- + * Exception Identification for DAT Exceptions" from the hardware (aka + * "int_parm_long"), which does in fact contain the is_write value. + * The rt signal handler, as far as I can tell, does not give this val= ue + * at all. Not that we could get to it from here even if it were. + * So fall back to parsing instructions. Treat read-modify-write ones= as + * writes, which is not fully correct, but for tracking self-modifying= code + * this is better than treating them as reads. Checking si_addr page = flags + * might be a viable improvement, albeit a racy one. + */ + /* ??? This is not even close to complete. */ + switch (pinsn[0] >> 8) { + case 0x50: /* ST */ + case 0x42: /* STC */ + case 0x40: /* STH */ + case 0xba: /* CS */ + case 0xbb: /* CDS */ + return true; + case 0xc4: /* RIL format insns */ + switch (pinsn[0] & 0xf) { + case 0xf: /* STRL */ + case 0xb: /* STGRL */ + case 0x7: /* STHRL */ + return true; + } + break; + case 0xc8: /* SSF format insns */ + switch (pinsn[0] & 0xf) { + case 0x2: /* CSST */ + return true; + } + break; + case 0xe3: /* RXY format insns */ + switch (pinsn[2] & 0xff) { + case 0x50: /* STY */ + case 0x24: /* STG */ + case 0x72: /* STCY */ + case 0x70: /* STHY */ + case 0x8e: /* STPQ */ + case 0x3f: /* STRVH */ + case 0x3e: /* STRV */ + case 0x2f: /* STRVG */ + return true; + } + break; + case 0xeb: /* RSY format insns */ + switch (pinsn[2] & 0xff) { + case 0x14: /* CSY */ + case 0x30: /* CSG */ + case 0x31: /* CDSY */ + case 0x3e: /* CDSG */ + case 0xe4: /* LANG */ + case 0xe6: /* LAOG */ + case 0xe7: /* LAXG */ + case 0xe8: /* LAAG */ + case 0xea: /* LAALG */ + case 0xf4: /* LAN */ + case 0xf6: /* LAO */ + case 0xf7: /* LAX */ + case 0xfa: /* LAAL */ + case 0xf8: /* LAA */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/ho= st-signal.h index f4b4d65031..0e83f9358d 100644 --- a/linux-user/host/s390x/host-signal.h +++ b/linux-user/host/s390x/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../s390/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8f4e788304..0810b71ba0 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,93 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__s390__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - unsigned long pc; - uint16_t *pinsn; - int is_write =3D 0; - - pc =3D uc->uc_mcontext.psw.addr; - - /* - * ??? On linux, the non-rt signal handler has 4 (!) arguments instead - * of the normal 2 arguments. The 4th argument contains the "Translat= ion- - * Exception Identification for DAT Exceptions" from the hardware (aka - * "int_parm_long"), which does in fact contain the is_write value. - * The rt signal handler, as far as I can tell, does not give this val= ue - * at all. Not that we could get to it from here even if it were. - * So fall back to parsing instructions. Treat read-modify-write ones= as - * writes, which is not fully correct, but for tracking self-modifying= code - * this is better than treating them as reads. Checking si_addr page = flags - * might be a viable improvement, albeit a racy one. - */ - /* ??? This is not even close to complete. */ - pinsn =3D (uint16_t *)pc; - switch (pinsn[0] >> 8) { - case 0x50: /* ST */ - case 0x42: /* STC */ - case 0x40: /* STH */ - case 0xba: /* CS */ - case 0xbb: /* CDS */ - is_write =3D 1; - break; - case 0xc4: /* RIL format insns */ - switch (pinsn[0] & 0xf) { - case 0xf: /* STRL */ - case 0xb: /* STGRL */ - case 0x7: /* STHRL */ - is_write =3D 1; - } - break; - case 0xc8: /* SSF format insns */ - switch (pinsn[0] & 0xf) { - case 0x2: /* CSST */ - is_write =3D 1; - } - break; - case 0xe3: /* RXY format insns */ - switch (pinsn[2] & 0xff) { - case 0x50: /* STY */ - case 0x24: /* STG */ - case 0x72: /* STCY */ - case 0x70: /* STHY */ - case 0x8e: /* STPQ */ - case 0x3f: /* STRVH */ - case 0x3e: /* STRV */ - case 0x2f: /* STRVG */ - is_write =3D 1; - } - break; - case 0xeb: /* RSY format insns */ - switch (pinsn[2] & 0xff) { - case 0x14: /* CSY */ - case 0x30: /* CSG */ - case 0x31: /* CDSY */ - case 0x3e: /* CDSG */ - case 0xe4: /* LANG */ - case 0xe6: /* LAOG */ - case 0xe7: /* LAXG */ - case 0xe8: /* LAAG */ - case 0xea: /* LAALG */ - case 0xf4: /* LAN */ - case 0xf6: /* LAO */ - case 0xf7: /* LAX */ - case 0xfa: /* LAAL */ - case 0xf8: /* LAA */ - is_write =3D 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__mips__) +#if defined(__mips__) =20 #if defined(__misp16) || defined(__mips_micromips) #error "Unsupported encoding" --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633110256829700.7755743633251; Fri, 1 Oct 2021 10:44:16 -0700 (PDT) Received: from localhost ([::1]:38498 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMZz-00052l-PT for importer@patchew.org; Fri, 01 Oct 2021 13:44:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM51-0004uQ-Ok for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:15 -0400 Received: from mail-qv1-xf2e.google.com ([2607:f8b0:4864:20::f2e]:38668) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4s-00053a-Gg for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:15 -0400 Received: by mail-qv1-xf2e.google.com with SMTP id cv2so5984132qvb.5 for ; Fri, 01 Oct 2021 10:12:06 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TsF7+ye4ZFBKtVDH6YOEuxIjbYiQw3V/Xwn+HbNdAZw=; b=xcfH53GOYY/XORKDdh+TaaHqHwMOqUSCuZauYC7JY3M5tlPDcLCyaFPeXCoZ6x6Rs9 PykvbQXZUuYAEuH5LVxO98mIkZzOP7cpv0QtLZnAiU21qRs4kL9kEzPQjV7NGNpDE3VF CpcvR27GD9KpDgda9mk4LG+s+7+spyHmyGV5e9jnlXXRNbNQ6x+gB+ZNM0EBdRBq0OWO MmX3Gr6E2LCf3W63ZRpE+juHrxZqZ8/S85xh/KpKY3dxl3+03cf3IzPr0O5WzFOAf8dD MVMKtmxdrl5PGIlYv3X8+R03ag3uXzmDJx0COIrU90s3sqvmxbn/dnwL+/FcN7lw90Iz wXBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TsF7+ye4ZFBKtVDH6YOEuxIjbYiQw3V/Xwn+HbNdAZw=; b=kIyLii/R/svAgtUfdayFY0TcV3xGZfIj8AnGRUWe6itsdyep7bCWXVBvnNc+dzwKZJ Ir4sOyT0P+WUYZR6ONeLPI+C1I/Cg0RQWNLe2kBmg0RAjaskFb0ygL5KgMyPAf3YqU1o xLyokZx9s76Z8/hS4nyalbvxPPRJHECkozUj3Oq4dxuVgdZb4PkUMoWzSVm2a3yjvaX1 JI0kEXuDV60y4o2iBVnQ/WsUBQCryOEn3hGsz3YEE1qGnSN3ULCMLXcMcFyJ7g725+91 YiQ84LPhmE34m8ELr3Y/5DADH8NGg+ddV8AcfV5aJcQ3Pr0NAjNNaL2dhwPpx1cxi6dM 0rug== X-Gm-Message-State: AOAM531+CtXebfkZaT5wvkWjnxXLU3l8WNK7zjlpCSs3S6uUCzJCGdlT A/vxen+YCCBJlTzeqhm9d6jF+/k22r7RZg== X-Google-Smtp-Source: ABdhPJy11oCutXUkgvMQACrDN8OT8L1vVHdqzT+7NK3PL8E+mStqh4eJMI/0Ci+XS/7TdmQXGI98Ng== X-Received: by 2002:a05:6214:921:: with SMTP id dk1mr3533735qvb.31.1633108325460; Fri, 01 Oct 2021 10:12:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 14/41] linux-user/host/mips: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:24 -0400 Message-Id: <20211001171151.1739472-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633110257198100001 Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/host/mips/host-signal.h | 62 +++++++++++++++++++++++++++++- accel/tcg/user-exec.c | 52 +------------------------ 2 files changed, 62 insertions(+), 52 deletions(-) diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host= -signal.h index f4b4d65031..9c83e51130 100644 --- a/linux-user/host/mips/host-signal.h +++ b/linux-user/host/mips/host-signal.h @@ -1 +1,61 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_HOST_SIGNAL_H +#define MIPS_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +#if defined(__misp16) || defined(__mips_micromips) +#error "Unsupported encoding" +#endif + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn =3D *(uint32_t *)host_signal_pc(uc); + + /* Detect all store instructions at program counter. */ + switch ((insn >> 26) & 077) { + case 050: /* SB */ + case 051: /* SH */ + case 052: /* SWL */ + case 053: /* SW */ + case 054: /* SDL */ + case 055: /* SDR */ + case 056: /* SWR */ + case 070: /* SC */ + case 071: /* SWC1 */ + case 074: /* SCD */ + case 075: /* SDC1 */ + case 077: /* SD */ +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 + case 072: /* SWC2 */ + case 076: /* SDC2 */ +#endif + return true; + case 023: /* COP1X */ + /* + * Required in all versions of MIPS64 since + * MIPS64r1 and subsequent versions of MIPS32r2. + */ + switch (insn & 077) { + case 010: /* SWXC1 */ + case 011: /* SDXC1 */ + case 015: /* SUXC1 */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0810b71ba0..42d1ad189b 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,57 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__mips__) - -#if defined(__misp16) || defined(__mips_micromips) -#error "Unsupported encoding" -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - uintptr_t pc =3D uc->uc_mcontext.pc; - uint32_t insn =3D *(uint32_t *)pc; - int is_write =3D 0; - - /* Detect all store instructions at program counter. */ - switch((insn >> 26) & 077) { - case 050: /* SB */ - case 051: /* SH */ - case 052: /* SWL */ - case 053: /* SW */ - case 054: /* SDL */ - case 055: /* SDR */ - case 056: /* SWR */ - case 070: /* SC */ - case 071: /* SWC1 */ - case 074: /* SCD */ - case 075: /* SDC1 */ - case 077: /* SD */ -#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 - case 072: /* SWC2 */ - case 076: /* SDC2 */ -#endif - is_write =3D 1; - break; - case 023: /* COP1X */ - /* Required in all versions of MIPS64 since - MIPS64r1 and subsequent versions of MIPS32r2. */ - switch (insn & 077) { - case 010: /* SWXC1 */ - case 011: /* SDXC1 */ - case 015: /* SUXC1 */ - is_write =3D 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__riscv) +#if defined(__riscv) =20 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109098066158.6096449350357; Fri, 1 Oct 2021 10:24:58 -0700 (PDT) Received: from localhost ([::1]:50386 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMHI-0008EI-P4 for importer@patchew.org; Fri, 01 Oct 2021 13:24:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54798) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM50-0004o1-2J for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:14 -0400 Received: from mail-qk1-x730.google.com ([2607:f8b0:4864:20::730]:38617) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4t-00053w-9A for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:11 -0400 Received: by mail-qk1-x730.google.com with SMTP id q81so9852540qke.5 for ; Fri, 01 Oct 2021 10:12:06 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b88MeJ0VB21CqXeC9kfaVd7KTqjTS4pXJD2Bd6nXvIA=; b=eUZtB5RDwhksYQZxZBMueSYTrmGJyVbFWPJEkw7E2P196yP1ne4rarQgPIbExZguPR SY9AbhRMSUI45aIIZc/IfTcHbu5ETVDHKI/wV2jC/pzT1DymS2FuGtdknHubyOsWshR8 wwQrfXxANJ97jyM/fwzMOxBb/Zhkad9A+w7xsLSXRz9CQXSkbN6qy4bkQwgQCgbeqLYj Y20P1Zvx1J/qqdcnGMWf9P+9M/MAAPNbW+1wp3Kgv+h/DVvsV0TY3huedcu8WXazwiGl GFjX9TBW+24wHHQogl60q7mTEKD5cFFBuVKaCz3QbJ8+EVVpCORe/9981wN77rPJdjw7 DpWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b88MeJ0VB21CqXeC9kfaVd7KTqjTS4pXJD2Bd6nXvIA=; b=AcfTYVjxgPRlyxfcFyJIAngb0xWLV5MF9lXRSpnF9Fio8N0T3Vtpdfz2FEbt/cB0Mj F5pg1e6EB3euAPyzJ6uMJK8UYuVuFgG6ejwNMG5HFkjNz1FI8uvwSxCwgtC9pOP+OsW7 2leI51UtqGqHF9E9bAhEEODbyzEftEMT1AFJta3mr3Z4nBkwPqk6O81guSoHlu65Wf8+ EzsWVpj8AriA955met5BAbTTrtxgmbgsTykUcaBq7aW/PMfw+ZjE8Q7eNxPWUmYTqvub /xb7YLNxVbD1eAGnWYkamllMLEjeVJacHbI0cwikqe8QQKfBUQEWlhizJMqVUns2whDz yB7w== X-Gm-Message-State: AOAM5308rCo3cGI7b1o/g84cnpD2dpwV/5oiqgeipkldIatq0OQt2WN9 Met6RY6UlEN8pgrqzxgXwNouqEDtaTKvgA== X-Google-Smtp-Source: ABdhPJx9u2FX+B45gIeV5d8kEVrOJOSGSaDrMdX59RKYxq9DImcCzPywPyVTdxpVVs5F5d5Ow5s6ew== X-Received: by 2002:a37:bd87:: with SMTP id n129mr10442344qkf.428.1633108326314; Fri, 01 Oct 2021 10:12:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 15/41] linux-user/host/riscv: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:25 -0400 Message-Id: <20211001171151.1739472-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::730; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x730.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109099202100001 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 85 +++++++++++++++++- accel/tcg/user-exec.c | 134 ---------------------------- 2 files changed, 84 insertions(+), 135 deletions(-) diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/ho= st-signal.h index f4b4d65031..5860dce7d7 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -1 +1,84 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef RISCV_HOST_SIGNAL_H +#define RISCV_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.__gregs[REG_PC]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn =3D *(uint32_t *)host_signal_pc(uc); + + /* + * Detect store by reading the instruction at the program + * counter. Note: we currently only generate 32-bit + * instructions so we thus only detect 32-bit stores + */ + switch (((insn >> 0) & 0b11)) { + case 3: + switch (((insn >> 2) & 0b11111)) { + case 8: + switch (((insn >> 12) & 0b111)) { + case 0: /* sb */ + case 1: /* sh */ + case 2: /* sw */ + case 3: /* sd */ + case 4: /* sq */ + return true; + default: + break; + } + break; + case 9: + switch (((insn >> 12) & 0b111)) { + case 2: /* fsw */ + case 3: /* fsd */ + case 4: /* fsq */ + return true; + default: + break; + } + break; + default: + break; + } + } + + /* Check for compressed instructions */ + switch (((insn >> 13) & 0b111)) { + case 7: + switch (insn & 0b11) { + case 0: /*c.sd */ + case 2: /* c.sdsp */ + return true; + default: + break; + } + break; + case 6: + switch (insn & 0b11) { + case 0: /* c.sw */ + case 3: /* c.swsp */ + return true; + default: + break; + } + break; + default: + break; + } + + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 42d1ad189b..01e7e69e7f 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -139,64 +139,6 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset= _t *old_set, } } =20 -/* - * 'pc' is the host PC at which the exception was raised. - * 'address' is the effective address of the memory exception. - * 'is_write' is 1 if a write caused the exception and otherwise 0. - * 'old_set' is the signal set which should be restored. - */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) -{ - CPUState *cpu =3D current_cpu; - CPUClass *cc; - unsigned long host_addr =3D (unsigned long)info->si_addr; - MMUAccessType access_type =3D adjust_signal_pc(&pc, is_write); - abi_ptr guest_addr; - - /* For synchronous signals we expect to be coming from the vCPU - * thread (so current_cpu should be valid) and either from running - * code or during translation which can fault as we cross pages. - * - * If neither is true then something has gone wrong and we should - * abort rather than try and restart the vCPU execution. - */ - if (!cpu || !cpu->running) { - printf("qemu:%s received signal outside vCPU context @ pc=3D0x%" - PRIxPTR "\n", __func__, pc); - abort(); - } - -#if defined(DEBUG_SIGNAL) - printf("qemu: SIGSEGV pc=3D0x%08lx address=3D%08lx w=3D%d oldset=3D0x%= 08lx\n", - pc, host_addr, is_write, *(unsigned long *)old_set); -#endif - - /* Convert forcefully to guest address space, invalid addresses - are still valid segv ones */ - guest_addr =3D h2g_nocheck(host_addr); - - /* XXX: locking issue */ - if (is_write && - info->si_signo =3D=3D SIGSEGV && - info->si_code =3D=3D SEGV_ACCERR && - h2g_valid(host_addr) && - handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { - return 1; - } - - /* - * There is no way the target can handle this other than raising - * an exception. Undo signal and retaddr state prior to longjmp. - */ - sigprocmask(SIG_SETMASK, old_set, NULL); - - cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); -} - static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) @@ -255,82 +197,6 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__riscv) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - greg_t pc =3D uc->uc_mcontext.__gregs[REG_PC]; - uint32_t insn =3D *(uint32_t *)pc; - int is_write =3D 0; - - /* Detect store by reading the instruction at the program - counter. Note: we currently only generate 32-bit - instructions so we thus only detect 32-bit stores */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - is_write =3D 1; - break; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - is_write =3D 1; - break; - default: - break; - } - break; - default: - break; - } - } - - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - is_write =3D 1; - break; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - is_write =3D 1; - break; - default: - break; - } - break; - default: - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - /* The softmmu versions of these helpers are in cputlb.c. */ =20 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109888076635.012315106961; Fri, 1 Oct 2021 10:38:08 -0700 (PDT) Received: from localhost ([::1]:57926 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMU2-0007Fn-UF for importer@patchew.org; Fri, 01 Oct 2021 13:38:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54800) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM50-0004oD-3e for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:14 -0400 Received: from mail-qk1-x733.google.com ([2607:f8b0:4864:20::733]:35400) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4u-00054W-4J for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:13 -0400 Received: by mail-qk1-x733.google.com with SMTP id c7so9853912qka.2 for ; Fri, 01 Oct 2021 10:12:07 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+vyWXP6Fx9Nim2ldoxF0eSsJbEhC7OEjuYcEJUYRKoA=; b=U//2ifMmkqOL6DQASXcBeNMQnns/b181XCtp0N2yXnltdQ86YBODzqctMlykc1krMJ a6OfT5oJqO8z6IEr4HElTpJVWLgBFZeCoXDc5WW70n4RPQz2zZ3+AK6PFNinzvrVYmM+ lfqxPqVIz2GoLGThWhMAfLtqUKNu38o2QBVfG9QaSbaLR9rWol2WXtq4rvIfJPzl2r+X s0uhkvN6YYGPFBFdW7z0rNCPKlNqCY5XTB9YSKjaBoCB5FVIDhyBvvt2Zva3oGRkWEHy 5FEzgWHxT6lBl8eQlneySIcyW0gpdk+gkpn3KM90FgS+uRLmpfqD6/R3Tk3qFhd+N8Je 7m6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+vyWXP6Fx9Nim2ldoxF0eSsJbEhC7OEjuYcEJUYRKoA=; b=Ot2tkdeYC8R2nzHvp3otBf4TaOamPU4/iVx+wYW1bova4R1wLm365zAXIIKXmFLmN4 iUzcPu8wpvBQ6B4YcYt4KKZpcxiN23sEIePRtqtWxD5e2lrDrdyVJl8oAA/UEb7iu4hS CTkQU+NcRfdfhlqvB5Nn0O/RbOnW/Jrtf1amAzU392HA/2iemd2LBRx0tFqeYUCX9j7S D5CnuYEZnbvlqlaLWvwV2tnzWh7SGPPu2Cdg30uQrYX4/cZKfOD+bynuml9GhdzjaW+Y cKJ3M8YdKtWP35HMSmDFNEcz1hRnwO0lZR98PrRjgPjR9/GyJ/I2VQBEGr+Dz77UCNKo vm6g== X-Gm-Message-State: AOAM5319qDZ6ko3RMeiWr6+ifoyYdzHlOpzbJ00WgXopKBoyXXSxhB9M KSB4BA3EGIm5b7Lmsl+fOa7NNcz3tguTUQ== X-Google-Smtp-Source: ABdhPJwZBK+kuCNODQef30MFac+OMpZCwsXgQSQV22GFzcYA90ZtRGD+wpkZH9SvOKfKXh18K943bA== X-Received: by 2002:a37:bf02:: with SMTP id p2mr10702194qkf.503.1633108327052; Fri, 01 Oct 2021 10:12:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 16/41] target/arm: Fixup comment re handle_cpu_signal Date: Fri, 1 Oct 2021 13:11:26 -0400 Message-Id: <20211001171151.1739472-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::733; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x733.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109890530100001 Content-Type: text/plain; charset="utf-8" The named function no longer exists. Refer to host_signal_handler instead. Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index dab5f1d1cd..07be55b7e1 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -6118,7 +6118,7 @@ DO_LDN_2(4, dd, MO_64) * linux-user/ in its get_user/put_user macros. * * TODO: Construct some helpers, written in assembly, that interact with - * handle_cpu_signal to produce memory ops which can properly report errors + * host_signal_handler to produce memory ops which can properly report err= ors * without racing. */ =20 --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109503422491.17633463215793; Fri, 1 Oct 2021 10:31:43 -0700 (PDT) Received: from localhost ([::1]:39472 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMNq-0003C2-BZ for importer@patchew.org; Fri, 01 Oct 2021 13:31:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54820) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM51-0004rY-2J for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:15 -0400 Received: from mail-qk1-x736.google.com ([2607:f8b0:4864:20::736]:43602) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4u-000567-Mx for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:14 -0400 Received: by mail-qk1-x736.google.com with SMTP id 138so9803051qko.10 for ; Fri, 01 Oct 2021 10:12:08 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nMBhe6wRyQJffJfKqR3e4B4BjhzuFHvBY7lYZ6XbL2k=; b=hiXQ3mmw5CBhTiIe+H0zJFUOd8tQlCu6I7USJ9pr7fUw9L66NMmICsOqxlPs8R3Gho llCdRf3wWjVoI138TAgVv4z65YGzmQHm3v/jEOPQE0Y8xOes4knIgigu/pbacllm25m/ urZQGqYjvyFYSNJQ1yWzXpPNT9GhgxHTTE6tVuhkj1eqW/eN5McrYX9WyyHue8JekTBH pueo29vmGAM/b0VAcmg/XGr2OOTgqkn5YmSvaoneuDxmoOR0Nxob3nuoBQmO0hA6tnXK VZq57jP6FUnA3prwlFdPi2ai3LUlwMpV7Q0aJvWbEK933n9cOsGr+jcrbTDTc0w73tMM zenA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nMBhe6wRyQJffJfKqR3e4B4BjhzuFHvBY7lYZ6XbL2k=; b=5DzzG1YWWdPShZwzBNEtzwvxHsZ5n0wtMY8Wz72523t2uaJDCUt1lKpt2kIq8UrWK9 7RDuNPiQH511WX5Ho9m7cfIQJlJOyfNKmZXinL0givoplRY18fE7r9ZJg9J6tEPNwvTs a312WYX+GNJmvnJv6pp5WujsSquthcD5i/NeQ0UsNjez5s+PJyWZw2zV+TlJGtRESLU6 +9jyk4VPLpiSJneqqkKVuZC8LaJbvJFG2xE2nnLBO2KKMBMV/lMfw7gDxzDn8dY15lJn AGHkcpTlvSD/qi8+w6GUuFaob2dbHUQZGG0+TINoppitBXOYxn1h7EbOXsQRl/a6/+49 9DEg== X-Gm-Message-State: AOAM532u7TqwLOxRktCUo8iPw+CDWTjLJRl/GjZ5phNcF57RXGSKzxNM KOPYZWVCzhMAq95X3MT0jWMl/KmsJJ5ygg== X-Google-Smtp-Source: ABdhPJxXEptVnIRiJgPkCgvNAJHYlWUVI47UnRYTinbxOUAJ7QeFNfhiXJLtwJKYtyadGA1dEzujNg== X-Received: by 2002:a37:67cb:: with SMTP id b194mr10154077qkc.379.1633108327799; Fri, 01 Oct 2021 10:12:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 17/41] linux-user/host/riscv: Improve host_signal_write Date: Fri, 1 Oct 2021 13:11:27 -0400 Message-Id: <20211001171151.1739472-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x736.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109505352100001 Content-Type: text/plain; charset="utf-8" Do not read 4 bytes before we determine the size of the insn. Simplify triple switches in favor of checking major opcodes. Include the missing cases of compact fsd and fsdsp. Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 83 ++++++++++------------------- 1 file changed, 28 insertions(+), 55 deletions(-) diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/ho= st-signal.h index 5860dce7d7..ab06d70964 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -17,65 +17,38 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) =20 static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { - uint32_t insn =3D *(uint32_t *)host_signal_pc(uc); - /* - * Detect store by reading the instruction at the program - * counter. Note: we currently only generate 32-bit - * instructions so we thus only detect 32-bit stores + * Detect store by reading the instruction at the program counter. + * Do not read more than 16 bits, because we have not yet determined + * the size of the instruction. */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - return true; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - return true; - default: - break; - } - break; - default: - break; - } + const uint16_t *pinsn =3D (const uint16_t *)host_signal_pc(uc); + uint16_t insn =3D pinsn[0]; + + /* 16-bit instructions */ + switch (insn & 0xe003) { + case 0xa000: /* c.fsd */ + case 0xc000: /* c.sw */ + case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */ + case 0xa002: /* c.fsdsp */ + case 0xc002: /* c.swsp */ + case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */ + return true; } =20 - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - return true; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - return true; - default: - break; - } - break; - default: - break; + /* 32-bit instructions, major opcodes */ + switch (insn & 0x7f) { + case 0x23: /* store */ + case 0x27: /* store-fp */ + return true; + case 0x2f: /* amo */ + /* + * The AMO function code is in bits 25-31, unread as yet. + * The AMO functions are LR (read), SC (write), and the + * rest are all read-modify-write. + */ + insn =3D pinsn[1]; + return (insn >> 11) !=3D 2; /* LR */ } =20 return false; --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109293288803.1666122269561; Fri, 1 Oct 2021 10:28:13 -0700 (PDT) Received: from localhost ([::1]:59130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMKR-0005iH-8O for importer@patchew.org; Fri, 01 Oct 2021 13:28:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM50-0004py-HF for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:14 -0400 Received: from mail-qk1-x72e.google.com ([2607:f8b0:4864:20::72e]:42628) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4v-00056t-T5 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:14 -0400 Received: by mail-qk1-x72e.google.com with SMTP id x12so9810800qkf.9 for ; Fri, 01 Oct 2021 10:12:09 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=plpjMgZs0Fmj1no4dWQvatctpg292W263ogwu9LIdH8=; b=otGns6K9LbdwNOmejpmuDxPUaHT3dlCKnwXo+BvZwjQp6r9i/YX32rNDzD1o7qWfkH yDH0qmoEZ/b+DnMzVjWRgsbFgcA02KDlIfSgVqbVAnFAXxx3wckiR456+kX1aM6Tx/Av dpM+25P9ciO3tcMtOHnQ8+wLl719rGCM6p/Rwi+8Yf43nJqT7BUUdoPJsVjLrBLILBsY wrVtZB9BXvTgo3SkBRkpcMp8rtBDUITFU9DEdLm9R2oKurS+XROF0VgvGqWSOqohRY02 kAvBkzDEukaNe/9AVPjP4YafY/IyV2BlKXQ7aZTwveXGenZjIjuVNqcPF2iZ8Izm/IFa RLtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=plpjMgZs0Fmj1no4dWQvatctpg292W263ogwu9LIdH8=; b=6z2Rb3ASIvcJuzzNdvv/fMDH2IWbcL/b/Ddhhz0ZrUk6Nc/jIUrswi5MneBBFCSY/0 pT9XguxVsfVPDoSCwQQqtUJXBcFRBVT4CLlB77hlGDo7HsFiVXJ1bED7ciE+O1KEayIg ryG3naLpm2hhcUjBQzkk9Fa5qr0VX97rvtEiZ/PKqvwL8aX38wLYKW89NUihZcbOiZy+ /916Hd0TIyXdtgcH2Uj+GQwbjRPRaiRN/JQHyxwV+QR0asG1GmqlTnQf+658HwizpOzi HH7cJJGICFIWWNtD2qTP1Db2WGeKg7tcqSnuzyJVzpvc0aQ1NnA8o7vDfcE90pe2pmLH jHVA== X-Gm-Message-State: AOAM532Q+P4Tgj3xmGth3as415Tu/LQ+CphaRfLowFHxUQf4xDpHYDv5 WJXlkjpeJ6uPvcozXkI9OMd+nMua3d6vQw== X-Google-Smtp-Source: ABdhPJxKkmVpz6DZfDCDbezX6eVGCRrvL2RmU1sG3eWshNrFYFInCdlOVIYtQsf6Y4A8+gLTmKmC5Q== X-Received: by 2002:a37:27d5:: with SMTP id n204mr10251474qkn.31.1633108328922; Fri, 01 Oct 2021 10:12:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 18/41] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Date: Fri, 1 Oct 2021 13:11:28 -0400 Message-Id: <20211001171151.1739472-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72e; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109294656100001 Now that all of the linux-user hosts have been converted to host-signal.h, drop the compatibility code. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ------------ linux-user/signal.c | 14 -------------- 2 files changed, 26 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5f94d799aa..5dd663c153 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,18 +685,6 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_= write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); =20 -/** - * cpu_signal_handler - * @signum: host signal number - * @pinfo: host siginfo_t - * @puc: host ucontext_t - * - * To be called from the SIGBUS and SIGSEGV signal handler to inform the - * virtual cpu of exceptions. Returns true if the signal was handled by - * the virtual CPU. - */ -int cpu_signal_handler(int signum, void *pinfo, void *puc); - #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/linux-user/signal.c b/linux-user/signal.c index bab47a6962..537c6c41c0 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -777,17 +777,6 @@ static void host_signal_handler(int host_sig, siginfo_= t *info, void *puc) ucontext_t *uc =3D puc; struct emulated_sigtable *k; int guest_sig; - -#ifdef HOST_SIGNAL_PLACEHOLDER - /* the CPU emulator uses some host signals to detect exceptions, - we forward to it some signals */ - if ((host_sig =3D=3D SIGSEGV || host_sig =3D=3D SIGBUS) - && info->si_code > 0) { - if (cpu_signal_handler(host_sig, info, puc)) { - return; - } - } -#else uintptr_t pc =3D 0; bool sync_sig =3D false; =20 @@ -847,7 +836,6 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) =20 sync_sig =3D true; } -#endif =20 /* get target signal number */ guest_sig =3D host_to_target_signal(host_sig); @@ -862,7 +850,6 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) k->pending =3D guest_sig; ts->signal_pending =3D 1; =20 -#ifndef HOST_SIGNAL_PLACEHOLDER /* * For synchronous signals, unwind the cpu state to the faulting * insn and then exit back to the main loop so that the signal @@ -872,7 +859,6 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) cpu->exception_index =3D EXCP_INTERRUPT; cpu_loop_exit_restore(cpu, pc); } -#endif =20 rewind_if_in_safe_syscall(puc); =20 --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109185007720.9640010075942; Fri, 1 Oct 2021 10:26:25 -0700 (PDT) Received: from localhost ([::1]:54102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMIh-0002Oq-QC for importer@patchew.org; Fri, 01 Oct 2021 13:26:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54848) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM52-0004vl-3s for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:16 -0400 Received: from mail-qk1-x72a.google.com ([2607:f8b0:4864:20::72a]:46675) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4w-00057j-S4 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:15 -0400 Received: by mail-qk1-x72a.google.com with SMTP id b65so9793570qkc.13 for ; Fri, 01 Oct 2021 10:12:10 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p8GaNWW3vnRejpH0QBiQY2hh87QfB4bhIFphc+bCE2U=; b=ox9tk89ixmAYJEEJzNWoTUksyuhcuCJXzjxJwtioEpDbReFXDyyRKCEixMq/SSqlhN JWWrClTrPMjO7wbDVKM37vapqsBQ04qKUK+XsQkGFf6btJlLda5YwrFv8Hzzlhfwnkqb l40rQ/AbP1qAmk1BcqVl1JflaA4UbTQK60Y4F4fdoA7yujhXjfKrrHjJkrAmoYDkrBtR QieK/ThoW+zBG2OS4M5OB/pAc0oalqaD4Zip8L6AecZ9B4wdHMrnJadTYc8GSaIIUB8O 6QGoUOXvRiXslJ/htg4hNnlgTpi40ZP1hI2c7Q+sEK5QD6izSfhiH0okGPvbsProKfNk oLOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p8GaNWW3vnRejpH0QBiQY2hh87QfB4bhIFphc+bCE2U=; b=POU1b2LESo2VpiDHxJxzn3bqILBXmEnkIWvlS8WDI4T8vY99JTq231lZdWBFHM8NAh ApnLtqUn6evZwz/KYFGigx0G2g+4vY63Rp6+T5X9BdGehVAboJzNXHZRF0vSPK4kq6wP 7u/pZa8dg7/Nfol9LHhlnnLnL5YssH8MgNxiWIdMBskDZ7tqAGUJ8h90DjPVFVctexlL nxlyvJusWJnsg7U7CWTl/T31fntseTpYFuYUBUdkUbS9Rr3BaI/ix8iTOcrYERp0BN4W lDGa6TGhqxNslKZQVDTiIirXqyfW5+Ldn6cGMt350naw3v7bK7tAfXHe9uqPETwqTTKx G3LQ== X-Gm-Message-State: AOAM533UWzSBnG/4SwL+4pACDv6hy1pWyhy5bA+tda5zTeT9n48Hik7l QNXQFAzKP/8xXPiTFzIv32HgxVFK4qe8bA== X-Google-Smtp-Source: ABdhPJzajbUnqlGr0/vlrs4ODqYrS5kppdl6C4+VNA76C0ULhqSQzOaf9WxuQfzWIyKv4+7f9ew0WA== X-Received: by 2002:a37:8e44:: with SMTP id q65mr10304663qkd.372.1633108329891; Fri, 01 Oct 2021 10:12:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 19/41] hw/core: Add TCGCPUOps.record_sigsegv Date: Fri, 1 Oct 2021 13:11:29 -0400 Message-Id: <20211001171151.1739472-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72a; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109185489100003 Add a new user-only interface for updating cpu state before raising a signal. This will replace tlb_fill for user-only and should result in less boilerplate for each guest. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 6cbe17f2e6..41718b695b 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -111,6 +111,32 @@ struct TCGCPUOps { */ bool (*io_recompile_replay_branch)(CPUState *cpu, const TranslationBlock *tb); +#else + /** + * record_sigsegv: + * @cpu: cpu context + * @addr: faulting guest address + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * We are about to raise SIGSEGV with si_code set for @maperr, + * and si_addr set for @addr. Record anything further needed + * for the signal ucontext_t. + * + * If the emulated kernel does not provide anything to the signal + * handler with anything besides the user context registers, and + * the siginfo_t, then this hook need do nothing and may be omitted. + * Otherwise, record the data and return; the caller will raise + * the signal, unwind the cpu state, and return to the main loop. + * + * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided + * so that a "normal" cpu exception can be raised. In this case, + * the signal must be raised by the architecture cpu_loop. + */ + void (*record_sigsegv)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ =20 --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633110500442425.396681157423; Fri, 1 Oct 2021 10:48:20 -0700 (PDT) Received: from localhost ([::1]:47048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMdv-0002XF-Dj for importer@patchew.org; Fri, 01 Oct 2021 13:48:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54870) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM52-0004xo-JB for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:16 -0400 Received: from mail-qv1-xf2c.google.com ([2607:f8b0:4864:20::f2c]:34491) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4z-00059N-Oo for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:16 -0400 Received: by mail-qv1-xf2c.google.com with SMTP id x8so6002966qvp.1 for ; Fri, 01 Oct 2021 10:12:11 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. 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Use the new record_sigsegv target hook. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 15 +++++++++++++++ accel/tcg/user-exec.c | 33 ++++++++++++++++++--------------- linux-user/signal.c | 30 ++++++++++++++++++++++-------- 3 files changed, 55 insertions(+), 23 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5dd663c153..14e554d27d 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,6 +685,21 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_= write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); =20 +/** + * cpu_loop_exit_segv: + * @cpu: the cpu context + * @addr: the guest address of the fault + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGSEGV, and jump to the main cpu loop. + */ +void QEMU_NORETURN cpu_loop_exit_segv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 01e7e69e7f..1fd38ea624 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -143,35 +143,38 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) { - int flags; + int acc_flag; + bool maperr; =20 switch (access_type) { case MMU_DATA_STORE: - flags =3D PAGE_WRITE; + acc_flag =3D PAGE_WRITE_ORG; break; case MMU_DATA_LOAD: - flags =3D PAGE_READ; + acc_flag =3D PAGE_READ; break; case MMU_INST_FETCH: - flags =3D PAGE_EXEC; + acc_flag =3D PAGE_EXEC; break; default: g_assert_not_reached(); } =20 - if (!guest_addr_valid_untagged(addr) || - page_check_range(addr, 1, flags) < 0) { - if (nonfault) { - return TLB_INVALID_MASK; - } else { - CPUState *cpu =3D env_cpu(env); - CPUClass *cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type, - MMU_USER_IDX, false, ra); - g_assert_not_reached(); + if (guest_addr_valid_untagged(addr)) { + int page_flags =3D page_get_flags(addr); + if (page_flags & acc_flag) { + return 0; /* success */ } + maperr =3D !(page_flags & PAGE_VALID); + } else { + maperr =3D true; } - return 0; + + if (nonfault) { + return TLB_INVALID_MASK; + } + + cpu_loop_exit_segv(env_cpu(env), addr, access_type, maperr, ra); } =20 int probe_access_flags(CPUArchState *env, target_ulong addr, diff --git a/linux-user/signal.c b/linux-user/signal.c index 537c6c41c0..8c22f711f1 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -685,9 +685,27 @@ void force_sigsegv(int oldsig) } force_sig(TARGET_SIGSEGV); } - #endif =20 +void cpu_loop_exit_segv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, bool maperr, uintptr_t = ra) +{ + const struct TCGCPUOps *tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; + + if (tcg_ops->record_sigsegv) { + tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); + } else if (tcg_ops->tlb_fill) { + tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, = ra); + g_assert_not_reached(); + } + + force_sig_fault(TARGET_SIGSEGV, + maperr ? TARGET_SEGV_MAPERR : TARGET_SEGV_ACCERR, + addr); + cpu->exception_index =3D EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, ra); +} + /* abort execution with signal */ static void QEMU_NORETURN dump_core_and_abort(int target_sig) { @@ -803,7 +821,7 @@ static void host_signal_handler(int host_sig, siginfo_t= *info, void *puc) access_type =3D adjust_signal_pc(&pc, is_write); =20 if (host_sig =3D=3D SIGSEGV) { - const struct TCGCPUOps *tcg_ops; + bool maperr =3D true; =20 if (info->si_code =3D=3D SEGV_ACCERR && h2g_valid(host_addr)) { /* If this was a write to a TB protected page, restart. */ @@ -818,18 +836,14 @@ static void host_signal_handler(int host_sig, siginfo= _t *info, void *puc) * which means that we may get ACCERR when we want MAPERR. */ if (page_get_flags(guest_addr) & PAGE_VALID) { - /* maperr =3D false; */ + maperr =3D false; } else { info->si_code =3D SEGV_MAPERR; } } =20 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); - - tcg_ops =3D CPU_GET_CLASS(cpu)->tcg_ops; - tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); + cpu_loop_exit_segv(cpu, guest_addr, access_type, maperr, pc); } else { sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); } --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633108929231881.3540249450195; Fri, 1 Oct 2021 10:22:09 -0700 (PDT) Received: from localhost ([::1]:42424 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMEa-0002tE-3k for importer@patchew.org; Fri, 01 Oct 2021 13:22:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM52-0004w2-4o for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:16 -0400 Received: from mail-qk1-x732.google.com ([2607:f8b0:4864:20::732]:44776) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4z-00059l-Q1 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:15 -0400 Received: by mail-qk1-x732.google.com with SMTP id 194so9804185qkj.11 for ; Fri, 01 Oct 2021 10:12:12 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Sf9skOTdSQRGdKDCQ03O+bONiWBitaK9Yr/SJ3+lYKM=; b=yYOAOkIwwjKjILSTBDJEBFLPCoIKmcKnZm+B23qp1zX01ixLfQUibVDoxVAc/dmh7f kjWtnnx45xr6ZN/Qsve6G/6o3HMcIbkK2lBgj+UIOBSLhZrwYLHt1iSaD+n3d3e5jvki mogEKvUAaQeP+Ox7Z4Q0KEdF8XrNUFhgqZBAbSsoe6xf+OHdai7L3GzIqmfp1gVaaWQ4 RBnHxOuPbTiKPXTaXzBzRDbok8e9QIlEGcIg3pqRFtldJlIJa6zfm1wgm7R01T5vBJHd kihni2EAajU5gzpsAxlAr/I4Cqg9b1qfJRGivAJoSy0WE/CtZPG0Buwdx+d1k2v1VGex fZ9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Sf9skOTdSQRGdKDCQ03O+bONiWBitaK9Yr/SJ3+lYKM=; b=pr1RUDWQKwfMVFg+a0iul1LY7QJ26MprGRSFEdeAbpL0iO9VgmggFUc0lELFHpinr4 KvGGoQuci94FKFneVdNghxQzm0sjIjckKjLf8SJkXjwoDCNuPtm3j9BTlFKzlcp2nFeL Epmc1kLGYvZzPrI1MNPWA9OIKGpTMoiX8w2e42Ooiog+iT31sBKlqhwJ+RDUt7eCaVtb v+1MciF5D0J17ScCz9JJItRYtYGOpwiM06wsvVXPNlsZLSyaX73wZO3+XAmWf9kWMfza 4aCTd2xIaCkKgen7Bpyo6SRbKsnrFD7tDBp4uKTu0L3lriLJ7SGaXLTg0jDHOx4j46X8 Z7+A== X-Gm-Message-State: AOAM533Zk73TR/n4sDPldOtMbwmSPYR9gFjcvIHiOsUeFT6v7/fPnBgE Gw1guH6jQ4l5poo0WtefsoHPJpFdx/udvw== X-Google-Smtp-Source: ABdhPJxE6SkliJeHpFkF0PYv8TZEqIPbnOaJNS1JKAbVbUqORTsIvtYjPUDHzxYow+DTtnyagViZCQ== X-Received: by 2002:a37:6851:: with SMTP id d78mr10473807qkc.220.1633108331851; Fri, 01 Oct 2021 10:12:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 21/41] target/alpha: Make alpha_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:31 -0400 Message-Id: <20211001171151.1739472-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::732; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x732.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633108931305100003 Content-Type: text/plain; charset="utf-8" The fallback code in raise_sigsegv is sufficient for alpha-linux-user. Remove the code from cpu_loop that handled EXCP_MMFAULT. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/cpu.h | 7 ++++--- linux-user/alpha/cpu_loop.c | 8 -------- target/alpha/cpu.c | 2 +- target/alpha/helper.c | 13 +------------ 4 files changed, 6 insertions(+), 24 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 772828cc26..ec6657a490 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -439,9 +439,6 @@ void alpha_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU =20 void alpha_cpu_list(void); -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); =20 @@ -449,12 +446,16 @@ uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); + #ifndef CONFIG_USER_ONLY void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retad= dr); +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif =20 static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *= pc, diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 1b00a81385..4cc8e0a55c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -54,14 +54,6 @@ void cpu_loop(CPUAlphaState *env) fprintf(stderr, "External interrupt. Exit\n"); exit(EXIT_FAILURE); break; - case EXCP_MMFAULT: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D (page_get_flags(env->trap_arg0) & PAGE_VALID - ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); - info._sifields._sigfault._addr =3D env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 93e16a2ffb..52031ca981 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -218,9 +218,9 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { =20 static const struct TCGCPUOps alpha_tcg_ops =3D { .initialize =3D alpha_translate_init, - .tlb_fill =3D alpha_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D alpha_cpu_tlb_fill, .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, .do_interrupt =3D alpha_cpu_do_interrupt, .do_transaction_failed =3D alpha_cpu_do_transaction_failed, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 81550d9e2f..266d56ea73 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -119,18 +119,7 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned r= eg, uint64_t val) *cpu_alpha_addr_gr(env, reg) =3D val; } =20 -#if defined(CONFIG_USER_ONLY) -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - AlphaCPU *cpu =3D ALPHA_CPU(cs); - - cs->exception_index =3D EXCP_MMFAULT; - cpu->env.trap_arg0 =3D address; - cpu_loop_exit_restore(cs, retaddr); -} -#else +#ifndef CONFIG_USER_ONLY /* Returns the OSF/1 entMM failure indication, or -1 on success. */ static int get_physical_address(CPUAlphaState *env, target_ulong addr, int prot_need, int mmu_idx, --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109687682973.4207851047363; Fri, 1 Oct 2021 10:34:47 -0700 (PDT) Received: from localhost ([::1]:48034 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMQo-0000Wu-L6 for importer@patchew.org; Fri, 01 Oct 2021 13:34:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM53-00050T-Fr for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:17 -0400 Received: from mail-qv1-xf2a.google.com ([2607:f8b0:4864:20::f2a]:46631) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM4z-00059s-R4 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:17 -0400 Received: by mail-qv1-xf2a.google.com with SMTP id gs10so5960158qvb.13 for ; Fri, 01 Oct 2021 10:12:13 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c4orM2+k/w36SObBWIcKDbAPe9+W3VGWuqCQu4MwkhQ=; b=ISZSPyoqnInbLT4amaVBpq1c+UCl2x2aHxa++rXoEoRooNJOAaPMYFigVc8giI18Rl +MICo0zWP41vRJ6GPpiiuMx2C1XJP1ZAJn/myacVu3hWRcXVkDG+rL0/b5uAFIPqk7M9 yYwnXVBQwcDz6Rf6HmeFV4UhwepWeB9tYWJ2Hp+Yv3UBtkNYx4Pj8qgY6N+uheCC2Y98 shcPrUfEeNcRAlbbCEIlILGHHOawXp7h1TOEmt8wwtAAWv7ufe5nYoaPL4+wYFfcURYQ GVKkCFiwzJ8U0KzlnISobug6mUTvgkK09uYlQmMgi6i0Lw8c2kQ8igCw/nf5p5bMlv7F G1Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c4orM2+k/w36SObBWIcKDbAPe9+W3VGWuqCQu4MwkhQ=; b=lJZt4gBV/+EG7SYPga4VbvmfbXERykMd6DCZd4kiAxD6SRTFbGVNieUUI9uqlH/TKs kJETS7CA/7SwAQFU5bIb7N7Cb1Kx4oOnf+BwzWnXjV37cj0c4jYjgPQBShQ/WtuEaFLB rTNB/rHa18fWt3i3SlzKexxNktY7/H3vWxM0W4hAspYz2dsbe5hkLB+rBXRk2An7SJnF tl0fGTVJQ7fwvvGRbnWol5IGabAnaKrvDSwZ11X97kH1b399piLitpuOJ/yql4iPI347 nVjBYN1dBB+qpe/dMWN6/Y8pjV82xPn3PRlOVkWA3VkLXIFph5A2vh15tVHgAvJwGVOV m1mA== X-Gm-Message-State: AOAM531oqTcwCXLh0MZbqBxlkXV3FIGFOeNPRT2MhslBCnwJW+1DbWpW HEyKxX5RJLoaf9DxSfm8agG56roG0aMDKw== X-Google-Smtp-Source: ABdhPJzgDAPmr4/NQkUgUDSfIOeHT8dLwbQU/XbKEBsGvMvutXGTX4Bfvay437jQ7o2Y5aVzqjd+fg== X-Received: by 2002:ad4:5643:: with SMTP id bl3mr10198290qvb.54.1633108332577; Fri, 01 Oct 2021 10:12:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 22/41] target/arm: Use cpu_loop_exit_segv for mte tag lookup Date: Fri, 1 Oct 2021 13:11:32 -0400 Message-Id: <20211001171151.1739472-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2a; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109688224100001 Content-Type: text/plain; charset="utf-8" Use the new os interface for raising the exception, rather than calling arm_cpu_tlb_fill directly. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/mte_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 724175210b..1500a498b0 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -84,10 +84,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int= ptr_mmu_idx, uintptr_t index; =20 if (!(flags & (ptr_access =3D=3D MMU_DATA_STORE ? PAGE_WRITE_ORG : PAG= E_READ))) { - /* SIGSEGV */ - arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, - ptr_mmu_idx, false, ra); - g_assert_not_reached(); + cpu_loop_exit_segv(env_cpu(env), ptr, ptr_access, + !(flags & PAGE_VALID), ra); } =20 /* Require both MAP_ANON and PROT_MTE for the page. */ --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633110680861972.4749329581488; Fri, 1 Oct 2021 10:51:20 -0700 (PDT) Received: from localhost ([::1]:55468 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMgp-0008Mu-NZ for importer@patchew.org; Fri, 01 Oct 2021 13:51:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54908) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM53-000524-VG for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:17 -0400 Received: from mail-qt1-x834.google.com ([2607:f8b0:4864:20::834]:36495) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM50-00059w-7j for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:17 -0400 Received: by mail-qt1-x834.google.com with SMTP id l13so9640208qtv.3 for ; Fri, 01 Oct 2021 10:12:13 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MEdAv6cRA9BBhR4lgddgtqkvjCOWQwmTeigzGsiVe00=; b=c2/PCTGmxFAl0TLyzDRB7+HZIZysaWYlbZ+OuKovOl7lPsrCRxIrsz1Vac6AGvWSe1 KI3bwazbDzCYiaYVtE6le0ouZUeZkJ/WT4y3HTcS4sTsIqJEsEBjLkMpa5UKt4ewUQib 0plFN5JOozU5lzzMoTQ2+RBSAz2OFxaQoNU+rQxvaAhOM+j7sQws6UfdHOyiciKwcU/J ux3a9V8Y2sobCRr3e+XG7v4CWbKQGI6oJxRAqL8q65TdAzvp2MA7x1kviVJYSDBDlYWO dwWZ4LnwFE+v2F7aiLGh8sguiNBW5YWfidvdtKZKwxsgQXvqoCN81iFDHVzyjtXwZ6MZ fdjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MEdAv6cRA9BBhR4lgddgtqkvjCOWQwmTeigzGsiVe00=; b=RzEqLCDXVNsyR1Nay3skI4qdZ0Wbq+KXdJqaLnv3xRfGrKyYBsrqhAs1oMr1LrOwdF V2gYUTIGgwxYLTomfpiXydYxBPd5hWPw+D+tc2Iw3qknt6urXQ77Z8z4Gd0GqHIAjCQO S0zeamA1hUr7xsddgJewEnWD4Q1/lCJU0jV4iFUc815zjwY2ybhEPHycaIHmxmF1eH2j WfsuH5nvuVEsnJXimc7F9X4Jv+V00Ku+T7zH7nKdjwrlmw05jVQ3zf7ShrCL1GJyMGmg 6IT+f76RZL3YM9EmwvffxFI40f2Ks64sQilHBX1yrtN0xsLLu16cuCMQXJZno8ByX41o YRGw== X-Gm-Message-State: AOAM531KQyB3BxauSF08VU63Zqd506wkQXYSGiLyURzxXor7ggXy2Fsr yPmsJuKmmqUBkbAXHw3auyH1xRUBdKiuyQ== X-Google-Smtp-Source: ABdhPJxNpruzr96ElwLGZAdAKitmgpXuG+7zQ4BXiqapMUIIqyCIgRH6+QjyBg21sWdjdDEg2I2MVw== X-Received: by 2002:a05:622a:181d:: with SMTP id t29mr14136633qtc.337.1633108333357; Fri, 01 Oct 2021 10:12:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 23/41] target/arm: Implement arm_cpu_record_sigsegv Date: Fri, 1 Oct 2021 13:11:33 -0400 Message-Id: <20211001171151.1739472-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633110682164100001 Content-Type: text/plain; charset="utf-8" Because of the complexity of setting ESR, continue to use arm_deliver_fault. This means we cannot remove the code within cpu_loop that decodes EXCP_DATA_ABORT and EXCP_PREFETCH_ABORT. But using the new hook means that we don't have to do the page_get_flags check manually, and we'll be able to restrict the tlb_fill hook to sysemu later. Signed-off-by: Richard Henderson --- target/arm/internals.h | 6 ++++++ target/arm/cpu.c | 6 ++++-- target/arm/cpu_tcg.c | 6 ++++-- target/arm/tlb_helper.c | 36 +++++++++++++++++++----------------- 4 files changed, 33 insertions(+), 21 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 9fbb364968..984c84d27e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -544,9 +544,15 @@ static inline bool arm_extabort_type(MemTxResult resul= t) return result !=3D MEMTX_DECODE_ERROR; } =20 +#ifdef CONFIG_USER_ONLY +void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif =20 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 641a8c2d3d..7a18a58ca0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2031,10 +2031,12 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D= { static const struct TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, - .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, =20 -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D arm_cpu_record_sigsegv, +#else + .tlb_fill =3D arm_cpu_tlb_fill, .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .do_interrupt =3D arm_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0d5adccf1a..7b3bea2fbb 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -898,10 +898,12 @@ static void pxa270c5_initfn(Object *obj) static const struct TCGCPUOps arm_v7m_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, - .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, =20 -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D arm_cpu_record_sigsegv, +#else + .tlb_fill =3D arm_cpu_tlb_fill, .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, .do_interrupt =3D arm_v7m_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 3107f9823e..dc5860180f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -147,28 +147,12 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } =20 -#endif /* !defined(CONFIG_USER_ONLY) */ - bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { ARMCPU *cpu =3D ARM_CPU(cs); ARMMMUFaultInfo fi =3D {}; - -#ifdef CONFIG_USER_ONLY - int flags =3D page_get_flags(useronly_clean_ptr(address)); - if (flags & PAGE_VALID) { - fi.type =3D ARMFault_Permission; - } else { - fi.type =3D ARMFault_Translation; - } - fi.level =3D 3; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); -#else hwaddr phys_addr; target_ulong page_size; int prot, ret; @@ -210,5 +194,23 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, cpu_restore_state(cs, retaddr, true); arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); } -#endif } +#else +void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) +{ + ARMMMUFaultInfo fi =3D { + .type =3D maperr ? ARMFault_Translation : ARMFault_Permission, + .level =3D 3, + }; + ARMCPU *cpu =3D ARM_CPU(cs); + + /* + * We report both ESR and FAR to signal handlers. + * For now, it's easiest to deliver the fault normally. + */ + cpu_restore_state(cs, ra, true); + arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); +} +#endif /* !defined(CONFIG_USER_ONLY) */ --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109851960563.7788381384604; Fri, 1 Oct 2021 10:37:31 -0700 (PDT) Received: from localhost ([::1]:56662 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMTS-0006Oi-Po for importer@patchew.org; Fri, 01 Oct 2021 13:37:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54902) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM53-00051R-Lb for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:17 -0400 Received: from mail-qt1-x834.google.com ([2607:f8b0:4864:20::834]:40673) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM51-0005Bm-6m for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:17 -0400 Received: by mail-qt1-x834.google.com with SMTP id b16so9624091qtt.7 for ; Fri, 01 Oct 2021 10:12:14 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eeVnsYGPYAHebpgHrC5W3wwVNSfsNcsD0o1AtI7xBGA=; b=CLcl0fmUQ3wSGr/VMjEUqbNgm26UVqUT8ER6rVWFVVONZDp/1TePOgg8Qnp1iIogTE hXbiRiMOxpoHS03O/xsf8jNNU1hMchvl+pCTWqs//+sjW0g9RiDCUbmMTG4kcxxGS7zl gCEHXBKoxWjdkYPXJa0oPTCjgTDe9OtflqzDZ9zc6gXzzXLy1VmwFOAty4ooQxSjaurk hbVk4NQBgruJazkYotkopLp0qupec1u+SeGWxGIenI86YiWM8Z2hicJVlenXaR4jowhN ZhEVSd7LLIHhZs7+w3hITpWi2Em4eEVTAJY3f62bgJ3w3Ya3D9nMNtZdQlDv2e6VWRMX O7hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eeVnsYGPYAHebpgHrC5W3wwVNSfsNcsD0o1AtI7xBGA=; b=HO0XJyJTBKBp7X/36xI6lKE9tYFvVhVSSo4iqm3HhJNlFWF1xnaIZLVfG48Yye82lr csW9fmt/+bLYor7mZR9IP+vtPrmJDWLrbl0qpvfBT6oy9sooon+/a06sishdC8qqeJua AKnc1jiIOUgkQFSVrCT/04uVLrp/75p3MqPw33FIQL4YCOdN5iy3WZwk2rCAR1SftVZB YIDPOuFMJ0SN58F38iJJH7AH74vz4NHXGB9RugjR0rTMqQxdvFpf1n80qZE95R7uqtuC o4o3Vh8u41BCM5AvFur7W1ns3XGUmj5OA1NEH2FC60y95vqtLZ0F5cymSXagU72eNr9P Fc4Q== X-Gm-Message-State: AOAM532REFifN5o/0VMsHzPYcqaK6p+4hQh6QaSUe1cKGLlc0y6tyEZy F9bQdWk608ngdFoWV9OC8kj4yEtfwwn9aA== X-Google-Smtp-Source: ABdhPJwGLXHt1xfs1JsJTGiiMdF2Mzt0itQF6cjJakNWDr0YqMRy1t9DOo9bUiUE985EqnFzhF9m8w== X-Received: by 2002:ac8:764a:: with SMTP id i10mr13887145qtr.414.1633108334250; Fri, 01 Oct 2021 10:12:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 24/41] target/cris: Make cris_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:34 -0400 Message-Id: <20211001171151.1739472-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , alex.bennee@linaro.org, laurent@vivier.eu, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109853932100001 The fallback code in raise_sigsegv is sufficient for cris-linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. This makes all of the code in helper.c sysemu only, so remove the ifdefs and move the file to cris_softmmu_ss. Cc: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/cris/cpu.h | 8 ++++---- linux-user/cris/cpu_loop.c | 10 ---------- target/cris/cpu.c | 4 ++-- target/cris/helper.c | 18 ------------------ target/cris/meson.build | 7 +++++-- 5 files changed, 11 insertions(+), 36 deletions(-) diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 6603565f83..b445b194ea 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -189,6 +189,10 @@ extern const VMStateDescription vmstate_cris_cpu; void cris_cpu_do_interrupt(CPUState *cpu); void crisv10_cpu_do_interrupt(CPUState *cpu); bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req); + +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif =20 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); @@ -251,10 +255,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bo= ol ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } =20 -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0 diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index b9085619c4..0d5d268609 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -37,16 +37,6 @@ void cpu_loop(CPUCRISState *env) process_queued_cpu_work(cs); =20 switch (trapnr) { - case 0xaa: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->pregs[PR_EDA]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index c2e7483f5b..ed6c781342 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -205,9 +205,9 @@ static const struct SysemuCPUOps cris_sysemu_ops =3D { =20 static const struct TCGCPUOps crisv10_tcg_ops =3D { .initialize =3D cris_initialize_crisv10_tcg, - .tlb_fill =3D cris_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D cris_cpu_tlb_fill, .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .do_interrupt =3D crisv10_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -215,9 +215,9 @@ static const struct TCGCPUOps crisv10_tcg_ops =3D { =20 static const struct TCGCPUOps crisv32_tcg_ops =3D { .initialize =3D cris_initialize_tcg, - .tlb_fill =3D cris_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D cris_cpu_tlb_fill, .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .do_interrupt =3D cris_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/helper.c b/target/cris/helper.c index 36926faf32..a0d6ecdcd3 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -39,22 +39,6 @@ #define D_LOG(...) do { } while (0) #endif =20 -#if defined(CONFIG_USER_ONLY) - -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - CRISCPU *cpu =3D CRIS_CPU(cs); - - cs->exception_index =3D 0xaa; - cpu->env.pregs[PR_EDA] =3D address; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - - static void cris_shift_ccs(CPUCRISState *env) { uint32_t ccs; @@ -304,5 +288,3 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 return ret; } - -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/meson.build b/target/cris/meson.build index 67c3793c85..c1e326d950 100644 --- a/target/cris/meson.build +++ b/target/cris/meson.build @@ -2,13 +2,16 @@ cris_ss =3D ss.source_set() cris_ss.add(files( 'cpu.c', 'gdbstub.c', - 'helper.c', 'op_helper.c', 'translate.c', )) =20 cris_softmmu_ss =3D ss.source_set() -cris_softmmu_ss.add(files('mmu.c', 'machine.c')) +cris_softmmu_ss.add(files( + 'helper.c', + 'machine.c', + 'mmu.c', +)) =20 target_arch +=3D {'cris': cris_ss} target_softmmu_arch +=3D {'cris': cris_softmmu_ss} --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kQq48uinsO7YylDhnHpQEq7bEF7K0DH0ooQKeZ28gIs=; b=P7sgxRwKcGnzx8/NU7x2zpkmBdAQ8+FhiZOPALlK4fdZ3iS2eRQnNxSm7h3/+iZ6PP rsXgcY4KYj/1gPMwtis9OrynI7ELmTk6xY1TJyUVeU2/AVmmcm6fyNX7oq5mJht55q+C yLUXpzqlGPj+/gV71fg7uw2+KmlfbAeZ5Qm8vcdchVHrK0pHxUAXk+HfjGXBTOkPlFWu U3W2Cuzhc1ouEDH3iRltjWIfuWe4W4DH25IoVMFL1lMG93fG+MkWbSm46l597fLtPdaS yLDojQdfjhi8/ORN6p7EHKSMWMpKaTm6d8x6d7EYBdnPMeoQvrbBmZ8NnNDbQz3BZ4lV Ce2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kQq48uinsO7YylDhnHpQEq7bEF7K0DH0ooQKeZ28gIs=; b=h5Mms0Iitp3b7tIJoDhdN2nftipZOdhZUQwBboghdR7AZjlFfHIUBCYBeuFINm5zRp 4tVTnTvv78KOWCXfidcgep6BGAUsX3yQOFquY0+pfYvGXQzPCSz4A9nqyFBZdwv6h4wR S3r+yM02r2zW/NBWcMMYhqPF1ymxXvazKoV9KnonBASWFpwdNAl3vW5KMU6ZwqGr6iDy S+XJ/FF0cR94cyZhQJSKANhQEGpe9UMg9Atx0vqULWwcz8/jkMeiEELxvhkekRvBclFm xKfkWLV18QH6APRBu9TDBZRL1WgvwUTu3B/SxziPjOmOMftOVPikv9RytUczRkvvvRrJ Adjg== X-Gm-Message-State: AOAM533qjE5Gjs+Q59CcjreHYm1P0TnLT8qfqZJpvjvE76PRwPiMzkdH zZrtdflspI+MWepWFt75JUtlBFOaGEKfCQ== X-Google-Smtp-Source: ABdhPJy4xt/rQKfzyiADxhIrKaVEkmpv9cLo5f/xdN/x4Mj2KNy1xOKv7ETRRiYDbcqiZ3gzrRmfJg== X-Received: by 2002:a37:41ca:: with SMTP id o193mr10861873qka.187.1633108335112; Fri, 01 Oct 2021 10:12:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 25/41] target/hexagon: Remove hexagon_cpu_tlb_fill Date: Fri, 1 Oct 2021 13:11:35 -0400 Message-Id: <20211001171151.1739472-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72e; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Taylor Simpson , alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633108977962100001 Content-Type: text/plain; charset="utf-8" The fallback code in raise_sigsegv is sufficient for hexagon. Remove the code from cpu_loop that raises SIGSEGV. Cc: Taylor Simpson Signed-off-by: Richard Henderson Reviewed-by: Taylor Simpson --- linux-user/hexagon/cpu_loop.c | 24 +----------------------- target/hexagon/cpu.c | 23 ----------------------- 2 files changed, 1 insertion(+), 46 deletions(-) diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index bee2a9e4ea..6b24cbaba9 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -28,8 +28,7 @@ void cpu_loop(CPUHexagonState *env) { CPUState *cs =3D env_cpu(env); - int trapnr, signum, sigcode; - target_ulong sigaddr; + int trapnr; target_ulong syscallnum; target_ulong ret; =20 @@ -39,10 +38,6 @@ void cpu_loop(CPUHexagonState *env) cpu_exec_end(cs); process_queued_cpu_work(cs); =20 - signum =3D 0; - sigcode =3D 0; - sigaddr =3D 0; - switch (trapnr) { case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ @@ -65,12 +60,6 @@ void cpu_loop(CPUHexagonState *env) env->gpr[0] =3D ret; } break; - case HEX_EXCP_FETCH_NO_UPAGE: - case HEX_EXCP_PRIV_NO_UREAD: - case HEX_EXCP_PRIV_NO_UWRITE: - signum =3D TARGET_SIGSEGV; - sigcode =3D TARGET_SEGV_MAPERR; - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); break; @@ -79,17 +68,6 @@ void cpu_loop(CPUHexagonState *env) trapnr); exit(EXIT_FAILURE); } - - if (signum) { - target_siginfo_t info =3D { - .si_signo =3D signum, - .si_errno =3D 0, - .si_code =3D sigcode, - ._sifields._sigfault._addr =3D sigaddr - }; - queue_signal(env, info.si_signo, QEMU_SI_KILL, &info); - } - process_pending_signals(env); } } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 3338365c16..160a46a3d5 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -245,34 +245,11 @@ static void hexagon_cpu_init(Object *obj) qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_prope= rty); } =20 -static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ -#ifdef CONFIG_USER_ONLY - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index =3D HEX_EXCP_FETCH_NO_UPAGE; - break; - case MMU_DATA_LOAD: - cs->exception_index =3D HEX_EXCP_PRIV_NO_UREAD; - break; - case MMU_DATA_STORE: - cs->exception_index =3D HEX_EXCP_PRIV_NO_UWRITE; - break; - } - cpu_loop_exit_restore(cs, retaddr); -#else -#error System mode not implemented for Hexagon -#endif -} - #include "hw/core/tcg-cpu-ops.h" =20 static const struct TCGCPUOps hexagon_tcg_ops =3D { .initialize =3D hexagon_translate_init, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, - .tlb_fill =3D hexagon_tlb_fill, }; =20 static void hexagon_cpu_class_init(ObjectClass *c, void *data) --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633110241328172.56511292399694; Fri, 1 Oct 2021 10:44:01 -0700 (PDT) Received: from localhost ([::1]:37498 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMZk-0004Nd-6K for importer@patchew.org; Fri, 01 Oct 2021 13:44:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54926) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM54-00054R-RU for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:20 -0400 Received: from mail-qk1-x72e.google.com ([2607:f8b0:4864:20::72e]:42629) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM52-0005E4-S4 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:18 -0400 Received: by mail-qk1-x72e.google.com with SMTP id x12so9811156qkf.9 for ; Fri, 01 Oct 2021 10:12:16 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jdc9xUljuMqC9v+WfiNACe7k1BrlAm8+Ia/kMx84Cy4=; b=vVMy3Qv2zCl393tPfHiMTEvfTN325WQlNvLAtnHJ7Nfe0QPAVPQ18wIFJBgzChN65n VeNmMeyOMHBDQ3KvRsXW7F5KPnRLC8KPNl9+FTSV+AY/WmHsrrRS/t9aeLdWuopuFqEw Kq+FXiZ5uOwgIPYzzNxiIjIcw20e3q9vQvuWzUap+F71FjpP2jVAQlwS5MAyhF5aICg7 9onyuWKKi7/8nvOGXUQEPJ9JzRiG23mMnqWcA8g3utoAAZ7NUukZMbYELmcuojqMcxoK aBJTc9+E5WypqCUegxq9jWNODTPjP5cP1fc2s8tcRnHycyWaZP3ke1kZVzUKsGQIgtJS ZSfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jdc9xUljuMqC9v+WfiNACe7k1BrlAm8+Ia/kMx84Cy4=; b=nZDw/fXV748YqF0Nv6YYvy2m8MC80+uy0+26O6BPa1pVCvcls70JNMzqbsBzbO93vs JmHtCpg3kLg2ERZcfp26rrqlzDB8H4sv5JoQpRG6Wk+MEXZjthmnbCzQHLAvfpyi6ncV o/j0MQAKwjJ3IhDOfVssI5pVqpFqwZfI01aPog00vUHXLZ6fAz8OwIwzc4xQB3Tq57OI 2JC7z6WEmXCVGKsMb3iXsQmXenzrprRW2UfyrLkkMRmLUxqzeQsqaJL2agJLfKSxsWTw Da+31innWvP0YAaYCwTwllPfL8HbHlDqlzyzRK8iF3/jcc4UvBBDopjzzuiPt7VVphJo lw2g== X-Gm-Message-State: AOAM530McqEhHegALN3sLL/jHjr4DjUuBW+WIwMbDxgf+6NzsuETUOn9 +v1rftUIcPBIMynx4g2OsfBZCrGFcn6ZxA== X-Google-Smtp-Source: ABdhPJzBe8yt0DLfimhiS9hq9Gz9G90ZJiQOIEmJksmHjERKsmwfew3ntjr/kQ7RotKkiTPz0wDo/g== X-Received: by 2002:a37:64ce:: with SMTP id y197mr10665772qkb.399.1633108335904; Fri, 01 Oct 2021 10:12:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 26/41] target/hppa: Make hppa_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:36 -0400 Message-Id: <20211001171151.1739472-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72e; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633110241836100001 Content-Type: text/plain; charset="utf-8" The fallback code in raise_sigsegv is sufficient for hppa-linux-user. Remove the code from cpu_loop that raised SIGSEGV. This makes all of the code in mem_helper.c sysemu only, so remove the ifdefs and move the file to hppa_softmmu_ss. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 +- linux-user/hppa/cpu_loop.c | 16 ---------------- target/hppa/cpu.c | 2 +- target/hppa/mem_helper.c | 15 --------------- target/hppa/meson.build | 6 ++++-- 5 files changed, 6 insertions(+), 35 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d3cb7a279f..294fd7297f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -323,10 +323,10 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vad= dr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); +#ifndef CONFIG_USER_ONLY bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 81607a9b27..e0a62deeb9 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -144,22 +144,6 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f =3D env->gr[31]; env->iaoq_b =3D env->gr[31] + 4; break; - case EXCP_ITLB_MISS: - case EXCP_DTLB_MISS: - case EXCP_NA_ITLB_MISS: - case EXCP_NA_DTLB_MISS: - case EXCP_IMP: - case EXCP_DMP: - case EXCP_DMB: - case EXCP_PAGE_REF: - case EXCP_DMAR: - case EXCP_DMPI: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr =3D env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 89cba9d7a2..23eb254228 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -145,9 +145,9 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { static const struct TCGCPUOps hppa_tcg_ops =3D { .initialize =3D hppa_translate_init, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, - .tlb_fill =3D hppa_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D hppa_cpu_tlb_fill, .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, .do_interrupt =3D hppa_cpu_do_interrupt, .do_unaligned_access =3D hppa_cpu_do_unaligned_access, diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index afc5b56c3e..bf07445cd1 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -24,20 +24,6 @@ #include "hw/core/cpu.h" #include "trace.h" =20 -#ifdef CONFIG_USER_ONLY -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - HPPACPU *cpu =3D HPPA_CPU(cs); - - /* ??? Test between data page fault and data memory protection trap, - which would affect si_code. */ - cs->exception_index =3D EXCP_DMP; - cpu->env.cr[CR_IOR] =3D address; - cpu_loop_exit_restore(cs, retaddr); -} -#else static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) { int i; @@ -392,4 +378,3 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulon= g vaddr) hppa_tlb_entry *ent =3D hppa_find_tlb(env, vaddr); return ent ? ent->ar_type : -1; } -#endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/meson.build b/target/hppa/meson.build index 8a7ff82efc..021e42a2d0 100644 --- a/target/hppa/meson.build +++ b/target/hppa/meson.build @@ -7,13 +7,15 @@ hppa_ss.add(files( 'gdbstub.c', 'helper.c', 'int_helper.c', - 'mem_helper.c', 'op_helper.c', 'translate.c', )) =20 hppa_softmmu_ss =3D ss.source_set() -hppa_softmmu_ss.add(files('machine.c')) +hppa_softmmu_ss.add(files( + 'machine.c', + 'mem_helper.c', +)) =20 target_arch +=3D {'hppa': hppa_ss} target_softmmu_arch +=3D {'hppa': hppa_softmmu_ss} --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109104614708.2902280219103; Fri, 1 Oct 2021 10:25:04 -0700 (PDT) Received: from localhost ([::1]:50976 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMHP-0000Af-Iv for importer@patchew.org; Fri, 01 Oct 2021 13:25:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM55-00054S-I2 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:20 -0400 Received: from mail-qk1-x733.google.com ([2607:f8b0:4864:20::733]:41703) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM53-0005F8-UO for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:19 -0400 Received: by mail-qk1-x733.google.com with SMTP id m7so9817756qke.8 for ; Fri, 01 Oct 2021 10:12:17 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bcv7+vrfVWDaxhREKP7oW3QycojCjuZf0xWMtNuZYi8=; b=cRH7O3PCIdNSdTUWPql16AGN37Jk7cpBm+xRH2InaSSDBRikY8r5epoUkoX/jAbyFA bVKITLVDsY0yELRFvIrjus2OjzFzp2YktjznTxOjCRY6j0WmqYz4ZSGHVivcgBzVK0Vs Y9iicmMfowAM1sUOfeMBrLY2pO7WKKbzQUyEDgYC46VmjUbU/rKar6jNClD+ObjmVKQE p2EuW2cVOE+Tu40NIZ8m8PoeN5qb/srLPDNTtzHZp8RYX/V4IFsSVN4PjJhPZlYJ2FW1 38M2M0pvFo6wt6TvUskAmHunRQyZoDN2SuK2qVGk5ngEe4HlULeS/zbYv15TR9Kvhri6 RvNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bcv7+vrfVWDaxhREKP7oW3QycojCjuZf0xWMtNuZYi8=; b=WcVvrX2hOD+jEg5C3NGk0Xxfd3mD3J0DR1OEQvvug0z1zv/82WKtybd0plQx1NZaqV AEUHHHPvhdYs1GM9X2OMclHvA6nnmqqUdDn55jyLrlFO50J1RIyEjqtaYVmC5uy5tjKB OIXGWYqeQooFziFRLN4GMhi2PONwwivnZfJ0F2HBLhgOs1sRQjELAme4+tp9OPECLLeg V03vvdQ0vB11lb18jgSCUwNqnYmHcrXy2HF2wlXcW5045oiCeJnDbFnzcRJ3/jz+wePD rlXAh1kprzPxXxS98b7V2tzP4Pw3GW/tVKugvxxTJQqxNjETI7LCtN1WBk17PaxpLTBQ zc8Q== X-Gm-Message-State: AOAM530IYwbQd8kWMYYeBHRD6+gY7tSaGsINVdd5F4nFngbokCRlijH7 feONhdlTP8lVnZDOBvTYR/XJcjg+ISak5A== X-Google-Smtp-Source: ABdhPJy7Ffd9v1PjMdxP3u+dUqAbZjytsdKCmZjOQtrf4ZqlEKev0+8f8n0fZqkrgN/kptxo9ptcqQ== X-Received: by 2002:a37:746:: with SMTP id 67mr10466779qkh.465.1633108337064; Fri, 01 Oct 2021 10:12:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 27/41] target/i386: Implement x86_cpu_record_sigsegv Date: Fri, 1 Oct 2021 13:11:37 -0400 Message-Id: <20211001171151.1739472-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::733; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x733.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109105819100003 Record cr2, error_code, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. Use the maperr parameter to properly set PG_ERROR_P_MASK. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 6 ++++++ target/i386/tcg/tcg-cpu.c | 3 ++- target/i386/tcg/user/excp_helper.c | 23 +++++++++++++++++------ 3 files changed, 25 insertions(+), 7 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 60ca09e95e..0a4401e917 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -43,9 +43,15 @@ bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif =20 /* helper.c */ +#ifdef CONFIG_USER_ONLY +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif =20 void breakpoint_handler(CPUState *cs); =20 diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 3ecfae34cb..6fdfdf9598 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -72,10 +72,11 @@ static const struct TCGCPUOps x86_tcg_ops =3D { .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .cpu_exec_enter =3D x86_cpu_exec_enter, .cpu_exec_exit =3D x86_cpu_exec_exit, - .tlb_fill =3D x86_cpu_tlb_fill, #ifdef CONFIG_USER_ONLY .fake_user_interrupt =3D x86_cpu_do_interrupt, + .record_sigsegv =3D x86_cpu_record_sigsegv, #else + .tlb_fill =3D x86_cpu_tlb_fill, .do_interrupt =3D x86_cpu_do_interrupt, .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, .debug_excp_handler =3D breakpoint_handler, diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp= _helper.c index a89b5228fd..cd507e2a1b 100644 --- a/target/i386/tcg/user/excp_helper.c +++ b/target/i386/tcg/user/excp_helper.c @@ -22,18 +22,29 @@ #include "exec/exec-all.h" #include "tcg/helper-tcg.h" =20 -bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; =20 + /* + * The error_code that hw reports as part of the exception frame + * is copied to linux sigcontext.err. The exception_index is + * copied to linux sigcontext.trapno. Short of inventing a new + * place to store the trapno, we cannot let our caller raise the + * signal and set exception_index to EXCP_INTERRUPT. + */ env->cr[2] =3D addr; - env->error_code =3D (access_type =3D=3D MMU_DATA_STORE) << PG_ERROR_W_= BIT; - env->error_code |=3D PG_ERROR_U_MASK; + env->error_code =3D ((access_type =3D=3D MMU_DATA_STORE) << PG_ERROR_W= _BIT) + | (maperr ? 0 : PG_ERROR_P_MASK) + | PG_ERROR_U_MASK; cs->exception_index =3D EXCP0E_PAGE; + + /* Disable do_interrupt_user. */ env->exception_is_int =3D 0; env->exception_next_eip =3D -1; - cpu_loop_exit_restore(cs, retaddr); + + cpu_loop_exit_restore(cs, ra); } --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109299750636.3202230093553; Fri, 1 Oct 2021 10:28:19 -0700 (PDT) Received: from localhost ([::1]:59642 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMKY-00062j-Gb for importer@patchew.org; Fri, 01 Oct 2021 13:28:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54982) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM5A-00057R-Jp for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:25 -0400 Received: from mail-qv1-xf2e.google.com ([2607:f8b0:4864:20::f2e]:37663) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM55-0005G4-91 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:24 -0400 Received: by mail-qv1-xf2e.google.com with SMTP id o13so253958qvm.4 for ; Fri, 01 Oct 2021 10:12:18 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G1HWedffqhycyxP8d2WDLOk4nPDaQm4JAuhJ0f230MI=; b=vQnMVrMdTud4hPh9849gToubme1/ecnkXnebmDninxdpRxb81tWN5nG/hXuOBHhpSr z1+ceETpmivgbRdOHyy9nmNf0/DZbRQqN4XpZ56rw5YOj9qvhvZZ11WaWrMGKsKaarIq Ptv8qMBJFYIrt9lk8xuYocf/IlIb9Vhtyxo3HjH6oKOdTMNFx14FGxGn1jkCpqYlMHU4 25VVQ4c57kxvUmYupyKSvzcRBkQVQpjvPlZydpojt2xe3ZXaQllwItw6wtKCrK6lgd/z GZK6Vo98/JITUE9MxOGOAEItMsJHpRNe3qApxtxSm064QWZGpy/7PaWE68dm3yCcNwne sdrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G1HWedffqhycyxP8d2WDLOk4nPDaQm4JAuhJ0f230MI=; b=QD9TlLUfduTeEZrP/EwsSQ+zORsqlgq1nppcNlXEOynzmWlJxmtzwwsI9r9mQjtHD1 NScmXNtQjZxcHbDgiwt34PsIjuuDkCfr2+tojNj8xM6Uhx2UNLHoAUR1N2qjuXBg0TX0 c2fyjrdCicFJjBsEkioo7zWj8pdDvHluGn/k5mZqeTcs9auwMyvZT3a3NvuCpPKw+LbV uFm2dxyVOxkn2pgL7ItL9qnkq8wttcfr/hkLXRiFJzwBwsQyjm+lkSNQZ2dVf75rUgv2 n+UmFgQbzJuT2Q14fr99nrUDth0JxG+34DgwIxLeHHu4X3+KRU3Igsy6YbjNo96VT+rc 1ynw== X-Gm-Message-State: AOAM531lQjuUpU6uFAKp1nawyHxc3I+stjXabtL+2Iuhobtx73AcaqUf SD1Jc7Jj33cm+NYUqmr0MTH7TvQWrk7huw== X-Google-Smtp-Source: ABdhPJxHU8fwlYKH7zeMVzfZQziyhlvCotkqVskyhdpdXL02vsdWYSFCcRgw3XFigB1IscIV7Ahevw== X-Received: by 2002:a0c:b2c5:: with SMTP id d5mr10179990qvf.65.1633108338023; Fri, 01 Oct 2021 10:12:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 28/41] target/m68k: Make m68k_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:38 -0400 Message-Id: <20211001171151.1739472-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109301087100001 Content-Type: text/plain; charset="utf-8" The fallback code in raise_sigsegv is sufficient for m68k-linux-user. Remove the code from cpu_loop that handled EXCP_ACCESS. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- linux-user/m68k/cpu_loop.c | 10 ---------- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 6 +----- 3 files changed, 2 insertions(+), 16 deletions(-) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index ebf32be78f..790bd558c3 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -90,16 +90,6 @@ void cpu_loop(CPUM68KState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; - case EXCP_ACCESS: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->mmu.ar; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_DEBUG: info.si_signo =3D TARGET_SIGTRAP; info.si_errno =3D 0; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 66d22d1189..c7aeb7da9c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -515,9 +515,9 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { =20 static const struct TCGCPUOps m68k_tcg_ops =3D { .initialize =3D m68k_tcg_init, - .tlb_fill =3D m68k_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D m68k_cpu_tlb_fill, .cpu_exec_interrupt =3D m68k_cpu_exec_interrupt, .do_interrupt =3D m68k_cpu_do_interrupt, .do_transaction_failed =3D m68k_cpu_transaction_failed, diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 137a3e1a3d..5728e48585 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -978,16 +978,12 @@ void m68k_set_irq_level(M68kCPU *cpu, int level, uint= 8_t vector) } } =20 -#endif - bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType qemu_access_type, int mmu_idx, bool probe, uintptr_t retaddr) { M68kCPU *cpu =3D M68K_CPU(cs); CPUM68KState *env =3D &cpu->env; - -#ifndef CONFIG_USER_ONLY hwaddr physical; int prot; int access_type; @@ -1051,12 +1047,12 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, if (!(access_type & ACCESS_STORE)) { env->mmu.ssw |=3D M68K_RW_040; } -#endif =20 cs->exception_index =3D EXCP_ACCESS; env->mmu.ar =3D address; cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ =20 uint32_t HELPER(bitrev)(uint32_t x) { --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109520174564.5321854685545; Fri, 1 Oct 2021 10:32:00 -0700 (PDT) Received: from localhost ([::1]:40082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMO7-0003aD-3H for importer@patchew.org; Fri, 01 Oct 2021 13:31:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55024) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM5C-00059E-1r for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:26 -0400 Received: from mail-qv1-xf2f.google.com ([2607:f8b0:4864:20::f2f]:39764) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM55-0005HN-O3 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:25 -0400 Received: by mail-qv1-xf2f.google.com with SMTP id a14so5983865qvb.6 for ; Fri, 01 Oct 2021 10:12:19 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XFe/Vw3cr/4hcwv1jUnUaBVa+r7ZoPXYiTXFgPNQ9tk=; b=hN0VzbmAKpG9vNs3ycl/GIdoifB2BWVlyH5jMqcd7zECz5NFyhnscNEjBA8hjZ30af 3LvFg85gHF29/3V9YtGR3X5JQTO7AbUb0tKPiJqUXxVcXZBagS3GAkBI3FcVgp5c7e5L nnb0lQBbzrzHiircP0mKtgROlT1M8Zic2r78H86QdOM7pf4SgYJEtW2ASnu6zKQhVFU0 457umLNgZXsbmc2DxMa+fp18gKgxnZdXlzFFetWYU7FLRpLeJ7IsFpsuHCtq9zc5lY6a hTnOlt370bWmoP2CGXnLINK5/6sLgBYiAbehHkXHoIIKXLPJX7aGLvPwSA9MFiKtpFOW vJwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XFe/Vw3cr/4hcwv1jUnUaBVa+r7ZoPXYiTXFgPNQ9tk=; b=pfgvWONjdrsqoJ9nNhddmGxfmAOuVsvJX8UXX6Y+C7BuCqTgrlYRHtvICTp8KYVEtU Di4/odnoAX6Rl4CbVw93+k+hmmMVSHOi+dZ6Ya2sPBtgGlfJd8ZLTO/sRXlpf2D36FrE dBkfMWq+6gAgji0hMKmYVorCHmCCzvPrQPkX+K/vpPllRCvcOG6ANwCPLYR4zFax5gJ0 xI08qflr0rxphj5MIA8/dl0hZNCTsKd8zpSO71Tqtvj8kcL8CtsU3afNeIIQaylq1Hd0 nwRsKCJK9qTxBrhZaTXpq47Dsh5qgntDDXfm+wxTsU3ME3R48jW1qwnd9Im3WmlcHlpJ d9MQ== X-Gm-Message-State: AOAM5304xJPP5AoiiUy7yuTiL+UhQMeOPy2sggj47Tmf9H1fRfX1jpla CT/odWU+SaNFksM3ndssU54+KplEJUbp9A== X-Google-Smtp-Source: ABdhPJw5M5zEKytm/f4Ln0ysd2xqTblg3pVCcmMO+QXmL1evcsbuDLOzvrF1KRDemuP9APHpbLiG2Q== X-Received: by 2002:a05:6214:987:: with SMTP id dt7mr11395223qvb.65.1633108338759; Fri, 01 Oct 2021 10:12:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 29/41] target/microblaze: Make mb_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:39 -0400 Message-Id: <20211001171151.1739472-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2f; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109521921100001 Content-Type: text/plain; charset="utf-8" The fallback code in raise_sigsegv is sufficient for mb linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. Cc: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 8 ++++---- linux-user/microblaze/cpu_loop.c | 10 ---------- target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 13 +------------ 4 files changed, 6 insertions(+), 27 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b7a848bbae..e9cd0b88de 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -394,10 +394,6 @@ void mb_tcg_init(void); #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ =20 -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - typedef CPUMBState CPUArchState; typedef MicroBlazeCPU ArchCPU; =20 @@ -415,6 +411,10 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *en= v, target_ulong *pc, } =20 #if !defined(CONFIG_USER_ONLY) +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c index 52222eb93f..a94467dd2d 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -37,16 +37,6 @@ void cpu_loop(CPUMBState *env) process_queued_cpu_work(cs); =20 switch (trapnr) { - case 0xaa: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 15db277925..b9c888b87e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -365,9 +365,9 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { static const struct TCGCPUOps mb_tcg_ops =3D { .initialize =3D mb_tcg_init, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, - .tlb_fill =3D mb_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D mb_cpu_tlb_fill, .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, .do_interrupt =3D mb_cpu_do_interrupt, .do_transaction_failed =3D mb_cpu_transaction_failed, diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index dd2aecd1d5..a607fe68e5 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -24,18 +24,7 @@ #include "qemu/host-utils.h" #include "exec/log.h" =20 -#if defined(CONFIG_USER_ONLY) - -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - cs->exception_index =3D 0xaa; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, MMUAccessType access_type) { --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109401345726.533448443501; Fri, 1 Oct 2021 10:30:01 -0700 (PDT) Received: from localhost ([::1]:34458 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMMA-00087z-0m for importer@patchew.org; Fri, 01 Oct 2021 13:29:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM5C-0005AE-Ad for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:26 -0400 Received: from mail-qt1-x832.google.com ([2607:f8b0:4864:20::832]:46068) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM5A-0005Hn-8A for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:25 -0400 Received: by mail-qt1-x832.google.com with SMTP id r1so9592328qta.12 for ; Fri, 01 Oct 2021 10:12:20 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6mS1vCOgpN+V+J5nlq9LKRVT4rEwhx/pTcxKt2Kvegg=; b=oMEguWANqVRdFfaZpS+NyyN+QKTmwzS+fxLIpoBkuqlzDSV4fDFnSKR7qiQdlkp/cS 54keSaotJBTMjhySIX7D0RLzfOx1+kkUuDC7oASlf3bgeeOeUZH71iX8Jka9NWUEaQ+T n7DhU3e6m35cT2E4QpZjMnjqlE2ay69j/mc78DZHnm1zrs+YwzcKBBJrKaIqtfPPJjeK cjZhKgTiQ5muoGIua3TwA8vLJeL/oRKMaU2Fx+zgcFvYR5e6iNakyzNT0kDs0nXj5eRp rAvEy/x0zWJHfPj+36wLRFK1qZ1mEHMgcliwQOaxcURXPjJVXcXom2B7FqLaOnu7RqrB 08Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6mS1vCOgpN+V+J5nlq9LKRVT4rEwhx/pTcxKt2Kvegg=; b=6I6dui6HtNX+2B2SHaM2E0ybPr89sCSF5yhzXNSf3OB+aw/3zhrtw5LhGl0vOD8iov /7bIxndnhib/+hp249uPrcoy50zhdyarCszJhd4ZYdHCFy0+JbfHwYywsy6EOaePU0bG ihzsfKsKnJaHwRXqRQyU7F+rFAAEjPmVTwuvkKjocoSFeWTcdUKhGTjO6EI2N/mgP+Ek kfkBDVm6tJ1k2w69SqYA6JRfLfWwldpYr3FvBQemRIiACb+t+yGuguCkcytmrfTMOavM EXp7Li0xZXOEMb07wbMjSBMgAW4EHdoZcWO33jR9TRTJQptXmi/XG/Ae985PiVizzQIQ F2og== X-Gm-Message-State: AOAM530bDJ81C1IU+WGJIM5SoFkVd2pwPWywBgMJLNaSYK4wvbkf6fbQ Wb8TkBk4bGYFEtUkWJbkODq0SiqLnVvO2g== X-Google-Smtp-Source: ABdhPJz3H3i1xaIzSvJvY99Wz7LB4nB54ZgZPM2f/aSBfpuPwMyZafkqF/Giq/0gvocx7GVlI+3WVQ== X-Received: by 2002:ac8:148b:: with SMTP id l11mr14304016qtj.298.1633108339652; Fri, 01 Oct 2021 10:12:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 30/41] target/mips: Make mips_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:40 -0400 Message-Id: <20211001171151.1739472-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109402522100001 Content-Type: text/plain; charset="utf-8" The fallback code in raise_sigsegv is sufficient for mips linux-user. This means we can remove tcg/user/tlb_helper.c entirely. Remove the code from cpu_loop that raised SIGSEGV. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/tcg-internal.h | 7 ++-- linux-user/mips/cpu_loop.c | 11 ------ target/mips/cpu.c | 2 +- target/mips/tcg/user/tlb_helper.c | 59 ------------------------------- target/mips/tcg/meson.build | 3 -- target/mips/tcg/user/meson.build | 3 -- 6 files changed, 5 insertions(+), 80 deletions(-) delete mode 100644 target/mips/tcg/user/tlb_helper.c delete mode 100644 target/mips/tcg/user/meson.build diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index bad3deb611..466768aec4 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -18,9 +18,6 @@ void mips_tcg_init(void); =20 void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; @@ -60,6 +57,10 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, MemTxResult response, uintptr_t retadd= r); void cpu_mips_tlb_flush(CPUMIPSState *env); =20 +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + #endif /* !CONFIG_USER_ONLY */ =20 #endif diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cb03fb066b..b735c99a24 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -158,17 +158,6 @@ done_syscall: } env->active_tc.gpr[2] =3D ret; break; - case EXCP_TLBL: - case EXCP_TLBS: - case EXCP_AdEL: - case EXCP_AdES: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->CP0_BadVAddr; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_CpU: case EXCP_RI: info.si_signo =3D TARGET_SIGILL; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 00e0c55d0e..4aae23934b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -539,9 +539,9 @@ static const struct SysemuCPUOps mips_sysemu_ops =3D { static const struct TCGCPUOps mips_tcg_ops =3D { .initialize =3D mips_tcg_init, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, - .tlb_fill =3D mips_cpu_tlb_fill, =20 #if !defined(CONFIG_USER_ONLY) + .tlb_fill =3D mips_cpu_tlb_fill, .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .do_interrupt =3D mips_cpu_do_interrupt, .do_transaction_failed =3D mips_cpu_do_transaction_failed, diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c deleted file mode 100644 index 210c6d529e..0000000000 --- a/target/mips/tcg/user/tlb_helper.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * MIPS TLB (Translation lookaside buffer) helpers. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#include "qemu/osdep.h" - -#include "cpu.h" -#include "exec/exec-all.h" -#include "internal.h" - -static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type) -{ - CPUState *cs =3D env_cpu(env); - - env->error_code =3D 0; - if (access_type =3D=3D MMU_INST_FETCH) { - env->error_code |=3D EXCP_INST_NOTAVAIL; - } - - /* Reference to kernel address from user mode or supervisor mode */ - /* Reference to supervisor address from user mode */ - if (access_type =3D=3D MMU_DATA_STORE) { - cs->exception_index =3D EXCP_AdES; - } else { - cs->exception_index =3D EXCP_AdEL; - } - - /* Raise exception */ - if (!(env->hflags & MIPS_HFLAG_DM)) { - env->CP0_BadVAddr =3D address; - } -} - -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - /* data access */ - raise_mmu_exception(env, address, access_type); - do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); -} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 8f6f7508b6..98003779ae 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -28,9 +28,6 @@ mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'mxu_translate.c', )) =20 -if have_user - subdir('user') -endif if have_system subdir('sysemu') endif diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.= build deleted file mode 100644 index 79badcd321..0000000000 --- a/target/mips/tcg/user/meson.build +++ /dev/null @@ -1,3 +0,0 @@ -mips_user_ss.add(files( - 'tlb_helper.c', -)) --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633110992070958.5635594971003; Fri, 1 Oct 2021 10:56:32 -0700 (PDT) Received: from localhost ([::1]:44192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMlr-0003Cy-2f for importer@patchew.org; Fri, 01 Oct 2021 13:56:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55130) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM5F-0005D9-GQ for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:29 -0400 Received: from mail-qt1-x82c.google.com ([2607:f8b0:4864:20::82c]:41506) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM5A-0005IN-CR for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:29 -0400 Received: by mail-qt1-x82c.google.com with SMTP id t2so9610480qtx.8 for ; Fri, 01 Oct 2021 10:12:20 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g+FO3WUb/++tC//nR4BBTKuJptT+iDAQAdjiSDu9yJ4=; b=tNv6UJvR/q/twh/HuK2f6V2vcbWw+nyQYBqovb6Yqx6QD29mQ6Fq8vmNLkqCgeZwgn LcXvhKs/sZ8pSxXQQmwWT3JwMePRiyxaSqXpG6KgH0ThkkzslKzyHFrlAIGUIkNWl5sf 8CFqtZe6/H5UM2uVI5uDiv8NX+bg0fEgbnffXDumWWhATNw0JqnUmE4CDK0EWPM7elhq AmGextJ1FokF9NwvB8YZin9e2Tf1sYwqyMCEzaDrYAtyvDlWtY3Sb3IdoURtXJ+EyG8P TP/q0ySrl0y7ZvXMMQwBqHAgq0Rpe2QL2SBrz5L+nhIuM9vK8eBSqSopqmJH2BTNDIok smEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g+FO3WUb/++tC//nR4BBTKuJptT+iDAQAdjiSDu9yJ4=; b=B00K3Z57iMJirecRBpaF7yyQ16QY6V/CWePWfosSRg1mD/Up/vlrATpfW88JaUhJo8 ZEcG3OAoqEuSRLpgYdGg4RF+OBNtmlSdeyytHQ1vp8jbmDb9oDKoIqdloFlsUtG12O0H PUXP5QkYayGxhXNRCsl1xa3vDtsoCQ3SJYV5gFwJZ0V8w+T+QyZFeRpVebp0MSqF5kDU Ue8ZT0lVZY13pUdf3gz55TdgZ37k1WpjcwVwuujg8Mi7IGeJOFfZkxN7j0Cf2QIidbDA 9pirRL68CdUCpTIymiC5QuxndRn6rGONbFzR5rSo4IG1V84AIwGoscPLAWouc7XNvTJz JhKg== X-Gm-Message-State: AOAM53153cZirZjtWZwL98ktuLNOEuCVkRkVhUByj4vRLwy+CHXJQyjn secMaXtaFkBBrWMyurp8lOGRcH9QjOw2vw== X-Google-Smtp-Source: ABdhPJxcWh/H9Oz3iyT3FO63JSePwL7VsG8EaF6QeS2hJM0XA2gaQ/knRhIRZ4Yt/xqMLq75rzUU4g== X-Received: by 2002:ac8:429a:: with SMTP id o26mr14382995qtl.317.1633108340454; Fri, 01 Oct 2021 10:12:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 31/41] target/nios2: Implement nios2_cpu_record_sigsegv Date: Fri, 1 Oct 2021 13:11:41 -0400 Message-Id: <20211001171151.1739472-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82c; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633110994918100001 Content-Type: text/plain; charset="utf-8" Because the linux-user kuser page handling is currently implemented by detecting magic addresses in the unnamed 0xaa trap, we cannot simply remove nios2_cpu_tlb_fill and rely on the fallback code. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/nios2/cpu.h | 6 ++++++ target/nios2/cpu.c | 6 ++++-- target/nios2/helper.c | 7 ++++--- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index a80587338a..1a69ed7a49 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -218,9 +218,15 @@ static inline int cpu_mmu_index(CPUNios2State *env, bo= ol ifetch) MMU_SUPERVISOR_IDX; } =20 +#ifdef CONFIG_USER_ONLY +void nios2_cpu_record_sigsegv(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif =20 static inline int cpu_interrupts_enabled(CPUNios2State *env) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 947bb09bc1..421cad114a 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -220,9 +220,11 @@ static const struct SysemuCPUOps nios2_sysemu_ops =3D { =20 static const struct TCGCPUOps nios2_tcg_ops =3D { .initialize =3D nios2_tcg_init, - .tlb_fill =3D nios2_cpu_tlb_fill, =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D nios2_cpu_record_sigsegv, +#else + .tlb_fill =3D nios2_cpu_tlb_fill, .cpu_exec_interrupt =3D nios2_cpu_exec_interrupt, .do_interrupt =3D nios2_cpu_do_interrupt, .do_unaligned_access =3D nios2_cpu_do_unaligned_access, diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 53be8398e9..e5c98650e1 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -38,10 +38,11 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[R_EA] =3D env->regs[R_PC] + 4; } =20 -bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { + /* FIXME: Disentangle kuser page from linux-user sigsegv handling. */ cs->exception_index =3D 0xaa; cpu_loop_exit_restore(cs, retaddr); } --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163310969547359.798360697873704; Fri, 1 Oct 2021 10:34:55 -0700 (PDT) Received: from localhost ([::1]:48728 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMQw-00010X-9C for importer@patchew.org; Fri, 01 Oct 2021 13:34:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55036) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM5C-00059h-53 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:26 -0400 Received: from mail-qv1-xf2c.google.com ([2607:f8b0:4864:20::f2c]:34492) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM5A-0005IV-9c for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:25 -0400 Received: by mail-qv1-xf2c.google.com with SMTP id x8so6003373qvp.1 for ; Fri, 01 Oct 2021 10:12:21 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cVCx2jHCPvPujkZ/wrXYdO47hYaVZq7kiqP/WMFmGDE=; b=Aew/8u6YB1iOZFN9N26/Kz5Qxnb6h66J9LkqbKIXer9tEZW+3Q01jRo5cXWzwKyMfQ 3Lf93TBnKIdNWC0wRE2m/yimQvIHzW1b4Z1dwBu5ufPHeNkuqu0zwwAGNVrtiHOm4RFO BBXaW5hcC6ZAL5tYKg7QrTJHzTXlrcTHEt8pM6sgpomtlPQ4qqocotVzoUg5rzKr+xhY OUIzsIcPVxv82juVuzpDm3uEGQzhZapKcJ5wbhyHthYxo22z33TLe5prSoix2YtGhV58 ZfRXbUG8UnaGVQOnunMBYicOD/er8mw1wEWE7OedRumxVomIczYs8xN5reksKeuh+QuF CIFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cVCx2jHCPvPujkZ/wrXYdO47hYaVZq7kiqP/WMFmGDE=; b=ZY6oSXgQxHY+hJOMAX25q2wET7NU2ELp6rg7/52Md8+q1huhsKwSvr5uf9iaOwkOj+ XbsstFZaKLy41HmER5fMT4cTgqzIEcrgBVea1TK3gWHbrprLIMVtBw2BTu74iwpvkbE3 UsFnmOPJ561iwx3/gJA8lm2VRoqOCKGffickGYhrA7hyqlmg/MsyJZnbjtoTsggAcsgF wfRKqTQHvcvpIryX6Jwb5NDYpXDm7fhF3eEoBs/x6euzxFStlTsRZp8lGEzRg+Ns2ajF zAXqjDJHF8iSwM08dIqmLaP5KMWkkXMHkTrGN7msz3dyHjzLWCEJRDaWRn7i0wq6tia9 vupQ== X-Gm-Message-State: AOAM533kgcozzgsDdvFtUUrFQgFcrssLLOSlFjhYikWHrJgQp0mUxExP WZgiFzVgFjqPmQ4n+y5aQjM+KSlkOG6ymQ== X-Google-Smtp-Source: ABdhPJzyWKY2LfvmqiOqyVMaSgPHdMqpVwOpBaOqEvzriY/ZXypnB7p1bjB53mTuKQ3Gwwnh1hSpYg== X-Received: by 2002:a05:6214:5b1:: with SMTP id by17mr8179346qvb.18.1633108341355; Fri, 01 Oct 2021 10:12:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 32/41] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE Date: Fri, 1 Oct 2021 13:11:42 -0400 Message-Id: <20211001171151.1739472-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109697255100001 Content-Type: text/plain; charset="utf-8" The kernel vectors both of these through unhandled_exception, which results in force_sig(SIGSEGV). This isn't very useful for userland when enabling overflow traps or fpu traps, but c'est la vie. Cc: Stafford Horne Signed-off-by: Richard Henderson --- linux-user/openrisc/cpu_loop.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index f6360db47c..de5417a262 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -56,13 +56,17 @@ void cpu_loop(CPUOpenRISCState *env) break; case EXCP_DPF: case EXCP_IPF: - case EXCP_RANGE: info.si_signo =3D TARGET_SIGSEGV; info.si_errno =3D 0; info.si_code =3D TARGET_SEGV_MAPERR; info._sifields._sigfault._addr =3D env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; + case EXCP_RANGE: + case EXCP_FPE: + /* ??? The kernel vectors both of these to unhandled_exception= . */ + force_sig(TARGET_SIGSEGV); + break; case EXCP_ALIGN: info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; @@ -77,13 +81,6 @@ void cpu_loop(CPUOpenRISCState *env) info._sifields._sigfault._addr =3D env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_FPE: - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - info.si_code =3D 0; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_INTERRUPT: /* We processed the pending cpu work above. */ break; --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109882515626.6135126919846; Fri, 1 Oct 2021 10:38:02 -0700 (PDT) Received: from localhost ([::1]:57436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMTw-0006vo-6O for importer@patchew.org; Fri, 01 Oct 2021 13:38:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55074) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM5D-0005Bb-3C for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:28 -0400 Received: from mail-qt1-x835.google.com ([2607:f8b0:4864:20::835]:39515) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM5A-0005Ib-CD for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:26 -0400 Received: by mail-qt1-x835.google.com with SMTP id j13so9634624qtq.6 for ; Fri, 01 Oct 2021 10:12:22 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bhFTWYUd/DdGCKOIwhaKfMZGLTFXZbTF8Lut7J+0pC4=; b=ms8cDPku6CsT7oadKBdKUoWiqGzmZmjw02tvLWHNlMkpOc+F2A9xYzc7s0P7Gxl6Kt FYmmPUmiYb9uTaqDvGqbt7RpHx/2y6UE9LS5kcVvEwDE5qkB834bZcdc6tkv5PnBHYRZ rBCyj69yKuCL23clZhh8t2cK+tLuQEyK57qeWiu4I6JfNV9AnB+VcwF+HyRSl+Vp2K6U YEz2aGPbpQx092ZbX6j0vRlZpE+z0Goe2eSFtk87lwlgzxcxr4AwWfN3SGLgr2wDkdEB 3OIBzFzOB65No6l1Yug423mYDwloWrkAmk7vH0imwojzqmtLnVO0qFJJKrm4dUgRX3qH mxVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bhFTWYUd/DdGCKOIwhaKfMZGLTFXZbTF8Lut7J+0pC4=; b=hTRU29fukkntJB0rxm2mCV24P6VHD0vCjvnb8sC79q0g1ctOdoX4b9dEOK9HVpoa39 AM0Q2pE1SnxyE2dQuz3FJA8X5Xr4ueSHHrM2rtR7DvAppQmVaZ382vqYo8Nf/vim4ytx dbZUq0XVfafSvjNULi/LZIQs03t/HJgCKfPZ/RCq5Qj7DpLzsCyLMnGbkFv5gXI9ROwN u2HaUhaGxC3u93zevdvj4UHf/BZ4n34Y/7VaZgwfehkdXAe2dHvErgLIwRrIEHJMsWQ0 CXq8W/whfQQuqiCWdXvfJVygkb6VYsQCojNYF2WzROcojhtE/iX1ym0rb2eaOTiY8N89 PzOA== X-Gm-Message-State: AOAM530KHuco4L0qJubY5V2odcQJvHnzxjue3INrTkfehJD0KAOYc8PR s4Ta9Tp4yEhcaeff/bvUIaruOlNWQw4TJw== X-Google-Smtp-Source: ABdhPJxejEBE9fG1kOuTRkEXMSv0zipKT0gwvSDif087LAPwcqjxz8jMfggQ35TEpXtL0Q0WT+nR/Q== X-Received: by 2002:ac8:59ca:: with SMTP id f10mr14411387qtf.334.1633108342200; Fri, 01 Oct 2021 10:12:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 33/41] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:43 -0400 Message-Id: <20211001171151.1739472-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109883684100001 Content-Type: text/plain; charset="utf-8" The fallback code in raise_sigsegv is sufficient for openrisc. This makes all of the code in mmu.c sysemu only, so remove the ifdefs and move the file to openrisc_softmmu_ss. Remove the code from cpu_loop that handled EXCP_DPF. Cc: Stafford Horne Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/openrisc/cpu.h | 7 ++++--- linux-user/openrisc/cpu_loop.c | 8 -------- target/openrisc/cpu.c | 2 +- target/openrisc/mmu.c | 8 -------- target/openrisc/meson.build | 2 +- 5 files changed, 6 insertions(+), 21 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 187a4a114e..ee069b080c 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -317,14 +317,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu= , vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg= ); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); int print_insn_or1k(bfd_vma addr, disassemble_info *info); =20 #define cpu_list cpu_openrisc_list =20 #ifndef CONFIG_USER_ONLY +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + extern const VMStateDescription vmstate_openrisc_cpu; =20 void openrisc_cpu_do_interrupt(CPUState *cpu); diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index de5417a262..fb37fb7651 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -54,14 +54,6 @@ void cpu_loop(CPUOpenRISCState *env) cpu_set_gpr(env, 11, ret); } break; - case EXCP_DPF: - case EXCP_IPF: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_RANGE: case EXCP_FPE: /* ??? The kernel vectors both of these to unhandled_exception= . */ diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 27cb04152f..dfbafc5236 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -186,9 +186,9 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { =20 static const struct TCGCPUOps openrisc_tcg_ops =3D { .initialize =3D openrisc_translate_init, - .tlb_fill =3D openrisc_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D openrisc_cpu_tlb_fill, .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .do_interrupt =3D openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 94df8c7bef..91cedf4125 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -23,11 +23,8 @@ #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "qemu/host-utils.h" -#ifndef CONFIG_USER_ONLY #include "hw/loader.h" -#endif =20 -#ifndef CONFIG_USER_ONLY static inline void get_phys_nommu(hwaddr *phys_addr, int *prot, target_ulong address) { @@ -94,7 +91,6 @@ static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_ad= dr, int *prot, return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS; } } -#endif =20 static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, int exception) @@ -113,7 +109,6 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, in= t size, OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); int excp =3D EXCP_DPF; =20 -#ifndef CONFIG_USER_ONLY int prot; hwaddr phys_addr; =20 @@ -138,13 +133,11 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, = int size, if (probe) { return false; } -#endif =20 raise_mmu_exception(cpu, addr, excp); cpu_loop_exit_restore(cs, retaddr); } =20 -#ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); @@ -177,4 +170,3 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, v= addr addr) return phys_addr; } } -#endif diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build index e445dec4a0..84322086ec 100644 --- a/target/openrisc/meson.build +++ b/target/openrisc/meson.build @@ -10,7 +10,6 @@ openrisc_ss.add(files( 'fpu_helper.c', 'gdbstub.c', 'interrupt_helper.c', - 'mmu.c', 'sys_helper.c', 'translate.c', )) @@ -19,6 +18,7 @@ openrisc_softmmu_ss =3D ss.source_set() openrisc_softmmu_ss.add(files( 'interrupt.c', 'machine.c', + 'mmu.c', )) =20 target_arch +=3D {'openrisc': openrisc_ss} --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163311025038599.50769007796544; Fri, 1 Oct 2021 10:44:10 -0700 (PDT) Received: from localhost ([::1]:38146 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMZt-0004pC-0f for importer@patchew.org; Fri, 01 Oct 2021 13:44:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM5E-0005C8-1H for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:29 -0400 Received: from mail-qt1-x835.google.com ([2607:f8b0:4864:20::835]:34808) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM5A-0005If-CK for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:27 -0400 Received: by mail-qt1-x835.google.com with SMTP id m26so9646193qtn.1 for ; Fri, 01 Oct 2021 10:12:23 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h+WX/Xz3j7uTzh8f9NwZfFO9w7icTNNLSs9RiVXjf3k=; b=mCrnYTJnJbIbGzuxs5qDnO0t4J7n5Fu+Qhpm2DHKICihgqmI6wflxWRy8RtkQg40eY E5ZC8hEIUbbTCfnCh3aujUhfw5Vgf9gBybenKAwTc2H2C3Nm2FpodLkkPme+C/55yPUF PmIwSX0OI6w2W5H58XRYRnQ/sixHb28XQnAd2NgX0Bm+yf0AC3yLmjpMN3dl9R23NHom u28E+AGfGnJFeJsOYOuLnLDV3YTk1ZImviLjptMKDoJF2+RJfCSFA/WCAU6wK3armwYU WLa7tAQf+RZAJqH+DNOTAizAyV9NPhYQqn42Ap1usXn+c66PZDNkgB6cjzqZU8gHogAs hwnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h+WX/Xz3j7uTzh8f9NwZfFO9w7icTNNLSs9RiVXjf3k=; b=tQlTs4Lv1O3eiRf7pUHizf3h/Z8Gk2qt8BS4pti9C4qfHRwA87xSbvSsDP+XJVJ4fL /5Bgy4eiXwL595k2f0pQVLGLQyp0i/UmEEpoRe3UUY20GDEF2F3se1nvOXMCsmA48eO8 gBOSd04Wq6GCSn4TNTE9JR71n38Hx58SuwStDW26f3bC5pd5nBnOQuygmKUzFTSNhsYQ yPvKnXN0sMzTqnVKJ/ckJeUVTsZs5IQMCinbI9EySj+3An0rAgx35ng2Km1tp5yhoTns 4S2FQ3FnMcWNLbBivHdkhtCI+MM8R+l0/DuuFjlg+1htuNXgkQ9yPqbvEVg8z9Pa5jp8 Yz+A== X-Gm-Message-State: AOAM532/W/1e2lqgk/O/rc9Uhfa8YCSyGX9viIaXPGQWMT12LEyYyZsk FuiIoT7zS0Zca5wtT+ya0xVqOt6wLcUobA== X-Google-Smtp-Source: ABdhPJwKGjTuE5TNy6NU/FlFmn+Y5yF2ow3hn/mbcHu0tpmo8gB+BLk+kVvRk04vlmR4A3/R6wgagw== X-Received: by 2002:ac8:7143:: with SMTP id h3mr14627375qtp.242.1633108343053; Fri, 01 Oct 2021 10:12:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 34/41] target/ppc: Implement ppc_cpu_record_sigsegv Date: Fri, 1 Oct 2021 13:11:44 -0400 Message-Id: <20211001171151.1739472-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, alex.bennee@linaro.org, laurent@vivier.eu, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633110252422100001 Record DAR, DSISR, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. This is exactly what the user-mode ppc_cpu_tlb_fill does, so simply rename it as ppc_cpu_record_sigsegv. Cc: qemu-ppc@nongnu.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 3 --- target/ppc/internal.h | 9 +++++++++ target/ppc/cpu_init.c | 6 ++++-- target/ppc/user_only_helper.c | 15 +++++++++++---- 4 files changed, 24 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 01d3773bc7..60d1117845 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1278,9 +1278,6 @@ extern const VMStateDescription vmstate_ppc_cpu; =20 /*************************************************************************= ****/ void ppc_translate_init(void); -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); =20 #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1(CPUPPCState *env, target_ulong value); diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 55284369f5..339974b7d8 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0) #define PTE_PTEM_MASK 0x7FFFFFBF #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) =20 +#ifdef CONFIG_USER_ONLY +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif =20 #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6aad01d1d3..ec8da08f0b 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -9014,9 +9014,11 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { =20 static const struct TCGCPUOps ppc_tcg_ops =3D { .initialize =3D ppc_translate_init, - .tlb_fill =3D ppc_cpu_tlb_fill, =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D ppc_cpu_record_sigsegv, +#else + .tlb_fill =3D ppc_cpu_tlb_fill, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .do_interrupt =3D ppc_cpu_do_interrupt, .cpu_exec_enter =3D ppc_cpu_exec_enter, diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index aa3f867596..7ff76f7a06 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -21,16 +21,23 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "internal.h" =20 - -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; int exception, error_code; =20 + /* + * Both DSISR and the "trap number" (exception vector offset, + * looked up from exception_index) are present in the linux-user + * signal frame. + * FIXME: we don't actually populate the trap number properly. + * It would be easiest to fill in an env->trap value now. + */ if (access_type =3D=3D MMU_INST_FETCH) { exception =3D POWERPC_EXCP_ISI; error_code =3D 0x40000000; --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633110507231880.6821896237847; Fri, 1 Oct 2021 10:48:27 -0700 (PDT) Received: from localhost ([::1]:47536 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMe2-0002sw-7v for importer@patchew.org; Fri, 01 Oct 2021 13:48:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55142) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM5G-0005EC-QH for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:31 -0400 Received: from mail-qv1-xf2d.google.com ([2607:f8b0:4864:20::f2d]:38669) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM5B-0005Io-KS for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:30 -0400 Received: by mail-qv1-xf2d.google.com with SMTP id cv2so5984752qvb.5 for ; Fri, 01 Oct 2021 10:12:24 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7570NHxgZZiIlSGX0IMLoQr+WiKI3C5JO5f+PGrIgpw=; b=wsQNFhzeKyj2bCz5AcZFLwdtCU02LAWPz0h/7AgxFq1cxGPpGwG/hdhPhdSw1d24UU qlFZTnC2dI7OclCLRG436teRdwYjCNdp9qfmuLs+oBmTe+MrhJyZmPejJMY5Eh1GobWM NWm9RLZc+kLhpWMMXTS3aSeOm4gC1yeYM06WMElsYUcVePXB7bdD/X9umFjGTdLzO4RP hiEGhP9I/z7/CbQE0ROBM9e9M8i3urviRUj23uRNPFzGlUm7t/ac3UN0R/yd6HShOOOW lmuGfyIEp3tjiFJlbFTMKXVIrXP0zxSkl19s+MP/LZRO0k9KsIMhXtOCXWvxEZOZ4bGA L5+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7570NHxgZZiIlSGX0IMLoQr+WiKI3C5JO5f+PGrIgpw=; b=UFiDHZz13PqxA2twJD1iZZaQgJiNDJ9U8Fr9N+reMuB1pI0DiZ3ZWxqVzWThSbvu1E t8/pZMH1ShbysLHXC9Nr0yNVZWqx5fX9woYuikVPl3A8ItZYgiL5I85CXPBNeJdgHg/V 3jGGRP89SnXqpZcDvn1xxjyckfmNJyOzsVpXRFyWBsrz8WnETO6rIAbNbblPX5c56Szm 0k11Q4pPTsZjyNzDjOxRp+/o81BfpQFgkjSLhWomMcjrKcrH59Qu6f6JRDBgtpf1O1Ct orqo78Z6ldY/UnGqMK99+nliwWMfa3/6cTpatU1r7UhPZoXoeRVMYRWUup5Tz1FryJVK +qJg== X-Gm-Message-State: AOAM533puEMx8EfkBtuBmah67mSRPdGMbaBIKBainZWm01lI83Nj5Ikg PvQSY6KcVj3q9Ee8szP07fnbXBfXCWyHfg== X-Google-Smtp-Source: ABdhPJy196vMpgGdWwjrcjD+zyZzfrMpsGQCQ4DlQ1BjOYynxlq+sHxvs/5lmaKpVmyYEyYF0U9dnA== X-Received: by 2002:a05:6214:1465:: with SMTP id c5mr9982163qvy.66.1633108343860; Fri, 01 Oct 2021 10:12:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:45 -0400 Message-Id: <20211001171151.1739472-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2d; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633110509377100001 Content-Type: text/plain; charset="utf-8" The fallback code in raise_sigsegv is sufficient for riscv. Remove the code from cpu_loop that raised SIGSEGV. Cc: qemu-riscv@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- linux-user/riscv/cpu_loop.c | 7 ------- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 21 +-------------------- 3 files changed, 2 insertions(+), 28 deletions(-) diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 9859a366e4..aef019b1c8 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -87,13 +87,6 @@ void cpu_loop(CPURISCVState *env) sigcode =3D TARGET_TRAP_BRKPT; sigaddr =3D env->pc; break; - case RISCV_EXCP_INST_PAGE_FAULT: - case RISCV_EXCP_LOAD_PAGE_FAULT: - case RISCV_EXCP_STORE_PAGE_FAULT: - signum =3D TARGET_SIGSEGV; - sigcode =3D TARGET_SEGV_MAPERR; - sigaddr =3D env->badaddr; - break; case RISCV_EXCP_SEMIHOST: env->gpr[xA0] =3D do_common_semihosting(cs); env->pc +=3D 4; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7c626d89cd..0292a72feb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -675,9 +675,9 @@ static const struct SysemuCPUOps riscv_sysemu_ops =3D { static const struct TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, - .tlb_fill =3D riscv_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D riscv_cpu_tlb_fill, .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d41d5cd27c..b520d6fc78 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -748,7 +748,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(env, cs->exception_index, retaddr); } -#endif /* !CONFIG_USER_ONLY */ =20 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -756,7 +755,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; -#ifndef CONFIG_USER_ONLY vaddr im_address; hwaddr pa =3D 0; int prot, prot2, prot_pmp; @@ -888,25 +886,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } =20 return true; - -#else - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index =3D RISCV_EXCP_INST_PAGE_FAULT; - break; - case MMU_DATA_LOAD: - cs->exception_index =3D RISCV_EXCP_LOAD_PAGE_FAULT; - break; - case MMU_DATA_STORE: - cs->exception_index =3D RISCV_EXCP_STORE_PAGE_FAULT; - break; - default: - g_assert_not_reached(); - } - env->badaddr =3D address; - cpu_loop_exit_restore(cs, retaddr); -#endif } +#endif /* !CONFIG_USER_ONLY */ =20 /* * Handle Traps --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633110832615191.11361172167472; Fri, 1 Oct 2021 10:53:52 -0700 (PDT) Received: from localhost ([::1]:35676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMjH-0005oB-DY for importer@patchew.org; Fri, 01 Oct 2021 13:53:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55102) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM5D-0005C6-ON for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:29 -0400 Received: from mail-qv1-xf2e.google.com ([2607:f8b0:4864:20::f2e]:33573) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM5B-0005JN-N1 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:27 -0400 Received: by mail-qv1-xf2e.google.com with SMTP id a9so6024843qvf.0 for ; Fri, 01 Oct 2021 10:12:25 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ed7k7oV00Ud53qqbt9Yos8IyOCfVvxLg7PyS2NKYTH0=; b=YqPuSya7aCdRIEKhEZod8HGV9ua3R+yxBLeyblsT5laePgT52MagP+1aAx17IaONM9 vvNdRwRvsL0SdcZAqB337o1VBULjbYB494ZiUxkyKlL60FX3mFClWhTPJFZSiQu1OQ0I 17iVJL1IVZ/5jdQtYRBulvsYqUu+O+N2svS+z3tGlnfaVaszRdMEAylMMxczYfF69glu EtJcQWCC7mK8QW5Vp6JFlMspjKrei4w4myat7peXhO59dZKaTIEQkYcjgE9bGDYV4AL9 W28IYjK10PdkF6ppl4pfD/dsvfCZ8BfWx0l58hx9sXjl7pYYfvRp7pcx/unid5AcdxK6 W69w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ed7k7oV00Ud53qqbt9Yos8IyOCfVvxLg7PyS2NKYTH0=; b=5B7/VNLaESzsj9kN6nosLcTracZqsYxhLB0dI80tTCtZv6oS+Vk4DwvL7bcXp7mEcO 5IEcrD7pOSKdn0OflGbqIEUu2o3Y3tUfgpwAvIwjDDBnwFiM3RvqNfPEIywUc4IdyUqu eMz+fIjsU/1W3b0KztWacBWGQQPexZnVNkR/Pg+0Tr+q5pYC9NmJSlRSVACrKqKybauJ lrNNSjyY9T1ss98kTyE0LkBb60hNyIfFS28YIvG5H5YcZA8hoZiyVGB5ig6/M1YbMWTh eSjm5/xJm32d26KhHrd3EK9RlasJY8pLeI0mNROoAd/VKobkVq7kqEq+jplhlpyxvnwG IUdQ== X-Gm-Message-State: AOAM530o6GKjshfJbfa3xByADe1d11GnkJ6huUf54EWCAZh8UokOwCfZ v6tKHzISJx3VRmsiVlr8SzzjGR6r4GzFuw== X-Google-Smtp-Source: ABdhPJxjwVr0EjcSMMkLvLGBJz+8OvgSZzyOjRvNf6R8FKMqMj5vJKAPIPk9eNYd6/xQeG/mvHeqWg== X-Received: by 2002:a0c:df0c:: with SMTP id g12mr11460642qvl.25.1633108344711; Fri, 01 Oct 2021 10:12:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 36/41] target/s390x: Use probe_access_flags in s390_probe_access Date: Fri, 1 Oct 2021 13:11:46 -0400 Message-Id: <20211001171151.1739472-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633110833591100001 Content-Type: text/plain; charset="utf-8" Not sure why the user-only code wasn't rewritten to use probe_access_flags at the same time that the sysemu code was converted. For the purpose of user-only, this is an exact replacement. Cc: qemu-s390x@nongnu.org Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 0bf775a37d..596270e45d 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -142,20 +142,12 @@ static int s390_probe_access(CPUArchState *env, targe= t_ulong addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t ra) { +#if defined(CONFIG_USER_ONLY) + return probe_access_flags(env, addr, access_type, mmu_idx, + nonfault, phost, ra); +#else int flags; =20 -#if defined(CONFIG_USER_ONLY) - flags =3D page_get_flags(addr); - if (!(flags & (access_type =3D=3D MMU_DATA_LOAD ? PAGE_READ : PAGE_WR= ITE_ORG))) { - env->__excp_addr =3D addr; - flags =3D (flags & PAGE_VALID) ? PGM_PROTECTION : PGM_ADDRESSING; - if (nonfault) { - return flags; - } - tcg_s390_program_interrupt(env, flags, ra); - } - *phost =3D g2h(env_cpu(env), addr); -#else /* * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr= =3D=3DNULL * to detect if there was an exception during tlb_fill(). @@ -174,8 +166,8 @@ static int s390_probe_access(CPUArchState *env, target_= ulong addr, int size, (access_type =3D=3D MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ), ra); } -#endif return 0; +#endif } =20 static int access_prepare_nf(S390Access *access, CPUS390XState *env, --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633111152282624.5011511130957; Fri, 1 Oct 2021 10:59:12 -0700 (PDT) Received: from localhost ([::1]:53506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMoR-0000xP-6D for importer@patchew.org; Fri, 01 Oct 2021 13:59:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55182) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM5I-0005Fp-9y for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:35 -0400 Received: from mail-qt1-x82e.google.com ([2607:f8b0:4864:20::82e]:40669) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM5D-0005Kz-CU for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:32 -0400 Received: by mail-qt1-x82e.google.com with SMTP id b16so9624701qtt.7 for ; Fri, 01 Oct 2021 10:12:26 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jEmAGke+Q2SF6dInMRgXkKJGhuJtK6GWTLvXnPINEiA=; b=g22jRRh55mZ5K8H4u4kGvD3IkpvkvmwQDSYSIbTxkIX18IMGlxIcUclxX9JedDNm7J e72Bu3fT10hpvk18l1cGIivyM77+qTK9/UoUvSbKGzpPmp0lstvlKbKJxI+jQyf/T7mR IO2cgwHEJtkW7ShIBIrkj/9S/p9XGZGoAmhfGjH5l+ULWBoV28j5x7jIPZXldoQngSS7 emXc43CtTY3KVTgEv9mwX8jlTOb2938cpDMt4qVKH2QgKjkfi3nhQT4/nJ5Pc05t2U+S vjuw/tuP/UbH72iiAFLSp3mXxKBJWABVyh9qCML/1uOpkEehZZOBXF/qoqmyME+53vg4 mLMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jEmAGke+Q2SF6dInMRgXkKJGhuJtK6GWTLvXnPINEiA=; b=wU8Y9UaGoBuqlyBYOMRO00YNrsBPZCLOcKXUDZ8vsRSlRrLWmbZEnO1XskADZpN2Ri XTUZtF5GeK3sIefVzJHkbG7qylxVUlfsyKNsAMbwzpsNJ8avC4H/aEBO/YwD/f1NleoL wev0FhLF827tX4pQ/ojeDJgmXXdloq4vSEBNKcMdwvslHd9Tlev/jii/xeFzucLtb9ox CFrRwsx0dE3AbEYpfuq6/R9ZAapn1BiWQcYn/72t3PL4WUMqBfdFaBSAqSmq2oyTCPjK 4C2ydHILqfwxFoNJiFsNlvA03gDELdQRQJnSYYYTa1fh/KiYP67SiwjjqlEShX9ROnOb Hjdg== X-Gm-Message-State: AOAM531ePWKxuF9BuClQKDtV0ngeR3EYTaCTQctXT+hhkAflN3ZSpSjW WgKVTmj+byIY9I+QILj4AdFoR+f3qnHDGA== X-Google-Smtp-Source: ABdhPJyx8msEYtKOem4n9zEb9mHs0l3oY2YfTrqbU+6p78QibKTYVFilCLaDBRteIEVkFT4GNpiqyw== X-Received: by 2002:ac8:434d:: with SMTP id a13mr14325274qtn.91.1633108345528; Fri, 01 Oct 2021 10:12:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 37/41] target/s390x: Implement s390_cpu_record_sigsegv Date: Fri, 1 Oct 2021 13:11:47 -0400 Message-Id: <20211001171151.1739472-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82e; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82e.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, alex.bennee@linaro.org, laurent@vivier.eu, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633111154173100001 Move the masking of the address from cpu_loop into s390_cpu_record_sigsegv -- this is governed by hw, not linux. This does mean we have to raise our own exception, rather than return to the fallback. Use maperr to choose between PGM_PROTECTION and PGM_ADDRESSING. Use the appropriate si_code for each in cpu_loop. Cc: qemu-s390x@nongnu.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/s390x-internal.h | 13 ++++++++++--- linux-user/s390x/cpu_loop.c | 13 ++++++------- target/s390x/cpu.c | 6 ++++-- target/s390x/tcg/excp_helper.c | 18 +++++++++++------- 4 files changed, 31 insertions(+), 19 deletions(-) diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 27d4a03ca1..163aa4f94a 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -270,13 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; =20 +#ifdef CONFIG_USER_ONLY +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr); +#else +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif + =20 /* fpu_helper.c */ uint32_t set_cc_nz_f32(float32 v); diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index 69b69981f6..d089c8417e 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -24,8 +24,6 @@ #include "cpu_loop-common.h" #include "signal-common.h" =20 -/* s390x masks the fault address it reports in si_addr for SIGSEGV and SIG= BUS */ -#define S390X_FAIL_ADDR_MASK -4096LL =20 static int get_pgm_data_si_code(int dxc_code) { @@ -111,12 +109,13 @@ void cpu_loop(CPUS390XState *env) n =3D TARGET_ILL_ILLOPC; goto do_signal_pc; case PGM_PROTECTION: + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_ACCERR, + env->__excp_addr); + break; case PGM_ADDRESSING: - sig =3D TARGET_SIGSEGV; - /* XXX: check env->error_code */ - n =3D TARGET_SEGV_MAPERR; - addr =3D env->__excp_addr & S390X_FAIL_ADDR_MASK; - goto do_signal; + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, + env->__excp_addr); + break; case PGM_EXECUTE: case PGM_SPECIFICATION: case PGM_SPECIAL_OP: diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7b7b05f1d3..593dda75c4 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -266,9 +266,11 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 static const struct TCGCPUOps s390_tcg_ops =3D { .initialize =3D s390x_translate_init, - .tlb_fill =3D s390_cpu_tlb_fill, =20 -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv =3D s390_cpu_record_sigsegv, +#else + .tlb_fill =3D s390_cpu_tlb_fill, .cpu_exec_interrupt =3D s390_cpu_exec_interrupt, .do_interrupt =3D s390_cpu_do_interrupt, .debug_excp_handler =3D s390x_cpu_debug_excp_handler, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 3d6662a53c..b923d080fc 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -89,16 +89,20 @@ void s390_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D -1; } =20 -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { S390CPU *cpu =3D S390_CPU(cs); =20 - trigger_pgm_exception(&cpu->env, PGM_ADDRESSING); - /* On real machines this value is dropped into LowMem. Since this - is userland, simply put this someplace that cpu_loop can find it. = */ - cpu->env.__excp_addr =3D address; + trigger_pgm_exception(&cpu->env, maperr ? PGM_ADDRESSING : PGM_PROTECT= ION); + /* + * On real machines this value is dropped into LowMem. Since this + * is userland, simply put this someplace that cpu_loop can find it. + * S390 only gives the page of the fault, not the exact address. + * C.f. the construction of TEC in mmu_translate(). + */ + cpu->env.__excp_addr =3D address & TARGET_PAGE_MASK; cpu_loop_exit_restore(cs, retaddr); } =20 --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633110485486205.0090669682835; Fri, 1 Oct 2021 10:48:05 -0700 (PDT) Received: from localhost ([::1]:46046 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMdg-0001pl-2s for importer@patchew.org; Fri, 01 Oct 2021 13:48:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55200) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM5L-0005GN-Kq for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:35 -0400 Received: from mail-qv1-xf2c.google.com ([2607:f8b0:4864:20::f2c]:43750) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM5D-0005MG-EI for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:35 -0400 Received: by mail-qv1-xf2c.google.com with SMTP id k3so1358406qve.10 for ; Fri, 01 Oct 2021 10:12:26 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QnIuy+UNML3N+Vecxph501fC1v8l7RElAhe1SJhJNCk=; b=rB07Vx0y2mdCo6zIZAeaa28kFsqoxZiliNPDUXMNiFPbWQcbvY45St3YZ4KoW5eLS4 gx1qW7nQ+gEdocu06ws26EL9W2ccS4Cz+uNxpNJlgvpk1AxbfQkE70nX7IN7+mfNu+O/ QMwkUs0I7q/nc10/F8dCf3WPHlketzxrYHhPKC0+eznOxKtPatZdghGBcjOgUJaphvLI RQ375tH+lUfoJsW71nZWwoPqP0lReMzQb4sQ1fjbkD2hZ2U5418QqJLEKoZET89DeKm8 SsILiTfQKGGzUZyHa9bpDX2RyxLy6neQOnhp+JTBvPlXc5PaXBMU3RysqVgMZBsI3WTV w+Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QnIuy+UNML3N+Vecxph501fC1v8l7RElAhe1SJhJNCk=; b=6Aeg554nPa7qADl9UBx4ZZxzxM8+tAeDEKwDbAZpiQuyA1DBKaNtztE+3thhhUphey 0SVWR8Kbwpqyu7g3Xu71dmMKYVWrReZ3l/tI67P5ODxAHhiC+LpuptQheCTGiDoJKuNO iVQ+OOm/sPLUqgCQeI53VmmXHYv0+z40ViVEN+Uyx9uVzG3/grmVFVEAEb1H46fX4jzE VKGOVEYgSZBnl/AQKF17FjJbzfOQ2hC/6QpqF0psNB9P7/covLFdRfwb20GwIu09R4XB N3TI5nnaXkT12yb3pq1rMvZ7BqM7OrqSZQWS7wPijTMTyWIpoIIGvUVRRvQw8PLodnEp DDDw== X-Gm-Message-State: AOAM532KnNaw+feu9S2G3LOW/+xaPztZ+EtmYthLx7R/INiZ4LlqAKs1 9b5jAuy6h3cWfE1G8TIo4f8XNZbQWV5iGw== X-Google-Smtp-Source: ABdhPJwpRouVfTFiU3SLhS8QbZynz436cvCsDqDE+sbo+TfAi9+5YmVQ5ok9XIPQ2hmKPvbAucHKuQ== X-Received: by 2002:ad4:4652:: with SMTP id y18mr11349825qvv.2.1633108346370; Fri, 01 Oct 2021 10:12:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 38/41] target/sh4: Make sh4_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:48 -0400 Message-Id: <20211001171151.1739472-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, Yoshinori Sato Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633110487779100007 Content-Type: text/plain; charset="utf-8" The fallback code in raise_sigsegv is sufficient for sh4. Remove the code from cpu_loop that raised SIGSEGV. Cc: Yoshinori Sato Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 6 +++--- linux-user/sh4/cpu_loop.c | 8 -------- target/sh4/cpu.c | 2 +- target/sh4/helper.c | 9 +-------- 4 files changed, 5 insertions(+), 20 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index dc81406646..4cfb109f56 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -213,12 +213,12 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, va= ddr addr, uintptr_t retaddr) QEMU_NORETURN; =20 void sh4_translate_init(void); +void sh4_cpu_list(void); + +#if !defined(CONFIG_USER_ONLY) bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); - -void sh4_cpu_list(void); -#if !defined(CONFIG_USER_ONLY) void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void cpu_sh4_invalidate_tlb(CPUSH4State *s); diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index 65b8972e3c..ac9b01840c 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -65,14 +65,6 @@ void cpu_loop(CPUSH4State *env) info.si_code =3D TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case 0xa0: - case 0xc0: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->tea; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); arch_interrupt =3D false; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 2047742d03..06b2691dc4 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -236,9 +236,9 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { static const struct TCGCPUOps superh_tcg_ops =3D { .initialize =3D sh4_translate_init, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, - .tlb_fill =3D superh_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D superh_cpu_tlb_fill, .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, .do_interrupt =3D superh_cpu_do_interrupt, .do_unaligned_access =3D superh_cpu_do_unaligned_access, diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 53cb9c3b63..6a620e36fc 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -796,8 +796,6 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) return false; } =20 -#endif /* !CONFIG_USER_ONLY */ - bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -806,11 +804,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, CPUSH4State *env =3D &cpu->env; int ret; =20 -#ifdef CONFIG_USER_ONLY - ret =3D (access_type =3D=3D MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE : - access_type =3D=3D MMU_INST_FETCH ? MMU_ITLB_VIOLATION : - MMU_DTLB_VIOLATION_READ); -#else target_ulong physical; int prot; =20 @@ -829,7 +822,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, if (ret !=3D MMU_DTLB_MULTIPLE && ret !=3D MMU_ITLB_MULTIPLE) { env->pteh =3D (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_M= ASK); } -#endif =20 env->tea =3D address; switch (ret) { @@ -868,3 +860,4 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633110685175819.8634787388894; Fri, 1 Oct 2021 10:51:25 -0700 (PDT) Received: from localhost ([::1]:55832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMgu-0000DO-1r for importer@patchew.org; Fri, 01 Oct 2021 13:51:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55212) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM5M-0005J4-9X for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:36 -0400 Received: from mail-qt1-x836.google.com ([2607:f8b0:4864:20::836]:43942) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM5E-0005Mh-0e for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:12:36 -0400 Received: by mail-qt1-x836.google.com with SMTP id a13so9613435qtw.10 for ; Fri, 01 Oct 2021 10:12:27 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Kxx36+JaRB0XOezqbrSvE6VIGRNmwbnwHPsqVvcTcY0=; b=FGUKBeAURoEDspZaPW+aMnUHm/9D6hijb+iqPsbH2xd+uuc36AVvDPDBPLyJ0e3o8e L5Zf69UR1fXRW5KhqsjkqwaCGmeimdx5Syly07ESxkdMowX0Dts0lO2TOqa7v/PwvqdK jWNwCjJx1KV1ws7zf+MS+/eXk8IwbsXNN1cjvXvJ794i79wnp4FvEE9hNX19EWXFKSlb 6YhnpccM+hZDN+7Ivig6hAIjL17mCK+WgIvC7HB/r4M2vu4DzthRi+QFYoxg4NA6iMyO jrL+0ADjLblTyMED2QR3h+EczXuVfJRaJcgpX9c7LOnDd9tN0C2cj25Vb1HPuTOpzFlS tYvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kxx36+JaRB0XOezqbrSvE6VIGRNmwbnwHPsqVvcTcY0=; b=cCtg3xZD3UuvGy/HgAe7zlsXy89HV0MQuEBLjIMWJFEuiVZiM/m1DnKDXf+x9Zdr+F b/N2IUUjHel9S5MprifduuqUfVuAbZXimoMLt/hYjFSc12zLR3cImP5Vo/FjgxYqwTWe tP3ReOOiF/T5BzesFDV/tE+Z4mctaCNqnIMISc8TJnjxYLddghodd4PwJwnTQ128S8w+ pTozk5KUyDI49Q0PXn6bU6cTgfmU0it8rC3UgIQcQNpWWfGfm0JLVp71tCOKKv47jndH l/w70M+tpXlnMqPyPAi2KMIazqB7K2pBxDC9CG1YvA4MhCWmQHNfc7NSey7lrv6VmKqZ j9RA== X-Gm-Message-State: AOAM533FUwGkLAkmyC+CLc8PVUL387lxC9ERIeeikAzDf/HHilc4XI5Q LCI6w7HIkwlw/Yg3qdszQmWpoqGpiIctFA== X-Google-Smtp-Source: ABdhPJwFe5Grqpya30jelXmnFWGf2x/Dlg/kPfHtFwyENpUO/OdrGnok0zChsw1YHk61Rsl66PJmug== X-Received: by 2002:ac8:6b43:: with SMTP id x3mr14317403qts.190.1633108347187; Fri, 01 Oct 2021 10:12:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 39/41] target/sparc: Make sparc_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:49 -0400 Message-Id: <20211001171151.1739472-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::836; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x836.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633110686644100001 Content-Type: text/plain; charset="utf-8" The fallback code in raise_sigsegv is sufficient for sparc. This makes all of the code in mmu_helper.c sysemu only, so remove the ifdefs and move the file to sparc_softmmu_ss. Remove the code from cpu_loop that handled TT_DFAULT and TT_TFAULT. Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- linux-user/sparc/cpu_loop.c | 25 ------------------------- target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 25 ------------------------- target/sparc/meson.build | 2 +- 4 files changed, 2 insertions(+), 52 deletions(-) diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index ad29b4eb6a..0ba65e431c 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -219,17 +219,6 @@ void cpu_loop (CPUSPARCState *env) case TT_WIN_UNF: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->mmuregs[4]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #else case TT_SPILL: /* window overflow */ save_window(env); @@ -237,20 +226,6 @@ void cpu_loop (CPUSPARCState *env) case TT_FILL: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - if (trapnr =3D=3D TT_DFAULT) - info._sifields._sigfault._addr =3D env->dmmu.mmuregs[4= ]; - else - info._sifields._sigfault._addr =3D cpu_tsptr(env)->tpc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #ifndef TARGET_ABI32 case 0x16e: flush_windows(env); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 21dd27796d..55268ed2a1 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -865,9 +865,9 @@ static const struct SysemuCPUOps sparc_sysemu_ops =3D { static const struct TCGCPUOps sparc_tcg_ops =3D { .initialize =3D sparc_tcg_init, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, - .tlb_fill =3D sparc_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D sparc_cpu_tlb_fill, .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, .do_interrupt =3D sparc_cpu_do_interrupt, .do_transaction_failed =3D sparc_cpu_do_transaction_failed, diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a44473a1c7..2ad47391d0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -25,30 +25,6 @@ =20 /* Sparc MMU emulation */ =20 -#if defined(CONFIG_USER_ONLY) - -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; - - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D TT_TFAULT; - } else { - cs->exception_index =3D TT_DFAULT; -#ifdef TARGET_SPARC64 - env->dmmu.mmuregs[4] =3D address; -#else - env->mmuregs[4] =3D address; -#endif - } - cpu_loop_exit_restore(cs, retaddr); -} - -#else - #ifndef TARGET_SPARC64 /* * Sparc V8 Reference MMU (SRMMU) @@ -926,4 +902,3 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) } return phys_addr; } -#endif diff --git a/target/sparc/meson.build b/target/sparc/meson.build index a3638b9503..a801802ee2 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -6,7 +6,6 @@ sparc_ss.add(files( 'gdbstub.c', 'helper.c', 'ldst_helper.c', - 'mmu_helper.c', 'translate.c', 'win_helper.c', )) @@ -16,6 +15,7 @@ sparc_ss.add(when: 'TARGET_SPARC64', if_true: files('int6= 4_helper.c', 'vis_helpe sparc_softmmu_ss =3D ss.source_set() sparc_softmmu_ss.add(files( 'machine.c', + 'mmu_helper.c', 'monitor.c', )) =20 --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633109614271427.5983752926968; Fri, 1 Oct 2021 10:33:34 -0700 (PDT) Received: from localhost ([::1]:43834 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMPc-00069z-1R for importer@patchew.org; Fri, 01 Oct 2021 13:33:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55718) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM8B-000220-Mn for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:15:31 -0400 Received: from mail-qt1-x833.google.com ([2607:f8b0:4864:20::833]:34318) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM89-0007mi-O6 for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:15:31 -0400 Received: by mail-qt1-x833.google.com with SMTP id m26so9655797qtn.1 for ; Fri, 01 Oct 2021 10:15:29 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id l5sm3697516qtq.4.2021.10.01.10.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:15:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A8ETRQBRZXwQK5lj7iW4qTnPhlNs9ObgZ0AlK9jyPww=; b=vFuynkTVLmhgEsICW00TbB9HI3WxeIqySmsz7K+3vlRNUSkU3U3nOJHP2Hi4uY9vet oqyxTXHO8B7vfYnL6FE4dE4becBZzBFDx+CSL6HMQ2iKGqYUPYlOts3ccW2WRnUlfOHr 2td1Ae7Wf932SSPpmyajOVBOjk2GYIvTCOI6zDI8VlYFgR0kdsPyNRmfnT71MsbppZd2 CvBHBE/27FlaXjpnE3Z4Jc1qpF60hefcFxx5l0CMx8mMciTmPiKOYI5fTV8bIWFZd0Mm p1z4JVeQgu0QinDSVqk7i5hiGQteTPSaEZNGiyJ78Utz+dOHjXhwsTKKFZZ3OC+Kweb8 J6bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A8ETRQBRZXwQK5lj7iW4qTnPhlNs9ObgZ0AlK9jyPww=; b=KcPfj9PMW+so+7LJNBPAncd+mYAycZjdTZt6Cfb+zr7Id983518Tp/CxW5EZZgQeSY hvtgn7lYexPoYJCQPpAKz5sgU1Lor3ORO18/E+7eV4Y474DJzw/PpxLxs52XuMdSPSF5 gL2ou2gpbAr1PtqS/cTQeqv3ALVR4jY+87jA2s2JGpNOJoRgOREdFIDpgf/06yyld2kh ljnZjmRYmvozw/WC/RDouaz1LTfc4lCo3oROM5iL/wDS2kM3FGTczJW1P8WKeMYc9XHQ 79/QleVcO6vj+5+5vRjZjKb2gEgRxtIs+mq+ZhmwhcCiPSzMY5NthiUs8bsOmQSKqPHZ BJzQ== X-Gm-Message-State: AOAM530ia7Qf73tZwU07+oIxRgq5ih2O5kFmHhOs7wXGkqXjDLGPs0oH 1zKTP/rW2+fL8lREuqWktBKxXpBF3djDcA== X-Google-Smtp-Source: ABdhPJwCpn/pOyRB/TECXA6NbhwAefxWtSsJtmh2p77zzhSo+K4RFCNy2olElaaxA3c/YyEGPhu/6w== X-Received: by 2002:a05:622a:147:: with SMTP id v7mr14435760qtw.212.1633108528818; Fri, 01 Oct 2021 10:15:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 40/41] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:50 -0400 Message-Id: <20211001171151.1739472-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::833; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x833.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633109615524100001 Content-Type: text/plain; charset="utf-8" The fallback code in raise_sigsegv is sufficient for xtensa. Remove the code from cpu_loop that raised SIGSEGV. Cc: Max Filippov Signed-off-by: Richard Henderson Acked-by: Max Filippov Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/xtensa/cpu.h | 2 +- linux-user/xtensa/cpu_loop.c | 9 --------- target/xtensa/cpu.c | 2 +- target/xtensa/helper.c | 22 +--------------------- 4 files changed, 3 insertions(+), 32 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index f9a510ca46..02143f2f77 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -563,10 +563,10 @@ struct XtensaCPU { }; =20 =20 +#ifndef CONFIG_USER_ONLY bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index 622afbcd34..a83490ab35 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -226,15 +226,6 @@ void cpu_loop(CPUXtensaState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; =20 - case LOAD_PROHIBITED_CAUSE: - case STORE_PROHIBITED_CAUSE: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr =3D env->sregs[EXCVADDR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - default: fprintf(stderr, "exccause =3D %d\n", env->sregs[EXCCAUSE]); g_assert_not_reached(); diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c1cbd03595..224f723236 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -192,10 +192,10 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = =3D { =20 static const struct TCGCPUOps xtensa_tcg_ops =3D { .initialize =3D xtensa_translate_init, - .tlb_fill =3D xtensa_cpu_tlb_fill, .debug_excp_handler =3D xtensa_breakpoint_handler, =20 #ifndef CONFIG_USER_ONLY + .tlb_fill =3D xtensa_cpu_tlb_fill, .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, .do_interrupt =3D xtensa_cpu_do_interrupt, .do_transaction_failed =3D xtensa_cpu_do_transaction_failed, diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f18ab383fd..29d216ec1b 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -242,27 +242,7 @@ void xtensa_cpu_list(void) } } =20 -#ifdef CONFIG_USER_ONLY - -bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; - - qemu_log_mask(CPU_LOG_INT, - "%s: rw =3D %d, address =3D 0x%08" VADDR_PRIx ", size = =3D %d\n", - __func__, access_type, address, size); - env->sregs[EXCVADDR] =3D address; - env->sregs[EXCCAUSE] =3D (access_type =3D=3D MMU_DATA_STORE ? - STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE= ); - cs->exception_index =3D EXC_USER; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) --=20 2.25.1 From nobody Mon Feb 9 21:47:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633110873030259.5598292474209; Fri, 1 Oct 2021 10:54:33 -0700 (PDT) Received: from localhost ([::1]:39214 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWMjv-00089d-LR for importer@patchew.org; Fri, 01 Oct 2021 13:54:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55724) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWM8C-00024X-9k for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:15:32 -0400 Received: from mail-qt1-x834.google.com ([2607:f8b0:4864:20::834]:34319) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWM8A-0007nf-Lf for qemu-devel@nongnu.org; Fri, 01 Oct 2021 13:15:31 -0400 Received: by mail-qt1-x834.google.com with SMTP id m26so9655851qtn.1 for ; Fri, 01 Oct 2021 10:15:30 -0700 (PDT) Received: from localhost.localdomain (c-67-174-166-185.hsd1.ga.comcast.net. [67.174.166.185]) by smtp.gmail.com with ESMTPSA id l5sm3697516qtq.4.2021.10.01.10.15.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:15:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iPL+UEtKoL8lJ1cyR3L2m8ieOZFTWfsG23UG08w8UQA=; b=lAPempVc8wKoCpsCyl7WPizXjjoRoKUIKutQDgqLcxRhw7QBy0BxLYrht4oKg0isT4 zOlLhpP2bm7/id7TvMYJ1b+GU84WV8m4bso67TY4kY7v/wPtLZwCGzWtFks2nAHiU7gK C0YNteDLdHvMWlrjoi3jwWFPqcuv5FUruHTBldgQavauA0Qf+MgxbS9rWa+uYHBe8aj5 nP3Q2HN9ZyJBRJ5aB2+4dhh+o2wsWRInuzamwdveUZZTSWg7/PAU+O7zLaoUps+gMU0T 3PCTIIXnvUdA1plp4RL/+GgBR8riSefC4Xx35wKauR3oVbZgMUgJDgNzU/JZ6MV8iYt+ MLcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iPL+UEtKoL8lJ1cyR3L2m8ieOZFTWfsG23UG08w8UQA=; b=aiZNJYvtjsMcFHxq3Ye1/sLymfsp5rj65kYGObqC5qP17i5rQSBR9c19JRXWdWfwGc zvh/2W4fCy7uAPhkSyLIMmUbYo2EZc6gcyj9mEFToj+V+eLFL+o+VFRQHIV0gF7rpDxJ SEsvZAfi5Ez3Yvv0fkRGjnMDSnPQbRZt72a3KiOMoiXLD4WglKlP8lJfu3H3dNCQvTp7 Sq4XYspFuRCzTgdxWuT3sJmbrSJ4c4BwzeZrv2S//g9EcRKqbcGBu/W0ByvR2tR44Xp+ lIsEOs8TWcgF7Y+4JSZP1R6aph19spEZg/HVkMVS2iujGjrwTrNLAoQKPPxxJgj0qAr4 ld/A== X-Gm-Message-State: AOAM531w7iRMaImzUuxhcDPNGVkA9+Pae7Ssn65a1WKnTSttp0ttUSAC odwQw76AOmF2NuMu4jgz1/7CWCm3vr3lmQ== X-Google-Smtp-Source: ABdhPJzHFC3svVyqxQADWjy6VBZDGrHRTTk2XDh3VIMaDTjbnaXDe25twIY7MlD5luhNrd3b4rxsxA== X-Received: by 2002:ac8:5685:: with SMTP id h5mr14364478qta.153.1633108529762; Fri, 01 Oct 2021 10:15:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 41/41] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Date: Fri, 1 Oct 2021 13:11:51 -0400 Message-Id: <20211001171151.1739472-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633110873489100001 We have replaced tlb_fill with record_sigsegv for user mod. Move the declaration to restrict it to system emulation. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 22 ++++++++++------------ linux-user/signal.c | 3 --- 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 41718b695b..8eadd404c8 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -35,18 +35,6 @@ struct TCGCPUOps { void (*cpu_exec_enter)(CPUState *cpu); /** @cpu_exec_exit: Callback for cpu_exec cleanup */ void (*cpu_exec_exit)(CPUState *cpu); - /** - * @tlb_fill: Handle a softmmu tlb miss or user-only address fault - * - * For system mode, if the access is valid, call tlb_set_page - * and return true; if the access is invalid, and probe is - * true, return false; otherwise raise an exception and do - * not return. For user-only mode, always raise an exception - * and do not return. - */ - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); =20 @@ -68,6 +56,16 @@ struct TCGCPUOps { #ifdef CONFIG_SOFTMMU /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** + * @tlb_fill: Handle a softmmu tlb miss + * + * If the access is valid, call tlb_set_page and return true; + * if the access is invalid and probe is true, return false; + * otherwise raise an exception and do not return. + */ + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); /** * @do_transaction_failed: Callback for handling failed memory transac= tions * (ie bus faults or external aborts; not MMU faults) diff --git a/linux-user/signal.c b/linux-user/signal.c index 8c22f711f1..d32bc5e1e5 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -694,9 +694,6 @@ void cpu_loop_exit_segv(CPUState *cpu, target_ulong add= r, =20 if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); - } else if (tcg_ops->tlb_fill) { - tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, = ra); - g_assert_not_reached(); } =20 force_sig_fault(TARGET_SIGSEGV, --=20 2.25.1