From nobody Mon Feb 9 14:02:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1632928710351519.4059763327315; Wed, 29 Sep 2021 08:18:30 -0700 (PDT) Received: from localhost ([::1]:40886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVbLl-0003RN-1H for importer@patchew.org; Wed, 29 Sep 2021 11:18:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVbFw-0005at-HB for qemu-devel@nongnu.org; Wed, 29 Sep 2021 11:12:24 -0400 Received: from out4-smtp.messagingengine.com ([66.111.4.28]:34333) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVbFr-0006Ne-LX for qemu-devel@nongnu.org; Wed, 29 Sep 2021 11:12:24 -0400 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.nyi.internal (Postfix) with ESMTP id 0C0655C0167; Wed, 29 Sep 2021 11:12:17 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Wed, 29 Sep 2021 11:12:17 -0400 Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 29 Sep 2021 11:12:16 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=fm3; bh= I3+qvDL6zWSWgYaf+kszEoKeHqmUgf28ArcBTIjLQaw=; b=PgFI7YK4mHjVfnUI MNl0zUHQw0EpDeryi9F101CG1IsYqlS/OmSOeJ5Fa/0FyK0nZ1tFlQzGqWtnFhqD h5hTdxZWY9gh2xwKGrTIm90aosM4feCcMIgvQG03SG9XlVhuWnuSzMbxY99kt/hz MD0TowvYjYd12ENgId262J/ZmNcJ9dfUA75HxwX973827RN65Rf/zT9iSc/mqkq3 vOrojxaLJ9qcQ5uo+bUdRXQAeMJaoaHVFBKP7r/DlDWCSph1nc2pxdE3V6G3vAaz H9GiLQlJmZKPK1glDWQEOkp02BOBxZnQhI4NZ+9lVtpkt0Jxx7mCS8+z3uEMHyeN vnHpSg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; bh=I3+qvDL6zWSWgYaf+kszEoKeHqmUgf28ArcBTIjLQ aw=; b=Prl1M5vUcnAL4uLgiu65zvTVri+aC1S/ttdlZApANl8ZrsmxIR5rZzv4s umPiJBvMwyF0DblunDRBl3PzyfmPGludtjNLtZYH2t5nkf4H/hLM4aWMQYySb3X8 n+7yToqqeH53e77OJnKNsFeU8tcXPddi5BJm3ZY1K2VB4c+paft65s1PWtvZY9UH hZ27OCtzBlzLbGINHDcVCYejxztTI+jASKROtNV07Gbyn8lxGBsJo3VAdCVQnCtw OAVD+ExBaUHnIZn5xYYSH8/bBC5E5V+nNi8W22QGhp/hj2ar/KKc2tcs2j7H72ee prRSUTNrl2BZ/J61h2U+aZ+eeJtlQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudekvddgkeefucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhggtgfgsehtke ertdertdejnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghn ghesfhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepheduvdettdelheehgf egveetkeekhfejvdejtdfguefgkeejtddvveeujeevkeelnecuvehluhhsthgvrhfuihii vgeptdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhi hgohgrthdrtghomh X-ME-Proxy: From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH v2 1/3] hw/mips/boston: Massage memory map information Date: Wed, 29 Sep 2021 16:12:09 +0100 Message-Id: <20210929151211.108-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210929151211.108-1-jiaxun.yang@flygoat.com> References: <20210929151211.108-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.28; envelope-from=jiaxun.yang@flygoat.com; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@syrmia.com, f4bug@amsat.org, paulburton@kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1632928712828100001 Use memmap array to uinfy address of memory map. That would allow us reuse address information for FDT generation. Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daud=C3=A9 -- v2: Fix minor style issue, fix uart map size --- hw/mips/boston.c | 95 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 71 insertions(+), 24 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 20b06865b2..5c720440fb 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -64,6 +64,44 @@ struct BostonState { hwaddr fdt_base; }; =20 +enum { + BOSTON_LOWDDR, + BOSTON_PCIE0, + BOSTON_PCIE1, + BOSTON_PCIE2, + BOSTON_PCIE2_MMIO, + BOSTON_CM, + BOSTON_GIC, + BOSTON_CDMM, + BOSTON_CPC, + BOSTON_PLATREG, + BOSTON_UART, + BOSTON_LCD, + BOSTON_FLASH, + BOSTON_PCIE1_MMIO, + BOSTON_PCIE0_MMIO, + BOSTON_HIGHDDR, +}; + +static const MemMapEntry boston_memmap[] =3D { + [BOSTON_LOWDDR] =3D { 0x0, 0x10000000 }, + [BOSTON_PCIE0] =3D { 0x10000000, 0x2000000 }, + [BOSTON_PCIE1] =3D { 0x12000000, 0x2000000 }, + [BOSTON_PCIE2] =3D { 0x14000000, 0x2000000 }, + [BOSTON_PCIE2_MMIO] =3D { 0x16000000, 0x100000 }, + [BOSTON_CM] =3D { 0x16100000, 0x20000 }, + [BOSTON_GIC] =3D { 0x16120000, 0x20000 }, + [BOSTON_CDMM] =3D { 0x16140000, 0x8000 }, + [BOSTON_CPC] =3D { 0x16200000, 0x8000 }, + [BOSTON_PLATREG] =3D { 0x17ffd000, 0x1000 }, + [BOSTON_UART] =3D { 0x17ffe000, 0x20 }, + [BOSTON_LCD] =3D { 0x17fff000, 0x8 }, + [BOSTON_FLASH] =3D { 0x18000000, 0x8000000 }, + [BOSTON_PCIE1_MMIO] =3D { 0x20000000, 0x20000000 }, + [BOSTON_PCIE0_MMIO] =3D { 0x40000000, 0x40000000 }, + [BOSTON_HIGHDDR] =3D { 0x80000000, 0x0 }, +}; + enum boston_plat_reg { PLAT_FPGA_BUILD =3D 0x00, PLAT_CORE_CL =3D 0x04, @@ -275,24 +313,22 @@ type_init(boston_register_types) =20 static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr) { - const uint32_t cm_base =3D 0x16100000; - const uint32_t gic_base =3D 0x16120000; - const uint32_t cpc_base =3D 0x16200000; - /* Move CM GCRs */ bl_gen_write_ulong(&p, cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BA= SE_OFS), - cm_base); + boston_memmap[BOSTON_CM].base); =20 /* Move & enable GIC GCRs */ bl_gen_write_ulong(&p, - cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE= _OFS), - gic_base | GCR_GIC_BASE_GICEN_MSK); + cpu_mips_phys_to_kseg1(NULL, + boston_memmap[BOSTON_CM].base + GCR_GIC_BASE_O= FS), + boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN= _MSK); =20 /* Move & enable CPC GCRs */ bl_gen_write_ulong(&p, - cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE= _OFS), - cpc_base | GCR_CPC_BASE_CPCEN_MSK); + cpu_mips_phys_to_kseg1(NULL, + boston_memmap[BOSTON_CM].base + GCR_CPC_BASE_O= FS), + boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN= _MSK); =20 /* * Setup argument registers to follow the UHI boot protocol: @@ -333,8 +369,9 @@ static const void *boston_fdt_filter(void *opaque, cons= t void *fdt_orig, ram_low_sz =3D MIN(256 * MiB, machine->ram_size); ram_high_sz =3D machine->ram_size - ram_low_sz; qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg", - 1, 0x00000000, 1, ram_low_sz, - 1, 0x90000000, 1, ram_high_sz); + 1, boston_memmap[BOSTON_LOWDDR].base, 1, = ram_low_sz, + 1, boston_memmap[BOSTON_HIGHDDR].base + r= am_low_sz, + 1, ram_high_sz); =20 fdt =3D g_realloc(fdt, fdt_totalsize(fdt)); qemu_fdt_dumpdtb(fdt, fdt_sz); @@ -438,11 +475,13 @@ static void boston_mach_init(MachineState *machine) sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); =20 flash =3D g_new(MemoryRegion, 1); - memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, + memory_region_init_rom(flash, NULL, "boston.flash", boston_memmap[BOST= ON_FLASH].size, &error_fatal); - memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); + memory_region_add_subregion_overlap(sys_mem, boston_memmap[BOSTON_FLAS= H].base, + flash, 0); =20 - memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram,= 0); + memory_region_add_subregion_overlap(sys_mem, boston_memmap[BOSTON_HIGH= DDR].base, + machine->ram, 0); =20 ddr_low_alias =3D g_new(MemoryRegion, 1); memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", @@ -451,32 +490,40 @@ static void boston_mach_init(MachineState *machine) memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); =20 xilinx_pcie_init(sys_mem, 0, - 0x10000000, 32 * MiB, - 0x40000000, 1 * GiB, + boston_memmap[BOSTON_PCIE0].base, + boston_memmap[BOSTON_PCIE0].size, + boston_memmap[BOSTON_PCIE0_MMIO].base, + boston_memmap[BOSTON_PCIE0_MMIO].size, get_cps_irq(&s->cps, 2), false); =20 xilinx_pcie_init(sys_mem, 1, - 0x12000000, 32 * MiB, - 0x20000000, 512 * MiB, + boston_memmap[BOSTON_PCIE1].base, + boston_memmap[BOSTON_PCIE1].size, + boston_memmap[BOSTON_PCIE1_MMIO].base, + boston_memmap[BOSTON_PCIE1_MMIO].size, get_cps_irq(&s->cps, 1), false); =20 pcie2 =3D xilinx_pcie_init(sys_mem, 2, - 0x14000000, 32 * MiB, - 0x16000000, 1 * MiB, + boston_memmap[BOSTON_PCIE2].base, + boston_memmap[BOSTON_PCIE2].size, + boston_memmap[BOSTON_PCIE2_MMIO].base, + boston_memmap[BOSTON_PCIE2_MMIO].size, get_cps_irq(&s->cps, 0), true); =20 platreg =3D g_new(MemoryRegion, 1); memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, - "boston-platregs", 0x1000); - memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0); + "boston-platregs", + boston_memmap[BOSTON_PLATREG].size); + memory_region_add_subregion_overlap(sys_mem, + boston_memmap[BOSTON_PLATREG].base, platreg, 0); =20 - s->uart =3D serial_mm_init(sys_mem, 0x17ffe000, 2, + s->uart =3D serial_mm_init(sys_mem, boston_memmap[BOSTON_UART].base, 2, get_cps_irq(&s->cps, 3), 10000000, serial_hd(0), DEVICE_NATIVE_ENDIAN); =20 lcd =3D g_new(MemoryRegion, 1); memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8= ); - memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0); + memory_region_add_subregion_overlap(sys_mem, boston_memmap[BOSTON_LCD]= .base, lcd, 0); =20 chr =3D qemu_chr_new("lcd", "vc:320x240", NULL); qemu_chr_fe_init(&s->lcd_display, chr, NULL); --=20 2.30.2 From nobody Mon Feb 9 14:02:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1632928441553927.8516032134755; Wed, 29 Sep 2021 08:14:01 -0700 (PDT) Received: from localhost ([::1]:33798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVbHU-00073D-As for importer@patchew.org; Wed, 29 Sep 2021 11:14:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45098) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVbFu-0005ZQ-2i for qemu-devel@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.28; envelope-from=jiaxun.yang@flygoat.com; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@syrmia.com, f4bug@amsat.org, paulburton@kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1632928442802100001 ELF kernel allows us debugging much easier with DWARF symbols. Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daud=C3=A9 -- v2: Use g_autofree --- hw/mips/boston.c | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 5c720440fb..5d3f054a3e 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" =20 +#include "elf.h" #include "hw/boards.h" #include "hw/char/serial.h" #include "hw/ide/pci.h" @@ -546,10 +547,37 @@ static void boston_mach_init(MachineState *machine) exit(1); } } else if (machine->kernel_filename) { - fit_err =3D load_fit(&boston_fit_loader, machine->kernel_filename,= s); - if (fit_err) { - error_report("unable to load FIT image"); - exit(1); + uint64_t kernel_entry, kernel_low, kernel_high, kernel_size; + + kernel_size =3D load_elf(machine->kernel_filename, NULL, + cpu_mips_kseg0_to_phys, NULL, + (uint64_t *)&kernel_entry, + (uint64_t *)&kernel_low, (uint64_t *)&kernel_hi= gh, + NULL, 0, EM_MIPS, 1, 0); + + if (kernel_size) { + hwaddr dtb_paddr =3D QEMU_ALIGN_UP(kernel_high, 64 * KiB); + hwaddr dtb_vaddr =3D cpu_mips_phys_to_kseg0(NULL, dtb_paddr); + + s->kernel_entry =3D kernel_entry; + if (machine->dtb) { + int dt_size; + g_autofree const void *dtb_file_data, *dtb_load_data; + + dtb_file_data =3D load_device_tree(machine->dtb, &dt_size); + dtb_load_data =3D boston_fdt_filter(s, dtb_file_data, NULL= , &dtb_vaddr); + + /* Calculate real fdt size after filter */ + dt_size =3D fdt_totalsize(dtb_load_data); + rom_add_blob_fixed("dtb", dtb_load_data, dt_size, dtb_padd= r); + } + } else { + /* Try to load file as FIT */ + fit_err =3D load_fit(&boston_fit_loader, machine->kernel_filen= ame, s); + if (fit_err) { + error_report("unable to load kernel image"); + exit(1); + } } =20 gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, --=20 2.30.2 From nobody Mon Feb 9 14:02:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1632928444718996.4381838011452; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.28; envelope-from=jiaxun.yang@flygoat.com; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@syrmia.com, f4bug@amsat.org, paulburton@kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1632928446953100001 Content-Type: text/plain; charset="utf-8" Generate FDT on our own if no dtb argument supplied. Avoid introducing unused device in FDT with user supplied dtb. Signed-off-by: Jiaxun Yang -- v2: Address f4bug cmments (Thanks!) --- hw/mips/boston.c | 234 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 226 insertions(+), 8 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 5d3f054a3e..4c1a951b10 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -49,6 +49,15 @@ typedef struct BostonState BostonState; DECLARE_INSTANCE_CHECKER(BostonState, BOSTON, TYPE_BOSTON) =20 +#define FDT_IRQ_TYPE_NONE 0 +#define FDT_IRQ_TYPE_LEVEL_HIGH 4 +#define FDT_GIC_SHARED 0 +#define FDT_GIC_LOCAL 1 +#define FDT_BOSTON_CLK_SYS 1 +#define FDT_BOSTON_CLK_CPU 2 +#define FDT_PCI_IRQ_MAP_PINS 4 +#define FDT_PCI_IRQ_MAP_DESCS 6 + struct BostonState { SysBusDevice parent_obj; =20 @@ -435,6 +444,213 @@ xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_= nr, return XILINX_PCIE_HOST(dev); } =20 + +static void fdt_create_pcie(void *fdt, int gic_ph, int irq, hwaddr reg_bas= e, + hwaddr reg_size, hwaddr mmio_base, hwaddr mmio= _size) +{ + int i; + char *name, *intc_name; + uint32_t intc_ph; + uint32_t interrupt_map[FDT_PCI_IRQ_MAP_PINS][FDT_PCI_IRQ_MAP_DESCS]; + + intc_ph =3D qemu_fdt_alloc_phandle(fdt); + name =3D g_strdup_printf("/soc/pci@%" HWADDR_PRIx, reg_base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "xlnx,axi-pcie-host-1= .00.a"); + qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); + qemu_fdt_setprop_cells(fdt, name, "reg", reg_base, reg_size); + + qemu_fdt_setprop_cell(fdt, name, "#address-cells", 3); + qemu_fdt_setprop_cell(fdt, name, "#size-cells", 2); + qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", 1); + + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", gic_ph); + qemu_fdt_setprop_cells(fdt, name, "interrupts", FDT_GIC_SHARED, irq, + FDT_IRQ_TYPE_LEVEL_HIGH); + + qemu_fdt_setprop_cells(fdt, name, "ranges", 0x02000000, 0, mmio_base, + mmio_base, 0, mmio_size); + qemu_fdt_setprop_cells(fdt, name, "bus-range", 0x00, 0xff); + + + + intc_name =3D g_strdup_printf("%s/interrupt-controller", name); + qemu_fdt_add_subnode(fdt, intc_name); + qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(fdt, intc_name, "#address-cells", 0); + qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); + qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_ph); + + qemu_fdt_setprop_cells(fdt, name, "interrupt-map-mask", 0, 0, 0, 7); + for (i =3D 0; i < FDT_PCI_IRQ_MAP_PINS; i++) { + uint32_t *irqmap =3D interrupt_map[i]; + + irqmap[0] =3D cpu_to_be32(0); + irqmap[1] =3D cpu_to_be32(0); + irqmap[2] =3D cpu_to_be32(0); + irqmap[3] =3D cpu_to_be32(i + 1); + irqmap[4] =3D cpu_to_be32(intc_ph); + irqmap[5] =3D cpu_to_be32(i + 1); + } + qemu_fdt_setprop(fdt, name, "interrupt-map", &interrupt_map, sizeof(in= terrupt_map)); + + g_free(intc_name); + g_free(name); +} + +static const void *create_fdt(BostonState *s, const MemMapEntry *memmap, i= nt *dt_size) +{ + void *fdt; + int cpu; + MachineState *mc =3D s->mach; + uint32_t platreg_ph, gic_ph, clk_ph; + char *name, *gic_name, *platreg_name, *stdout_name; + static const char * const syscon_compat[2] =3D {"img,boston-platform-r= egs", "syscon"}; + + fdt =3D create_device_tree(dt_size); + if (!fdt) { + error_report("create_device_tree() failed"); + exit(1); + } + + platreg_ph =3D qemu_fdt_alloc_phandle(fdt); + gic_ph =3D qemu_fdt_alloc_phandle(fdt); + clk_ph =3D qemu_fdt_alloc_phandle(fdt); + + qemu_fdt_setprop_string(fdt, "/", "model", "img,boston"); + qemu_fdt_setprop_string(fdt, "/", "compatible", "img,boston"); + qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1); + qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1); + + + qemu_fdt_add_subnode(fdt, "/cpus"); + qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); + qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); + + for (cpu =3D 0; cpu < mc->smp.cpus; cpu++) { + name =3D g_strdup_printf("/cpus/cpu@%d", cpu); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "img,mips"); + qemu_fdt_setprop_string(fdt, name, "status", "okay"); + qemu_fdt_setprop_cell(fdt, name, "reg", cpu); + qemu_fdt_setprop_string(fdt, name, "device_type", "cpu"); + qemu_fdt_setprop_cells(fdt, name, "clocks", clk_ph, FDT_BOSTON_CLK= _CPU); + g_free(name); + } + + qemu_fdt_add_subnode(fdt, "/soc"); + qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); + qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); + qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1); + qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x1); + + fdt_create_pcie(fdt, gic_ph, 2, memmap[BOSTON_PCIE0].base, memmap[BOST= ON_PCIE0].size, + memmap[BOSTON_PCIE0_MMIO].base, memmap[BOSTON_PCIE0_MM= IO].size); + + fdt_create_pcie(fdt, gic_ph, 1, memmap[BOSTON_PCIE1].base, memmap[BOST= ON_PCIE1].size, + memmap[BOSTON_PCIE1_MMIO].base, memmap[BOSTON_PCIE1_MM= IO].size); + + fdt_create_pcie(fdt, gic_ph, 0, memmap[BOSTON_PCIE2].base, memmap[BOST= ON_PCIE2].size, + memmap[BOSTON_PCIE2_MMIO].base, memmap[BOSTON_PCIE2_MM= IO].size); + + /* GIC with it's timer node */ + gic_name =3D g_strdup_printf("/soc/interrupt-controller@%" HWADDR_PRIx, + memmap[BOSTON_GIC].base); + qemu_fdt_add_subnode(fdt, gic_name); + qemu_fdt_setprop_string(fdt, gic_name, "compatible", "mti,gic"); + qemu_fdt_setprop_cells(fdt, gic_name, "reg", memmap[BOSTON_GIC].base, + memmap[BOSTON_GIC].size); + qemu_fdt_setprop(fdt, gic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(fdt, gic_name, "#interrupt-cells", 3); + qemu_fdt_setprop_cell(fdt, gic_name, "phandle", gic_ph); + + name =3D g_strdup_printf("%s/timer", gic_name); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "mti,gic-timer"); + qemu_fdt_setprop_cells(fdt, name, "interrupts", FDT_GIC_LOCAL, 1, + FDT_IRQ_TYPE_NONE); + qemu_fdt_setprop_cells(fdt, name, "clocks", clk_ph, FDT_BOSTON_CLK_CPU= ); + g_free(name); + g_free(gic_name); + + /* CDMM node */ + name =3D g_strdup_printf("/soc/cdmm@%" HWADDR_PRIx, memmap[BOSTON_CDMM= ].base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "mti,mips-cdmm"); + qemu_fdt_setprop_cells(fdt, name, "reg", memmap[BOSTON_CDMM].base, + memmap[BOSTON_CDMM].size); + g_free(name); + + /* CPC node */ + name =3D g_strdup_printf("/soc/cpc@%" HWADDR_PRIx, memmap[BOSTON_CPC].= base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "mti,mips-cpc"); + qemu_fdt_setprop_cells(fdt, name, "reg", memmap[BOSTON_CPC].base, + memmap[BOSTON_CPC].size); + g_free(name); + + /* platreg and it's clk node */ + platreg_name =3D g_strdup_printf("/soc/system-controller@%" HWADDR_PRI= x, + memmap[BOSTON_PLATREG].base); + qemu_fdt_add_subnode(fdt, platreg_name); + qemu_fdt_setprop_string_array(fdt, platreg_name, "compatible", + (char **)&syscon_compat, + ARRAY_SIZE(syscon_compat)); + qemu_fdt_setprop_cells(fdt, platreg_name, "reg", memmap[BOSTON_PLATREG= ].base, + memmap[BOSTON_PLATREG].size); + qemu_fdt_setprop_cell(fdt, platreg_name, "phandle", platreg_ph); + + name =3D g_strdup_printf("%s/clock", platreg_name); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "img,boston-clock"); + qemu_fdt_setprop_cell(fdt, name, "#clock-cells", 1); + qemu_fdt_setprop_cell(fdt, name, "phandle", clk_ph); + g_free(name); + g_free(platreg_name); + + /* reboot node */ + name =3D g_strdup_printf("/soc/reboot"); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); + qemu_fdt_setprop_cell(fdt, name, "regmap", platreg_ph); + qemu_fdt_setprop_cell(fdt, name, "offset", 0x10); + qemu_fdt_setprop_cell(fdt, name, "mask", 0x10); + g_free(name); + + /* uart node */ + name =3D g_strdup_printf("/soc/uart@%" HWADDR_PRIx, memmap[BOSTON_UART= ].base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); + qemu_fdt_setprop_cells(fdt, name, "reg", memmap[BOSTON_UART].base, + memmap[BOSTON_UART].size); + qemu_fdt_setprop_cell(fdt, name, "reg-shift", 0x2); + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", gic_ph); + qemu_fdt_setprop_cells(fdt, name, "interrupts", FDT_GIC_SHARED, 3, + FDT_IRQ_TYPE_LEVEL_HIGH); + qemu_fdt_setprop_cells(fdt, name, "clocks", clk_ph, FDT_BOSTON_CLK_SYS= ); + + qemu_fdt_add_subnode(fdt, "/chosen"); + stdout_name =3D g_strdup_printf("%s:115200", name); + qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", stdout_name); + g_free(stdout_name); + g_free(name); + + /* lcd node */ + name =3D g_strdup_printf("/soc/lcd@%" HWADDR_PRIx, memmap[BOSTON_LCD].= base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "img,boston-lcd"); + qemu_fdt_setprop_cells(fdt, name, "reg", memmap[BOSTON_LCD].base, + memmap[BOSTON_LCD].size); + g_free(name); + + name =3D g_strdup_printf("/memory@0"); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); + g_free(name); + + return fdt; +} + static void boston_mach_init(MachineState *machine) { DeviceState *dev; @@ -556,21 +772,23 @@ static void boston_mach_init(MachineState *machine) NULL, 0, EM_MIPS, 1, 0); =20 if (kernel_size) { + int dt_size; + g_autofree const void *dtb_file_data, *dtb_load_data; hwaddr dtb_paddr =3D QEMU_ALIGN_UP(kernel_high, 64 * KiB); hwaddr dtb_vaddr =3D cpu_mips_phys_to_kseg0(NULL, dtb_paddr); =20 s->kernel_entry =3D kernel_entry; if (machine->dtb) { - int dt_size; - g_autofree const void *dtb_file_data, *dtb_load_data; - dtb_file_data =3D load_device_tree(machine->dtb, &dt_size); - dtb_load_data =3D boston_fdt_filter(s, dtb_file_data, NULL= , &dtb_vaddr); - - /* Calculate real fdt size after filter */ - dt_size =3D fdt_totalsize(dtb_load_data); - rom_add_blob_fixed("dtb", dtb_load_data, dt_size, dtb_padd= r); + } else { + dtb_file_data =3D create_fdt(s, boston_memmap, &dt_size); } + + dtb_load_data =3D boston_fdt_filter(s, dtb_file_data, NULL, &d= tb_vaddr); + + /* Calculate real fdt size after filter */ + dt_size =3D fdt_totalsize(dtb_load_data); + rom_add_blob_fixed("dtb", dtb_load_data, dt_size, dtb_paddr); } else { /* Try to load file as FIT */ fit_err =3D load_fit(&boston_fit_loader, machine->kernel_filen= ame, s); --=20 2.30.2