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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id c132sm15873859wma.22.2021.09.25.07.53.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Sep 2021 07:53:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IiP54nTlira6zI1808uaFu0plQ+4ScQiNyLo+fDpcgY=; b=oa9N22veagxHVmHotr3xEvh0pdMb0uSKgqnKR1v15a7I8NE3DfxoWbsyw4DBFZspI7 jAIociFOwzbZX0OC0DzztlZ3Bd63o9jtbmV1eNjUg5g+lwkM4C4fT8lnNDvvI4JCY0pb JuBL+n5N5DHcnaDXuAoeDBUHAF79oFI8mpBeUyuWb+KthCDIMwZ+DxqqipW0i6Os4vyY CMfFwfw4WvPflHgwguRmWAMhj8xk/7hvTu9OefUXHNS8YS0pioV7dY9KiYiPqAlKWKZf 3bE8qcnljbGvYgV/3s1ingfgfs0D1W3LlQjsfrrypkLlgcXOWZy1hLOuqWpld2JrvfWc MxmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=IiP54nTlira6zI1808uaFu0plQ+4ScQiNyLo+fDpcgY=; b=JibYHRzRDYazbotoTYfjOWWlMRC+CeDwWJMTxsx+Q2mIBvUHU4hYEvxcrxOuWPCnE6 SDt+5+iyap5xQAIiANIgEHBacarTtx5GyBCb/OhFtdo7pM5bbcblYMDhJiwn7moMAk/M FNiljxNXGDW78xEeWiIu/8fO8ZM5WX18QrBQ8wdfkRNPsUkviT7dWI11UUk2+MWhxKIm Z/kMJPqbw2yn1NQCF84sAevh8PKw+K5yJAf+aGXzfOBrw2ygjysX6nh1Qc4lSH3J306Y vF7F/LqwCBBtXIVBAj5oDmGOhZuAfUM6dXjqlJcKbnd9wKeH1TEmy1hgfTSZ9ErdzeOU U4Vw== X-Gm-Message-State: AOAM532K4AjeyrLvoowvQfToQc4e0BFOYA0CjVQiSdTliW0FtvL/U7I2 wY4KqLQhJ2wyecLNcMT/KJU= X-Google-Smtp-Source: ABdhPJw0ZKv5G6qL/TsD0qZhdNETmr67E8gkLaWoXIQwbJfheOBtp9UTy7Ig0OZPSOtwh3h4gCNmcg== X-Received: by 2002:a05:600c:2109:: with SMTP id u9mr7226486wml.6.1632581622819; Sat, 25 Sep 2021 07:53:42 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Gibson , Greg Kurz , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs) Subject: [PATCH v7 30/40] target/ppc: Restrict has_work() handlers to sysemu and TCG Date: Sat, 25 Sep 2021 16:51:08 +0200 Message-Id: <20210925145118.1361230-31-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210925145118.1361230-1-f4bug@amsat.org> References: <20210925145118.1361230-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1632581626183100001 Restrict PowerPCCPUClass::has_work() and ppc_cpu_has_work() - SysemuCPUOps::has_work() implementation - to TCG sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/ppc/cpu-qom.h | 4 +++- target/ppc/cpu_init.c | 24 ++++++++++++++++++------ 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 36110112506..ff2bafcde6f 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -188,8 +188,10 @@ struct PowerPCCPUClass { uint32_t flags; int bfd_mach; uint32_t l1_dcache_size, l1_icache_size; - bool (*has_work)(CPUState *cpu); #ifndef CONFIG_USER_ONLY +#ifdef CONFIG_TCG + bool (*has_work)(CPUState *cpu); +#endif /* CONFIG_TCG */ unsigned int gdb_num_sprs; const char *gdb_spr_xml; #endif diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 2f7d262b176..5c134adeea9 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7583,6 +7583,7 @@ static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc= , uint32_t pvr) return false; } =20 +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool cpu_has_work_POWER7(CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -7616,6 +7617,7 @@ static bool cpu_has_work_POWER7(CPUState *cs) return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); } } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) { @@ -7629,7 +7631,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->pcr_supported =3D PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER7; pcc->check_pow =3D check_pow_nocheck; - pcc->has_work =3D cpu_has_work_POWER7; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -7672,6 +7673,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->lpcr_pm =3D LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; pcc->mmu_model =3D POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) + pcc->has_work =3D cpu_has_work_POWER7; pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; pcc->lrg_decr_bits =3D 32; #endif @@ -7742,6 +7744,7 @@ static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc= , uint32_t pvr) return false; } =20 +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool cpu_has_work_POWER8(CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -7783,6 +7786,7 @@ static bool cpu_has_work_POWER8(CPUState *cs) return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); } } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) { @@ -7796,7 +7800,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->pcr_supported =3D PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_= 2_05; pcc->init_proc =3D init_proc_POWER8; pcc->check_pow =3D check_pow_nocheck; - pcc->has_work =3D cpu_has_work_POWER8; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -7846,6 +7849,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) LPCR_P8_PECE3 | LPCR_P8_PECE4; pcc->mmu_model =3D POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) + pcc->has_work =3D cpu_has_work_POWER8; pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; pcc->lrg_decr_bits =3D 32; pcc->n_host_threads =3D 8; @@ -7939,6 +7943,7 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc= , uint32_t pvr) return false; } =20 +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool cpu_has_work_POWER9(CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -7996,6 +8001,7 @@ static bool cpu_has_work_POWER9(CPUState *cs) return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); } } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) { @@ -8010,7 +8016,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER9; pcc->check_pow =3D check_pow_nocheck; - pcc->has_work =3D cpu_has_work_POWER9; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -8059,6 +8064,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; pcc->mmu_model =3D POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) + pcc->has_work =3D cpu_has_work_POWER9; /* segment page size remain the same */ pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; pcc->radix_page_info =3D &POWER9_radix_page_info; @@ -8147,6 +8153,7 @@ static bool ppc_pvr_match_power10(PowerPCCPUClass *pc= c, uint32_t pvr) return false; } =20 +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool cpu_has_work_POWER10(CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -8204,6 +8211,7 @@ static bool cpu_has_work_POWER10(CPUState *cs) return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); } } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) { @@ -8219,7 +8227,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER10; pcc->check_pow =3D check_pow_nocheck; - pcc->has_work =3D cpu_has_work_POWER10; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -8271,6 +8278,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; pcc->mmu_model =3D POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) + pcc->has_work =3D cpu_has_work_POWER10; /* segment page size remain the same */ pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; pcc->radix_page_info =3D &POWER10_radix_page_info; @@ -8786,6 +8794,7 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.nip =3D value; } =20 +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool cpu_has_work_default(CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -8801,6 +8810,7 @@ static bool ppc_cpu_has_work(CPUState *cs) =20 return pcc->has_work(cs); } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 static void ppc_cpu_reset(DeviceState *dev) { @@ -9021,6 +9031,7 @@ static const struct TCGCPUOps ppc_tcg_ops =3D { .tlb_fill =3D ppc_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .has_work =3D ppc_cpu_has_work, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .do_interrupt =3D ppc_cpu_do_interrupt, .cpu_exec_enter =3D ppc_cpu_exec_enter, @@ -9041,13 +9052,11 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, &pcc->parent_unrealize); pcc->pvr_match =3D ppc_pvr_match_default; - pcc->has_work =3D cpu_has_work_default; device_class_set_props(dc, ppc_cpu_properties); =20 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); =20 cc->class_by_name =3D ppc_cpu_class_by_name; - cc->has_work =3D ppc_cpu_has_work; cc->dump_state =3D ppc_cpu_dump_state; cc->set_pc =3D ppc_cpu_set_pc; cc->gdb_read_register =3D ppc_cpu_gdb_read_register; @@ -9078,6 +9087,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, void = *data) =20 #ifdef CONFIG_TCG cc->tcg_ops =3D &ppc_tcg_ops; +#ifndef CONFIG_USER_ONLY + pcc->has_work =3D cpu_has_work_default; +#endif #endif /* CONFIG_TCG */ } =20 --=20 2.31.1