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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id i2sm11055407wrq.78.2021.09.25.07.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Sep 2021 07:52:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UE09P3+95R7azQiB3uAxKhFAUsJxXecPBFCz3ofDdJY=; b=m8uSzJJW5RbcD9v9b60DsxXyfZ8QYa5zKCrKDSbEKmRpjpjCykjDR1iOwS025VCpI5 dvKNxMPoyGFGX1l6OQkuho7vDjhsD8N/+605Br3KKhh7JVh4iYRvAlmYhvl8aXx0+rEq KqArJgcaa2rUbO0jIM1Re+vP0yW7aEr7gRn3nQJ26UwV/slNVSVT+U+PmahlhvEnOAPy zXeozL9OsjqENrKfiX1rozhV32LX/ehCc2SJniHaqQQ0XeHk75F9qKhRQo63smQxQihB 8AK2qb53yI6Qn37olIzRB+J+RiDG52jGE/2XLAhPXfXL+fdoL85OygikxHVjDmgcliE6 MnQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UE09P3+95R7azQiB3uAxKhFAUsJxXecPBFCz3ofDdJY=; b=hiriz8W6Dv98JwSOjaeF3F4KPTJDQvXHth4H4z17iEhS+4NhBMj9Ynvo4lJrNdZjIt HBnZFOZ8EglY3lvvZDqhm4VtU0DbQ/pRh+kJ44hLBuBSqJp6TOAHRAFOF+IXfNByCij9 ffw+55ho0NjkWAP1biRwn9XesowCKGnAX+kMDMc3MlfgiIAPsgczfRqeXi3EyQtOkXCL TKPrxDDli/EKE3ojk/umd1CG3KWoumpuF5WgQ3MoP7nBCDR6E+NcPblKKw66LwXT0a6X XOIji4gqZG1oq3hTGQDbqGhPhQIFzmUSRMqyl9jjmwIQ8KOCUillI7jO8jx67V64aGtH 6EKg== X-Gm-Message-State: AOAM531zMvGM+YAkUIPVvEpKvd9ZR4WXmcCn3FUyx9cQ1lLu/ANNh17w urROGeRASy7aFDLCgsSdIYyk4tMCGAg= X-Google-Smtp-Source: ABdhPJyOLg57AmHUcQNdi7KECrCqsQlmtqA6jqOtdUamLcrKxYhFA3ap/TRSZNYmaVF75G8uOcY0FA== X-Received: by 2002:a5d:4d02:: with SMTP id z2mr18010911wrt.8.1632581555396; Sat, 25 Sep 2021 07:52:35 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v7 16/40] target/arm: Explicit v7M cores use arm_cpu_has_work as CPUClass:has_work Date: Sat, 25 Sep 2021 16:50:54 +0200 Message-Id: <20210925145118.1361230-17-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210925145118.1361230-1-f4bug@amsat.org> References: <20210925145118.1361230-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1632581558842100001 ARM v7M cores inherit TYPE_ARM_CPU, so TYPE_ARM_CPU's class_init runs first and sets up most of the class fields, setting in particular the has_work handler to the generic arm_cpu_has_work(). Thus M-profile and A-profile share the same arm_cpu_has_work() function. Some of the checks the code there does are perhaps unnecessary for M-profile, but they're harmless. Since we want to move the has_work handler from CPUClass to TCGCPUOps, the next commit will be more explicit if we already register this handler in arm_v7m_class_init(). Since arm_cpu_has_work() is static to target/arm/cpu.c, we have to declare it in "internals.h" to be able to use it in target/arm/cpu_tcg.c. Suggested-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 2 ++ target/arm/cpu.c | 2 +- target/arm/cpu_tcg.c | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 9fbb3649682..f20aeb97fa0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -177,6 +177,8 @@ void arm_translate_init(void); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ =20 +bool arm_cpu_has_work(CPUState *cs); + /** * aarch64_sve_zcr_get_valid_len: * @cpu: cpu context diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 641a8c2d3d3..4b08f717f64 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -76,7 +76,7 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, } #endif /* CONFIG_TCG */ =20 -static bool arm_cpu_has_work(CPUState *cs) +bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0d5adccf1a7..9a0927ad5d0 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -920,6 +920,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *d= ata) =20 acc->info =3D data; #ifdef CONFIG_TCG + cc->has_work =3D arm_cpu_has_work; cc->tcg_ops =3D &arm_v7m_tcg_ops; #endif /* CONFIG_TCG */ =20 --=20 2.31.1