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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id o12sm10847045wms.15.2021.09.25.06.34.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Sep 2021 06:34:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b6QGRmQhDU8FF6ADnmxpod9FuARIY1Cf+w68oJokGzU=; b=U8OUkDUoE0kk8CcZBG64X0T8EdwalePjeZBqA8qwTGZJfjlRiGp5i51DzJ5dbgu5Da 9lNhph7Qfoapq2leTUZOMrneGDyvHGtlLSQrTLI6oGvBcBVX9w1e2yGTlR4ftVc8BLDY dtW1iCmYQzQgYplKqAmUVJphH7CH5jtfXHv5OG11Nh4Eide/J3h9SMEHfWJgh7gqIAAu SD7uAQ+NRKPFBqiE0inO26v2KzM4CqgJIfD0VdFH/rrCdI1d02asQ5xYyQwFsALexiOM 1e8UER2nps77Hdxksnd6LTHOtZUz/Ds6JfYWBDSrrRac3Tg+Af9l4V0fsldZTf2fyo68 s1Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=b6QGRmQhDU8FF6ADnmxpod9FuARIY1Cf+w68oJokGzU=; b=tVo3YWkf8qmiuw7ds/Ue07uZEnJf+cbqvKrXu3N1j6ZCsIxYfWpL6sAiErtSW+QDlk kbwM11xWxi4Vgo6RrqpVQpCYnEcaNsIUTyv7WZNxGk775Krx3Rwjnn90QLlF62JcVhNF k9cZc0Ib1CcUGNlRFmvRwNHd1EA1q6PFiMXxz78Va91SqXKAjV8nenedx1He7uCLD6+z vfr+B6n7KtvpweCpmpSynPp8nuM7uGAPb2VpmSQqPUWL/XfTPLK5ZhV8P1AYNB3YzTTu Ej0E5almZ7c699pSk8OQ6QyuIN8m9xsE0xT3+uB+6+M4DImc0owXZho/a6ps1PlDcTUj Vw5A== X-Gm-Message-State: AOAM5323Mva1uKQg5/7uY5ucWN2yUx2uTaa/bZU8dzvbkpkkQ4vGCF8Q ySVxCP1/KD1cFRjnwGs/6Ec= X-Google-Smtp-Source: ABdhPJwJeaZexEvLD2HsCaeHLXuER5kn+kLWsDGQ524v6mdF7Fsg0LaEX/usXU3qaLzxxX17jkv+IQ== X-Received: by 2002:adf:ecd2:: with SMTP id s18mr16941594wro.99.1632576864520; Sat, 25 Sep 2021 06:34:24 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Bin Meng , Alistair Francis , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH v2 3/3] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART Date: Sat, 25 Sep 2021 15:34:07 +0200 Message-Id: <20210925133407.1259392-4-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210925133407.1259392-1-f4bug@amsat.org> References: <20210925133407.1259392-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1632576867913100001 - Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it - Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize() - Add DeviceReset() method - Add vmstate structure for migration - Register device in 'input' category - Keep mchp_pfsoc_mmuart_create() behavior Note, serial_mm_init() calls qdev_set_legacy_instance_id(). This call is only needed for backwards-compatibility of incoming migration data with old versions of QEMU which implemented migration of devices with hand-rolled code. Since this device didn't previously handle migration at all, then it doesn't need to set the legacy instance ID. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- Cc: Peter Maydell I haven't kept Alistair R-b tag from v1. --- include/hw/char/mchp_pfsoc_mmuart.h | 12 +++- hw/char/mchp_pfsoc_mmuart.c | 105 +++++++++++++++++++++++----- 2 files changed, 97 insertions(+), 20 deletions(-) diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfs= oc_mmuart.h index 864ac1a36b5..b0e14ca3554 100644 --- a/include/hw/char/mchp_pfsoc_mmuart.h +++ b/include/hw/char/mchp_pfsoc_mmuart.h @@ -28,17 +28,23 @@ #ifndef HW_MCHP_PFSOC_MMUART_H #define HW_MCHP_PFSOC_MMUART_H =20 +#include "hw/sysbus.h" #include "hw/char/serial.h" =20 #define MCHP_PFSOC_MMUART_REG_COUNT 13 =20 +#define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart" +OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART) + typedef struct MchpPfSoCMMUartState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ MemoryRegion container; MemoryRegion iomem; - hwaddr base; - qemu_irq irq; =20 - SerialMM *serial; + SerialMM serial_mm; =20 uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT]; } MchpPfSoCMMUartState; diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c index ea586559761..22f3e78eb9e 100644 --- a/hw/char/mchp_pfsoc_mmuart.c +++ b/hw/char/mchp_pfsoc_mmuart.c @@ -22,8 +22,10 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "chardev/char.h" +#include "qapi/error.h" +#include "migration/vmstate.h" #include "hw/char/mchp_pfsoc_mmuart.h" +#include "hw/qdev-properties.h" =20 #define REGS_OFFSET 0x20 =20 @@ -67,26 +69,95 @@ static const MemoryRegionOps mchp_pfsoc_mmuart_ops =3D { }, }; =20 -MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, - hwaddr base, qemu_irq irq, Chardev *chr) +static void mchp_pfsoc_mmuart_reset(DeviceState *dev) { - MchpPfSoCMMUartState *s; + MchpPfSoCMMUartState *s =3D MCHP_PFSOC_UART(dev); =20 - s =3D g_new0(MchpPfSoCMMUartState, 1); + memset(s->reg, 0, sizeof(s->reg)); + device_cold_reset(DEVICE(&s->serial_mm)); +} =20 - memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000); +static void mchp_pfsoc_mmuart_init(Object *obj) +{ + MchpPfSoCMMUartState *s =3D MCHP_PFSOC_UART(obj); =20 - memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s, + object_initialize_child(obj, "serial-mm", &s->serial_mm, TYPE_SERIAL_M= M); + object_property_add_alias(obj, "chardev", OBJECT(&s->serial_mm), "char= dev"); +} + +static void mchp_pfsoc_mmuart_realize(DeviceState *dev, Error **errp) +{ + MchpPfSoCMMUartState *s =3D MCHP_PFSOC_UART(dev); + + qdev_prop_set_uint8(DEVICE(&s->serial_mm), "regshift", 2); + qdev_prop_set_uint32(DEVICE(&s->serial_mm), "baudbase", 399193); + qdev_prop_set_uint8(DEVICE(&s->serial_mm), "endianness", + DEVICE_LITTLE_ENDIAN); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->serial_mm), errp)) { + return; + } + + sysbus_pass_irq(SYS_BUS_DEVICE(dev), SYS_BUS_DEVICE(&s->serial_mm)); + + memory_region_init(&s->container, OBJECT(s), "mchp.pfsoc.mmuart", 0x10= 00); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); + + memory_region_add_subregion(&s->container, 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial_mm), = 0)); + + memory_region_init_io(&s->iomem, OBJECT(s), &mchp_pfsoc_mmuart_ops, s, "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET); memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem); - - s->base =3D base; - s->irq =3D irq; - - s->serial =3D serial_mm_init(&s->container, 0, 2, irq, 399193, chr, - DEVICE_LITTLE_ENDIAN); - - memory_region_add_subregion(sysmem, base, &s->container); - - return s; +} + +static const VMStateDescription mchp_pfsoc_mmuart_vmstate =3D { + .name =3D "mchp.pfsoc.uart", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(reg, MchpPfSoCMMUartState, + MCHP_PFSOC_MMUART_REG_COUNT), + VMSTATE_END_OF_LIST() + } +}; + +static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D mchp_pfsoc_mmuart_realize; + dc->reset =3D mchp_pfsoc_mmuart_reset; + dc->vmsd =3D &mchp_pfsoc_mmuart_vmstate; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); +} + +static const TypeInfo mchp_pfsoc_mmuart_info =3D { + .name =3D TYPE_MCHP_PFSOC_UART, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MchpPfSoCMMUartState), + .instance_init =3D mchp_pfsoc_mmuart_init, + .class_init =3D mchp_pfsoc_mmuart_class_init, +}; + +static void mchp_pfsoc_mmuart_register_types(void) +{ + type_register_static(&mchp_pfsoc_mmuart_info); +} + +type_init(mchp_pfsoc_mmuart_register_types) + +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, + hwaddr base, + qemu_irq irq, Chardev *chr) +{ + DeviceState *dev =3D qdev_new(TYPE_MCHP_PFSOC_UART); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + qdev_prop_set_chr(dev, "chardev", chr); + sysbus_realize(sbd, &error_fatal); + + memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(sbd, = 0)); + sysbus_connect_irq(sbd, 0, irq); + + return MCHP_PFSOC_UART(dev); } --=20 2.31.1