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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id x4sm3306588wmi.22.2021.09.25.06.34.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Sep 2021 06:34:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7I1aMI8lm45lQRDER9IXlE6p2aeABd+5vqCVhp5uc+w=; b=n4R5U8P3qzimBg7X1FOQsAjZtIFJ7JpOZP3uSB1w/AGD6X+i5pBAHsC5t4blQvU8DD yjsQQDk3+jyK5gyehnfsKRwtbFGXNavcVQAhT9koYeHOYjNm9Nu08o7SB8ezHbdAgXKq bl4eUnuCnbNmyvo6wOKsA3it+gup8AfKjgD2A8dgDVnwU3UijHMIwJm4JakMmp95mpdf FIJy5tljjHplKiNDf91o8nK4SmnHTP/Lt+25akCjoxpOq7Qyxb4gCfsn9zieN3AD7nR7 YaEdmK5JRJAc/Xdxee8rUg+DvuCD344zCQRLB3KarTXQ6xnL1xrtiwSj3S7TPTtNAQd6 AbLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=7I1aMI8lm45lQRDER9IXlE6p2aeABd+5vqCVhp5uc+w=; b=7JC66Ii2Qi5JJ7O8OVgmz1gpFeDXCdu3npvwrXmMEaiT9Pr7qwyVwlMiPJhYh1R7m1 8MALqKJFCf/Z2yX3hwFI8exrm7wEOAbt3b1QevZm1kOz6IVhQvHM+JgT+9yFHbBWmTMK J+lXfdcRS8zgKtZA0RqDrPHxG7995aEyBCLAbRMW0M/R2zFaVnwrX2KXxyrPtBdOKwp1 YJg1LjqwGnedgOJ6EVdbsgxBl1UrebIpn2WvPjKY5CmKPk5FU0fteFxUqELEEwZQf0Ay 7wTrsP6Mqp00HoGVHUdu1qJZS/8Rd0lUSn13Lj4jD61c1KqFgqjnwDiWCSSfT3HwWo7a 7+ag== X-Gm-Message-State: AOAM532DL74CnCoszxjoKs48HkF6qzi0covVG8T74rE5bRfansy8uMH4 AVXdL3yB52TB7tlGivzSh8c= X-Google-Smtp-Source: ABdhPJzAshCviCH1lX89S+tc2UXSWqxuQy/qblI9F1SVPsyPnwO3BcAlNy4YZrb6T8WYI3/nYO0XXA== X-Received: by 2002:a7b:ce94:: with SMTP id q20mr7333890wmj.83.1632576854849; Sat, 25 Sep 2021 06:34:14 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Bin Meng , Alistair Francis , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/3] hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition Date: Sat, 25 Sep 2021 15:34:05 +0200 Message-Id: <20210925133407.1259392-2-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210925133407.1259392-1-f4bug@amsat.org> References: <20210925133407.1259392-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1632576857019100001 The current MCHP_PFSOC_MMUART_REG_SIZE definition represent the size occupied by all the registers. However all registers are 32-bit wide, and the MemoryRegionOps handlers are restricted to 32-bit: static const MemoryRegionOps mchp_pfsoc_mmuart_ops =3D { .read =3D mchp_pfsoc_mmuart_read, .write =3D mchp_pfsoc_mmuart_write, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, Avoid being triskaidekaphobic, simplify by using the number of registers. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- include/hw/char/mchp_pfsoc_mmuart.h | 4 ++-- hw/char/mchp_pfsoc_mmuart.c | 14 ++++++++------ 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfs= oc_mmuart.h index f61990215f0..9c012e6c977 100644 --- a/include/hw/char/mchp_pfsoc_mmuart.h +++ b/include/hw/char/mchp_pfsoc_mmuart.h @@ -30,7 +30,7 @@ =20 #include "hw/char/serial.h" =20 -#define MCHP_PFSOC_MMUART_REG_SIZE 52 +#define MCHP_PFSOC_MMUART_REG_COUNT 13 =20 typedef struct MchpPfSoCMMUartState { MemoryRegion iomem; @@ -39,7 +39,7 @@ typedef struct MchpPfSoCMMUartState { =20 SerialMM *serial; =20 - uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)]; + uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT]; } MchpPfSoCMMUartState; =20 /** diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c index 2facf85c2d8..584e7fec17c 100644 --- a/hw/char/mchp_pfsoc_mmuart.c +++ b/hw/char/mchp_pfsoc_mmuart.c @@ -29,13 +29,14 @@ static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hw= addr addr, unsigned size) { MchpPfSoCMMUartState *s =3D opaque; =20 - if (addr >=3D MCHP_PFSOC_MMUART_REG_SIZE) { + addr >>=3D 2; + if (addr >=3D MCHP_PFSOC_MMUART_REG_COUNT) { qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=3D0x%" HWADDR_PRIx = "\n", - __func__, addr); + __func__, addr << 2); return 0; } =20 - return s->reg[addr / sizeof(uint32_t)]; + return s->reg[addr]; } =20 static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr, @@ -44,13 +45,14 @@ static void mchp_pfsoc_mmuart_write(void *opaque, hwadd= r addr, MchpPfSoCMMUartState *s =3D opaque; uint32_t val32 =3D (uint32_t)value; =20 - if (addr >=3D MCHP_PFSOC_MMUART_REG_SIZE) { + addr >>=3D 2; + if (addr >=3D MCHP_PFSOC_MMUART_REG_COUNT) { qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=3D0x%" HWADDR_= PRIx - " v=3D0x%x\n", __func__, addr, val32); + " v=3D0x%x\n", __func__, addr << 2, val32); return; } =20 - s->reg[addr / sizeof(uint32_t)] =3D val32; + s->reg[addr] =3D val32; } =20 static const MemoryRegionOps mchp_pfsoc_mmuart_ops =3D { --=20 2.31.1 From nobody Fri May 17 08:39:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1632576861; cv=none; d=zohomail.com; s=zohoarc; b=ktjbY7ro4IhTR8aLFoqEQw+lNxJtYUGWXPrqtQFrCq3ujFUD3nl5QzF1llttPYnnBFnlb4vU+ZTi8cGEwH03r0vu/K+/09BfVcNSQX4ytp1zAYj3AP1jXKM3sD0n6hjjVl8jm+i1Y9B7a36mOXFAu/R7zZl8Rs5wabijlJzIfSE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1632576861; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=614XFzlTEarTRy3LGVUK4v93mZwN/uZLaywbdLBpLD4=; b=WGpAAnWCX+fal0fZSYsbjuc3ZOMhmsddJs8iTotz3f8Bnh1In5M2bH37TAXYNAqxqdKo+QD310dNoylsurKWmYVf4FQbjXTNUBbkA4rkBsqR/7wWTVIjn6xke5RIGZTRxV0GfN54J11V2zGiM30nT5GtIc00U2fnK0NPh7u+YdA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) by mx.zohomail.com with SMTPS id 163257686149880.71470230164641; Sat, 25 Sep 2021 06:34:21 -0700 (PDT) Received: by mail-wr1-f45.google.com with SMTP id i23so36136802wrb.2 for ; Sat, 25 Sep 2021 06:34:20 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id u6sm13140224wrp.0.2021.09.25.06.34.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Sep 2021 06:34:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=614XFzlTEarTRy3LGVUK4v93mZwN/uZLaywbdLBpLD4=; b=Tq5xiyopZSoBQTEKkjZaHU+1BqPjUQrcHksLvyWg5E0XfgqoP8tT64SHTWuIVEWOuF hQqvwTtByOXTZjeOOScHyQhD2qtDlA872IvjSfxM8Fqfjx3nN6ID3AIK8A2qWzhtJ2LA Ap8qjF2sMzL6nrWJYqv9bMFfN6nBvYtTcJGrTC0/5KGm59w9ufWvHGsHP3wA+hFgMp97 jlevRe2jDLtTLlLwC2pAdK1rApuSwClh5Y7gMZJWD1uZXacllD/kKcH+2VhAOJAR45NQ 7RAk3TkofTXBJ52B/CSA8lpZ+E/d5DqLx76zvApRxi+vwYn3/ZifIl5vAGB07S7UkViQ U2WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=614XFzlTEarTRy3LGVUK4v93mZwN/uZLaywbdLBpLD4=; b=E0oXQKU5TGtEDdR4tfSepIr9Jlulh4A933YbzYDnmbG+/2TmxVZ9RuQfwnbxBCQ2Ek c8ud1xkKZE3dO1fX1RhpgvIIOXbvBdAvpaDC6Jc0KZN+wi1LI+OmebW4o7GDDxu+ltmK ATj9T2gpE1t+yAYQ6UdsAWQr39EAbE1iW/VwIOmmTu1z4nRROpb2UF9oRCgiuigixItI oiX1jJWNJQuYlGv8giaQIuZF9nUxOM99B4Q+GxYr8TKj8uchBoUuArdwCYAlQ5S+Ozi8 m8+JfdzuqTtGa0li3YFLmckhTsIHerbfNxj9U/i7ftt2SR+4zsH3JxnK4qOr/134BVK6 Tohg== X-Gm-Message-State: AOAM531AnLOkLlAMPO0nykJqexNdFm5ikwBSnaSJEZLdjDbTVj9nHVrJ 4PKUDshPKqwt6FYgRpYdLGE= X-Google-Smtp-Source: ABdhPJz4ZgC1WiLqx+H12UHTcskiozWwfHMksJZwZMReybNsr+yQIpuYAtl/cwVHe4gBcC7je+nmXQ== X-Received: by 2002:a7b:c4d5:: with SMTP id g21mr6818808wmk.47.1632576859677; Sat, 25 Sep 2021 06:34:19 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Bin Meng , Alistair Francis , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 2/3] hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container Date: Sat, 25 Sep 2021 15:34:06 +0200 Message-Id: <20210925133407.1259392-3-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210925133407.1259392-1-f4bug@amsat.org> References: <20210925133407.1259392-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1632576863507100001 Our device have 2 different I/O regions: - a 16550 UART mapped for 32-bit accesses - 13 extra registers Instead of mapping each region on the main bus, introduce a container, map the 2 devices regions on the container, and map the container on the main bus. Before: (qemu) info mtree ... 0000000020100000-000000002010001f (prio 0, i/o): serial 0000000020100020-000000002010101f (prio 0, i/o): mchp.pfsoc.mmuart 0000000020102000-000000002010201f (prio 0, i/o): serial 0000000020102020-000000002010301f (prio 0, i/o): mchp.pfsoc.mmuart 0000000020104000-000000002010401f (prio 0, i/o): serial 0000000020104020-000000002010501f (prio 0, i/o): mchp.pfsoc.mmuart 0000000020106000-000000002010601f (prio 0, i/o): serial 0000000020106020-000000002010701f (prio 0, i/o): mchp.pfsoc.mmuart After: (qemu) info mtree ... 0000000020100000-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart 0000000020100000-000000002010001f (prio 0, i/o): serial 0000000020100020-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart.re= gs 0000000020102000-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart 0000000020102000-000000002010201f (prio 0, i/o): serial 0000000020102020-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart.re= gs 0000000020104000-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart 0000000020104000-000000002010401f (prio 0, i/o): serial 0000000020104020-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart.re= gs 0000000020106000-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart 0000000020106000-000000002010601f (prio 0, i/o): serial 0000000020106020-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart.re= gs Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- include/hw/char/mchp_pfsoc_mmuart.h | 1 + hw/char/mchp_pfsoc_mmuart.c | 11 ++++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfs= oc_mmuart.h index 9c012e6c977..864ac1a36b5 100644 --- a/include/hw/char/mchp_pfsoc_mmuart.h +++ b/include/hw/char/mchp_pfsoc_mmuart.h @@ -33,6 +33,7 @@ #define MCHP_PFSOC_MMUART_REG_COUNT 13 =20 typedef struct MchpPfSoCMMUartState { + MemoryRegion container; MemoryRegion iomem; hwaddr base; qemu_irq irq; diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c index 584e7fec17c..ea586559761 100644 --- a/hw/char/mchp_pfsoc_mmuart.c +++ b/hw/char/mchp_pfsoc_mmuart.c @@ -25,6 +25,8 @@ #include "chardev/char.h" #include "hw/char/mchp_pfsoc_mmuart.h" =20 +#define REGS_OFFSET 0x20 + static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned= size) { MchpPfSoCMMUartState *s =3D opaque; @@ -72,16 +74,19 @@ MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRe= gion *sysmem, =20 s =3D g_new0(MchpPfSoCMMUartState, 1); =20 + memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000); + memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s, - "mchp.pfsoc.mmuart", 0x1000); + "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET); + memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem); =20 s->base =3D base; s->irq =3D irq; =20 - s->serial =3D serial_mm_init(sysmem, base, 2, irq, 399193, chr, + s->serial =3D serial_mm_init(&s->container, 0, 2, irq, 399193, chr, DEVICE_LITTLE_ENDIAN); =20 - memory_region_add_subregion(sysmem, base + 0x20, &s->iomem); + memory_region_add_subregion(sysmem, base, &s->container); =20 return s; } --=20 2.31.1 From nobody Fri May 17 08:39:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1632576866; cv=none; d=zohomail.com; s=zohoarc; b=PXqpv04lKaXWnisv186ipi0fAjmsPrUQJyIc222W3hfZsclIDrXMWjpK7K+lb+uatfr+rR3hiVPZ7xNIhKSeLj7KyEkBJbrdmrJBscm91v9cE90Ppb8oOf0Q7qwPkvnBM+X1ohNFsIwglttm3FaNIMGWrmxArI4F/NvxPjrrhjw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1632576866; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=b6QGRmQhDU8FF6ADnmxpod9FuARIY1Cf+w68oJokGzU=; b=RjOCf+ABFsjUvRRcesnlSaiBPOWZB2qzp1YlxvD6UV9DQTfPpkSvnX97gmyfuuvu+tvjnc4z+n4v9RdV48XLN3+xXBYSATWeKpzwT76bqkzaiBb5d4nRy83maHQUwpe8Pu7BpFLa/6N78HN98A/SyR+vsPqA78gJIydueJpJj8o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.zohomail.com with SMTPS id 1632576866316279.2164261117855; Sat, 25 Sep 2021 06:34:26 -0700 (PDT) Received: by mail-wr1-f52.google.com with SMTP id t18so36118252wrb.0 for ; Sat, 25 Sep 2021 06:34:25 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id o12sm10847045wms.15.2021.09.25.06.34.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Sep 2021 06:34:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b6QGRmQhDU8FF6ADnmxpod9FuARIY1Cf+w68oJokGzU=; b=U8OUkDUoE0kk8CcZBG64X0T8EdwalePjeZBqA8qwTGZJfjlRiGp5i51DzJ5dbgu5Da 9lNhph7Qfoapq2leTUZOMrneGDyvHGtlLSQrTLI6oGvBcBVX9w1e2yGTlR4ftVc8BLDY dtW1iCmYQzQgYplKqAmUVJphH7CH5jtfXHv5OG11Nh4Eide/J3h9SMEHfWJgh7gqIAAu SD7uAQ+NRKPFBqiE0inO26v2KzM4CqgJIfD0VdFH/rrCdI1d02asQ5xYyQwFsALexiOM 1e8UER2nps77Hdxksnd6LTHOtZUz/Ds6JfYWBDSrrRac3Tg+Af9l4V0fsldZTf2fyo68 s1Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=b6QGRmQhDU8FF6ADnmxpod9FuARIY1Cf+w68oJokGzU=; b=tVo3YWkf8qmiuw7ds/Ue07uZEnJf+cbqvKrXu3N1j6ZCsIxYfWpL6sAiErtSW+QDlk kbwM11xWxi4Vgo6RrqpVQpCYnEcaNsIUTyv7WZNxGk775Krx3Rwjnn90QLlF62JcVhNF k9cZc0Ib1CcUGNlRFmvRwNHd1EA1q6PFiMXxz78Va91SqXKAjV8nenedx1He7uCLD6+z vfr+B6n7KtvpweCpmpSynPp8nuM7uGAPb2VpmSQqPUWL/XfTPLK5ZhV8P1AYNB3YzTTu Ej0E5almZ7c699pSk8OQ6QyuIN8m9xsE0xT3+uB+6+M4DImc0owXZho/a6ps1PlDcTUj Vw5A== X-Gm-Message-State: AOAM5323Mva1uKQg5/7uY5ucWN2yUx2uTaa/bZU8dzvbkpkkQ4vGCF8Q ySVxCP1/KD1cFRjnwGs/6Ec= X-Google-Smtp-Source: ABdhPJwJeaZexEvLD2HsCaeHLXuER5kn+kLWsDGQ524v6mdF7Fsg0LaEX/usXU3qaLzxxX17jkv+IQ== X-Received: by 2002:adf:ecd2:: with SMTP id s18mr16941594wro.99.1632576864520; Sat, 25 Sep 2021 06:34:24 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Bin Meng , Alistair Francis , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH v2 3/3] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART Date: Sat, 25 Sep 2021 15:34:07 +0200 Message-Id: <20210925133407.1259392-4-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210925133407.1259392-1-f4bug@amsat.org> References: <20210925133407.1259392-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1632576867913100001 - Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it - Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize() - Add DeviceReset() method - Add vmstate structure for migration - Register device in 'input' category - Keep mchp_pfsoc_mmuart_create() behavior Note, serial_mm_init() calls qdev_set_legacy_instance_id(). This call is only needed for backwards-compatibility of incoming migration data with old versions of QEMU which implemented migration of devices with hand-rolled code. Since this device didn't previously handle migration at all, then it doesn't need to set the legacy instance ID. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- Cc: Peter Maydell I haven't kept Alistair R-b tag from v1. --- include/hw/char/mchp_pfsoc_mmuart.h | 12 +++- hw/char/mchp_pfsoc_mmuart.c | 105 +++++++++++++++++++++++----- 2 files changed, 97 insertions(+), 20 deletions(-) diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfs= oc_mmuart.h index 864ac1a36b5..b0e14ca3554 100644 --- a/include/hw/char/mchp_pfsoc_mmuart.h +++ b/include/hw/char/mchp_pfsoc_mmuart.h @@ -28,17 +28,23 @@ #ifndef HW_MCHP_PFSOC_MMUART_H #define HW_MCHP_PFSOC_MMUART_H =20 +#include "hw/sysbus.h" #include "hw/char/serial.h" =20 #define MCHP_PFSOC_MMUART_REG_COUNT 13 =20 +#define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart" +OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART) + typedef struct MchpPfSoCMMUartState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ MemoryRegion container; MemoryRegion iomem; - hwaddr base; - qemu_irq irq; =20 - SerialMM *serial; + SerialMM serial_mm; =20 uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT]; } MchpPfSoCMMUartState; diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c index ea586559761..22f3e78eb9e 100644 --- a/hw/char/mchp_pfsoc_mmuart.c +++ b/hw/char/mchp_pfsoc_mmuart.c @@ -22,8 +22,10 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "chardev/char.h" +#include "qapi/error.h" +#include "migration/vmstate.h" #include "hw/char/mchp_pfsoc_mmuart.h" +#include "hw/qdev-properties.h" =20 #define REGS_OFFSET 0x20 =20 @@ -67,26 +69,95 @@ static const MemoryRegionOps mchp_pfsoc_mmuart_ops =3D { }, }; =20 -MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, - hwaddr base, qemu_irq irq, Chardev *chr) +static void mchp_pfsoc_mmuart_reset(DeviceState *dev) { - MchpPfSoCMMUartState *s; + MchpPfSoCMMUartState *s =3D MCHP_PFSOC_UART(dev); =20 - s =3D g_new0(MchpPfSoCMMUartState, 1); + memset(s->reg, 0, sizeof(s->reg)); + device_cold_reset(DEVICE(&s->serial_mm)); +} =20 - memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000); +static void mchp_pfsoc_mmuart_init(Object *obj) +{ + MchpPfSoCMMUartState *s =3D MCHP_PFSOC_UART(obj); =20 - memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s, + object_initialize_child(obj, "serial-mm", &s->serial_mm, TYPE_SERIAL_M= M); + object_property_add_alias(obj, "chardev", OBJECT(&s->serial_mm), "char= dev"); +} + +static void mchp_pfsoc_mmuart_realize(DeviceState *dev, Error **errp) +{ + MchpPfSoCMMUartState *s =3D MCHP_PFSOC_UART(dev); + + qdev_prop_set_uint8(DEVICE(&s->serial_mm), "regshift", 2); + qdev_prop_set_uint32(DEVICE(&s->serial_mm), "baudbase", 399193); + qdev_prop_set_uint8(DEVICE(&s->serial_mm), "endianness", + DEVICE_LITTLE_ENDIAN); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->serial_mm), errp)) { + return; + } + + sysbus_pass_irq(SYS_BUS_DEVICE(dev), SYS_BUS_DEVICE(&s->serial_mm)); + + memory_region_init(&s->container, OBJECT(s), "mchp.pfsoc.mmuart", 0x10= 00); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); + + memory_region_add_subregion(&s->container, 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial_mm), = 0)); + + memory_region_init_io(&s->iomem, OBJECT(s), &mchp_pfsoc_mmuart_ops, s, "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET); memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem); - - s->base =3D base; - s->irq =3D irq; - - s->serial =3D serial_mm_init(&s->container, 0, 2, irq, 399193, chr, - DEVICE_LITTLE_ENDIAN); - - memory_region_add_subregion(sysmem, base, &s->container); - - return s; +} + +static const VMStateDescription mchp_pfsoc_mmuart_vmstate =3D { + .name =3D "mchp.pfsoc.uart", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(reg, MchpPfSoCMMUartState, + MCHP_PFSOC_MMUART_REG_COUNT), + VMSTATE_END_OF_LIST() + } +}; + +static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D mchp_pfsoc_mmuart_realize; + dc->reset =3D mchp_pfsoc_mmuart_reset; + dc->vmsd =3D &mchp_pfsoc_mmuart_vmstate; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); +} + +static const TypeInfo mchp_pfsoc_mmuart_info =3D { + .name =3D TYPE_MCHP_PFSOC_UART, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MchpPfSoCMMUartState), + .instance_init =3D mchp_pfsoc_mmuart_init, + .class_init =3D mchp_pfsoc_mmuart_class_init, +}; + +static void mchp_pfsoc_mmuart_register_types(void) +{ + type_register_static(&mchp_pfsoc_mmuart_info); +} + +type_init(mchp_pfsoc_mmuart_register_types) + +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, + hwaddr base, + qemu_irq irq, Chardev *chr) +{ + DeviceState *dev =3D qdev_new(TYPE_MCHP_PFSOC_UART); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + qdev_prop_set_chr(dev, "chardev", chr); + sysbus_realize(sbd, &error_fatal); + + memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(sbd, = 0)); + sysbus_connect_irq(sbd, 0, irq); + + return MCHP_PFSOC_UART(dev); } --=20 2.31.1