From nobody Tue Feb 10 09:58:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1632388958085740.2898655688522; Thu, 23 Sep 2021 02:22:38 -0700 (PDT) Received: from localhost ([::1]:36368 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mTKw9-0005iz-2r for importer@patchew.org; Thu, 23 Sep 2021 05:22:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42676) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mTKni-0001al-Pu for qemu-devel@nongnu.org; Thu, 23 Sep 2021 05:13:54 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:48650 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mTKnh-0007bl-2g for qemu-devel@nongnu.org; Thu, 23 Sep 2021 05:13:54 -0400 Received: from [2a00:23c4:8b9d:4100:5d98:71b5:90ca:dad1] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mTKnW-0003vl-Q8; Thu, 23 Sep 2021 10:13:46 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Thu, 23 Sep 2021 10:12:56 +0100 Message-Id: <20210923091308.13832-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210923091308.13832-1-mark.cave-ayland@ilande.co.uk> References: <20210923091308.13832-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8b9d:4100:5d98:71b5:90ca:dad1 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v5 08/20] nubus: generate bus error when attempting to access empty slots X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1632388960124100005 According to "Designing Cards and Drivers for the Macintosh Family" any att= empt to access an unimplemented address location on Nubus generates a bus error.= MacOS uses a custom bus error handler to detect empty Nubus slots, and with the c= urrent implementation assumes that all slots are occupied as the Nubus transactions never fail. Switch nubus_slot_ops and nubus_super_slot_ops over to use {read,write}_wit= h_attrs and hard-code them to return MEMTX_DECODE_ERROR so that unoccupied Nubus sl= ots will generate the expected bus error. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Laurent Vivier --- hw/nubus/nubus-bus.c | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/hw/nubus/nubus-bus.c b/hw/nubus/nubus-bus.c index b398423c99..3db8272524 100644 --- a/hw/nubus/nubus-bus.c +++ b/hw/nubus/nubus-bus.c @@ -28,23 +28,23 @@ static NubusBus *nubus_find(void) return NUBUS_BUS(object_resolve_path_type("", TYPE_NUBUS_BUS, NULL)); } =20 -static void nubus_slot_write(void *opaque, hwaddr addr, uint64_t val, - unsigned int size) +static MemTxResult nubus_slot_write(void *opaque, hwaddr addr, uint64_t va= l, + unsigned size, MemTxAttrs attrs) { - /* read only */ trace_nubus_slot_write(addr, val, size); + return MEMTX_DECODE_ERROR; } =20 -static uint64_t nubus_slot_read(void *opaque, hwaddr addr, - unsigned int size) +static MemTxResult nubus_slot_read(void *opaque, hwaddr addr, uint64_t *da= ta, + unsigned size, MemTxAttrs attrs) { trace_nubus_slot_read(addr, size); - return 0; + return MEMTX_DECODE_ERROR; } =20 static const MemoryRegionOps nubus_slot_ops =3D { - .read =3D nubus_slot_read, - .write =3D nubus_slot_write, + .read_with_attrs =3D nubus_slot_read, + .write_with_attrs =3D nubus_slot_write, .endianness =3D DEVICE_BIG_ENDIAN, .valid =3D { .min_access_size =3D 1, @@ -52,23 +52,25 @@ static const MemoryRegionOps nubus_slot_ops =3D { }, }; =20 -static void nubus_super_slot_write(void *opaque, hwaddr addr, uint64_t val, - unsigned int size) +static MemTxResult nubus_super_slot_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { - /* read only */ trace_nubus_super_slot_write(addr, val, size); + return MEMTX_DECODE_ERROR; } =20 -static uint64_t nubus_super_slot_read(void *opaque, hwaddr addr, - unsigned int size) +static MemTxResult nubus_super_slot_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) { trace_nubus_super_slot_read(addr, size); - return 0; + return MEMTX_DECODE_ERROR; } =20 static const MemoryRegionOps nubus_super_slot_ops =3D { - .read =3D nubus_super_slot_read, - .write =3D nubus_super_slot_write, + .read_with_attrs =3D nubus_super_slot_read, + .write_with_attrs =3D nubus_super_slot_write, .endianness =3D DEVICE_BIG_ENDIAN, .valid =3D { .min_access_size =3D 1, --=20 2.20.1