From nobody Mon Feb 9 09:47:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1632241941; cv=none; d=zohomail.com; s=zohoarc; b=mEIxkTwoGyXdDRv3PBSs8NKtk0+Ipb0TQSIp0r3TI/XTrTvyIZl8ByPpAByGRBwTQazqud9zBBbrcfT1sPJF5b08ZlwqGKNQ7mGxgPvADhy0vqgIRwaQv7CVNmHlxtkUy+rFNF+VH5SPrTIs1z/muTKNShOQ46oVmE3iD4B49AI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1632241941; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=StI9Wbs/qW2+W/kpKxKP65tcisHwg/BCZQKgVwHdxFI=; b=MxDy8f8GHseMN0xPwicLSz4DYAi5QGzJduWTjJTKAZaZrOe1FfDRBUD4CyzthAnkEHVF2tH5Z1RbTVmpsptsbqm7ZU33ntNdiXHADqNGbqLnSrUHiP14FrZUPVkqKIgJ7QRpBPobvKk5hZZMRo26ounYGiRr/DV1XH/ma2s8S04= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163224194164436.28412790050436; Tue, 21 Sep 2021 09:32:21 -0700 (PDT) Received: from localhost ([::1]:51674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSigt-0002jQ-MB for importer@patchew.org; Tue, 21 Sep 2021 12:32:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47094) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSido-0008Lt-GX for qemu-devel@nongnu.org; Tue, 21 Sep 2021 12:29:08 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:41603) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSidl-00029D-Kk for qemu-devel@nongnu.org; Tue, 21 Sep 2021 12:29:08 -0400 Received: by mail-wr1-x431.google.com with SMTP id w29so40987954wra.8 for ; Tue, 21 Sep 2021 09:29:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q7sm19841014wru.56.2021.09.21.09.29.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Sep 2021 09:29:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=StI9Wbs/qW2+W/kpKxKP65tcisHwg/BCZQKgVwHdxFI=; b=poKbrtZ75QCFRPGSZET0Z9lRQYP6MBoc694tkn05MT6x4MeIV4dNxYerGiJ1SPtzaA Mv3tNlQVrRdfEX6ojqO/8aISZRZaCAFzNQ5Apptg92VGlmwd5HEftYlZd1xs3n8REwhI aVWHOX3F5kSSDhfJupjEOZZ09sUi/Vo6zbls0ylRSP3u93EmrpUAmjI9ZXW72RYL5YKr N6+cMQP3eJntug0Y3PPGVvF4oURv4EA3jAySgzTy83cZ/gilNNgJwelK1cCXrmErdq6v 1ThnovNqB453l5MxXlgCSMmneXP/5pBCIQex+R5hHyNC7VnWZVc3afY5CRqgd44xXzxN LrbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=StI9Wbs/qW2+W/kpKxKP65tcisHwg/BCZQKgVwHdxFI=; b=LG8R7OYF9US5S+ufwY2/0h8p7uh7lgKiIY8MVrl4uheCGdSbR25eBZJSm0XkFhpQZz DWEaPRt8VWcyfvLKLaW6HHz4hCZa3pKHZcVYLZLGuOfbcNzAMOQeZtdp2dwsh5ZcIEiI Y84PxWvG3VxcsB129xF9A1JiEr5Plxoa1Wg8vw/bfXyHiPh/16Rat6M5dKaxRR3N3N2y 3ThqKYdnIBhu+9+4/dKYcZamyZrmUCyh609scUWsULYwqP4DCEljCtYqQCj2KIm2WZdN k+cy1JeKKO6HcT/296kcoaQOE2xWMNX5WcKp76tmqfKFDYJAX+lqG7/U6GI21K4/8OhF 8O3w== X-Gm-Message-State: AOAM532Sp5enFwhgqwBeznleYIlrIL4D3m6SkZpNyZ0auLmiKv/otzbi z8Vv9p+RCsqtDkVVtBRofxN2hw== X-Google-Smtp-Source: ABdhPJyc7JZXTXjRalnb4HP7twyUWUCbgA0YaxIPom5uOgyXieW2hpVO6PrHB4YcN7/w47ACkGxLmg== X-Received: by 2002:a1c:403:: with SMTP id 3mr5669011wme.161.1632241744204; Tue, 21 Sep 2021 09:29:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/5] configs: Don't include 32-bit-only GDB XML in aarch64 linux configs Date: Tue, 21 Sep 2021 17:28:57 +0100 Message-Id: <20210921162901.17508-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210921162901.17508-1-peter.maydell@linaro.org> References: <20210921162901.17508-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luis Machado Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1632241942676100002 Content-Type: text/plain; charset="utf-8" The aarch64-linux QEMU usermode binaries can never run 32-bit code, so they do not need to include the GDB XML for it. (arm_cpu_register_gdb_regs_for_features() will not use these XML files if the CPU has ARM_FEATURE_AARCH64, so we will not advertise to gdb that we have them.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- configs/targets/aarch64-linux-user.mak | 2 +- configs/targets/aarch64_be-linux-user.mak | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch= 64-linux-user.mak index 4713253709f..d0c603c54ec 100644 --- a/configs/targets/aarch64-linux-user.mak +++ b/configs/targets/aarch64-linux-user.mak @@ -1,5 +1,5 @@ TARGET_ARCH=3Daarch64 TARGET_BASE_ARCH=3Darm -TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.x= ml gdb-xml/arm-m-profile.xml +TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml TARGET_HAS_BFLT=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aa= rch64_be-linux-user.mak index fae831558da..d3ee10c00f3 100644 --- a/configs/targets/aarch64_be-linux-user.mak +++ b/configs/targets/aarch64_be-linux-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Daarch64 TARGET_BASE_ARCH=3Darm TARGET_WORDS_BIGENDIAN=3Dy -TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.x= ml gdb-xml/arm-m-profile.xml +TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml TARGET_HAS_BFLT=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy --=20 2.20.1 From nobody Mon Feb 9 09:47:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1632241953; cv=none; d=zohomail.com; s=zohoarc; b=cD4oqbr4kBPTEsh0b6Nnm9rgxmPtia/0Rt8UwIYy52Ecx3p2B+tS1MGVWmae6Ej988JIzEvZPF6rED1nrvJgZCG2OslL0zRRd6beXT5vyYeH7w/J5D6fH37vfggXu0jyI/zb2d3ifyyZaZsvKtPnGliDEsHVXX0KfBZnjC84j/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1632241953; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VHb17IfanSTmLS+2/xtwkgJnWlHcbTTMTVtLLMK51LM=; b=cXiJpooWf41cUcdWjDbqDQ+HrJMQfm84V8uj6oOtJsKG8oGl5/MvKLYo3tCvrWg/JO99zEq9jk5tlaafR9UusXfwJLz2o2bD/51cVriYRGSuzvNF6+oDjGrd0zJlfM3437IO9DRwQK1xdgGqc2l5+FmNZbxWDuE7f+exDhyeGUA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1632241953645248.44980136650668; Tue, 21 Sep 2021 09:32:33 -0700 (PDT) Received: from localhost ([::1]:51794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSih6-0002oj-G2 for importer@patchew.org; Tue, 21 Sep 2021 12:32:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47136) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSidp-0008Nb-S8 for qemu-devel@nongnu.org; Tue, 21 Sep 2021 12:29:09 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:44861) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSidn-00029u-MN for qemu-devel@nongnu.org; Tue, 21 Sep 2021 12:29:09 -0400 Received: by mail-wr1-x435.google.com with SMTP id d6so40767129wrc.11 for ; Tue, 21 Sep 2021 09:29:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q7sm19841014wru.56.2021.09.21.09.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Sep 2021 09:29:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VHb17IfanSTmLS+2/xtwkgJnWlHcbTTMTVtLLMK51LM=; b=Gj/Fm9tPaPhll9ETWjNeNKNbCOXJqPK1qOFQ4N1L2WfndEINeUqT+Nxeu61sTHo4yD xq884hhOOykw2z4xLWo+QM7aetryEks4F01PFYJNQJH9L3pIfFuh5QFTt5/Uc9Vg9aLj ez91tAC9hNlnYOJMt7bg5v8vYRA0ZVW1vIV9B/OEpC3BiBM2bYFu8L14eHhl4NOKNztz NS2hiBDMeOqhIDzKYxGi3mJ8qjLhScslLpp1uoeyFi+64a+qNEmQj3SOiO1QOCK+MIWv pVE/dERuubmKKS/jscOqjv/jx81dr6bew3vR5dwqd8OraHQa1XazeA325bawOZ7BspdO rAig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VHb17IfanSTmLS+2/xtwkgJnWlHcbTTMTVtLLMK51LM=; b=LsPEZfR2bO8w2AnDkvaoeQg7XLeBYwunxq85Q9KaTKmje2LW40dEg8ZW+vLgWmPqJm yqPutYlACwcp0gWuxiB5qTl+Pr+IxcmpHRgB3km9Guhc9DDZs5a/n8fQ6CbrjY+gknIQ 60n6eGR2zdswkzmqpAaWRdiiTVTApsYUNib1XiJ8SNZ91kFtgHhv+gdStZe6AJSZ60a8 5vL07ppMaYkhT/h0h+slOPVfxFiqztO7aG2VxES8RJT8gRHcGnhI7EH1nrg9cTIiYo40 brTyX/tFV/9Kx9iMjVJuHgjsiOH53zh3DYW96AjH5YeQUZbXHq+bdy1E3QbPoZyZYtll 38xw== X-Gm-Message-State: AOAM532K+CFLs3ad/VR1JuuQkIfCNHgx4cuOi3k33WDdE0Z8aidlJyED nGp9DF7l6LOEYH2nFXiFhSFIjg== X-Google-Smtp-Source: ABdhPJzqcOlV5E3Tq/iy0drcX6mmtZDlpbyVEyj8bRA0cSaRrB8+Xf+6F+dlW+jD1vLiFY5El3Pb+Q== X-Received: by 2002:adf:f24a:: with SMTP id b10mr37259167wrp.281.1632241744833; Tue, 21 Sep 2021 09:29:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/5] target/arm: Fix coding style issues in gdbstub code in helper.c Date: Tue, 21 Sep 2021 17:28:58 +0100 Message-Id: <20210921162901.17508-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210921162901.17508-1-peter.maydell@linaro.org> References: <20210921162901.17508-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luis Machado Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1632241954333100001 Content-Type: text/plain; charset="utf-8" We're going to move this code to a different file; fix the coding style first so checkpatch doesn't complain. This includes deleting the spurious 'break' statements after returns in the vfp_gdb_get_reg() function. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b210da2bc26..179038ad3da 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -72,9 +72,12 @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray = *buf, int reg) } } switch (reg - nregs) { - case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); brea= k; - case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break; - case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); brea= k; + case 0: + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); + case 1: + return gdb_get_reg32(buf, vfp_get_fpscr(env)); + case 2: + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); } return 0; } @@ -98,9 +101,15 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *b= uf, int reg) } } switch (reg - nregs) { - case 0: env->vfp.xregs[ARM_VFP_FPSID] =3D ldl_p(buf); return 4; - case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; - case 2: env->vfp.xregs[ARM_VFP_FPEXC] =3D ldl_p(buf) & (1 << 30); retu= rn 4; + case 0: + env->vfp.xregs[ARM_VFP_FPSID] =3D ldl_p(buf); + return 4; + case 1: + vfp_set_fpscr(env, ldl_p(buf)); + return 4; + case 2: + env->vfp.xregs[ARM_VFP_FPEXC] =3D ldl_p(buf) & (1 << 30); + return 4; } return 0; } @@ -119,7 +128,7 @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GB= yteArray *buf, int reg) return gdb_get_reg32(buf, vfp_get_fpsr(env)); case 33: /* FPCR */ - return gdb_get_reg32(buf,vfp_get_fpcr(env)); + return gdb_get_reg32(buf, vfp_get_fpcr(env)); default: return 0; } --=20 2.20.1 From nobody Mon Feb 9 09:47:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1632242012; cv=none; d=zohomail.com; s=zohoarc; b=LlPxduVm29/JtPjSHoY9Y7x3ZbvgSQMDyDWJPUwdNg3pV7HCYKOjWvUHDMiy7CjdJQadlUfxMVrCs7Vbhu4f5DZgG7Jqty319TiLYI4Z84XMlyAMLJTRexXJnIhG7WyUxj0XnCfe5+WUCBfdvChPkXRhKvBM8VGK7hSTuDUBzAw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1632242012; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=661NXzoZSewDkW9mRtuYRVyfw4QA+0j5LFjWByhJsA8=; b=jFzIlGnL9OXhBj6u8iEK24rabT+J3ASp9kT1D/rT3cZuKumJF6tLGOVQ7AaHSj2zBt2WFn1Wr82oZxTqXUFIUXYS7NoV23ClU6CZ3uQcBdBYkgZC5BVONzv99PaVcE23G5IbNZvomq9lwLjh+2lSACgzX8XMF8vP4GpUzxCfxSQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1632242012144537.2232689397672; Tue, 21 Sep 2021 09:33:32 -0700 (PDT) Received: from localhost ([::1]:53870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSii2-0004LE-4J for importer@patchew.org; Tue, 21 Sep 2021 12:33:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47142) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSidp-0008Ni-Vk for qemu-devel@nongnu.org; Tue, 21 Sep 2021 12:29:10 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:36824) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSidn-0002AO-6x for qemu-devel@nongnu.org; Tue, 21 Sep 2021 12:29:09 -0400 Received: by mail-wr1-x42b.google.com with SMTP id g16so40940001wrb.3 for ; Tue, 21 Sep 2021 09:29:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q7sm19841014wru.56.2021.09.21.09.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Sep 2021 09:29:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=661NXzoZSewDkW9mRtuYRVyfw4QA+0j5LFjWByhJsA8=; b=SQd1b89MfhZMhSS037T/7TIJyVd4P0w7X0h+u0JwfAdC6SWEuoA3x8vNMixcAtuyYH PUckEhYE8qVlJ5FX36R7lMXPZBDaSjqDddeyHBEtOmn22oMTw82lK5UrLkonuq+fYFIh JwQmgaKH/HtJtNMHLAqjxiOtNb2YRJyFln4axNEl2orUknKSf9z2L21H1S4kL0iXpxcS dxZcgx5FZ/usjLXKhWo9i4+NEaBwaxc/kXAHLvkTDrJP+tBH7Tpu1binU7mkPxMgIe2G HguPwETN/0K+mytImgoFPxfI9dKNfvb5+Gx0YRKN2YaHRhaeyo46HIyz9fvZ65LSybxO 04mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=661NXzoZSewDkW9mRtuYRVyfw4QA+0j5LFjWByhJsA8=; b=lG6Pw8PsEph0PwjHegm0T9nkWiF87hhZ7nM5DljQZU07GT7+qs+YCgOh0K/0gDVRPp sTU2nEzjtFxHby6mokuLC2seNqKRtWOfCTLqpI2AWoP47lABlGrKrSBtZhWCvG1BaRDy JQ+h8cNsPkE+wG1BEmA7V1jBnHjdClLj9qxgcpudvxLZv9PBrS0ijRKNXm6bIhUy3+Cf O93hr8RO7/UfKLgRNml23gMr4i65karGCjMvurmI+S80wHjYODWHyBcg1WeCjQnOI19Q vw4Y3TN3WQrapMOJlWlXgVHKSTdhxeRCXTgOoSoCOCSfTWjSGWex/BNKyFUnvA26ltWd Jj2g== X-Gm-Message-State: AOAM533Au56i8HUrWcq23xtrnxQypi/9SXiiovmHXhL9tecZZgk4TBaP qTNJrUsUaFt+b7GmZcRmj7L7UA== X-Google-Smtp-Source: ABdhPJwLadhiMxcAHfrzBuUflZIn7NH6uDuSEsCwArHIIi8kskIDVIhheW+3OCXsek/qC1XRbG5Z4Q== X-Received: by 2002:a5d:630a:: with SMTP id i10mr36806786wru.178.1632241745713; Tue, 21 Sep 2021 09:29:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/5] target/arm: Move gdbstub related code out of helper.c Date: Tue, 21 Sep 2021 17:28:59 +0100 Message-Id: <20210921162901.17508-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210921162901.17508-1-peter.maydell@linaro.org> References: <20210921162901.17508-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luis Machado Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1632242013747100003 Content-Type: text/plain; charset="utf-8" Currently helper.c includes some code which is part of the arm target's gdbstub support. This code has a better home: in gdbstub.c and gdbstub64.c. Move it there. Because aarch64_fpu_gdb_get_reg() and aarch64_fpu_gdb_set_reg() move into gdbstub64.c, this means that they're now compiled only for TARGET_AARCH64 rather than always. That is the only case when they would ever be used, but it does mean that the ifdef in arm_cpu_register_gdb_regs_for_features() needs to be adjusted to match. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/internals.h | 7 ++ target/arm/gdbstub.c | 130 ++++++++++++++++++++ target/arm/gdbstub64.c | 140 +++++++++++++++++++++ target/arm/helper.c | 271 ----------------------------------------- 4 files changed, 277 insertions(+), 271 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index cd2ea8a3883..d6f8c0bc927 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1226,4 +1226,11 @@ enum MVEECIState { /* All other values reserved */ }; =20 +#ifdef TARGET_AARCH64 +int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); +int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); +#endif + #endif diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 826601b3415..cbf156d192f 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -19,6 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" +#include "internals.h" #include "exec/gdbstub.h" =20 typedef struct RegisterSysregXmlParam { @@ -124,6 +125,98 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) return 0; } =20 +static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D env_archcpu(env); + int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; + + /* VFP data registers are always little-endian. */ + if (reg < nregs) { + return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); + } + if (arm_feature(env, ARM_FEATURE_NEON)) { + /* Aliases for Q regs. */ + nregs +=3D 16; + if (reg < nregs) { + uint64_t *q =3D aa32_vfp_qreg(env, reg - 32); + return gdb_get_reg128(buf, q[0], q[1]); + } + } + switch (reg - nregs) { + case 0: + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); + case 1: + return gdb_get_reg32(buf, vfp_get_fpscr(env)); + case 2: + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); + } + return 0; +} + +static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D env_archcpu(env); + int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; + + if (reg < nregs) { + *aa32_vfp_dreg(env, reg) =3D ldq_le_p(buf); + return 8; + } + if (arm_feature(env, ARM_FEATURE_NEON)) { + nregs +=3D 16; + if (reg < nregs) { + uint64_t *q =3D aa32_vfp_qreg(env, reg - 32); + q[0] =3D ldq_le_p(buf); + q[1] =3D ldq_le_p(buf + 8); + return 16; + } + } + switch (reg - nregs) { + case 0: + env->vfp.xregs[ARM_VFP_FPSID] =3D ldl_p(buf); + return 4; + case 1: + vfp_set_fpscr(env, ldl_p(buf)); + return 4; + case 2: + env->vfp.xregs[ARM_VFP_FPEXC] =3D ldl_p(buf) & (1 << 30); + return 4; + } + return 0; +} + +/** + * arm_get/set_gdb_*: get/set a gdb register + * @env: the CPU state + * @buf: a buffer to copy to/from + * @reg: register number (offset from start of group) + * + * We return the number of bytes copied + */ + +static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D env_archcpu(env); + const ARMCPRegInfo *ri; + uint32_t key; + + key =3D cpu->dyn_sysreg_xml.data.cpregs.keys[reg]; + ri =3D get_arm_cp_reginfo(cpu->cp_regs, key); + if (ri) { + if (cpreg_field_is_64bit(ri)) { + return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); + } else { + return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); + } + } + return 0; +} + +static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) +{ + return 0; +} + static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_= xml, ARMCPRegInfo *ri, uint32_t ri_key, int bitsize, int regnum) @@ -319,3 +412,40 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, cons= t char *xmlname) } return NULL; } + +void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) +{ + CPUState *cs =3D CPU(cpu); + CPUARMState *env =3D &cpu->env; + + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + /* + * The lower part of each SVE register aliases to the FPU + * registers so we don't need to include both. + */ +#ifdef TARGET_AARCH64 + if (isar_feature_aa64_sve(&cpu->isar)) { + gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_s= vereg, + arm_gen_dynamic_svereg_xml(cs, cs->gd= b_num_regs), + "sve-registers.xml", 0); + } else { + gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, + aarch64_fpu_gdb_set_reg, + 34, "aarch64-fpu.xml", 0); + } +#endif + } else if (arm_feature(env, ARM_FEATURE_NEON)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 51, "arm-neon.xml", 0); + } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 35, "arm-vfp3.xml", 0); + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 19, "arm-vfp.xml", 0); + } + gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, + arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_re= gs), + "system-registers.xml", 0); + +} diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 251539ef799..596878666d7 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -17,7 +17,9 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "cpu.h" +#include "internals.h" #include "exec/gdbstub.h" =20 int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) @@ -69,3 +71,141 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_= t *mem_buf, int n) /* Unknown register. */ return 0; } + +int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +{ + switch (reg) { + case 0 ... 31: + { + /* 128 bit FP register - quads are in LE order */ + uint64_t *q =3D aa64_vfp_qreg(env, reg); + return gdb_get_reg128(buf, q[1], q[0]); + } + case 32: + /* FPSR */ + return gdb_get_reg32(buf, vfp_get_fpsr(env)); + case 33: + /* FPCR */ + return gdb_get_reg32(buf, vfp_get_fpcr(env)); + default: + return 0; + } +} + +int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + switch (reg) { + case 0 ... 31: + /* 128 bit FP register */ + { + uint64_t *q =3D aa64_vfp_qreg(env, reg); + q[0] =3D ldq_le_p(buf); + q[1] =3D ldq_le_p(buf + 8); + return 16; + } + case 32: + /* FPSR */ + vfp_set_fpsr(env, ldl_p(buf)); + return 4; + case 33: + /* FPCR */ + vfp_set_fpcr(env, ldl_p(buf)); + return 4; + default: + return 0; + } +} + +int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D env_archcpu(env); + + switch (reg) { + /* The first 32 registers are the zregs */ + case 0 ... 31: + { + int vq, len =3D 0; + for (vq =3D 0; vq < cpu->sve_max_vq; vq++) { + len +=3D gdb_get_reg128(buf, + env->vfp.zregs[reg].d[vq * 2 + 1], + env->vfp.zregs[reg].d[vq * 2]); + } + return len; + } + case 32: + return gdb_get_reg32(buf, vfp_get_fpsr(env)); + case 33: + return gdb_get_reg32(buf, vfp_get_fpcr(env)); + /* then 16 predicates and the ffr */ + case 34 ... 50: + { + int preg =3D reg - 34; + int vq, len =3D 0; + for (vq =3D 0; vq < cpu->sve_max_vq; vq =3D vq + 4) { + len +=3D gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); + } + return len; + } + case 51: + { + /* + * We report in Vector Granules (VG) which is 64bit in a Z reg + * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. + */ + int vq =3D sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + return gdb_get_reg64(buf, vq * 2); + } + default: + /* gdbstub asked for something out our range */ + qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__,= reg); + break; + } + + return 0; +} + +int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* The first 32 registers are the zregs */ + switch (reg) { + /* The first 32 registers are the zregs */ + case 0 ... 31: + { + int vq, len =3D 0; + uint64_t *p =3D (uint64_t *) buf; + for (vq =3D 0; vq < cpu->sve_max_vq; vq++) { + env->vfp.zregs[reg].d[vq * 2 + 1] =3D *p++; + env->vfp.zregs[reg].d[vq * 2] =3D *p++; + len +=3D 16; + } + return len; + } + case 32: + vfp_set_fpsr(env, *(uint32_t *)buf); + return 4; + case 33: + vfp_set_fpcr(env, *(uint32_t *)buf); + return 4; + case 34 ... 50: + { + int preg =3D reg - 34; + int vq, len =3D 0; + uint64_t *p =3D (uint64_t *) buf; + for (vq =3D 0; vq < cpu->sve_max_vq; vq =3D vq + 4) { + env->vfp.pregs[preg].p[vq / 4] =3D *p++; + len +=3D 8; + } + return len; + } + case 51: + /* cannot set vg via gdbstub */ + return 0; + default: + /* gdbstub asked for something out our range */ + break; + } + + return 0; +} diff --git a/target/arm/helper.c b/target/arm/helper.c index 179038ad3da..deca59a3e61 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12,7 +12,6 @@ #include "trace.h" #include "cpu.h" #include "internals.h" -#include "exec/gdbstub.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "qemu/main-loop.h" @@ -54,110 +53,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64= _t address, static void switch_mode(CPUARMState *env, int mode); static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); =20 -static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) -{ - ARMCPU *cpu =3D env_archcpu(env); - int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; - - /* VFP data registers are always little-endian. */ - if (reg < nregs) { - return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); - } - if (arm_feature(env, ARM_FEATURE_NEON)) { - /* Aliases for Q regs. */ - nregs +=3D 16; - if (reg < nregs) { - uint64_t *q =3D aa32_vfp_qreg(env, reg - 32); - return gdb_get_reg128(buf, q[0], q[1]); - } - } - switch (reg - nregs) { - case 0: - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); - case 1: - return gdb_get_reg32(buf, vfp_get_fpscr(env)); - case 2: - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); - } - return 0; -} - -static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) -{ - ARMCPU *cpu =3D env_archcpu(env); - int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; - - if (reg < nregs) { - *aa32_vfp_dreg(env, reg) =3D ldq_le_p(buf); - return 8; - } - if (arm_feature(env, ARM_FEATURE_NEON)) { - nregs +=3D 16; - if (reg < nregs) { - uint64_t *q =3D aa32_vfp_qreg(env, reg - 32); - q[0] =3D ldq_le_p(buf); - q[1] =3D ldq_le_p(buf + 8); - return 16; - } - } - switch (reg - nregs) { - case 0: - env->vfp.xregs[ARM_VFP_FPSID] =3D ldl_p(buf); - return 4; - case 1: - vfp_set_fpscr(env, ldl_p(buf)); - return 4; - case 2: - env->vfp.xregs[ARM_VFP_FPEXC] =3D ldl_p(buf) & (1 << 30); - return 4; - } - return 0; -} - -static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int = reg) -{ - switch (reg) { - case 0 ... 31: - { - /* 128 bit FP register - quads are in LE order */ - uint64_t *q =3D aa64_vfp_qreg(env, reg); - return gdb_get_reg128(buf, q[1], q[0]); - } - case 32: - /* FPSR */ - return gdb_get_reg32(buf, vfp_get_fpsr(env)); - case 33: - /* FPCR */ - return gdb_get_reg32(buf, vfp_get_fpcr(env)); - default: - return 0; - } -} - -static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) -{ - switch (reg) { - case 0 ... 31: - /* 128 bit FP register */ - { - uint64_t *q =3D aa64_vfp_qreg(env, reg); - q[0] =3D ldq_le_p(buf); - q[1] =3D ldq_le_p(buf + 8); - return 16; - } - case 32: - /* FPSR */ - vfp_set_fpsr(env, ldl_p(buf)); - return 4; - case 33: - /* FPCR */ - vfp_set_fpcr(env, ldl_p(buf)); - return 4; - default: - return 0; - } -} - static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) { assert(ri->fieldoffset); @@ -217,134 +112,6 @@ static void write_raw_cp_reg(CPUARMState *env, const = ARMCPRegInfo *ri, } } =20 -/** - * arm_get/set_gdb_*: get/set a gdb register - * @env: the CPU state - * @buf: a buffer to copy to/from - * @reg: register number (offset from start of group) - * - * We return the number of bytes copied - */ - -static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) -{ - ARMCPU *cpu =3D env_archcpu(env); - const ARMCPRegInfo *ri; - uint32_t key; - - key =3D cpu->dyn_sysreg_xml.data.cpregs.keys[reg]; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, key); - if (ri) { - if (cpreg_field_is_64bit(ri)) { - return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); - } else { - return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); - } - } - return 0; -} - -static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) -{ - return 0; -} - -#ifdef TARGET_AARCH64 -static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) -{ - ARMCPU *cpu =3D env_archcpu(env); - - switch (reg) { - /* The first 32 registers are the zregs */ - case 0 ... 31: - { - int vq, len =3D 0; - for (vq =3D 0; vq < cpu->sve_max_vq; vq++) { - len +=3D gdb_get_reg128(buf, - env->vfp.zregs[reg].d[vq * 2 + 1], - env->vfp.zregs[reg].d[vq * 2]); - } - return len; - } - case 32: - return gdb_get_reg32(buf, vfp_get_fpsr(env)); - case 33: - return gdb_get_reg32(buf, vfp_get_fpcr(env)); - /* then 16 predicates and the ffr */ - case 34 ... 50: - { - int preg =3D reg - 34; - int vq, len =3D 0; - for (vq =3D 0; vq < cpu->sve_max_vq; vq =3D vq + 4) { - len +=3D gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); - } - return len; - } - case 51: - { - /* - * We report in Vector Granules (VG) which is 64bit in a Z reg - * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. - */ - int vq =3D sve_zcr_len_for_el(env, arm_current_el(env)) + 1; - return gdb_get_reg64(buf, vq * 2); - } - default: - /* gdbstub asked for something out our range */ - qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__,= reg); - break; - } - - return 0; -} - -static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) -{ - ARMCPU *cpu =3D env_archcpu(env); - - /* The first 32 registers are the zregs */ - switch (reg) { - /* The first 32 registers are the zregs */ - case 0 ... 31: - { - int vq, len =3D 0; - uint64_t *p =3D (uint64_t *) buf; - for (vq =3D 0; vq < cpu->sve_max_vq; vq++) { - env->vfp.zregs[reg].d[vq * 2 + 1] =3D *p++; - env->vfp.zregs[reg].d[vq * 2] =3D *p++; - len +=3D 16; - } - return len; - } - case 32: - vfp_set_fpsr(env, *(uint32_t *)buf); - return 4; - case 33: - vfp_set_fpcr(env, *(uint32_t *)buf); - return 4; - case 34 ... 50: - { - int preg =3D reg - 34; - int vq, len =3D 0; - uint64_t *p =3D (uint64_t *) buf; - for (vq =3D 0; vq < cpu->sve_max_vq; vq =3D vq + 4) { - env->vfp.pregs[preg].p[vq / 4] =3D *p++; - len +=3D 8; - } - return len; - } - case 51: - /* cannot set vg via gdbstub */ - return 0; - default: - /* gdbstub asked for something out our range */ - break; - } - - return 0; -} -#endif /* TARGET_AARCH64 */ - static bool raw_accessors_invalid(const ARMCPRegInfo *ri) { /* Return true if the regdef would cause an assertion if you called @@ -8711,44 +8478,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) #endif } =20 -void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) -{ - CPUState *cs =3D CPU(cpu); - CPUARMState *env =3D &cpu->env; - - if (arm_feature(env, ARM_FEATURE_AARCH64)) { - /* - * The lower part of each SVE register aliases to the FPU - * registers so we don't need to include both. - */ -#ifdef TARGET_AARCH64 - if (isar_feature_aa64_sve(&cpu->isar)) { - gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_s= vereg, - arm_gen_dynamic_svereg_xml(cs, cs->gd= b_num_regs), - "sve-registers.xml", 0); - } else -#endif - { - gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, - aarch64_fpu_gdb_set_reg, - 34, "aarch64-fpu.xml", 0); - } - } else if (arm_feature(env, ARM_FEATURE_NEON)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 51, "arm-neon.xml", 0); - } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 35, "arm-vfp3.xml", 0); - } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 19, "arm-vfp.xml", 0); - } - gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_re= gs), - "system-registers.xml", 0); - -} - /* Sort alphabetically by type name, except for "any". */ static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) { --=20 2.20.1 From nobody Mon Feb 9 09:47:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q7sm19841014wru.56.2021.09.21.09.29.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Sep 2021 09:29:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TUr52VVjSox7QlwwUlvluUaP8NJZfKJMZXIF71lXSE0=; b=amx69U+3QHHTT4aIh0IRIL9s4U31vq0VJZkFdxSbuv+Z0I1ujGr0Kmc6CMy65NBmog 92Qn6pGPyhd1B34PBDXt/nCa1yiqVMvWjz06ofc7qXb6CYF4QWIl70qoivelJVGlDCm4 phgXVaK5muwFTgIR+2SOy0Lx/uHuzkFGxD8omUxmSTRqARJu/Dl86dVANTx3FPJIvday ZAY15kzZGk2CQXUdHdbGOWTdwohNENA7n2XhHGvQmKkCuq6y1wjNaEEZkGbiURVsgh+s sslzBYbRj1uwPO82q0bbqyw2sTibgypmzTV7gKL2TCCsvVB8oeOmt/Rm70LiDlLb0wFa i/Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TUr52VVjSox7QlwwUlvluUaP8NJZfKJMZXIF71lXSE0=; b=HB9ntp67KtDFIcKPAmYDpY+qaVJZ7P2tFmWWD+WuYd7NpUSXvlJkg0Lfl3jsP9m/2v ME0QIxWa3Js5FnD8sTzhK+3dVvDa3VL8Oy/DAEZrEH03MJqTedfWXlV1cQU3fHgDqIP/ wRI5X76DDIDn8oqZnzvQbdQNJLrkiUZJZbaYtYXVdJ2MPYlSHQJceDum2CodgnIpHXpI aB0hGNL9bnrkGVtO7HyP6Zcasgsw/lWkeYNzS4qsS4NyDLW25qcI5avf0WGWN9Yom5aJ zMoblVeq74BjgMLOs20G6MX1WvVzNYtgeE1pC/NQ96AITE90kLu7qQfGo89d2YrCnTs2 zoQA== X-Gm-Message-State: AOAM533sTgJvTD3ehjMB8D6KX2ymC6xcXznK978OfD1Cy7aGVUtoPFZ7 tSSVxmZ8O05LhxPi2ej26ZI2ZQ== X-Google-Smtp-Source: ABdhPJwSUcvGP4YvzDD2V1yZ+fYcbBaGjst6nJnrmxMfYnZBcsu9dvlB0GObiz68CT4VdrO4ICQNYw== X-Received: by 2002:a05:600c:201:: with SMTP id 1mr5589971wmi.5.1632241746531; Tue, 21 Sep 2021 09:29:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/5] target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML Date: Tue, 21 Sep 2021 17:29:00 +0100 Message-Id: <20210921162901.17508-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210921162901.17508-1-peter.maydell@linaro.org> References: <20210921162901.17508-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luis Machado Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1632242190315100001 Content-Type: text/plain; charset="utf-8" Currently we send VFP XML which includes D0..D15 or D0..D31, plus FPSID, FPSCR and FPEXC. The upstream GDB tolerates this, but its definition of this XML feature does not include FPSID or FPEXC. In particular, for M-profile cores there are no FPSID or FPEXC registers, so advertising those is wrong. Move FPSID and FPEXC into their own bit of XML which we only send for A and R profile cores. This brings our definition of the XML org.gnu.gdb.arm.vfp feature into line with GDB's own (at least for non-Neon cores...) and means we don't claim to have FPSID and FPEXC on M-profile. (It seems unlikely to me that any gdbstub users really care about being able to look at FPEXC and FPSID; but we've supplied them to gdb for a decade and it's not hard to keep doing so.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- configs/targets/aarch64-softmmu.mak | 2 +- configs/targets/arm-linux-user.mak | 2 +- configs/targets/arm-softmmu.mak | 2 +- configs/targets/armeb-linux-user.mak | 2 +- target/arm/gdbstub.c | 56 ++++++++++++++++++++-------- gdb-xml/arm-neon.xml | 2 - gdb-xml/arm-vfp-sysregs.xml | 17 +++++++++ gdb-xml/arm-vfp.xml | 2 - gdb-xml/arm-vfp3.xml | 2 - 9 files changed, 61 insertions(+), 26 deletions(-) create mode 100644 gdb-xml/arm-vfp-sysregs.xml diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-= softmmu.mak index 7703127674e..13d40b55e6d 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,5 +1,5 @@ TARGET_ARCH=3Daarch64 TARGET_BASE_ARCH=3Darm TARGET_SUPPORTS_MTTCG=3Dy -TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.x= ml gdb-xml/arm-m-profile.xml +TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sy= sregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_NEED_FDT=3Dy diff --git a/configs/targets/arm-linux-user.mak b/configs/targets/arm-linux= -user.mak index e741ffd4d30..acecc339e38 100644 --- a/configs/targets/arm-linux-user.mak +++ b/configs/targets/arm-linux-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Darm TARGET_SYSTBL_ABI=3Dcommon,oabi TARGET_SYSTBL=3Dsyscall.tbl -TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml +TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-prof= ile.xml TARGET_HAS_BFLT=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.= mak index 84a98f48186..f6c95ba07a4 100644 --- a/configs/targets/arm-softmmu.mak +++ b/configs/targets/arm-softmmu.mak @@ -1,4 +1,4 @@ TARGET_ARCH=3Darm TARGET_SUPPORTS_MTTCG=3Dy -TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml +TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-prof= ile.xml TARGET_NEED_FDT=3Dy diff --git a/configs/targets/armeb-linux-user.mak b/configs/targets/armeb-l= inux-user.mak index 255e44e8b0a..662c73d8fbd 100644 --- a/configs/targets/armeb-linux-user.mak +++ b/configs/targets/armeb-linux-user.mak @@ -2,6 +2,6 @@ TARGET_ARCH=3Darm TARGET_SYSTBL_ABI=3Dcommon,oabi TARGET_SYSTBL=3Dsyscall.tbl TARGET_WORDS_BIGENDIAN=3Dy -TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml +TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-prof= ile.xml TARGET_HAS_BFLT=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index cbf156d192f..e0dcb33e325 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -144,11 +144,7 @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArra= y *buf, int reg) } switch (reg - nregs) { case 0: - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); - case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); - case 2: - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); } return 0; } @@ -172,13 +168,31 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t = *buf, int reg) } } switch (reg - nregs) { + case 0: + vfp_set_fpscr(env, ldl_p(buf)); + return 4; + } + return 0; +} + +static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) +{ + switch (reg) { + case 0: + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); + case 1: + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); + } + return 0; +} + +static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) +{ + switch (reg) { case 0: env->vfp.xregs[ARM_VFP_FPSID] =3D ldl_p(buf); return 4; case 1: - vfp_set_fpscr(env, ldl_p(buf)); - return 4; - case 2: env->vfp.xregs[ARM_VFP_FPEXC] =3D ldl_p(buf) & (1 << 30); return 4; } @@ -434,15 +448,25 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) 34, "aarch64-fpu.xml", 0); } #endif - } else if (arm_feature(env, ARM_FEATURE_NEON)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 51, "arm-neon.xml", 0); - } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 35, "arm-vfp3.xml", 0); - } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 19, "arm-vfp.xml", 0); + } else { + if (arm_feature(env, ARM_FEATURE_NEON)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 49, "arm-neon.xml", 0); + } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 33, "arm-vfp3.xml", 0); + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 17, "arm-vfp.xml", 0); + } + if (!arm_feature(env, ARM_FEATURE_M)) { + /* + * A and R profile have FP sysregs FPEXC and FPSID that we + * expose to gdb. + */ + gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_s= ysreg, + 2, "arm-vfp-sysregs.xml", 0); + } } gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_re= gs), diff --git a/gdb-xml/arm-neon.xml b/gdb-xml/arm-neon.xml index ce3ee03ec48..9dce0a996fc 100644 --- a/gdb-xml/arm-neon.xml +++ b/gdb-xml/arm-neon.xml @@ -82,7 +82,5 @@ =20 - - diff --git a/gdb-xml/arm-vfp-sysregs.xml b/gdb-xml/arm-vfp-sysregs.xml new file mode 100644 index 00000000000..c4aa2721c8d --- /dev/null +++ b/gdb-xml/arm-vfp-sysregs.xml @@ -0,0 +1,17 @@ + + + + + + + diff --git a/gdb-xml/arm-vfp.xml b/gdb-xml/arm-vfp.xml index b20881e9a99..ebed5b3d573 100644 --- a/gdb-xml/arm-vfp.xml +++ b/gdb-xml/arm-vfp.xml @@ -23,7 +23,5 @@ =20 - - diff --git a/gdb-xml/arm-vfp3.xml b/gdb-xml/arm-vfp3.xml index 227afd8017f..ef391c7144d 100644 --- a/gdb-xml/arm-vfp3.xml +++ b/gdb-xml/arm-vfp3.xml @@ -39,7 +39,5 @@ =20 - - --=20 2.20.1 From nobody Mon Feb 9 09:47:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q7sm19841014wru.56.2021.09.21.09.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Sep 2021 09:29:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3E7kwGW+up3GsQ28CwtzAbDb2VBzaxcDFqWQbjPeAEA=; b=pvKVaQn2e8Q+WDlpeh1skSR+tN/P7fC+WrGZG0hhddp/Ru/Jgjy4/36LQQ3/qdUynf poLwiSsiR14PTEF8W9zHZBx0dbuNWU6S4WquA1m7g1z3C1Fd+IKqqYZO2ELuSUemRxrI aJ1nu8WmFoaVJHLwmszoxVjFRWrGI+sWWhi6gN0WwWyH2WAvI5mRz1DLDtH2psN5IMSw AcaBTCIfdyOqPn2dINVhzIbon/kQfZbOo6iz/qKLN1dI4C7kuOlsHuobffLJJOqRn1cn XxPLI8DqzTQEK1ERycgYFTHUVtkAt2okk9IF/kROQ1dadfvGo1V6PShRKR19QQi+6OVg 1aWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3E7kwGW+up3GsQ28CwtzAbDb2VBzaxcDFqWQbjPeAEA=; b=M7je9I56CNdDU0ASFzte/aKdNRRGbiYFmxGx0YleQj0lvZb7+3OW8ynK15Lek4/E9F Vg0oLCLVwY39Ygajy0hoNLHdT2SR7EotgbfJmPtYlThChEqdvcpoM26G+msVxrnv4ZlR 4qCR7iAmRdXrIdtBpCuHYKT4+JjnSBMWuntI1S1QB+j25QCbDwdbi+XACMHuUJM1R1pv gxuwq7u0x+0DSvn1JN7HNe4FoHnktpOumx70I/XWE9bYDZ6YW/JXOwQl8JD3piFQXnPm 1u3lkXa9IbrHJaRv8YiBij3t3j5Ck4PHCK/4PToyt3hM5PfQazfOpM2PepmliknBz1mr Ts8Q== X-Gm-Message-State: AOAM532br1Csat9ZsEPwMPiUGB3EpQzmuV38GHhkYU6aWKBNhjkPw7XZ 3zMXQbPhNkzFZ818L8//bilthOxutjDF8w== X-Google-Smtp-Source: ABdhPJxXInD1Otfu/jruvW7LweOG2oWJ2MkBC+UD2qkgBbOq/6xEaMmhkHo7qzurAi/xZ5UpzocBwQ== X-Received: by 2002:a7b:c405:: with SMTP id k5mr5615050wmi.24.1632241747252; Tue, 21 Sep 2021 09:29:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/5] [RFC] target/arm: Advertise MVE to gdb when present Date: Tue, 21 Sep 2021 17:29:01 +0100 Message-Id: <20210921162901.17508-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210921162901.17508-1-peter.maydell@linaro.org> References: <20210921162901.17508-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luis Machado Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1632242247321100001 Content-Type: text/plain; charset="utf-8" Cortex-M CPUs with MVE should advertise this fact to gdb, using the org.gnu.gdb.arm.m-profile-mve XML feature, which defines the VPR register. Presence of this feature also tells gdb to create pseudo-registers Q0..Q7, so we do not need to tell gdb about them separately. Note that unless you have a very recent GDB that includes this fix: http://patches-tcwg.linaro.org/patch/58133/ gdb will mis-print the individual fields of the VPR register as zero (but showing the whole thing as hex, eg with "print /x $vpr" will give the correct value). NB: the gdb patches to implement this have not yet landed in gdb upstream, so this patch is RFC status only until that happens and the XML is finalized. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- configs/targets/aarch64-softmmu.mak | 2 +- configs/targets/arm-linux-user.mak | 2 +- configs/targets/arm-softmmu.mak | 2 +- configs/targets/armeb-linux-user.mak | 2 +- target/arm/gdbstub.c | 25 +++++++++++++++++++++++++ gdb-xml/arm-m-profile-mve.xml | 19 +++++++++++++++++++ 6 files changed, 48 insertions(+), 4 deletions(-) create mode 100644 gdb-xml/arm-m-profile-mve.xml diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-= softmmu.mak index 13d40b55e6d..d489e6da830 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,5 +1,5 @@ TARGET_ARCH=3Daarch64 TARGET_BASE_ARCH=3Darm TARGET_SUPPORTS_MTTCG=3Dy -TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sy= sregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml +TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sy= sregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-prof= ile-mve.xml TARGET_NEED_FDT=3Dy diff --git a/configs/targets/arm-linux-user.mak b/configs/targets/arm-linux= -user.mak index acecc339e38..3e10d6b15d5 100644 --- a/configs/targets/arm-linux-user.mak +++ b/configs/targets/arm-linux-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Darm TARGET_SYSTBL_ABI=3Dcommon,oabi TARGET_SYSTBL=3Dsyscall.tbl -TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-prof= ile.xml +TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-prof= ile.xml gdb-xml/arm-m-profile-mve.xml TARGET_HAS_BFLT=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.= mak index f6c95ba07a4..92c8349b964 100644 --- a/configs/targets/arm-softmmu.mak +++ b/configs/targets/arm-softmmu.mak @@ -1,4 +1,4 @@ TARGET_ARCH=3Darm TARGET_SUPPORTS_MTTCG=3Dy -TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-prof= ile.xml +TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-prof= ile.xml gdb-xml/arm-m-profile-mve.xml TARGET_NEED_FDT=3Dy diff --git a/configs/targets/armeb-linux-user.mak b/configs/targets/armeb-l= inux-user.mak index 662c73d8fbd..f81e5bf1fe4 100644 --- a/configs/targets/armeb-linux-user.mak +++ b/configs/targets/armeb-linux-user.mak @@ -2,6 +2,6 @@ TARGET_ARCH=3Darm TARGET_SYSTBL_ABI=3Dcommon,oabi TARGET_SYSTBL=3Dsyscall.tbl TARGET_WORDS_BIGENDIAN=3Dy -TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-prof= ile.xml +TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-prof= ile.xml gdb-xml/arm-m-profile-mve.xml TARGET_HAS_BFLT=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index e0dcb33e325..134da0d0ae3 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -199,6 +199,27 @@ static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_= t *buf, int reg) return 0; } =20 +static int mve_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +{ + switch (reg) { + case 0: + return gdb_get_reg32(buf, env->v7m.vpr); + default: + return 0; + } +} + +static int mve_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + switch (reg) { + case 0: + env->v7m.vpr =3D ldl_p(buf); + return 4; + default: + return 0; + } +} + /** * arm_get/set_gdb_*: get/set a gdb register * @env: the CPU state @@ -468,6 +489,10 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) 2, "arm-vfp-sysregs.xml", 0); } } + if (cpu_isar_feature(aa32_mve, cpu)) { + gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg, + 1, "arm-m-profile-mve.xml", 0); + } gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_re= gs), "system-registers.xml", 0); diff --git a/gdb-xml/arm-m-profile-mve.xml b/gdb-xml/arm-m-profile-mve.xml new file mode 100644 index 00000000000..cba664c4c5b --- /dev/null +++ b/gdb-xml/arm-m-profile-mve.xml @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + --=20 2.20.1