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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1632207287; x=1634799288; bh=AO1JuK3l7xcyFrzBrm x/exn5X0AAf6QqVyw+XZ3D90c=; b=ssvxBo806cPznaSxB1eyqPr7TTJNDSrgBV rwn48xaBHX8vQmczmr0Xtz3eF1Wooz0E/hzGZSs6DcQP76OFGW8h5A8NSLEhPAUe xMHu563di9HLfGHlbR0lt1FChrEEPQRCDtza1XoFXbDl4oUtwLt3XvgHsnX5iPoh ozweLLfGs5brbuZQ//W3ztnp6eX81YUzhQ2E9rKEBmUl0x65wtNmdR7jbaoyRITt CNveeD60xWB+gfANy7t1AesLczuL6Trft283yXooB9McInC1/9IuVpGj1iL+ZARL eB+3wZqu8ayqo0WB80QFzahMNKjedDjYLk5RjEVAYl9vI8R9dq/A== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Alistair Francis , Bin Meng , LIU Zhiwei Subject: [PULL v2 04/21] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines Date: Tue, 21 Sep 2021 16:53:55 +1000 Message-Id: <20210921065412.312381-5-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210921065412.312381-1-alistair.francis@opensource.wdc.com> References: <20210921065412.312381-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=891501f09=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1632207730214100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer and soft MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: LIU Zhiwei Message-id: 946e1ef5e268b24084c7ddad84c146de62a56736.1630301632.git.alistai= r.francis@wdc.com --- include/hw/intc/sifive_clint.h | 2 + hw/intc/sifive_clint.c | 68 ++++++++++++++++++++++++---------- 2 files changed, 50 insertions(+), 20 deletions(-) diff --git a/include/hw/intc/sifive_clint.h b/include/hw/intc/sifive_clint.h index a30be0f3d6..921b1561dd 100644 --- a/include/hw/intc/sifive_clint.h +++ b/include/hw/intc/sifive_clint.h @@ -40,6 +40,8 @@ typedef struct SiFiveCLINTState { uint32_t time_base; uint32_t aperture_size; uint32_t timebase_freq; + qemu_irq *timer_irqs; + qemu_irq *soft_irqs; } SiFiveCLINTState; =20 DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, diff --git a/hw/intc/sifive_clint.c b/hw/intc/sifive_clint.c index 99c870ced2..ab172d8e40 100644 --- a/hw/intc/sifive_clint.c +++ b/hw/intc/sifive_clint.c @@ -28,6 +28,12 @@ #include "hw/qdev-properties.h" #include "hw/intc/sifive_clint.h" #include "qemu/timer.h" +#include "hw/irq.h" + +typedef struct sifive_clint_callback { + SiFiveCLINTState *s; + int num; +} sifive_clint_callback; =20 static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) { @@ -39,7 +45,9 @@ static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) * Called when timecmp is written to update the QEMU timer or immediately * trigger timer interrupt if mtimecmp <=3D current timer value. */ -static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value, +static void sifive_clint_write_timecmp(SiFiveCLINTState *s, RISCVCPU *cpu, + int hartid, + uint64_t value, uint32_t timebase_freq) { uint64_t next; @@ -51,12 +59,12 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, u= int64_t value, if (cpu->env.timecmp <=3D rtc_r) { /* if we're setting an MTIMECMP value in the "past", immediately raise the timer interrupt */ - riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1)); + qemu_irq_raise(s->timer_irqs[hartid - s->hartid_base]); return; } =20 /* otherwise, set up the future timer interrupt */ - riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0)); + qemu_irq_lower(s->timer_irqs[hartid - s->hartid_base]); diff =3D cpu->env.timecmp - rtc_r; /* back to ns (note args switched in muldiv64) */ uint64_t ns_diff =3D muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_f= req); @@ -91,8 +99,9 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uin= t64_t value, */ static void sifive_clint_timer_cb(void *opaque) { - RISCVCPU *cpu =3D opaque; - riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1)); + sifive_clint_callback *state =3D opaque; + + qemu_irq_raise(state->s->timer_irqs[state->num]); } =20 /* CPU wants to read rtc or timecmp register */ @@ -158,7 +167,7 @@ static void sifive_clint_write(void *opaque, hwaddr add= r, uint64_t value, if (!env) { error_report("clint: invalid timecmp hartid: %zu", hartid); } else if ((addr & 0x3) =3D=3D 0) { - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MSIP, BOOL_TO_MASK(va= lue)); + qemu_set_irq(clint->soft_irqs[hartid - clint->hartid_base], va= lue); } else { error_report("clint: invalid sip write: %08x", (uint32_t)addr); } @@ -174,13 +183,13 @@ static void sifive_clint_write(void *opaque, hwaddr a= ddr, uint64_t value, } else if ((addr & 0x7) =3D=3D 0) { /* timecmp_lo */ uint64_t timecmp_hi =3D env->timecmp >> 32; - sifive_clint_write_timecmp(RISCV_CPU(cpu), + sifive_clint_write_timecmp(clint, RISCV_CPU(cpu), hartid, timecmp_hi << 32 | (value & 0xFFFFFFFF), clint->timebase_f= req); return; } else if ((addr & 0x7) =3D=3D 4) { /* timecmp_hi */ uint64_t timecmp_lo =3D env->timecmp; - sifive_clint_write_timecmp(RISCV_CPU(cpu), + sifive_clint_write_timecmp(clint, RISCV_CPU(cpu), hartid, value << 32 | (timecmp_lo & 0xFFFFFFFF), clint->timebase_f= req); } else { error_report("clint: invalid timecmp write: %08x", (uint32_t)a= ddr); @@ -226,6 +235,12 @@ static void sifive_clint_realize(DeviceState *dev, Err= or **errp) memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_clint_ops, s, TYPE_SIFIVE_CLINT, s->aperture_size); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); + + s->timer_irqs =3D g_malloc(sizeof(qemu_irq) * s->num_harts); + qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts); + + s->soft_irqs =3D g_malloc(sizeof(qemu_irq) * s->num_harts); + qdev_init_gpio_out(dev, s->soft_irqs, s->num_harts); } =20 static void sifive_clint_class_init(ObjectClass *klass, void *data) @@ -249,7 +264,6 @@ static void sifive_clint_register_types(void) =20 type_init(sifive_clint_register_types) =20 - /* * Create CLINT device. */ @@ -259,29 +273,43 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr = size, bool provide_rdtime) { int i; + + DeviceState *dev =3D qdev_new(TYPE_SIFIVE_CLINT); + qdev_prop_set_uint32(dev, "hartid-base", hartid_base); + qdev_prop_set_uint32(dev, "num-harts", num_harts); + qdev_prop_set_uint32(dev, "sip-base", sip_base); + qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); + qdev_prop_set_uint32(dev, "time-base", time_base); + qdev_prop_set_uint32(dev, "aperture-size", size); + qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D qemu_get_cpu(hartid_base + i); + RISCVCPU *rvcpu =3D RISCV_CPU(cpu); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; + sifive_clint_callback *cb =3D g_malloc0(sizeof(sifive_clint_callba= ck)); + if (!env) { + g_free(cb); continue; } if (provide_rdtime) { riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq= ); } + + cb->s =3D SIFIVE_CLINT(dev); + cb->num =3D i; env->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, - &sifive_clint_timer_cb, cpu); + &sifive_clint_timer_cb, cb); env->timecmp =3D 0; + + qdev_connect_gpio_out(dev, i, + qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER)= ); + qdev_connect_gpio_out(dev, num_harts + i, + qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_SOFT)); } =20 - DeviceState *dev =3D qdev_new(TYPE_SIFIVE_CLINT); - qdev_prop_set_uint32(dev, "hartid-base", hartid_base); - qdev_prop_set_uint32(dev, "num-harts", num_harts); - qdev_prop_set_uint32(dev, "sip-base", sip_base); - qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); - qdev_prop_set_uint32(dev, "time-base", time_base); - qdev_prop_set_uint32(dev, "aperture-size", size); - qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); return dev; } --=20 2.31.1