From nobody Fri May 17 13:45:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1632191385896449.00158068720566; Mon, 20 Sep 2021 19:29:45 -0700 (PDT) Received: from localhost ([::1]:44040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSVXU-0005er-RJ for importer@patchew.org; Mon, 20 Sep 2021 22:29:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSVTe-0005cc-2P for qemu-devel@nongnu.org; Mon, 20 Sep 2021 22:25:46 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:35598) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSVTW-0006Dw-Mp for qemu-devel@nongnu.org; Mon, 20 Sep 2021 22:25:44 -0400 Received: by mail-pg1-x52b.google.com with SMTP id e7so19320129pgk.2 for ; Mon, 20 Sep 2021 19:25:38 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id n9sm15297621pff.37.2021.09.20.19.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 19:25:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b0a6x8YG6fiEgthZKVT+Y1l/wqv7IPJugG1mhUmd6xQ=; b=PDE8VLAjg0Lqfp8jZDbSZhmBqAtLrIxhGWg43RCZSm/ZTun0etGWQmv+Er75xlOQUX KLAt/1gH/zm1jiPSv/7i6HOxog0HUlo1rup7E3Ou5XvsyYrRS3DNYQb9FgU9gem0hiFy aguKt8jYr771yXc65NYxjX2nnoGorTHG1teNZrx9dUHoSeuluBVgk4qcfR/9wk2TzOT2 B1iLzEM5tBfiVucx7y9YNz7riwwEA/Xkh8wM/WNatAmH0xls8nLk2Zw8Y6cAMIfRbNn+ ktCztfdvL3KQ8/9mmTF3zLRt40XJAdH/oec6kCu+mKy4bOF7fP7yHsFeFI46dTcItnYw qIrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b0a6x8YG6fiEgthZKVT+Y1l/wqv7IPJugG1mhUmd6xQ=; b=aMqqvQtbUN2LrgREf89yPtfTYCtxR3atj+RbLrTvWodIKDBNunJ60VHAocy8J+4Lbb vdeXsSbKHDS2T1p37gO8rNQphXlL5O8jJYpaX4h0vt+qUV2y3Y/Zk4S/E+RUJWe307j+ Xz7xF9CjrytZodNO+YGMaysnCtzpBvM7lDPFbuG6uLOrSMwKwIEv2TEaAmZJYjjZcj/g JV/piUx5ueSsoyKLZoSRyMC8bKx32T8L9B8AFyICyL6zJLIYCre2xA3Gk+yrwu3z3KXD kXd5ZUasbx24OMKwuaUwvYp1GQgqA4MYCsOGK98mdVlzNDGVTCigehNG0NxnUvDNzYOs fhrg== X-Gm-Message-State: AOAM53059oajVxXedwIflooeGl3pHWaUvNw+nVuvDHyds+D/kg0zwNUg tJUHgVW4hzwXWx4+wz4rSv95sKQU4rMwaA== X-Google-Smtp-Source: ABdhPJzaIZiBiM01peg/hc3JOGn/9BPxrnLl8x6ZumWir97dYK3RK3lkM7t6ofHQU24LFr7fpy2JGQ== X-Received: by 2002:aa7:9833:0:b0:444:d028:5edb with SMTP id q19-20020aa79833000000b00444d0285edbmr20718169pfl.55.1632191137155; Mon, 20 Sep 2021 19:25:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/10] include/exec: Move cpu_signal_handler declaration Date: Mon, 20 Sep 2021 19:25:25 -0700 Message-Id: <20210921022534.365291-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210921022534.365291-1-richard.henderson@linaro.org> References: <20210921022534.365291-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1632191387054100002 There is nothing target specific about this. The implementation is host specific, but the declaration is 100% common. Reviewed-By: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 13 +++++++++++++ target/alpha/cpu.h | 6 ------ target/arm/cpu.h | 7 ------- target/avr/cpu.h | 2 -- target/cris/cpu.h | 8 -------- target/hexagon/cpu.h | 3 --- target/hppa/cpu.h | 3 --- target/i386/cpu.h | 7 ------- target/m68k/cpu.h | 8 -------- target/microblaze/cpu.h | 7 ------- target/mips/cpu.h | 3 --- target/mips/internal.h | 2 -- target/nios2/cpu.h | 2 -- target/openrisc/cpu.h | 2 -- target/ppc/cpu.h | 7 ------- target/riscv/cpu.h | 2 -- target/rx/cpu.h | 4 ---- target/s390x/cpu.h | 7 ------- target/sh4/cpu.h | 3 --- target/sparc/cpu.h | 2 -- target/tricore/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- 22 files changed, 13 insertions(+), 89 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5d1b6d80fb..9d5987ba04 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -662,6 +662,19 @@ static inline tb_page_addr_t get_page_addr_code_hostp(= CPUArchState *env, } return addr; } + +/** + * cpu_signal_handler + * @signum: host signal number + * @pinfo: host siginfo_t + * @puc: host ucontext_t + * + * To be called from the SIGBUS and SIGSEGV signal handler to inform the + * virtual cpu of exceptions. Returns true if the signal was handled by + * the virtual CPU. + */ +int cpu_signal_handler(int signum, void *pinfo, void *puc); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 4e993bd15b..ce9ec32199 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -287,7 +287,6 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, int mmu_idx, uintptr_t retaddr); =20 #define cpu_list alpha_cpu_list -#define cpu_signal_handler cpu_alpha_signal_handler =20 typedef CPUAlphaState CPUArchState; typedef AlphaCPU ArchCPU; @@ -440,11 +439,6 @@ void alpha_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU =20 void alpha_cpu_list(void); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_alpha_signal_handler(int host_signum, void *pinfo, - void *puc); bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 09d9027734..751141915d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1121,12 +1121,6 @@ static inline bool is_a64(CPUARMState *env) return env->aarch64; } =20 -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_arm_signal_handler(int host_signum, void *pinfo, - void *puc); - /** * pmu_op_start/finish * @env: CPUARMState @@ -3015,7 +3009,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_syn= c); #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU =20 -#define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list =20 /* ARM has the following "translation regimes" (as the ARM ARM calls them): diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 93e3faa0a9..dceacf3cd7 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -175,7 +175,6 @@ static inline void set_avr_feature(CPUAVRState *env, in= t feature) } =20 #define cpu_list avr_cpu_list -#define cpu_signal_handler cpu_avr_signal_handler #define cpu_mmu_index avr_cpu_mmu_index =20 static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) @@ -187,7 +186,6 @@ void avr_cpu_tcg_init(void); =20 void avr_cpu_list(void); int cpu_avr_exec(CPUState *cpu); -int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc); int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, int len, bool is_write); =20 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index be021899ae..6603565f83 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -199,12 +199,6 @@ int crisv10_cpu_gdb_read_register(CPUState *cpu, GByte= Array *buf, int reg); int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_cris_signal_handler(int host_signum, void *pinfo, - void *puc); - void cris_initialize_tcg(void); void cris_initialize_crisv10_tcg(void); =20 @@ -250,8 +244,6 @@ enum { #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU =20 -#define cpu_signal_handler cpu_cris_signal_handler - /* MMU modes definitions */ #define MMU_USER_IDX 1 static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 2855dd3881..f7d043865b 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -129,9 +129,6 @@ typedef struct HexagonCPU { =20 #include "cpu_bits.h" =20 -#define cpu_signal_handler cpu_hexagon_signal_handler -int cpu_hexagon_signal_handler(int host_signum, void *pinfo, void *puc); - static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong= *pc, target_ulong *cs_base, uint32_t *f= lags) { diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7854675b90..d3cb7a279f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -319,9 +319,6 @@ static inline void cpu_hppa_change_prot_id(CPUHPPAState= *env) { } void cpu_hppa_change_prot_id(CPUHPPAState *env); #endif =20 -#define cpu_signal_handler cpu_hppa_signal_handler - -int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7dd664791a..c2954c71ea 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1947,12 +1947,6 @@ void cpu_x86_frstor(CPUX86State *s, target_ulong ptr= , int data32); void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); =20 -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_x86_signal_handler(int host_signum, void *pinfo, - void *puc); - /* cpu.c */ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, uint32_t vendor2, uint32_t vendor3); @@ -2020,7 +2014,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") #endif =20 -#define cpu_signal_handler cpu_x86_signal_handler #define cpu_list x86_cpu_list =20 /* MMU modes definitions */ diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 550eb028b6..a3423729ef 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -177,13 +177,6 @@ int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t= *buf, int reg); =20 void m68k_tcg_init(void); void m68k_cpu_init_gdb(M68kCPU *cpu); -/* - * you can call this signal handler from your SIGBUS and SIGSEGV - * signal handlers to inform the virtual CPU of exceptions. non zero - * is returned if the signal was handled by the virtual CPU. - */ -int cpu_m68k_signal_handler(int host_signum, void *pinfo, - void *puc); uint32_t cpu_m68k_get_ccr(CPUM68KState *env); void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); @@ -563,7 +556,6 @@ enum { #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_M68K_CPU =20 -#define cpu_signal_handler cpu_m68k_signal_handler #define cpu_list m68k_cpu_list =20 /* MMU modes definitions */ diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 40401c33b7..13ed3cd4dd 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -385,16 +385,9 @@ static inline void mb_cpu_write_msr(CPUMBState *env, u= int32_t val) } =20 void mb_tcg_init(void); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_mb_signal_handler(int host_signum, void *pinfo, - void *puc); =20 #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU =20 -#define cpu_signal_handler cpu_mb_signal_handler - /* MMU modes definitions */ #define MMU_NOMMU_IDX 0 #define MMU_KERNEL_IDX 1 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1dfe69c6c0..56b1cbd091 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1193,7 +1193,6 @@ struct MIPSCPU { =20 void mips_cpu_list(void); =20 -#define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list =20 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); @@ -1277,8 +1276,6 @@ enum { */ #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 =20 -int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); - #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU diff --git a/target/mips/internal.h b/target/mips/internal.h index eecdd10116..daddb05fd4 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -156,8 +156,6 @@ extern const VMStateDescription vmstate_mips_cpu; =20 #endif /* !CONFIG_USER_ONLY */ =20 -#define cpu_signal_handler cpu_mips_signal_handler - static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2ab82fdc71..88a511209c 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -193,7 +193,6 @@ struct Nios2CPU { =20 void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); -int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc); void dump_mmu(CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); @@ -206,7 +205,6 @@ void do_nios2_semihosting(CPUNios2State *env); #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU =20 #define cpu_gen_code cpu_nios2_gen_code -#define cpu_signal_handler cpu_nios2_signal_handler =20 #define CPU_SAVE_VERSION 1 =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index be6df81a81..187a4a114e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -320,11 +320,9 @@ void openrisc_translate_init(void); bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); int print_insn_or1k(bfd_vma addr, disassemble_info *info); =20 #define cpu_list cpu_openrisc_list -#define cpu_signal_handler cpu_openrisc_signal_handler =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_openrisc_cpu; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 362e7c4c5c..01d3773bc7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1278,12 +1278,6 @@ extern const VMStateDescription vmstate_ppc_cpu; =20 /*************************************************************************= ****/ void ppc_translate_init(void); -/* - * you can call this signal handler from your SIGBUS and SIGSEGV - * signal handlers to inform the virtual CPU of exceptions. non zero - * is returned if the signal was handled by the virtual CPU. - */ -int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc); bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -1371,7 +1365,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint3= 2_t val); #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU =20 -#define cpu_signal_handler cpu_ppc_signal_handler #define cpu_list ppc_cpu_list =20 /* MMU modes definitions */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e735e53e26..465142616a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -356,7 +356,6 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); =20 -#define cpu_signal_handler riscv_cpu_signal_handler #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index =20 @@ -372,7 +371,6 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64= _t (*fn)(uint32_t), void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); =20 void riscv_translate_init(void); -int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc); =20 diff --git a/target/rx/cpu.h b/target/rx/cpu.h index faa3606f52..4ac71aec37 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -134,13 +134,9 @@ int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *= buf, int reg); hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 void rx_translate_init(void); -int cpu_rx_signal_handler(int host_signum, void *pinfo, - void *puc); - void rx_cpu_list(void); void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); =20 -#define cpu_signal_handler cpu_rx_signal_handler #define cpu_list rx_cpu_list =20 #include "exec/cpu-all.h" diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index b26ae8fff2..3153d053e9 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -809,13 +809,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t ge= n, uint8_t ec_ga, #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_S390_CPU =20 -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); -#define cpu_signal_handler cpu_s390x_signal_handler - - /* interrupt.c */ #define RA_IGNORED 0 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t r= a); diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 017a770214..56f7c32df9 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -213,8 +213,6 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vadd= r addr, int mmu_idx, uintptr_t retaddr); =20 void sh4_translate_init(void); -int cpu_sh4_signal_handler(int host_signum, void *pinfo, - void *puc); bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -250,7 +248,6 @@ void cpu_load_tlb(CPUSH4State * env); #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU =20 -#define cpu_signal_handler cpu_sh4_signal_handler #define cpu_list sh4_cpu_list =20 /* MMU modes definitions */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 1f40d768d8..5a7f1ed5d6 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -648,13 +648,11 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, = target_ulong addr, int mmu_idx); #endif #endif -int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); =20 #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU =20 -#define cpu_signal_handler cpu_sparc_signal_handler #define cpu_list sparc_cpu_list =20 /* MMU modes definitions */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 4b61a2c03f..c461387e71 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -362,7 +362,6 @@ void fpu_set_state(CPUTriCoreState *env); =20 void tricore_cpu_list(void); =20 -#define cpu_signal_handler cpu_tricore_signal_handler #define cpu_list tricore_cpu_list =20 static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) @@ -377,7 +376,6 @@ typedef TriCoreCPU ArchCPU; =20 void cpu_state_reset(CPUTriCoreState *s); void tricore_tcg_init(void); -int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc); =20 static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong= *pc, target_ulong *cs_base, uint32_t *f= lags) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index cbb720e7cc..646965f379 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -584,7 +584,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vadd= r addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 -#define cpu_signal_handler cpu_xtensa_signal_handler #define cpu_list xtensa_cpu_list =20 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU @@ -613,7 +612,6 @@ void check_interrupts(CPUXtensaState *s); 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Mon, 20 Sep 2021 19:25:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 02/10] accel/tcg: Restrict cpu_handle_halt() to sysemu Date: Mon, 20 Sep 2021 19:25:26 -0700 Message-Id: <20210921022534.365291-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210921022534.365291-1-richard.henderson@linaro.org> References: <20210921022534.365291-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1632191267462100002 From: Philippe Mathieu-Daud=C3=A9 Commit 372579427a5 ("tcg: enable thread-per-vCPU") added the following comment describing EXCP_HALTED in qemu_tcg_cpu_thread_fn(): case EXCP_HALTED: /* during start-up the vCPU is reset and the thread is * kicked several times. If we don't ensure we go back * to sleep in the halted state we won't cleanly * start-up when the vCPU is enabled. * * cpu->halted should ensure we sleep in wait_io_event */ g_assert(cpu->halted); break; qemu_wait_io_event() is sysemu-specific, so we can restrict the cpu_handle_halt() call in cpu_exec() to system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-2-f4bug@amsat.org> Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 75dbc1e4e3..5fd1ed3422 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -588,8 +588,9 @@ static inline void tb_add_jump(TranslationBlock *tb, in= t n, =20 static inline bool cpu_handle_halt(CPUState *cpu) { +#ifndef CONFIG_USER_ONLY if (cpu->halted) { -#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) +#if defined(TARGET_I386) if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { X86CPU *x86_cpu =3D X86_CPU(cpu); qemu_mutex_lock_iothread(); @@ -597,13 +598,14 @@ static inline bool cpu_handle_halt(CPUState *cpu) cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); qemu_mutex_unlock_iothread(); } -#endif +#endif /* TARGET_I386 */ if (!cpu_has_work(cpu)) { return true; } =20 cpu->halted =3D 0; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1632191267598100003 Let the compiler decide about inlining. Remove tcg_out_ext8s and tcg_out_ext16s as unused. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 76 ++++++++++++++------------------------- 1 file changed, 27 insertions(+), 49 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index bf0eb84e2d..320795a637 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -187,7 +187,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, #endif =20 =20 -static inline bool is_p2m1(tcg_target_long val) +static bool is_p2m1(tcg_target_long val) { return val && ((val + 1) & val) =3D=3D 0; } @@ -361,8 +361,8 @@ typedef enum { /* * Type reg */ -static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, - TCGReg rd, TCGReg rs, TCGReg rt) +static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, + TCGReg rd, TCGReg rs, TCGReg rt) { int32_t inst; =20 @@ -376,8 +376,8 @@ static inline void tcg_out_opc_reg(TCGContext *s, MIPSI= nsn opc, /* * Type immediate */ -static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, - TCGReg rt, TCGReg rs, TCGArg imm) +static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, + TCGReg rt, TCGReg rs, TCGArg imm) { int32_t inst; =20 @@ -391,8 +391,8 @@ static inline void tcg_out_opc_imm(TCGContext *s, MIPSI= nsn opc, /* * Type bitfield */ -static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, - TCGReg rs, int msb, int lsb) +static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, + TCGReg rs, int msb, int lsb) { int32_t inst; =20 @@ -404,8 +404,8 @@ static inline void tcg_out_opc_bf(TCGContext *s, MIPSIn= sn opc, TCGReg rt, tcg_out32(s, inst); } =20 -static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn = opm, - MIPSInsn oph, TCGReg rt, TCGReg rs, +static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, + MIPSInsn oph, TCGReg rt, TCGReg rs, int msb, int lsb) { if (lsb >=3D 32) { @@ -422,8 +422,7 @@ static inline void tcg_out_opc_bf64(TCGContext *s, MIPS= Insn opc, MIPSInsn opm, /* * Type branch */ -static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, - TCGReg rt, TCGReg rs) +static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg = rs) { tcg_out_opc_imm(s, opc, rt, rs, 0); } @@ -431,8 +430,8 @@ static inline void tcg_out_opc_br(TCGContext *s, MIPSIn= sn opc, /* * Type sa */ -static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, - TCGReg rd, TCGReg rt, TCGArg sa) +static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, + TCGReg rd, TCGReg rt, TCGArg sa) { int32_t inst; =20 @@ -479,28 +478,27 @@ static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn o= pc, const void *target) return true; } =20 -static inline void tcg_out_nop(TCGContext *s) +static void tcg_out_nop(TCGContext *s) { tcg_out32(s, 0); } =20 -static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGAr= g sa) +static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); } =20 -static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGAr= g sa) +static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); } =20 -static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGAr= g sa) +static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); } =20 -static inline bool tcg_out_mov(TCGContext *s, TCGType type, - TCGReg ret, TCGReg arg) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { /* Simple reg-reg move, optimising out the 'do nothing' case */ if (ret !=3D arg) { @@ -612,27 +610,7 @@ static void tcg_out_bswap64(TCGContext *s, TCGReg ret,= TCGReg arg) } } =20 -static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); - } else { - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24); - } -} - -static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); - } else { - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); - } -} - -static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); @@ -656,8 +634,8 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, T= CGReg data, tcg_out_opc_imm(s, opc, data, addr, lo); } =20 -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { MIPSInsn opc =3D OPC_LD; if (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYPE_I32) { @@ -666,8 +644,8 @@ static inline void tcg_out_ld(TCGContext *s, TCGType ty= pe, TCGReg arg, tcg_out_ldst(s, opc, arg, arg1, arg2); } =20 -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { MIPSInsn opc =3D OPC_SD; if (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYPE_I32) { @@ -676,8 +654,8 @@ static inline void tcg_out_st(TCGContext *s, TCGType ty= pe, TCGReg arg, tcg_out_ldst(s, opc, arg, arg1, arg2); } =20 -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) { if (val =3D=3D 0) { tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); @@ -1637,9 +1615,9 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2= , MIPSInsn opcv6, } } =20 -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { MIPSInsn i1, i2; TCGArg a0, a1, a2; --=20 2.25.1 From nobody Fri May 17 13:45:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1632191379; cv=none; d=zohomail.com; s=zohoarc; b=V+Yr6UyCXHmo+wNo1Nmo/EJQR7kUnc9QboThuoc5/KSjhvf3ZY9r1Fj7n1qJN96IbUUO+rK63eHSfpbW/WFF0lHu6YKTjxB9dAx6vUkTL1jDVT5tPvvlGyD86Erqncikz0YYXa/BWlFrTsvWjZlADmdsDBQifOFkL4m1JbZnmtM= ARC-Message-Signature: i=1; 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Mon, 20 Sep 2021 19:25:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/10] tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr Date: Mon, 20 Sep 2021 19:25:28 -0700 Message-Id: <20210921022534.365291-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210921022534.365291-1-richard.henderson@linaro.org> References: <20210921022534.365291-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1632191380646100001 Weaning off of unique alignment requirements, so allow JAL to not reach the target. TCG_TMP1 is always available for use as a scratch because it is clobbered by the subroutine being called. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 320795a637..3a40af8799 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -573,8 +573,10 @@ static void tcg_out_bswap16(TCGContext *s, TCGReg ret,= TCGReg arg, int flags) =20 static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) { - bool ok =3D tcg_out_opc_jmp(s, OPC_JAL, sub); - tcg_debug_assert(ok); + if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); + tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); + } } =20 static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int fla= gs) --=20 2.25.1 From nobody Fri May 17 13:45:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 20 Sep 2021 19:25:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/10] tcg/mips: Unset TCG_TARGET_HAS_direct_jump Date: Mon, 20 Sep 2021 19:25:29 -0700 Message-Id: <20210921022534.365291-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210921022534.365291-1-richard.henderson@linaro.org> References: <20210921022534.365291-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1632191546249100001 Only use indirect jumps. Finish weaning away from the unique alignment requirements for code_gen_buffer. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 12 +++++------- tcg/mips/tcg-target.c.inc | 23 +++++------------------ 2 files changed, 10 insertions(+), 25 deletions(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 3a62055f04..c366fdf74b 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -39,11 +39,7 @@ #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define TCG_TARGET_NB_REGS 32 =20 -/* - * We have a 256MB branch region, but leave room to make sure the - * main executable is also within that region. - */ -#define MAX_CODE_GEN_BUFFER_SIZE (128 * MiB) +#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) =20 typedef enum { TCG_REG_ZERO =3D 0, @@ -136,7 +132,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 -#define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_direct_jump 0 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_TARGET_HAS_add2_i32 0 @@ -207,7 +203,9 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t) + QEMU_ERROR("code path is reachable"); =20 #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 3a40af8799..41ffa28394 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1654,17 +1654,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* direct jump method */ - s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); - /* Avoid clobbering the address during retranslation. */ - tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); - } else { - /* indirect jump method */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, - (uintptr_t)(s->tb_jmp_target_addr + a0)); - tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); - } + /* indirect jump method */ + tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, + (uintptr_t)(s->tb_jmp_target_addr + a0)); + tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); tcg_out_nop(s); set_jmp_reset_offset(s, a0); break; @@ -2538,13 +2532,6 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer = */ } =20 -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, - uintptr_t jmp_rw, uintptr_t addr) -{ - qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2)); - flush_idcache_range(jmp_rx, jmp_rw, 4); -} - typedef struct { DebugFrameHeader h; uint8_t fde_def_cfa[4]; --=20 2.25.1 From nobody Fri May 17 13:45:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 20 Sep 2021 19:25:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 06/10] tcg/mips: Drop special alignment for code_gen_buffer Date: Mon, 20 Sep 2021 19:25:30 -0700 Message-Id: <20210921022534.365291-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210921022534.365291-1-richard.henderson@linaro.org> References: <20210921022534.365291-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1632191269211100007 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/region.c | 91 ---------------------------------------------------- 1 file changed, 91 deletions(-) diff --git a/tcg/region.c b/tcg/region.c index e64c3ea230..9cc30d4922 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -467,38 +467,6 @@ static size_t tcg_n_regions(size_t tb_size, unsigned m= ax_cpus) (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \ ? DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE) =20 -#ifdef __mips__ -/* - * In order to use J and JAL within the code_gen_buffer, we require - * that the buffer not cross a 256MB boundary. - */ -static inline bool cross_256mb(void *addr, size_t size) -{ - return ((uintptr_t)addr ^ ((uintptr_t)addr + size)) & ~0x0ffffffful; -} - -/* - * We weren't able to allocate a buffer without crossing that boundary, - * so make do with the larger portion of the buffer that doesn't cross. - * Returns the new base and size of the buffer in *obuf and *osize. - */ -static inline void split_cross_256mb(void **obuf, size_t *osize, - void *buf1, size_t size1) -{ - void *buf2 =3D (void *)(((uintptr_t)buf1 + size1) & ~0x0ffffffful); - size_t size2 =3D buf1 + size1 - buf2; - - size1 =3D buf2 - buf1; - if (size1 < size2) { - size1 =3D size2; - buf1 =3D buf2; - } - - *obuf =3D buf1; - *osize =3D size1; -} -#endif - #ifdef USE_STATIC_CODE_GEN_BUFFER static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); @@ -526,12 +494,6 @@ static int alloc_code_gen_buffer(size_t tb_size, int s= plitwx, Error **errp) size =3D QEMU_ALIGN_DOWN(tb_size, qemu_real_host_page_size); } =20 -#ifdef __mips__ - if (cross_256mb(buf, size)) { - split_cross_256mb(&buf, &size, buf, size); - } -#endif - region.start_aligned =3D buf; region.total_size =3D size; =20 @@ -573,39 +535,6 @@ static int alloc_code_gen_buffer_anon(size_t size, int= prot, return -1; } =20 -#ifdef __mips__ - if (cross_256mb(buf, size)) { - /* - * Try again, with the original still mapped, to avoid re-acquiring - * the same 256mb crossing. - */ - size_t size2; - void *buf2 =3D mmap(NULL, size, prot, flags, -1, 0); - switch ((int)(buf2 !=3D MAP_FAILED)) { - case 1: - if (!cross_256mb(buf2, size)) { - /* Success! Use the new buffer. */ - munmap(buf, size); - break; - } - /* Failure. Work with what we had. */ - munmap(buf2, size); - /* fallthru */ - default: - /* Split the original buffer. Free the smaller half. */ - split_cross_256mb(&buf2, &size2, buf, size); - if (buf =3D=3D buf2) { - munmap(buf + size2, size - size2); - } else { - munmap(buf, size - size2); - } - size =3D size2; - break; - } - buf =3D buf2; - } -#endif - region.start_aligned =3D buf; region.total_size =3D size; return prot; @@ -620,35 +549,15 @@ static bool alloc_code_gen_buffer_splitwx_memfd(size_= t size, Error **errp) void *buf_rw =3D NULL, *buf_rx =3D MAP_FAILED; int fd =3D -1; =20 -#ifdef __mips__ - /* Find space for the RX mapping, vs the 256MiB regions. */ - if (alloc_code_gen_buffer_anon(size, PROT_NONE, - MAP_PRIVATE | MAP_ANONYMOUS | - MAP_NORESERVE, errp) < 0) { - return false; - } - /* The size of the mapping may have been adjusted. */ - buf_rx =3D region.start_aligned; - size =3D region.total_size; -#endif - buf_rw =3D qemu_memfd_alloc("tcg-jit", size, 0, &fd, errp); if (buf_rw =3D=3D NULL) { goto fail; } =20 -#ifdef __mips__ - void *tmp =3D mmap(buf_rx, size, PROT_READ | PROT_EXEC, - MAP_SHARED | MAP_FIXED, fd, 0); - if (tmp !=3D buf_rx) { - goto fail_rx; - } -#else buf_rx =3D mmap(NULL, size, PROT_READ | PROT_EXEC, MAP_SHARED, fd, 0); if (buf_rx =3D=3D MAP_FAILED) { goto fail_rx; } -#endif =20 close(fd); region.start_aligned =3D buf_rw; --=20 2.25.1 From nobody Fri May 17 13:45:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1632191548; cv=none; d=zohomail.com; s=zohoarc; b=D/pXhoGJNTQvS+jbjXYzBFzgOy+YNlH/4JHByXCnDDKlQPWQ82oBt3eUSqVpojoumbs+X2JCq8XHLAp9OQBSAqujBCj4NiBPvPtx3WL5PCqmqTsxd+CrcEdYn/dPut09yRTWGiHZCr6PTiFQpctjvGPI46+kDpnWK/SQahg6NVg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1632191548; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1632191548456100001 Let the compiler decide about inlining. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 45 +++++++++++++++++++------------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 688827968b..1763253edd 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -294,12 +294,12 @@ static const int tcg_target_call_oarg_regs[] =3D { bool use_vis3_instructions; #endif =20 -static inline int check_fit_i64(int64_t val, unsigned int bits) +static bool check_fit_i64(int64_t val, unsigned int bits) { return val =3D=3D sextract64(val, 0, bits); } =20 -static inline int check_fit_i32(int32_t val, unsigned int bits) +static bool check_fit_i32(int32_t val, unsigned int bits) { return val =3D=3D sextract32(val, 0, bits); } @@ -362,14 +362,14 @@ static bool tcg_target_const_match(int64_t val, TCGTy= pe type, int ct) } } =20 -static inline void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, - TCGReg rs2, int op) +static void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, + TCGReg rs2, int op) { tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2)); } =20 -static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, - int32_t offset, int op) +static void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, + int32_t offset, int op) { tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset)); } @@ -381,8 +381,7 @@ static void tcg_out_arithc(TCGContext *s, TCGReg rd, TC= GReg rs1, | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); } =20 -static inline bool tcg_out_mov(TCGContext *s, TCGType type, - TCGReg ret, TCGReg arg) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { if (ret !=3D arg) { tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); @@ -390,12 +389,12 @@ static inline bool tcg_out_mov(TCGContext *s, TCGType= type, return true; } =20 -static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) +static void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) { tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); } =20 -static inline void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t a= rg) +static void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg) { tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); } @@ -470,14 +469,14 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, } } =20 -static inline void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) { tcg_out_movi_int(s, type, ret, arg, false); } =20 -static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, - TCGReg a2, int op) +static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, + TCGReg a2, int op) { tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2)); } @@ -494,20 +493,20 @@ static void tcg_out_ldst(TCGContext *s, TCGReg ret, T= CGReg addr, } } =20 -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, - TCGReg arg1, intptr_t arg2) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, + TCGReg arg1, intptr_t arg2) { tcg_out_ldst(s, ret, arg1, arg2, (type =3D=3D TCG_TYPE_I32 ? LDUW : LD= X)); } =20 -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { tcg_out_ldst(s, arg, arg1, arg2, (type =3D=3D TCG_TYPE_I32 ? STW : STX= )); } =20 -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) { if (val =3D=3D 0) { tcg_out_st(s, type, TCG_REG_G0, base, ofs); @@ -527,12 +526,12 @@ static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret,= const void *arg) tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, (uintptr_t)arg & 0x3ff); } =20 -static inline void tcg_out_sety(TCGContext *s, TCGReg rs) +static void tcg_out_sety(TCGContext *s, TCGReg rs) { tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); } =20 -static inline void tcg_out_rdy(TCGContext *s, TCGReg rd) +static void tcg_out_rdy(TCGContext *s, TCGReg rd) { tcg_out32(s, RDY | INSN_RD(rd)); } @@ -552,7 +551,7 @@ static void tcg_out_div32(TCGContext *s, TCGReg rd, TCG= Reg rs1, uns ? ARITH_UDIV : ARITH_SDIV); } =20 -static inline void tcg_out_nop(TCGContext *s) +static void tcg_out_nop(TCGContext *s) { tcg_out32(s, NOP); } --=20 2.25.1 From nobody Fri May 17 13:45:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1632191382; cv=none; d=zohomail.com; s=zohoarc; b=f69rD5rIvOOOqTSTP3rbD19uVN8bDULCsXXDcNkN5VaQwTyoJajzeOBlpoKA9mzt71qEh4zO6V57JTH2c+Wn9Cw2bWH77LQtY1KQuB8WJt6Ff8bQioW3MgG+P+rcz3Zc9dls0ESaxYwWuoY8xpC80lkJ2Av4kZXXhjq7xKezR1w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1632191382; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1632191384916100001 This version of tcg_out_mov is emits a nop to fill the delay slot if the move is not required. The only current use, for INDEX_op_goto_ptr, will always require the move but properly documents the delay slot. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 1763253edd..9720d76abd 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -362,6 +362,11 @@ static bool tcg_target_const_match(int64_t val, TCGTyp= e type, int ct) } } =20 +static void tcg_out_nop(TCGContext *s) +{ + tcg_out32(s, NOP); +} + static void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, TCGReg rs2, int op) { @@ -389,6 +394,15 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, T= CGReg ret, TCGReg arg) return true; } =20 +static void tcg_out_mov_delay(TCGContext *s, TCGReg ret, TCGReg arg) +{ + if (ret !=3D arg) { + tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); + } else { + tcg_out_nop(s); + } +} + static void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) { tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); @@ -551,11 +565,6 @@ static void tcg_out_div32(TCGContext *s, TCGReg rd, TC= GReg rs1, uns ? ARITH_UDIV : ARITH_SDIV); } =20 -static void tcg_out_nop(TCGContext *s) -{ - tcg_out32(s, NOP); -} - static const uint8_t tcg_cond_to_bcond[] =3D { [TCG_COND_EQ] =3D COND_E, [TCG_COND_NE] =3D COND_NE, @@ -1349,7 +1358,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_ptr: tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); if (USE_REG_TB) { - tcg_out_arith(s, TCG_REG_TB, a0, TCG_REG_G0, ARITH_OR); + tcg_out_mov_delay(s, TCG_REG_TB, a0); } else { tcg_out_nop(s); } --=20 2.25.1 From nobody Fri May 17 13:45:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1632191608947344.3786961807102; Mon, 20 Sep 2021 19:33:28 -0700 (PDT) Received: from localhost ([::1]:54406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSVb5-0004It-JA for importer@patchew.org; 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Mon, 20 Sep 2021 19:25:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 09/10] hw/core: Make do_unaligned_access noreturn Date: Mon, 20 Sep 2021 19:25:33 -0700 Message-Id: <20210921022534.365291-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210921022534.365291-1-richard.henderson@linaro.org> References: <20210921022534.365291-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , peter.maydell@linaro.org, Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1632191610383100001 While we may have had some thought of allowing system-mode to return from this hook, we have no guests that require this. Reviewed-by: Alistair Francis Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 3 ++- target/alpha/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/microblaze/cpu.h | 2 +- target/mips/tcg/tcg-internal.h | 4 ++-- target/nios2/cpu.h | 4 ++-- target/ppc/internal.h | 4 ++-- target/riscv/cpu.h | 2 +- target/s390x/s390x-internal.h | 4 ++-- target/sh4/cpu.h | 4 ++-- target/xtensa/cpu.h | 4 ++-- target/hppa/cpu.c | 7 ++++--- 12 files changed, 23 insertions(+), 21 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 55123cb4d2..6cbe17f2e6 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -78,10 +78,11 @@ struct TCGCPUOps { MemTxResult response, uintptr_t retaddr); /** * @do_unaligned_access: Callback for unaligned access handling + * The callback must exit via raising an exception. */ void (*do_unaligned_access)(CPUState *cpu, vaddr addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + int mmu_idx, uintptr_t retaddr) QEMU_NORET= URN; =20 /** * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by A= RM diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index ce9ec32199..772828cc26 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -283,8 +283,8 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vad= dr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 #define cpu_list alpha_cpu_list =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index cd2ea8a388..8a77929793 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -594,7 +594,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, = ARMMMUIdx mmu_idx); /* Raise a data fault alignment exception for the specified virtual addres= s */ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + int mmu_idx, uintptr_t retaddr) QEMU_NORE= TURN; =20 /* arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 13ed3cd4dd..b7a848bbae 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -361,7 +361,7 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); #endif /* !CONFIG_USER_ONLY */ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + int mmu_idx, uintptr_t retaddr) QEMU_NORET= URN; void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index c7a77ddccd..bad3deb611 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -22,8 +22,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 const char *mips_exception_name(int32_t exception); =20 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 88a511209c..a80587338a 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -197,8 +197,8 @@ void dump_mmu(CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 void do_nios2_semihosting(CPUNios2State *env); =20 diff --git a/target/ppc/internal.h b/target/ppc/internal.h index b71406fa46..55284369f5 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -213,8 +213,8 @@ void helper_compute_fprf_float128(CPUPPCState *env, flo= at128 arg); =20 /* Raise a data fault alignment exception for the specified virtual addres= s */ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 /* translate.c */ =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 465142616a..5896aca346 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -344,7 +344,7 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch= ); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr); + uintptr_t retaddr) QEMU_NORETURN; bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 7a6aa4dacc..27d4a03ca1 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -274,8 +274,8 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 =20 /* fpu_helper.c */ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 56f7c32df9..dc81406646 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -209,8 +209,8 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, va= ddr addr); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 void sh4_translate_init(void); bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 646965f379..f9a510ca46 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -581,8 +581,8 @@ void xtensa_count_regs(const XtensaConfig *config, int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 #define cpu_list xtensa_cpu_list =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e8edd189bf..89cba9d7a2 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -72,9 +72,10 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disass= emble_info *info) } =20 #ifndef CONFIG_USER_ONLY -static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +static void QEMU_NORETURN +hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) { HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; --=20 2.25.1 From nobody Fri May 17 13:45:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1632191387023100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c16f96b401..dc8d8f1de2 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1130,10 +1130,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is_64) tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } - - if (guest_base =3D=3D 0) { - tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); - } else { + if (guest_base !=3D 0) { tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); } tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); @@ -1199,10 +1196,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is_64) tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } - - if (guest_base =3D=3D 0) { - tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); - } else { + if (guest_base !=3D 0) { tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); } tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); --=20 2.25.1