From nobody Tue Feb 10 04:17:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163215532689614.132290745276578; Mon, 20 Sep 2021 09:28:46 -0700 (PDT) Received: from localhost ([::1]:59522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSM9t-0006cZ-LU for importer@patchew.org; Mon, 20 Sep 2021 12:28:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSM4f-0005pF-MD for qemu-devel@nongnu.org; Mon, 20 Sep 2021 12:23:22 -0400 Received: from 6.mo548.mail-out.ovh.net ([188.165.58.48]:53485) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSM4Y-0004Ay-PS for qemu-devel@nongnu.org; Mon, 20 Sep 2021 12:23:21 -0400 Received: from mxplan5.mail.ovh.net (unknown [10.109.146.59]) by mo548.mail-out.ovh.net (Postfix) with ESMTPS id 1362620368; Mon, 20 Sep 2021 16:23:12 +0000 (UTC) Received: from kaod.org (37.59.142.103) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Mon, 20 Sep 2021 18:23:10 +0200 Authentication-Results: garm.ovh; auth=pass (GARM-103G0052dd609b7-64c2-4a11-b010-309c826dc833, C584E5EC745A9DFF7B561FC81DF43D5934FDEC9F) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Subject: [PATCH v2 01/12] aspeed/smc: Add watchdog Control/Status Registers Date: Mon, 20 Sep 2021 18:22:58 +0200 Message-ID: <20210920162309.1091711-2-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210920162309.1091711-1-clg@kaod.org> References: <20210920162309.1091711-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [37.59.142.103] X-ClientProxiedBy: DAG3EX2.mxp5.local (172.16.2.22) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: be3cb23c-aee0-4719-b80d-b7e5ec769d27 X-Ovh-Tracer-Id: 13073668244358728553 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvtddrudeivddgleelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrddutdefnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopegtlhhgsehkrghougdrohhrgh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.165.58.48; envelope-from=clg@kaod.org; helo=6.mo548.mail-out.ovh.net X-Spam_score_int: 0 X-Spam_score: -0.0 X-Spam_bar: / X-Spam_report: (-0.0 / 5.0 requ) RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Delevoryas , Joel Stanley Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1632155328465100001 The Aspeed SoCs have a dual boot function for firmware fail-over recovery. The system auto-reboots from the second flash if the main flash does not boot sucessfully within a certain amount of time. This function is called alternate boot (ABR) in the FMC controllers. On AST2400/AST2500, ABR is enabled by hardware strapping in SCU70 to enable the 2nd watchdog timer, on AST2600, through register SCU510. If the boot on the the main flash succeeds, the firmware should disable the 2nd watchdog timer. If not, the BMC is reset and the CE0 and CE1 mappings are swapped to restart the BMC from the 2nd flash. On the AST2600, the ABR registers controlling the 2nd watchdog timer were moved from the watchdog register to the FMC controller and the FMC model should be able to control WDT2 through its own register set. This requires more work. For now, add dummy read/write handlers to let the FW disable the 2nd watchdog without error. Reviewed-by: Peter Delevoryas Reported-by: Peter Delevoryas Signed-off-by: C=C3=A9dric Le Goater --- hw/ssi/aspeed_smc.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 331a2c544635..715f85007d5e 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -124,6 +124,13 @@ /* SPI dummy cycle data */ #define R_DUMMY_DATA (0x54 / 4) =20 +/* FMC_WDT2 Control/Status Register for Alternate Boot (AST2600) */ +#define R_FMC_WDT2_CTRL (0x64 / 4) +#define FMC_WDT2_CTRL_ALT_BOOT_MODE BIT(6) /* O: 2 chips 1: 1 chip */ +#define FMC_WDT2_CTRL_SINGLE_BOOT_MODE BIT(5) +#define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4) /* O: primary 1: alternate= */ +#define FMC_WDT2_CTRL_EN BIT(0) + /* DMA Control/Status Register */ #define R_DMA_CTRL (0x80 / 4) #define DMA_CTRL_REQUEST (1 << 31) @@ -263,12 +270,18 @@ static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *= s, uint32_t value); =20 #define ASPEED_SMC_FEATURE_DMA 0x1 #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2 +#define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4 =20 static inline bool aspeed_smc_has_dma(const AspeedSMCState *s) { return !!(s->ctrl->features & ASPEED_SMC_FEATURE_DMA); } =20 +static inline bool aspeed_smc_has_wdt_control(const AspeedSMCState *s) +{ + return !!(s->ctrl->features & ASPEED_SMC_FEATURE_WDT_CONTROL); +} + static const AspeedSMCController controllers[] =3D { { .name =3D "aspeed.smc-ast2400", @@ -388,7 +401,8 @@ static const AspeedSMCController controllers[] =3D { .segments =3D aspeed_segments_ast2600_fmc, .flash_window_base =3D ASPEED26_SOC_FMC_FLASH_BASE, .flash_window_size =3D 0x10000000, - .features =3D ASPEED_SMC_FEATURE_DMA, + .features =3D ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_WDT_CONTROL, .dma_flash_mask =3D 0x0FFFFFFC, .dma_dram_mask =3D 0x3FFFFFFC, .nregs =3D ASPEED_SMC_R_MAX, @@ -1019,6 +1033,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr = addr, unsigned int size) addr =3D=3D R_CE_CMD_CTRL || addr =3D=3D R_INTR_CTRL || addr =3D=3D R_DUMMY_DATA || + (aspeed_smc_has_wdt_control(s) && addr =3D=3D R_FMC_WDT2_CTRL) || (aspeed_smc_has_dma(s) && addr =3D=3D R_DMA_CTRL) || (aspeed_smc_has_dma(s) && addr =3D=3D R_DMA_FLASH_ADDR) || (aspeed_smc_has_dma(s) && addr =3D=3D R_DMA_DRAM_ADDR) || @@ -1350,6 +1365,8 @@ static void aspeed_smc_write(void *opaque, hwaddr add= r, uint64_t data, s->regs[addr] =3D value & 0xff; } else if (addr =3D=3D R_DUMMY_DATA) { s->regs[addr] =3D value & 0xff; + } else if (aspeed_smc_has_wdt_control(s) && addr =3D=3D R_FMC_WDT2_CTR= L) { + s->regs[addr] =3D value & FMC_WDT2_CTRL_EN; } else if (addr =3D=3D R_INTR_CTRL) { s->regs[addr] =3D value; } else if (aspeed_smc_has_dma(s) && addr =3D=3D R_DMA_CTRL) { --=20 2.31.1