From nobody Mon Apr 29 05:19:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1632106074015965.8301372902083; Sun, 19 Sep 2021 19:47:54 -0700 (PDT) Received: from localhost ([::1]:44264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mS9LT-00085E-SN for importer@patchew.org; Sun, 19 Sep 2021 22:47:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57442) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mS9Is-0005Cm-Ky for qemu-devel@nongnu.org; Sun, 19 Sep 2021 22:45:10 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:34576) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mS9Iq-0008Ca-NC for qemu-devel@nongnu.org; Sun, 19 Sep 2021 22:45:10 -0400 Received: by mail-pf1-x42c.google.com with SMTP id g14so14936718pfm.1 for ; Sun, 19 Sep 2021 19:45:08 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id fh3sm16164767pjb.8.2021.09.19.19.45.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Sep 2021 19:45:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CtQUY+VgkQT1rox5MwFOniOvDKV16giSUD56+x0u+Dc=; b=jq+L2dnpHgrIK8wcRbWEzdX1zmYvJLjQfMVbUGR4wS88LLKplbSxzc4XWI6Aik9tJ1 PH/bvimKg1PX70MeUorumde1SLeQgR7AmRRIjDxFihVrgnsHDg/8dAZBzByqroPcPJa1 UH0cawgvVP3AUID2VAIcK0pAr7YYvzqyWu2cr9RDvTbmnE2Jench5Hur/ggt/6nnwExk 9qWnipQvfkI+Kd3/7cTvJUg96W/2a5PO0XW6oDio2+RWdWB/4EBLIHApSV6Z9kTWC5cO a1kRrEdzysZS11olOY8N4Hra8SKhE+Aqaz8RtOwKdrIzbubzRRC61W+16bf+racCXJHB sGhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CtQUY+VgkQT1rox5MwFOniOvDKV16giSUD56+x0u+Dc=; b=0u7O/08xkQlyGdP/uCUyLiyw3YGH0E0sTNc5Gfbt6marp3ajH7sl04Nbp1E1mbeqkN dMBnJ74YztKAlCEjVnSJntH1MZ4miLUEagCG0xhvfEUkrLrnmM/iUiuLCiakUoYuFe1K gWflzsnmwefz6yAYZB4NyJcjDVWg2NBxUR4sCgsBpRJTIeopkz0SR5Im+Onca++x5QMt hIXMByqjZPAFByfPwqGsJKc/wVt+tnMZxuz3d0GK0wx2trmJ6hqk1Zfvuel/YTgyOhHB uaIR1wkz4zbkGI7JJfsLPJ4LFvU/tzsLxZ06LlA8otwfpbXSXGKDExn0JYyq+6U4M1mG RvVg== X-Gm-Message-State: AOAM531FbhEsHkPqg1odLz8orMMyWl0CnMtRUySBuU5Son0FfATKjvkc xqpePgRr5Wwc0F3hyk5kN+HIPon1fKMMtw== X-Google-Smtp-Source: ABdhPJyYR9qBS4L93E7BENRUPkFYmrGz6MebrvpJacEv/ZYH5nfvp91CO0yiLPJezhmCh73PEO9AWw== X-Received: by 2002:a65:6487:: with SMTP id e7mr21295360pgv.27.1632105907014; Sun, 19 Sep 2021 19:45:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 1/6] linux-user/aarch64: Handle EC_PCALIGNMENT Date: Sun, 19 Sep 2021 19:44:59 -0700 Message-Id: <20210920024504.625965-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210920024504.625965-1-richard.henderson@linaro.org> References: <20210920024504.625965-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1632106076524100001 Content-Type: text/plain; charset="utf-8" This will shortly be raised for execution with a misaligned pc. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 44 +++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 17 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 11e34cb100..6e03afb2bd 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -78,7 +78,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); - int trapnr, ec, fsc, si_code; + int trapnr, ec, fsc, si_sig, si_code; abi_long ret; =20 for (;;) { @@ -112,28 +112,38 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* We should only arrive here with EC in {DATAABORT, INSNABORT= }. */ ec =3D syn_get_ec(env->exception.syndrome); - assert(ec =3D=3D EC_DATAABORT || ec =3D=3D EC_INSNABORT); - - /* Both EC have the same format for FSC, or close enough. */ - fsc =3D extract32(env->exception.syndrome, 0, 6); - switch (fsc) { - case 0x04 ... 0x07: /* Translation fault, level {0-3} */ - si_code =3D TARGET_SEGV_MAPERR; + switch (ec) { + case EC_DATAABORT: + case EC_INSNABORT: + /* Both EC have the same format for FSC, or close enough. = */ + fsc =3D extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_sig =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_sig =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_ACCERR; + break; + case 0x11: /* Synchronous Tag Check Fault */ + si_sig =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_MTESERR; + break; + default: + g_assert_not_reached(); + } break; - case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ - case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ - si_code =3D TARGET_SEGV_ACCERR; - break; - case 0x11: /* Synchronous Tag Check Fault */ - si_code =3D TARGET_SEGV_MTESERR; + case EC_PCALIGNMENT: + si_sig =3D TARGET_SIGBUS; + si_code =3D TARGET_BUS_ADRALN; break; default: g_assert_not_reached(); } - - force_sig_fault(TARGET_SIGSEGV, si_code, env->exception.vaddre= ss); + force_sig_fault(si_sig, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: --=20 2.25.1 From nobody Mon Apr 29 05:19:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1632106074166157.81955121047963; Sun, 19 Sep 2021 19:47:54 -0700 (PDT) Received: from localhost ([::1]:44312 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mS9LU-00086n-Ve for importer@patchew.org; Sun, 19 Sep 2021 22:47:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57450) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mS9It-0005D0-5d for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1632106076527100002 Content-Type: text/plain; charset="utf-8" Pull the fault information from where we placed it, in arm_cpu_tlb_fill and arm_cpu_do_unaligned_access. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/arm/cpu_loop.c | 39 ++++++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index d4b4f0c71f..1377a80620 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -24,6 +24,7 @@ #include "cpu_loop-common.h" #include "signal-common.h" #include "semihosting/common-semi.h" +#include "target/arm/syndrome.h" =20 #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ @@ -279,8 +280,8 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint32_= t opcode) void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); - int trapnr; - unsigned int n, insn; + int trapnr, si_signo, si_code; + unsigned int n, insn, ec, fsc; abi_ulong ret; =20 for(;;) { @@ -422,9 +423,37 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* XXX: check env->error_code */ - force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, - env->exception.vaddress); + /* + * For user-only we don't set TTBCR_EAE, so we always get + * short-form FSC, which then tells us to look at the FSR. + */ + ec =3D syn_get_ec(env->exception.syndrome); + assert(ec =3D=3D EC_DATAABORT || ec =3D=3D EC_INSNABORT); + fsc =3D extract32(env->exception.syndrome, 0, 6); + assert(fsc =3D=3D 0x3f); + switch (env->exception.fsr & 0x1f) { + case 0x1: /* Alignment */ + si_signo =3D TARGET_SIGBUS; + si_code =3D TARGET_BUS_ADRALN; + break; + case 0x3: /* Access flag fault, level 1 */ + case 0x6: /* Access flag fault, level 2 */ + case 0x9: /* Domain fault, level 1 */ + case 0xb: /* Domain fault, level 2 */ + case 0xd: /* Permission fault, level 1 */ + case 0xf: /* Permission fault, level 2 */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_ACCERR; + break; + case 0x5: /* Translation fault, level 1 */ + case 0x7: /* Translation fault, level 2 */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_MAPERR; + break; + default: + g_assert_not_reached(); + } + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: --=20 2.25.1 From nobody Mon Apr 29 05:19:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1632106081; cv=none; d=zohomail.com; s=zohoarc; b=EOSvElIXBKMrMj4crBN2PFcsAKXLvUvexlZg/VoUa80lolAQSy45rZ8ZRlTLUPXbmeST5jB1bacwpZQ6vhANKae5uikol0ves8MujNKTltvAHk5HkKtGpV364kEnaF11roLi+obbA3DmXJUKxjC62t5P4WmO+R35BRbWSextaoA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1632106081; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cOM7VdjppvOQio1FebUdQG/S4ihUXuMBVVoQ3T4V5Ts=; b=YO7fG/Oz35xvZaG4+fBP1ipahIZ5mOY13GmxTlzG58U82fShXapF6kjNJEicLiMehOQUDvjKr0i1Gh9oDxAAbJ/7xXjQlyy4rQwrdmkkSXmNRA1lZJMEu+gPs6jb9kSbmv2QW1LUFofsgS+zH68NMKFTiT5mGp7Eiyxbf9I1zUI= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1632106082761100001 Content-Type: text/plain; charset="utf-8" For A64, any input to an indirect branch can cause this. For A32, many indirect branch paths force the branch to be aligned, but BXWritePC does not. This includes the BX instruction but also other interworking changes to PC. Prior to v8, this case is UNDEFINED. With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an exception or force align the PC. We choose to raise an exception because we have the infrastructure, it makes the generated code for gen_bx simpler, and it has the possibility of catching more guest bugs. Signed-off-by: Richard Henderson --- target/arm/helper.h | 1 + target/arm/syndrome.h | 5 +++++ target/arm/tlb_helper.c | 24 +++++++++++++++++++++++ target/arm/translate-a64.c | 23 +++++++++++++++++++--- target/arm/translate.c | 39 +++++++++++++++++++++++++++++++------- 5 files changed, 82 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 448a86edfd..b463d9343b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, DEF_HELPER_2(exception_internal, void, env, i32) DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, void, env, i32) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index f30f4130a2..8cde8e7243 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -282,4 +282,9 @@ static inline uint32_t syn_illegalstate(void) return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; } =20 +static inline uint32_t syn_pcalignment(void) +{ + return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index dc5860180f..1a50927bd6 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -9,6 +9,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/helper-proto.h" =20 static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, @@ -123,6 +124,29 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr v= addr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } =20 +void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) +{ + int target_el =3D exception_target_el(env); + + if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el)) { + /* + * To aarch64 and aarch32 el2, pc alignment has a + * special exception class. + */ + env->exception.vaddress =3D pc; + env->exception.fsr =3D 0; + raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), targe= t_el); + } else { + /* + * To aarch32 el1, pc alignment is like data alignment + * except with a prefetch abort. + */ + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_Alignment }; + arm_deliver_fault(env_archcpu(env), pc, MMU_INST_FETCH, + cpu_mmu_index(env, true), &fi); + } +} + #if !defined(CONFIG_USER_ONLY) =20 /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ab6b346e35..8c72e37de3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14752,8 +14752,10 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) { DisasContext *s =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; + uint64_t pc =3D s->base.pc_next; uint32_t insn; =20 + /* Singlestep exceptions have the highest priority. */ if (s->ss_active && !s->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -14768,13 +14770,28 @@ static void aarch64_tr_translate_insn(DisasContex= tBase *dcbase, CPUState *cpu) assert(s->base.num_insns =3D=3D 1); gen_swstep_exception(s, 0, 0); s->base.is_jmp =3D DISAS_NORETURN; + s->base.pc_next =3D pc + 4; return; } =20 - s->pc_curr =3D s->base.pc_next; - insn =3D arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b); + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abo= rt + * that we would receive from a translation fault via arm_ldl_code. + * This should only be possible after an indirect branch, at the + * start of the TB. + */ + assert(s->base.num_insns =3D=3D 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + s->base.is_jmp =3D DISAS_NORETURN; + s->base.pc_next =3D QEMU_ALIGN_UP(pc, 4); + return; + } + + s->pc_curr =3D pc; + insn =3D arm_ldl_code(env, &s->base, pc, s->sctlr_b); s->insn =3D insn; - s->base.pc_next +=3D 4; + s->base.pc_next =3D pc + 4; =20 s->fp_access_checked =3D false; s->sve_access_checked =3D false; diff --git a/target/arm/translate.c b/target/arm/translate.c index caefb1e1a1..62c396b880 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9497,7 +9497,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cpu) dc->insn_start =3D tcg_last_op(); } =20 -static bool arm_pre_translate_insn(DisasContext *dc) +static bool arm_check_kernelpage(DisasContext *dc) { #ifdef CONFIG_USER_ONLY /* Intercept jump to the magic kernel page. */ @@ -9509,7 +9509,11 @@ static bool arm_pre_translate_insn(DisasContext *dc) return true; } #endif + return false; +} =20 +static bool arm_check_ss_active(DisasContext *dc) +{ if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -9543,17 +9547,38 @@ static void arm_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; + uint32_t pc =3D dc->base.pc_next; unsigned int insn; =20 - if (arm_pre_translate_insn(dc)) { - dc->base.pc_next +=3D 4; + /* Singlestep exceptions have the highest priority. */ + if (arm_check_ss_active(dc)) { + dc->base.pc_next =3D pc + 4; return; } =20 - dc->pc_curr =3D dc->base.pc_next; - insn =3D arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abo= rt + * that we would receive from a translation fault via arm_ldl_code + * (or the execution of the kernelpage entrypoint). This should on= ly + * be possible after an indirect branch, at the start of the TB. + */ + assert(dc->base.num_insns =3D=3D 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + dc->base.is_jmp =3D DISAS_NORETURN; + dc->base.pc_next =3D QEMU_ALIGN_UP(pc, 4); + return; + } + + if (arm_check_kernelpage(dc)) { + dc->base.pc_next =3D pc + 4; + return; + } + + dc->pc_curr =3D pc; + insn =3D arm_ldl_code(env, &dc->base, pc, dc->sctlr_b); dc->insn =3D insn; - dc->base.pc_next +=3D 4; + dc->base.pc_next =3D pc + 4; disas_arm_insn(dc, insn); =20 arm_post_translate_insn(dc); @@ -9615,7 +9640,7 @@ static void thumb_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) uint32_t insn; bool is_16bit; =20 - if (arm_pre_translate_insn(dc)) { + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next +=3D 2; return; } --=20 2.25.1 From nobody Mon Apr 29 05:19:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Sun, 19 Sep 2021 19:45:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 4/6] target/arm: Assert thumb pc is aligned Date: Sun, 19 Sep 2021 19:45:02 -0700 Message-Id: <20210920024504.625965-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210920024504.625965-1-richard.henderson@linaro.org> References: <20210920024504.625965-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1632106325973100001 Content-Type: text/plain; charset="utf-8" Misaligned thumb PC is architecturally impossible. Assert is better than proceeding, in case we've missed something somewhere. Expand a comment about aligning the pc in gdbstub. Fail an incoming migrate if a thumb pc is misaligned. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/gdbstub.c | 9 +++++++-- target/arm/machine.c | 9 +++++++++ target/arm/translate.c | 3 +++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 826601b341..a54b42418b 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -76,8 +76,13 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) =20 tmp =3D ldl_p(mem_buf); =20 - /* Mask out low bit of PC to workaround gdb bugs. This will probably - cause problems if we ever implement the Jazelle DBX extensions. */ + /* + * Mask out low bits of PC to workaround gdb bugs. + * This avoids an assert in thumb_tr_translate_insn, because it is + * architecturally impossible to misalign the pc. + * This will probably cause problems if we ever implement the + * Jazelle DBX extensions. + */ if (n =3D=3D 15) { tmp &=3D ~1; } diff --git a/target/arm/machine.c b/target/arm/machine.c index 81e30de824..b5004a67e9 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -781,6 +781,15 @@ static int cpu_post_load(void *opaque, int version_id) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); =20 + /* + * Misaligned thumb pc is architecturally impossible. + * We have an assert in thumb_tr_translate_insn to verify this. + * Fail an incoming migrate to avoid this assert. + */ + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { + return -1; + } + if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 62c396b880..e522cd2fbe 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9640,6 +9640,9 @@ static void thumb_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) uint32_t insn; bool is_16bit; =20 + /* Misaligned thumb PC is architecturally impossible. */ + assert((dc->base.pc_next & 1) =3D=3D 0); + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next +=3D 2; return; --=20 2.25.1 From nobody Mon Apr 29 05:19:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1632106293818684.103379517585; Sun, 19 Sep 2021 19:51:33 -0700 (PDT) Received: from localhost ([::1]:53032 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mS9P2-0005Sg-NV for importer@patchew.org; Sun, 19 Sep 2021 22:51:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57542) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mS9Iw-0005DK-Gs for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1632106294927100001 Content-Type: text/plain; charset="utf-8" Both single-step and pc alignment faults have priority over breakpoint exceptions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2983e36dd3..32f3caec23 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -220,6 +220,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; + target_ulong pc; int n; =20 /* @@ -231,6 +232,28 @@ bool arm_debug_check_breakpoint(CPUState *cs) return false; } =20 + /* + * Single-step exceptions have priority over breakpoint exceptions. + * If single-step state is active-pending, suppress the bp. + */ + if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { + return false; + } + + /* + * PC alignment faults have priority over breakpoint exceptions. + */ + pc =3D is_a64(env) ? env->pc : env->regs[15]; + if ((is_a64(env) || !env->thumb) && (pc & 3) !=3D 0) { + return false; + } + + /* + * Instruction aborts have priority over breakpoint exceptions. + * TODO: We would need to look up the page for PC and verify that + * it is present and executable. + */ + for (n =3D 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { if (bp_wp_matches(cpu, n, false)) { return true; --=20 2.25.1 From nobody Mon Apr 29 05:19:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1632106270418539.8055739732997; Sun, 19 Sep 2021 19:51:10 -0700 (PDT) Received: from localhost ([::1]:51898 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mS9Of-0004gP-G2 for importer@patchew.org; Sun, 19 Sep 2021 22:51:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57554) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mS9Iy-0005EV-Ux for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1632106272188100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++ tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 +-- tests/tcg/arm/Makefile.target | 4 +++ 4 files changed, 89 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/aarch64/pcalign-a64.c create mode 100644 tests/tcg/arm/pcalign-a32.c diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a6= 4.c new file mode 100644 index 0000000000..6b9277f919 --- /dev/null +++ b/tests/tcg/aarch64/pcalign-a64.c @@ -0,0 +1,37 @@ +/* Test PC misalignment exception */ + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code =3D=3D BUS_ADRALN); + assert(info->si_addr =3D=3D expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa =3D { + .sa_sigaction =3D sigbus, + .sa_flags =3D SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 1\n\t" + "str %0, %1\n\t" + "br %0\n" + "1:" + : "=3D&r"(tmp), "=3Dm"(expected)); + abort(); +} diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c new file mode 100644 index 0000000000..3c9c8cc97b --- /dev/null +++ b/tests/tcg/arm/pcalign-a32.c @@ -0,0 +1,46 @@ +/* Test PC misalignment exception */ + +#ifdef __thumb__ +#error "This test must be compiled for ARM" +#endif + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code =3D=3D BUS_ADRALN); + assert(info->si_addr =3D=3D expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa =3D { + .sa_sigaction =3D sigbus, + .sa_flags =3D SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 2\n\t" + "str %0, %1\n\t" + "bx %0\n" + "1:" + : "=3D&r"(tmp), "=3Dm"(expected)); + + /* + * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns + * the address or not. If so, we can legitimately fall through. + */ + return EXIT_SUCCESS; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 2c05c90d17..1d967901bd 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,8 +8,8 @@ VPATH +=3D $(ARM_SRC) AARCH64_SRC=3D$(SRC_PATH)/tests/tcg/aarch64 VPATH +=3D $(AARCH64_SRC) =20 -# Float-convert Tests -AARCH64_TESTS=3Dfcvt +# Base architecture tests +AARCH64_TESTS=3Dfcvt pcalign-a64 =20 fcvt: LDFLAGS+=3D-lm =20 diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index 5ab59ed6ce..f509d823d4 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -29,6 +29,10 @@ run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) =20 +# PC alignment test +ARM_TESTS +=3D pcalign-a32 +pcalign-a32: CFLAGS+=3D-marm + ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y) =20 # Semihosting smoke test for linux-user --=20 2.25.1