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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631992035092100001 Content-Type: text/plain; charset="utf-8" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 74 ++++++++++++++++++++- accel/tcg/user-exec.c | 94 +-------------------------- 2 files changed, 74 insertions(+), 94 deletions(-) diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch6= 4/host-signal.h index f4b4d65031..02a55c3372 100644 --- a/linux-user/host/aarch64/host-signal.h +++ b/linux-user/host/aarch64/host-signal.h @@ -1 +1,73 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef AARCH64_HOST_SIGNAL_H +#define AARCH64_HOST_SIGNAL_H + +/* Pre-3.16 kernel headers don't have these, so provide fallback definitio= ns */ +#ifndef ESR_MAGIC +#define ESR_MAGIC 0x45535201 +struct esr_context { + struct _aarch64_ctx head; + uint64_t esr; +}; +#endif + +static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) +{ + return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; +} + +static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) +{ + return (struct _aarch64_ctx *)((char *)hdr + hdr->size); +} + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + struct _aarch64_ctx *hdr; + uint32_t insn; + + /* Find the esr_context, which has the WnR bit in it */ + for (hdr =3D first_ctx(uc); hdr->magic; hdr =3D next_ctx(hdr)) { + if (hdr->magic =3D=3D ESR_MAGIC) { + struct esr_context const *ec =3D (struct esr_context const *)h= dr; + uint64_t esr =3D ec->esr; + + /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR b= it */ + return extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6, = 1) =3D=3D 1; + } + } + + /* + * Fall back to parsing instructions; will only be needed + * for really ancient (pre-3.16) kernels. + */ + insn =3D *(uint32_t *)host_signal_pc(uc); + + return (insn & 0xbfff0000) =3D=3D 0x0c000000 /* C3.3.1 */ + || (insn & 0xbfe00000) =3D=3D 0x0c800000 /* C3.3.2 */ + || (insn & 0xbfdf0000) =3D=3D 0x0d000000 /* C3.3.3 */ + || (insn & 0xbfc00000) =3D=3D 0x0d800000 /* C3.3.4 */ + || (insn & 0x3f400000) =3D=3D 0x08000000 /* C3.3.6 */ + || (insn & 0x3bc00000) =3D=3D 0x39000000 /* C3.3.13 */ + || (insn & 0x3fc00000) =3D=3D 0x3d800000 /* ... 128bit */ + /* Ignore bits 10, 11 & 21, controlling indexing. */ + || (insn & 0x3bc00000) =3D=3D 0x38000000 /* C3.3.8-12 */ + || (insn & 0x3fe00000) =3D=3D 0x3c800000 /* ... 128bit */ + /* Ignore bits 23 & 24, controlling indexing. */ + || (insn & 0x3a400000) =3D=3D 0x28000000; /* C3.3.7,14-16 */ +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e9c29f917d..8f4e788304 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,99 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong add= r, int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -#if defined(__aarch64__) - -#if defined(__NetBSD__) - -#include -#include - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - ucontext_t *uc =3D puc; - siginfo_t *si =3D pinfo; - unsigned long pc; - int is_write; - uint32_t esr; - - pc =3D uc->uc_mcontext.__gregs[_REG_PC]; - esr =3D si->si_trap; - - /* - * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC - * is 0b10010x: then bit 6 is the WnR bit - */ - is_write =3D extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6, 1)= =3D=3D 1; - return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask); -} - -#else - -#ifndef ESR_MAGIC -/* Pre-3.16 kernel headers don't have these, so provide fallback definitio= ns */ -#define ESR_MAGIC 0x45535201 -struct esr_context { - struct _aarch64_ctx head; - uint64_t esr; -}; -#endif - -static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) -{ - return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; -} - -static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) -{ - return (struct _aarch64_ctx *)((char *)hdr + hdr->size); -} - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - siginfo_t *info =3D pinfo; - ucontext_t *uc =3D puc; - uintptr_t pc =3D uc->uc_mcontext.pc; - bool is_write; - struct _aarch64_ctx *hdr; - struct esr_context const *esrctx =3D NULL; - - /* Find the esr_context, which has the WnR bit in it */ - for (hdr =3D first_ctx(uc); hdr->magic; hdr =3D next_ctx(hdr)) { - if (hdr->magic =3D=3D ESR_MAGIC) { - esrctx =3D (struct esr_context const *)hdr; - break; - } - } - - if (esrctx) { - /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ - uint64_t esr =3D esrctx->esr; - is_write =3D extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6= , 1) =3D=3D 1; - } else { - /* - * Fall back to parsing instructions; will only be needed - * for really ancient (pre-3.16) kernels. - */ - uint32_t insn =3D *(uint32_t *)pc; - - is_write =3D ((insn & 0xbfff0000) =3D=3D 0x0c000000 /* C3.3.1 */ - || (insn & 0xbfe00000) =3D=3D 0x0c800000 /* C3.3.2 */ - || (insn & 0xbfdf0000) =3D=3D 0x0d000000 /* C3.3.3 */ - || (insn & 0xbfc00000) =3D=3D 0x0d800000 /* C3.3.4 */ - || (insn & 0x3f400000) =3D=3D 0x08000000 /* C3.3.6 */ - || (insn & 0x3bc00000) =3D=3D 0x39000000 /* C3.3.13 = */ - || (insn & 0x3fc00000) =3D=3D 0x3d800000 /* ... 128b= it */ - /* Ignore bits 10, 11 & 21, controlling indexing. */ - || (insn & 0x3bc00000) =3D=3D 0x38000000 /* C3.3.8-1= 2 */ - || (insn & 0x3fe00000) =3D=3D 0x3c800000 /* ... 128b= it */ - /* Ignore bits 23 & 24, controlling indexing. */ - || (insn & 0x3a400000) =3D=3D 0x28000000); /* C3.3.7,1= 4-16 */ - } - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - -#elif defined(__s390__) +#if defined(__s390__) =20 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) --=20 2.25.1