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[123.193.74.252]) by smtp.gmail.com with ESMTPSA id x13sm4834003pfp.133.2021.09.16.23.14.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 23:14:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Ceq7xG2rKmgdAKPaWV1qoKr+d9zuGGdp+1TrLijyAjo=; b=k7XgeqQCmmIadrpJjgdMjmt6D0WMKQvbCXg9MsSZAnZl7xLMgRD0YD2j1gGbotyoMJ xlr2sZACFvaVMfkgYUKHUO24cBSP6aQBQDKGbnXp8r9JO27ctBLWqvPLFP8zucDRrTU/ c3raEygAEj0c//eOrQaBjzs9845eRPOLnZdBcgZLyY/GGTVI0p/pf1qjVKA2C4xaFOF/ KsAP3Ht4OhLlo1QtEmvuPx+FglJZIGnD5DX0TcWoU1EsUf8PcfpYEUEsgjWziqwPb+5f dhoqbzppdZvLCK/34GUz95R9LESEiIZHvIGIi+dnLJtZ2GsGjBjUspnREdBOJPlpMbTJ X1Ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Ceq7xG2rKmgdAKPaWV1qoKr+d9zuGGdp+1TrLijyAjo=; b=1CQJl8EmZ9HE9tfPkHaTW4cnp8x9xE3jF/aOeamCNMNNJBScwltiMyMNOZSMmKNmFv YuW0nszQKhjIXAfgdL4DJ+n+9y7cgAACoiXCZ6TkPzFkTMAM2owOSGyatPCi7bpOEISC HA0QhpIo1RqQFw4lIQyHTk4L75ClAN4aM1qOSJHX2oBm7wI+wj4+8Vs29PJgIqKpaKiI ibq9Kv2PMaxUhpPb/AdhnUc3B4Sw9L6bnI8s337IvoldMsrsbZCwn34WXC2HeDwXNuuv rKS14x7bVEzg1Y2gK9VjP4Xy3GQwvAF+luuoe8NOJIprHZtOPpsJSTSxeos8zMLm7Hdx Mwpw== X-Gm-Message-State: AOAM532GkhASl1fVpnWlif9jbzltL/4UHwK8iTZMYLbnphxqZm4SNgtz 4jBJiZIQr7SszOKVlI/QoyS4bs9Qg7PfEA== X-Google-Smtp-Source: ABdhPJwuGI57hbhqwKtNOeGRT/q/kKMGcZY4pE32XK0i2WQUApv9qCdJ8a+I0hWbqicGqZRuudfxDQ== X-Received: by 2002:a65:64c3:: with SMTP id t3mr8470461pgv.244.1631859288224; Thu, 16 Sep 2021 23:14:48 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty() Date: Fri, 17 Sep 2021 14:14:39 +0800 Message-Id: <20210917061441.3757201-1-frank.chang@sifive.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Vincent Chen , Alistair Francis , Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631859387055100001 Content-Type: text/plain; charset="utf-8" From: Frank Chang When V=3D1, both vsstauts.FS and HS-level sstatus.FS are in effect. Modifying the floating-point state when V=3D1 causes both fields to be set to 3 (Dirty). However, it's possible that HS-level sstatus.FS is Clean and VS-level vsstatus.FS is Dirty at the time mark_fs_dirty() is called when V=3D1. We can't early return for this case because we still need to set sstatus.FS to Dirty according to spec. Signed-off-by: Frank Chang Reviewed-by: Vincent Chen Tested-by: Vincent Chen --- target/riscv/cpu.h | 3 +++ target/riscv/translate.c | 24 +++++++++++++++--------- 2 files changed, 18 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e735e53e26c..c5cae45f955 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -394,6 +394,7 @@ FIELD(TB_FLAGS, SEW, 5, 3) FIELD(TB_FLAGS, VILL, 8, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 9, 1) +FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) =20 bool riscv_cpu_is_32bit(CPURISCVState *env); =20 @@ -450,6 +451,8 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *= env, target_ulong *pc, get_field(env->hstatus, HSTATUS_HU))) { flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } + + flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, env->mstatus_= hs); } #endif =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 74b33fa3c90..2b48db6fd02 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -58,6 +58,7 @@ typedef struct DisasContext { target_ulong misa; uint32_t opcode; uint32_t mstatus_fs; + uint32_t mstatus_hs_fs; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for @@ -280,26 +281,30 @@ static void gen_jal(DisasContext *ctx, int rd, target= _ulong imm) static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; - target_ulong sd; + target_ulong sd =3D is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; + + if (ctx->virt_enabled && ctx->mstatus_hs_fs !=3D MSTATUS_FS) { + /* Remember the stage change for the rest of the TB. */ + ctx->mstatus_hs_fs =3D MSTATUS_FS; + + tmp =3D tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_temp_free(tmp); + } =20 if (ctx->mstatus_fs =3D=3D MSTATUS_FS) { return; } + /* Remember the state change for the rest of the TB. */ ctx->mstatus_fs =3D MSTATUS_FS; =20 tmp =3D tcg_temp_new(); - sd =3D is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - - if (ctx->virt_enabled) { - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - } tcg_temp_free(tmp); } #else @@ -533,6 +538,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->frm =3D -1; /* unknown rounding mode */ ctx->ext_ifencei =3D cpu->cfg.ext_ifencei; ctx->vlen =3D cpu->cfg.vlen; + ctx->mstatus_hs_fs =3D FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); --=20 2.25.1