Patches applied successfully (
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git fetch https://github.com/patchew-project/qemu tags/patchew/20210916214904.734206-1-alistair.francis@opensource.wdc.com
Maintainers: Vijai Kumar K <vijai@behindbytes.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>
docs/system/riscv/sifive_u.rst | 50 ++--
docs/system/riscv/virt.rst | 10 +
include/hw/intc/ibex_plic.h | 2 +
include/hw/intc/riscv_aclint.h | 80 +++++
include/hw/intc/sifive_clint.h | 60 ----
include/hw/intc/sifive_plic.h | 4 +
include/hw/riscv/sifive_u.h | 14 +-
include/hw/riscv/virt.h | 2 +
include/hw/timer/ibex_timer.h | 2 +
include/hw/timer/sifive_pwm.h | 62 ++++
target/riscv/cpu_bits.h | 12 +-
hw/dma/sifive_pdma.c | 54 +++-
hw/intc/ibex_plic.c | 17 +-
hw/intc/riscv_aclint.c | 460 +++++++++++++++++++++++++++++
hw/intc/sifive_clint.c | 287 ------------------
hw/intc/sifive_plic.c | 30 +-
hw/riscv/microchip_pfsoc.c | 13 +-
hw/riscv/opentitan.c | 13 +-
hw/riscv/shakti_c.c | 16 +-
hw/riscv/sifive_e.c | 15 +-
hw/riscv/sifive_u.c | 68 ++++-
hw/riscv/spike.c | 16 +-
hw/riscv/virt.c | 654 ++++++++++++++++++++++++++++-------------
hw/timer/ibex_timer.c | 17 +-
hw/timer/sifive_pwm.c | 468 +++++++++++++++++++++++++++++
target/riscv/cpu.c | 31 ++
target/riscv/cpu_helper.c | 3 +-
target/riscv/csr.c | 26 +-
hw/intc/Kconfig | 2 +-
hw/intc/meson.build | 2 +-
hw/riscv/Kconfig | 13 +-
hw/timer/Kconfig | 3 +
hw/timer/meson.build | 1 +
hw/timer/trace-events | 6 +
34 files changed, 1844 insertions(+), 669 deletions(-)
create mode 100644 include/hw/intc/riscv_aclint.h
delete mode 100644 include/hw/intc/sifive_clint.h
create mode 100644 include/hw/timer/sifive_pwm.h
create mode 100644 hw/intc/riscv_aclint.c
delete mode 100644 hw/intc/sifive_clint.c
create mode 100644 hw/timer/sifive_pwm.c