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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ilya Leoshkevich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631578690878100001 Content-Type: text/plain; charset="utf-8" From: Ilya Leoshkevich Signed-off-by: Ilya Leoshkevich [rth: Split out of a larger patch.] Signed-off-by: Richard Henderson --- include/exec/translator.h | 9 +++++---- target/arm/arm_ldst.h | 12 ++++++------ target/alpha/translate.c | 2 +- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 9 +++++---- target/hexagon/translate.c | 3 ++- target/hppa/translate.c | 2 +- target/i386/tcg/translate.c | 10 +++++----- target/m68k/translate.c | 2 +- target/mips/tcg/translate.c | 8 ++++---- target/openrisc/translate.c | 2 +- target/ppc/translate.c | 5 +++-- target/riscv/translate.c | 5 +++-- target/s390x/tcg/translate.c | 16 +++++++++------- target/sh4/translate.c | 4 ++-- target/sparc/translate.c | 2 +- target/xtensa/translate.c | 5 +++-- target/mips/tcg/micromips_translate.c.inc | 2 +- target/mips/tcg/mips16e_translate.c.inc | 4 ++-- target/mips/tcg/nanomips_translate.c.inc | 4 ++-- 20 files changed, 58 insertions(+), 50 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index d318803267..6c054e8d05 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -157,7 +157,8 @@ bool translator_use_goto_tb(DisasContextBase *db, targe= t_ulong dest); =20 #define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \ static inline type \ - fullname ## _swap(CPUArchState *env, abi_ptr pc, bool do_swap) \ + fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \ + abi_ptr pc, bool do_swap) \ { \ type ret =3D load_fn(env, pc); \ if (do_swap) { \ @@ -166,10 +167,10 @@ bool translator_use_goto_tb(DisasContextBase *db, tar= get_ulong dest); plugin_insn_append(&ret, sizeof(ret)); \ return ret; \ } \ - \ - static inline type fullname(CPUArchState *env, abi_ptr pc) \ + static inline type fullname(CPUArchState *env, \ + DisasContextBase *dcbase, abi_ptr pc) \ { \ - return fullname ## _swap(env, pc, false); \ + return fullname ## _swap(env, dcbase, pc, false); \ } =20 GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h index 057160e8da..cee0548a1c 100644 --- a/target/arm/arm_ldst.h +++ b/target/arm/arm_ldst.h @@ -24,15 +24,15 @@ #include "qemu/bswap.h" =20 /* Load an instruction and return it in the standard little-endian order */ -static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr, - bool sctlr_b) +static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s, + target_ulong addr, bool sctlr_b) { - return translator_ldl_swap(env, addr, bswap_code(sctlr_b)); + return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b)); } =20 /* Ditto, for a halfword (Thumb) instruction */ -static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, - bool sctlr_b) +static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s, + target_ulong addr, bool sctlr_b) { #ifndef CONFIG_USER_ONLY /* In big-endian (BE32) mode, adjacent Thumb instructions have been sw= apped @@ -41,7 +41,7 @@ static inline uint16_t arm_lduw_code(CPUARMState *env, ta= rget_ulong addr, addr ^=3D 2; } #endif - return translator_lduw_swap(env, addr, bswap_code(sctlr_b)); + return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b)); } =20 #endif diff --git a/target/alpha/translate.c b/target/alpha/translate.c index de6c0a8439..b034206688 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2971,7 +2971,7 @@ static void alpha_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUAlphaState *env =3D cpu->env_ptr; - uint32_t insn =3D translator_ldl(env, ctx->base.pc_next); + uint32_t insn =3D translator_ldl(env, &ctx->base, ctx->base.pc_next); =20 ctx->base.pc_next +=3D 4; ctx->base.is_jmp =3D translate_one(ctx, insn); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 422e2ac0c9..a52949b1f3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14655,7 +14655,7 @@ static void disas_a64_insn(CPUARMState *env, DisasC= ontext *s) uint32_t insn; =20 s->pc_curr =3D s->base.pc_next; - insn =3D arm_ldl_code(env, s->base.pc_next, s->sctlr_b); + insn =3D arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b); s->insn =3D insn; s->base.pc_next +=3D 4; =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 24b7f49d76..422fca353d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9302,7 +9302,7 @@ static bool insn_crosses_page(CPUARMState *env, Disas= Context *s) * boundary, so we cross the page if the first 16 bits indicate * that this is a 32 bit insn. */ - uint16_t insn =3D arm_lduw_code(env, s->base.pc_next, s->sctlr_b); + uint16_t insn =3D arm_lduw_code(env, &s->base, s->base.pc_next, s->sct= lr_b); =20 return !thumb_insn_is_16bit(s, s->base.pc_next, insn); } @@ -9540,7 +9540,7 @@ static void arm_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cpu) } =20 dc->pc_curr =3D dc->base.pc_next; - insn =3D arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b); + insn =3D arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); dc->insn =3D insn; dc->base.pc_next +=3D 4; disas_arm_insn(dc, insn); @@ -9610,11 +9610,12 @@ static void thumb_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) } =20 dc->pc_curr =3D dc->base.pc_next; - insn =3D arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b); + insn =3D arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); is_16bit =3D thumb_insn_is_16bit(dc, dc->base.pc_next, insn); dc->base.pc_next +=3D 2; if (!is_16bit) { - uint32_t insn2 =3D arm_lduw_code(env, dc->base.pc_next, dc->sctlr_= b); + uint32_t insn2 =3D arm_lduw_code(env, &dc->base, dc->base.pc_next, + dc->sctlr_b); =20 insn =3D insn << 16 | insn2; dc->base.pc_next +=3D 2; diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 54fdcaa5e8..6fb4e6853c 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -112,7 +112,8 @@ static int read_packet_words(CPUHexagonState *env, Disa= sContext *ctx, memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t)); for (nwords =3D 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { words[nwords] =3D - translator_ldl(env, ctx->base.pc_next + nwords * sizeof(uint32= _t)); + translator_ldl(env, &ctx->base, + ctx->base.pc_next + nwords * sizeof(uint32_t)); found_end =3D is_packet_end(words[nwords]); } if (!found_end) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b18150ef8d..3ce22cdd09 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4177,7 +4177,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ - uint32_t insn =3D translator_ldl(env, ctx->base.pc_next); + uint32_t insn =3D translator_ldl(env, &ctx->base, ctx->base.pc_nex= t); =20 /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index aacb605eee..a46be75b00 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2028,28 +2028,28 @@ static uint64_t advance_pc(CPUX86State *env, DisasC= ontext *s, int num_bytes) =20 static inline uint8_t x86_ldub_code(CPUX86State *env, DisasContext *s) { - return translator_ldub(env, advance_pc(env, s, 1)); + return translator_ldub(env, &s->base, advance_pc(env, s, 1)); } =20 static inline int16_t x86_ldsw_code(CPUX86State *env, DisasContext *s) { - return translator_ldsw(env, advance_pc(env, s, 2)); + return translator_ldsw(env, &s->base, advance_pc(env, s, 2)); } =20 static inline uint16_t x86_lduw_code(CPUX86State *env, DisasContext *s) { - return translator_lduw(env, advance_pc(env, s, 2)); + return translator_lduw(env, &s->base, advance_pc(env, s, 2)); } =20 static inline uint32_t x86_ldl_code(CPUX86State *env, DisasContext *s) { - return translator_ldl(env, advance_pc(env, s, 4)); + return translator_ldl(env, &s->base, advance_pc(env, s, 4)); } =20 #ifdef TARGET_X86_64 static inline uint64_t x86_ldq_code(CPUX86State *env, DisasContext *s) { - return translator_ldq(env, advance_pc(env, s, 8)); + return translator_ldq(env, &s->base, advance_pc(env, s, 8)); } #endif =20 diff --git a/target/m68k/translate.c b/target/m68k/translate.c index c34d9aed61..50a55f949c 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -415,7 +415,7 @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv = addr, TCGv val, static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s) { uint16_t im; - im =3D translator_lduw(env, s->pc); + im =3D translator_lduw(env, &s->base, s->pc); s->pc +=3D 2; return im; } diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 6f4a9a839c..148afec9dc 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -16041,17 +16041,17 @@ static void mips_tr_translate_insn(DisasContextBa= se *dcbase, CPUState *cs) =20 is_slot =3D ctx->hflags & MIPS_HFLAG_BMASK; if (ctx->insn_flags & ISA_NANOMIPS32) { - ctx->opcode =3D translator_lduw(env, ctx->base.pc_next); + ctx->opcode =3D translator_lduw(env, &ctx->base, ctx->base.pc_next= ); insn_bytes =3D decode_isa_nanomips(env, ctx); } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { - ctx->opcode =3D translator_ldl(env, ctx->base.pc_next); + ctx->opcode =3D translator_ldl(env, &ctx->base, ctx->base.pc_next); insn_bytes =3D 4; decode_opc(env, ctx); } else if (ctx->insn_flags & ASE_MICROMIPS) { - ctx->opcode =3D translator_lduw(env, ctx->base.pc_next); + ctx->opcode =3D translator_lduw(env, &ctx->base, ctx->base.pc_next= ); insn_bytes =3D decode_isa_micromips(env, ctx); } else if (ctx->insn_flags & ASE_MIPS16) { - ctx->opcode =3D translator_lduw(env, ctx->base.pc_next); + ctx->opcode =3D translator_lduw(env, &ctx->base, ctx->base.pc_next= ); insn_bytes =3D decode_ase_mips16e(env, ctx); } else { gen_reserved_instruction(ctx); diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index d6ea536744..5f3d430245 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1613,7 +1613,7 @@ static void openrisc_tr_translate_insn(DisasContextBa= se *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - uint32_t insn =3D translator_ldl(&cpu->env, dc->base.pc_next); + uint32_t insn =3D translator_ldl(&cpu->env, &dc->base, dc->base.pc_nex= t); =20 if (!decode(dc, insn)) { gen_illegal_exception(dc); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 171b216e17..5d8b06bd80 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -8585,7 +8585,7 @@ static void ppc_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cs) ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); =20 ctx->cia =3D pc =3D ctx->base.pc_next; - insn =3D translator_ldl_swap(env, pc, need_byteswap(ctx)); + insn =3D translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); ctx->base.pc_next =3D pc +=3D 4; =20 if (!is_prefix_insn(ctx, insn)) { @@ -8600,7 +8600,8 @@ static void ppc_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cs) gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN= ); ok =3D true; } else { - uint32_t insn2 =3D translator_ldl_swap(env, pc, need_byteswap(ctx)= ); + uint32_t insn2 =3D translator_ldl_swap(env, dcbase, pc, + need_byteswap(ctx)); ctx->base.pc_next =3D pc +=3D 4; ok =3D decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e356fc6c46..74b33fa3c9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -500,7 +500,8 @@ static void decode_opc(CPURISCVState *env, DisasContext= *ctx, uint16_t opcode) } else { uint32_t opcode32 =3D opcode; opcode32 =3D deposit32(opcode32, 16, 16, - translator_lduw(env, ctx->base.pc_next + 2)); + translator_lduw(env, &ctx->base, + ctx->base.pc_next + 2)); ctx->pc_succ_insn =3D ctx->base.pc_next + 4; if (!decode_insn32(ctx, opcode32)) { gen_exception_illegal(ctx); @@ -561,7 +562,7 @@ static void riscv_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPURISCVState *env =3D cpu->env_ptr; - uint16_t opcode16 =3D translator_lduw(env, ctx->base.pc_next); + uint16_t opcode16 =3D translator_lduw(env, &ctx->base, ctx->base.pc_ne= xt); =20 decode_opc(env, ctx, opcode16); ctx->base.pc_next =3D ctx->pc_succ_insn; diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 0632b0374b..f284870cd2 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -388,14 +388,16 @@ static void update_cc_op(DisasContext *s) } } =20 -static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc) +static inline uint64_t ld_code2(CPUS390XState *env, DisasContext *s, + uint64_t pc) { - return (uint64_t)cpu_lduw_code(env, pc); + return (uint64_t)translator_lduw(env, &s->base, pc); } =20 -static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc) +static inline uint64_t ld_code4(CPUS390XState *env, DisasContext *s, + uint64_t pc) { - return (uint64_t)(uint32_t)cpu_ldl_code(env, pc); + return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc); } =20 static int get_mem_index(DisasContext *s) @@ -6273,7 +6275,7 @@ static const DisasInsn *extract_insn(CPUS390XState *e= nv, DisasContext *s) ilen =3D s->ex_value & 0xf; op =3D insn >> 56; } else { - insn =3D ld_code2(env, pc); + insn =3D ld_code2(env, s, pc); op =3D (insn >> 8) & 0xff; ilen =3D get_ilen(op); switch (ilen) { @@ -6281,10 +6283,10 @@ static const DisasInsn *extract_insn(CPUS390XState = *env, DisasContext *s) insn =3D insn << 48; break; case 4: - insn =3D ld_code4(env, pc) << 32; + insn =3D ld_code4(env, s, pc) << 32; break; case 6: - insn =3D (insn << 48) | (ld_code4(env, pc + 2) << 16); + insn =3D (insn << 48) | (ld_code4(env, s, pc + 2) << 16); break; default: g_assert_not_reached(); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8704fea1ca..cf5fe9243d 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1907,7 +1907,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Stat= e *env) =20 /* Read all of the insns for the region. */ for (i =3D 0; i < max_insns; ++i) { - insns[i] =3D translator_lduw(env, pc + i * 2); + insns[i] =3D translator_lduw(env, &ctx->base, pc + i * 2); } =20 ld_adr =3D ld_dst =3D ld_mop =3D -1; @@ -2307,7 +2307,7 @@ static void sh4_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cs) } #endif =20 - ctx->opcode =3D translator_lduw(env, ctx->base.pc_next); + ctx->opcode =3D translator_lduw(env, &ctx->base, ctx->base.pc_next); decode_opc(ctx); ctx->base.pc_next +=3D 2; } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bb70ba17de..fdb8bbe5dc 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5855,7 +5855,7 @@ static void sparc_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cs) CPUSPARCState *env =3D cs->env_ptr; unsigned int insn; =20 - insn =3D translator_ldl(env, dc->pc); + insn =3D translator_ldl(env, &dc->base, dc->pc); dc->base.pc_next +=3D 4; disas_sparc_insn(dc, insn); =20 diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 20399d6a04..dcf6b500ef 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -882,7 +882,8 @@ static int arg_copy_compare(const void *a, const void *= b) static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) { xtensa_isa isa =3D dc->config->isa; - unsigned char b[MAX_INSN_LENGTH] =3D {translator_ldub(env, dc->pc)}; + unsigned char b[MAX_INSN_LENGTH] =3D {translator_ldub(env, &dc->base, + dc->pc)}; unsigned len =3D xtensa_op0_insn_len(dc, b[0]); xtensa_format fmt; int slot, slots; @@ -907,7 +908,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, Disa= sContext *dc) =20 dc->base.pc_next =3D dc->pc + len; for (i =3D 1; i < len; ++i) { - b[i] =3D translator_ldub(env, dc->pc + i); + b[i] =3D translator_ldub(env, &dc->base, dc->pc + i); } xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len); fmt =3D xtensa_format_decode(isa, dc->insnbuf); diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/mi= cromips_translate.c.inc index 5e95f47854..0da4c802a3 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -1627,7 +1627,7 @@ static void decode_micromips32_opc(CPUMIPSState *env,= DisasContext *ctx) uint32_t op, minor, minor2, mips32_op; uint32_t cond, fmt, cc; =20 - insn =3D translator_lduw(env, ctx->base.pc_next + 2); + insn =3D translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); ctx->opcode =3D (ctx->opcode << 16) | insn; =20 rt =3D (ctx->opcode >> 21) & 0x1f; diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips= 16e_translate.c.inc index 54071813f1..84d816603a 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -455,7 +455,7 @@ static void decode_i64_mips16(DisasContext *ctx, =20 static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) { - int extend =3D translator_lduw(env, ctx->base.pc_next + 2); + int extend =3D translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); int op, rx, ry, funct, sa; int16_t imm, offset; =20 @@ -688,7 +688,7 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasC= ontext *ctx) /* No delay slot, so just process as a normal instruction */ break; case M16_OPC_JAL: - offset =3D translator_lduw(env, ctx->base.pc_next + 2); + offset =3D translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); offset =3D (((ctx->opcode & 0x1f) << 21) | ((ctx->opcode >> 5) & 0x1f) << 16 | offset) << 2; diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nan= omips_translate.c.inc index a66ae26796..ccbcecad09 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -3656,7 +3656,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) int offset; int imm; =20 - insn =3D translator_lduw(env, ctx->base.pc_next + 2); + insn =3D translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); ctx->opcode =3D (ctx->opcode << 16) | insn; =20 rt =3D extract32(ctx->opcode, 21, 5); @@ -3775,7 +3775,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) break; case NM_P48I: { - insn =3D translator_lduw(env, ctx->base.pc_next + 4); + insn =3D translator_lduw(env, &ctx->base, ctx->base.pc_next + = 4); target_long addr_off =3D extract32(ctx->opcode, 0, 16) | insn = << 16; switch (extract32(ctx->opcode, 16, 5)) { case NM_LI48: --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ilya Leoshkevich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631578692729100003 Content-Type: text/plain; charset="utf-8" From: Ilya Leoshkevich translate_insn() implementations fetch instruction bytes piecemeal, which can cause qemu-user to generate inconsistent translations if another thread modifies them concurrently [1]. Fix by making pages containing translated instruction non-writable right before loading instruction bytes from them. [1] https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00644.html Signed-off-by: Ilya Leoshkevich Message-Id: <20210805204835.158918-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- include/exec/translate-all.h | 1 + include/exec/translator.h | 39 ++++++++++++++---------- accel/tcg/translate-all.c | 59 +++++++++++++++++++++--------------- accel/tcg/translator.c | 39 ++++++++++++++++++++++++ 4 files changed, 97 insertions(+), 41 deletions(-) diff --git a/include/exec/translate-all.h b/include/exec/translate-all.h index a557b4e2bb..9f646389af 100644 --- a/include/exec/translate-all.h +++ b/include/exec/translate-all.h @@ -33,6 +33,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, = tb_page_addr_t end); void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); =20 #ifdef CONFIG_USER_ONLY +void page_protect(tb_page_addr_t page_addr); int page_unprotect(target_ulong address, uintptr_t pc); #endif =20 diff --git a/include/exec/translator.h b/include/exec/translator.h index 6c054e8d05..9bc46eda59 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/plugin-gen.h" +#include "exec/translate-all.h" #include "tcg/tcg.h" =20 =20 @@ -74,6 +75,17 @@ typedef struct DisasContextBase { int num_insns; int max_insns; bool singlestep_enabled; +#ifdef CONFIG_USER_ONLY + /* + * Guest address of the last byte of the last protected page. + * + * Pages containing the translated instructions are made non-writable = in + * order to achieve consistency in case another thread is modifying the + * code while translate_insn() fetches the instruction bytes piecemeal. + * Such writer threads are blocked on mmap_lock() in page_unprotect(). + */ + target_ulong page_protect_end; +#endif } DisasContextBase; =20 /** @@ -156,28 +168,23 @@ bool translator_use_goto_tb(DisasContextBase *db, tar= get_ulong dest); */ =20 #define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \ - static inline type \ - fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \ - abi_ptr pc, bool do_swap) \ - { \ - type ret =3D load_fn(env, pc); \ - if (do_swap) { \ - ret =3D swap_fn(ret); \ - } \ - plugin_insn_append(&ret, sizeof(ret)); \ - return ret; \ - } \ + type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \ + abi_ptr pc, bool do_swap); \ static inline type fullname(CPUArchState *env, \ DisasContextBase *dcbase, abi_ptr pc) \ { \ return fullname ## _swap(env, dcbase, pc, false); \ } =20 -GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) -GEN_TRANSLATOR_LD(translator_ldsw, int16_t, cpu_ldsw_code, bswap16) -GEN_TRANSLATOR_LD(translator_lduw, uint16_t, cpu_lduw_code, bswap16) -GEN_TRANSLATOR_LD(translator_ldl, uint32_t, cpu_ldl_code, bswap32) -GEN_TRANSLATOR_LD(translator_ldq, uint64_t, cpu_ldq_code, bswap64) +#define FOR_EACH_TRANSLATOR_LD(F) \ + F(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) \ + F(translator_ldsw, int16_t, cpu_ldsw_code, bswap16) \ + F(translator_lduw, uint16_t, cpu_lduw_code, bswap16) \ + F(translator_ldl, uint32_t, cpu_ldl_code, bswap32) \ + F(translator_ldq, uint64_t, cpu_ldq_code, bswap64) + +FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD) + #undef GEN_TRANSLATOR_LD =20 #endif /* EXEC__TRANSLATOR_H */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bbfcfb698c..fb9ebfad9e 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1297,31 +1297,8 @@ static inline void tb_page_add(PageDesc *p, Translat= ionBlock *tb, invalidate_page_bitmap(p); =20 #if defined(CONFIG_USER_ONLY) - if (p->flags & PAGE_WRITE) { - target_ulong addr; - PageDesc *p2; - int prot; - - /* force the host page as non writable (writes will have a - page fault + mprotect overhead) */ - page_addr &=3D qemu_host_page_mask; - prot =3D 0; - for (addr =3D page_addr; addr < page_addr + qemu_host_page_size; - addr +=3D TARGET_PAGE_SIZE) { - - p2 =3D page_find(addr >> TARGET_PAGE_BITS); - if (!p2) { - continue; - } - prot |=3D p2->flags; - p2->flags &=3D ~PAGE_WRITE; - } - mprotect(g2h_untagged(page_addr), qemu_host_page_size, - (prot & PAGE_BITS) & ~PAGE_WRITE); - if (DEBUG_TB_INVALIDATE_GATE) { - printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_= addr); - } - } + /* translator_loop() must have made all TB pages non-writable */ + assert(!(p->flags & PAGE_WRITE)); #else /* if some code is already present, then the pages are already protected. So we handle the case where only the first TB is @@ -2394,6 +2371,38 @@ int page_check_range(target_ulong start, target_ulon= g len, int flags) return 0; } =20 +void page_protect(tb_page_addr_t page_addr) +{ + target_ulong addr; + PageDesc *p; + int prot; + + p =3D page_find(page_addr >> TARGET_PAGE_BITS); + if (p && (p->flags & PAGE_WRITE)) { + /* + * Force the host page as non writable (writes will have a page fa= ult + + * mprotect overhead). + */ + page_addr &=3D qemu_host_page_mask; + prot =3D 0; + for (addr =3D page_addr; addr < page_addr + qemu_host_page_size; + addr +=3D TARGET_PAGE_SIZE) { + + p =3D page_find(addr >> TARGET_PAGE_BITS); + if (!p) { + continue; + } + prot |=3D p->flags; + p->flags &=3D ~PAGE_WRITE; + } + mprotect(g2h_untagged(page_addr), qemu_host_page_size, + (prot & PAGE_BITS) & ~PAGE_WRITE); + if (DEBUG_TB_INVALIDATE_GATE) { + printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_= addr); + } + } +} + /* called from signal handler: invalidate the code and unprotect the * page. Return 0 if the fault was not handled, 1 if it was handled, * and 2 if it was handled but the caller must cause the TB to be diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index c53a7f8e44..390bd9db0a 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -42,6 +42,15 @@ bool translator_use_goto_tb(DisasContextBase *db, target= _ulong dest) return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) =3D=3D 0; } =20 +static inline void translator_page_protect(DisasContextBase *dcbase, + target_ulong pc) +{ +#ifdef CONFIG_USER_ONLY + dcbase->page_protect_end =3D pc | ~TARGET_PAGE_MASK; + page_protect(pc); +#endif +} + void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb, int max_insns) { @@ -56,6 +65,7 @@ void translator_loop(const TranslatorOps *ops, DisasConte= xtBase *db, db->num_insns =3D 0; db->max_insns =3D max_insns; db->singlestep_enabled =3D cflags & CF_SINGLE_STEP; + translator_page_protect(db, db->pc_next); =20 ops->init_disas_context(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ @@ -137,3 +147,32 @@ void translator_loop(const TranslatorOps *ops, DisasCo= ntextBase *db, } #endif } + +static inline void translator_maybe_page_protect(DisasContextBase *dcbase, + target_ulong pc, size_t l= en) +{ +#ifdef CONFIG_USER_ONLY + target_ulong end =3D pc + len - 1; + + if (end > dcbase->page_protect_end) { + translator_page_protect(dcbase, end); + } +#endif +} + +#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \ + type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \ + abi_ptr pc, bool do_swap) \ + { \ + translator_maybe_page_protect(dcbase, pc, sizeof(type)); \ + type ret =3D load_fn(env, pc); \ + if (do_swap) { \ + ret =3D swap_fn(ret); \ + } \ + plugin_insn_append(&ret, sizeof(ret)); \ + return ret; \ + } + +FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD) + +#undef GEN_TRANSLATOR_LD --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631578879694100001 Content-Type: text/plain; charset="utf-8" We need to be able to represent VEX.W on a 32-bit host, where REX.W will always be zero. Fixes the encoding for VPSLLVQ and VPSRLVQ. Fixes: a2ce146a068 ("tcg/i386: Support vector variable shift opcodes") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 98d924b91a..997510109d 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -241,8 +241,9 @@ static bool tcg_target_const_match(int64_t val, TCGType= type, int ct) #define P_EXT 0x100 /* 0x0f opcode prefix */ #define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ #define P_DATA16 0x400 /* 0x66 opcode prefix */ +#define P_VEXW 0x1000 /* Set VEX.W =3D 1 */ #if TCG_TARGET_REG_BITS =3D=3D 64 -# define P_REXW 0x1000 /* Set REX.W =3D 1 */ +# define P_REXW P_VEXW /* Set REX.W =3D 1; match VEXW */ # define P_REXB_R 0x2000 /* REG field as byte register */ # define P_REXB_RM 0x4000 /* R/M field as byte register */ # define P_GS 0x8000 /* gs segment override */ @@ -410,13 +411,13 @@ static bool tcg_target_const_match(int64_t val, TCGTy= pe type, int ct) #define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) -#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW) +#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW) #define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) #define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) -#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_REXW) +#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW) #define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) #define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) -#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_REXW) +#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW) #define OPC_VZEROUPPER (0x77 | P_EXT) #define OPC_XCHG_ax_r32 (0x90) =20 @@ -576,7 +577,7 @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int= r, int v, =20 /* Use the two byte form if possible, which cannot encode VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */ - if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) =3D=3D P_EXT + if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_VEXW)) =3D=3D P_EXT && ((rm | index) & 8) =3D=3D 0) { /* Two byte VEX prefix. */ tcg_out8(s, 0xc5); @@ -601,7 +602,7 @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int= r, int v, tmp |=3D (rm & 8 ? 0 : 0x20); /* VEX.B */ tcg_out8(s, tmp); =20 - tmp =3D (opc & P_REXW ? 0x80 : 0); /* VEX.W */ + tmp =3D (opc & P_VEXW ? 0x80 : 0); /* VEX.W */ } =20 tmp |=3D (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631578879; cv=none; d=zohomail.com; s=zohoarc; b=G79rbOlij5O9hi8JtBcWMkQisdfYtVIqC7Mi4BgBh5eEAv9iwfQmsNNAMb97NnlalHJcVBmARQ91YiiWdmy4Dcv79xtOuVy/NanyMCl/oOFgdgReHmvgGAD3GPW+3QRKvPXlFACNBI7VTvwNwvtKN0BPAai7E9jKiKQiUC+8oTw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631578879; 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Mon, 13 Sep 2021 17:15:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/44] accel/tcg: remove redundant TCG_KICK_PERIOD define Date: Mon, 13 Sep 2021 17:14:16 -0700 Message-Id: <20210914001456.793490-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631578881727100003 From: Luc Michel The TCG_KICK_PERIOD macro is already defined in tcg-accel-ops-rr.h. Remove it from tcg-accel-ops-rr.c. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210811141229.12470-1-lmichel@kalray.eu> Signed-off-by: Richard Henderson --- accel/tcg/tcg-accel-ops-rr.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index c02c061ecb..a5fd26190e 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -60,8 +60,6 @@ void rr_kick_vcpu_thread(CPUState *unused) static QEMUTimer *rr_kick_vcpu_timer; static CPUState *rr_current_cpu; =20 -#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10) - static inline int64_t rr_next_kick_time(void) { return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD; --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 13 Sep 2021 17:15:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/44] tcg: Remove tcg_global_reg_new defines Date: Mon, 13 Sep 2021 17:14:17 -0700 Message-Id: <20210914001456.793490-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579673232100002 From: Bin Meng Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"), these tcg_global_reg_new_ macros are not used anywhere. Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210816143507.11200-1-bmeng.cn@gmail.com> Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 2 -- target/hppa/translate.c | 3 --- 2 files changed, 5 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 2a654f350c..0545a6224c 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -843,7 +843,6 @@ static inline void tcg_gen_plugin_cb_end(void) =20 #if TARGET_LONG_BITS =3D=3D 32 #define tcg_temp_new() tcg_temp_new_i32() -#define tcg_global_reg_new tcg_global_reg_new_i32 #define tcg_global_mem_new tcg_global_mem_new_i32 #define tcg_temp_local_new() tcg_temp_local_new_i32() #define tcg_temp_free tcg_temp_free_i32 @@ -851,7 +850,6 @@ static inline void tcg_gen_plugin_cb_end(void) #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 #else #define tcg_temp_new() tcg_temp_new_i64() -#define tcg_global_reg_new tcg_global_reg_new_i64 #define tcg_global_mem_new tcg_global_mem_new_i64 #define tcg_temp_local_new() tcg_temp_local_new_i64() #define tcg_temp_free tcg_temp_free_i64 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3ce22cdd09..c3698cf067 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -34,7 +34,6 @@ =20 #undef TCGv #undef tcg_temp_new -#undef tcg_global_reg_new #undef tcg_global_mem_new #undef tcg_temp_local_new #undef tcg_temp_free @@ -59,7 +58,6 @@ #define TCGv_reg TCGv_i64 =20 #define tcg_temp_new tcg_temp_new_i64 -#define tcg_global_reg_new tcg_global_reg_new_i64 #define tcg_global_mem_new tcg_global_mem_new_i64 #define tcg_temp_local_new tcg_temp_local_new_i64 #define tcg_temp_free tcg_temp_free_i64 @@ -155,7 +153,6 @@ #else #define TCGv_reg TCGv_i32 #define tcg_temp_new tcg_temp_new_i32 -#define tcg_global_reg_new tcg_global_reg_new_i32 #define tcg_global_mem_new tcg_global_mem_new_i32 #define tcg_temp_local_new tcg_temp_local_new_i32 #define tcg_temp_free tcg_temp_free_i32 --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579028675100001 Content-Type: text/plain; charset="utf-8" If __APPLE__, ensure that _CALL_DARWIN is set, then remove our local TCG_TARGET_CALL_DARWIN. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e0f4665213..2202ce017e 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -25,8 +25,8 @@ #include "elf.h" #include "../tcg-pool.c.inc" =20 -#if defined _CALL_DARWIN || defined __APPLE__ -#define TCG_TARGET_CALL_DARWIN +#if !defined _CALL_DARWIN && defined __APPLE__ +#define _CALL_DARWIN 1 #endif #ifdef _CALL_SYSV # define TCG_TARGET_CALL_ALIGN_ARGS 1 @@ -169,7 +169,7 @@ static const int tcg_target_call_oarg_regs[] =3D { }; =20 static const int tcg_target_callee_save_regs[] =3D { -#ifdef TCG_TARGET_CALL_DARWIN +#ifdef _CALL_DARWIN TCG_REG_R11, #endif TCG_REG_R14, @@ -2372,7 +2372,7 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int co= unt) # define LINK_AREA_SIZE (6 * SZR) # define LR_OFFSET (1 * SZR) # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR) -#elif defined(TCG_TARGET_CALL_DARWIN) +#elif defined(_CALL_DARWIN) # define LINK_AREA_SIZE (6 * SZR) # define LR_OFFSET (2 * SZR) #elif TCG_TARGET_REG_BITS =3D=3D 64 --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Brad Smith Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579223195100001 Content-Type: text/plain; charset="utf-8" Clang only sets _CALL_ELF for ppc64, and nothing at all to specify the ABI for ppc32. Make a good guess based on other symbols. Reported-by: Brad Smith Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 2202ce017e..5e1fac914a 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -25,9 +25,24 @@ #include "elf.h" #include "../tcg-pool.c.inc" =20 -#if !defined _CALL_DARWIN && defined __APPLE__ -#define _CALL_DARWIN 1 -#endif +/* + * Standardize on the _CALL_FOO symbols used by GCC: + * Apple XCode does not define _CALL_DARWIN. + * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV (32-bit). + */ +#if !defined(_CALL_SYSV) && \ + !defined(_CALL_DARWIN) && \ + !defined(_CALL_AIX) && \ + !defined(_CALL_ELF) +# if defined(__APPLE__) +# define _CALL_DARWIN +# elif defined(__ELF__) && TCG_TARGET_REG_BITS =3D=3D 32 +# define _CALL_SYSV +# else +# error "Unknown ABI" +# endif +#endif=20 + #ifdef _CALL_SYSV # define TCG_TARGET_CALL_ALIGN_ARGS 1 #endif --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Jose R. Ziviani" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631579452756100001 From: "Jose R. Ziviani" Commit 5e8892db93 fixed several function signatures but tcg_out_vec_op for arm is missing. It causes a build error on armv6 and armv7: tcg-target.c.inc:2718:42: error: argument 5 of type 'const TCGArg *' {aka 'const unsigned int *'} declared as a pointer [-Werror=3Darray-paramet= er=3D] const TCGArg *args, const int *const_args) ~~~~~~~~~~~~~~^~~~ ../tcg/tcg.c:120:41: note: previously declared as an array 'const TCGArg[16= ]' {aka 'const unsigned int[16]'} const TCGArg args[TCG_MAX_OP_ARGS], ~~~~~~~~~~~~~~^~~~ Signed-off-by: Jose R. Ziviani Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210908185338.7927-1-jziviani@suse.de> Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 007ceee68e..e5b4f86841 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2715,7 +2715,8 @@ static const ARMInsn vec_cmp0_insn[16] =3D { =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGType type =3D vecl + TCG_TYPE_V64; unsigned q =3D vecl; --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579043760100001 From: Philippe Mathieu-Daud=C3=A9 Commit f1c671f96cb ("target/avr: Introduce basic CPU class object") added to target/avr/cpu.h: #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" #endif Remove the CONFIG_USER_ONLY definition introduced by mistake in commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"). Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-By: Warner Losh Message-Id: <20210911165434.531552-2-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/avr/cpu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index ea14175ca5..5d70e34dd5 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -197,10 +197,7 @@ static const struct TCGCPUOps avr_tcg_ops =3D { .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, .tlb_fill =3D avr_cpu_tlb_fill, - -#ifndef CONFIG_USER_ONLY .do_interrupt =3D avr_cpu_do_interrupt, -#endif /* !CONFIG_USER_ONLY */ }; =20 static void avr_cpu_class_init(ObjectClass *oc, void *data) --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 13 Sep 2021 17:15:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/44] target/i386: Restrict sysemu-only fpu_helper helpers Date: Mon, 13 Sep 2021 17:14:22 -0700 Message-Id: <20210914001456.793490-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579892332100001 From: Philippe Mathieu-Daud=C3=A9 Restrict some sysemu-only fpu_helper helpers (see commit 83a3d9c7402: "i386: separate fpu_helper sysemu-only parts"). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-3-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/i386/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 71ae3141c3..1a36c53c18 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1837,11 +1837,14 @@ void x86_cpu_list(void); int cpu_x86_support_mca_broadcast(CPUX86State *env); =20 int cpu_get_pic_interrupt(CPUX86State *s); + +#ifndef CONFIG_USER_ONLY /* MSDOS compatibility mode FPU exception support */ void x86_register_ferr_irq(qemu_irq irq); void fpu_check_raise_ferr_irq(CPUX86State *s); void cpu_set_ignne(void); void cpu_clear_ignne(void); +#endif =20 /* mpx_helper.c */ void cpu_sync_bndcs_hflags(CPUX86State *env); --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 13 Sep 2021 17:15:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 11/44] target/i386: Simplify TARGET_X86_64 #ifdef'ry Date: Mon, 13 Sep 2021 17:14:23 -0700 Message-Id: <20210914001456.793490-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631580116260100001 From: Philippe Mathieu-Daud=C3=A9 Merge two TARGET_X86_64 consecutive blocks. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-4-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/i386/tcg/seg_helper.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index cef68b610a..56263e358d 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -929,9 +929,7 @@ static void do_interrupt64(CPUX86State *env, int intno,= int is_int, e2); env->eip =3D offset; } -#endif =20 -#ifdef TARGET_X86_64 void helper_sysret(CPUX86State *env, int dflag) { int cpl, selector; @@ -984,7 +982,7 @@ void helper_sysret(CPUX86State *env, int dflag) DESC_W_MASK | DESC_A_MASK); } } -#endif +#endif /* TARGET_X86_64 */ =20 /* real mode interrupt */ static void do_interrupt_real(CPUX86State *env, int intno, int is_int, --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579047903100001 From: Philippe Mathieu-Daud=C3=A9 The do_transaction_failed() is restricted to system emulation since commit cbc183d2d9f ("cpu: move cc->transaction_failed to tcg_ops"). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-5-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 2345cb59c7..1e0cb1535c 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -568,10 +568,12 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, bool probe, uintptr_t retaddr); void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); +#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, unsigned size, MMUAccessType access_= type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t reta= ddr); +#endif /* !CONFIG_USER_ONLY */ void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 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d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fdyym3tRuWcxUVb7GR3eybl5FQ5L8A5RDTBUJNCEnuc=; b=xMGqv3oNdfcoWa40xBM2kxd15aHKpXIbQFY+/FzpdLEy6VRILf2TFMAcwDr3/6SkBw FDkWzHD3vFaoHIaFdrYlWnkcPsOgzrSIC0SVlMqDJb7HfkU5KBI6ZEEZD9Om/o8iGuAq IM3VEutME1NkdHuku/8QGIbRrWQY7HLYWV6pkUxkAVBh4JaDshVIIam53v7rzAzE4fkL e/mM0Wrr3csMqiYkBttlOuiuS/rj4V0V8W+3NuGEAxdvxoSCYgNHpkVh6SbuVGrAyTq9 mNxmOawmxU1O04cnlAMYyCLoHxNDy105+3cZ3WFgl1KUdMUwZESEvIIo3VIZ/OVm+BkX u1Bw== X-Gm-Message-State: AOAM530d8hli2wPLh4ZDbzq6/gtq7hJb9f5sUhsWYmv4tlWIam9nh/0M 4L051zpohFtbO3OVnmlOcRBdqx9tEFW1mw== X-Google-Smtp-Source: ABdhPJxkArHGlf2WP5jio6zHkSVZL1PVchfjjesT71mjINzvBe3aU4CgE6Z0y70D7karT4GCyKc87Q== X-Received: by 2002:a17:902:aa88:b0:13a:95d:d059 with SMTP id d8-20020a170902aa8800b0013a095dd059mr12769638plr.65.1631578507762; Mon, 13 Sep 2021 17:15:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 13/44] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt Date: Mon, 13 Sep 2021 17:14:25 -0700 Message-Id: <20210914001456.793490-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631580557593100001 From: Philippe Mathieu-Daud=C3=A9 do_interrupt() is sysemu specific. However due to some X86 specific hack, it is also used in user-mode emulation, which is why it couldn't be restricted to CONFIG_SOFTMMU (see the comment around added in commit 78271684719: "cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"). Keep the hack but rename the handler as fake_user_interrupt() and restrict do_interrupt() to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-6-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 22 ++++++++++++++-------- accel/tcg/cpu-exec.c | 4 ++-- target/i386/tcg/tcg-cpu.c | 6 ++++-- 3 files changed, 20 insertions(+), 12 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index eab27d0c03..6c7ab9600b 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -37,14 +37,6 @@ struct TCGCPUOps { void (*cpu_exec_exit)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); - /** - * @do_interrupt: Callback for interrupt handling. - * - * note that this is in general SOFTMMU only, but it actually isn't - * because of an x86 hack (accel/tcg/cpu-exec.c), so we cannot put it - * in the SOFTMMU section in general. - */ - void (*do_interrupt)(CPUState *cpu); /** * @tlb_fill: Handle a softmmu tlb miss or user-only address fault * @@ -61,6 +53,20 @@ struct TCGCPUOps { void (*debug_excp_handler)(CPUState *cpu); =20 #ifdef NEED_CPU_H +#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386) + /** + * @fake_user_interrupt: Callback for 'fake exception' handling. + * + * Simulate 'fake exception' which will be handled outside the + * cpu execution loop (hack for x86 user mode). + */ + void (*fake_user_interrupt)(CPUState *cpu); +#else + /** + * @do_interrupt: Callback for interrupt handling. + */ + void (*do_interrupt)(CPUState *cpu); +#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ #ifdef CONFIG_SOFTMMU /** * @do_transaction_failed: Callback for handling failed memory transac= tions diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index e5c0ccd1a2..2838177e7f 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -651,8 +651,8 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) loop */ #if defined(TARGET_I386) CPUClass *cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops->do_interrupt(cpu); -#endif + cc->tcg_ops->fake_user_interrupt(cpu); +#endif /* TARGET_I386 */ *ret =3D cpu->exception_index; cpu->exception_index =3D -1; return true; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 93a79a5741..04c35486a2 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -73,9 +73,11 @@ static const struct TCGCPUOps x86_tcg_ops =3D { .cpu_exec_enter =3D x86_cpu_exec_enter, .cpu_exec_exit =3D x86_cpu_exec_exit, .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, - .do_interrupt =3D x86_cpu_do_interrupt, .tlb_fill =3D x86_cpu_tlb_fill, -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .fake_user_interrupt =3D x86_cpu_do_interrupt, +#else + .do_interrupt =3D x86_cpu_do_interrupt, .debug_excp_handler =3D breakpoint_handler, .debug_check_breakpoint =3D x86_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631578692847100005 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-7-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 2 +- target/alpha/cpu.c | 2 +- target/alpha/helper.c | 5 ++--- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 82df108967..4e993bd15b 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -274,10 +274,10 @@ struct AlphaCPU { =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_alpha_cpu; -#endif =20 void alpha_cpu_do_interrupt(CPUState *cpu); bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif /* !CONFIG_USER_ONLY */ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 4871ad0c0a..93e16a2ffb 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -218,10 +218,10 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D= { =20 static const struct TCGCPUOps alpha_tcg_ops =3D { .initialize =3D alpha_translate_init, - .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, .tlb_fill =3D alpha_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, .do_interrupt =3D alpha_cpu_do_interrupt, .do_transaction_failed =3D alpha_cpu_do_transaction_failed, .do_unaligned_access =3D alpha_cpu_do_unaligned_access, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 4f56fe4d23..81550d9e2f 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -293,7 +293,6 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } -#endif /* USER_ONLY */ =20 void alpha_cpu_do_interrupt(CPUState *cs) { @@ -348,7 +347,6 @@ void alpha_cpu_do_interrupt(CPUState *cs) =20 cs->exception_index =3D -1; =20 -#if !defined(CONFIG_USER_ONLY) switch (i) { case EXCP_RESET: i =3D 0x0000; @@ -404,7 +402,6 @@ void alpha_cpu_do_interrupt(CPUState *cs) =20 /* Switch to PALmode. */ env->flags |=3D ENV_FLAG_PAL_MODE; -#endif /* !USER_ONLY */ } =20 bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -451,6 +448,8 @@ bool alpha_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) return false; } =20 +#endif /* !CONFIG_USER_ONLY */ + void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags) { static const char linux_reg_names[31][4] =3D { --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631580800282100001 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-8-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 +-- target/arm/cpu.c | 7 +++++-- target/arm/cpu_tcg.c | 6 +++--- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6a987f65e4..cfd755cff9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1040,11 +1040,10 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clust= ersz); =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; -#endif =20 void arm_cpu_do_interrupt(CPUState *cpu); void arm_v7m_cpu_do_interrupt(CPUState *cpu); -bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif /* !CONFIG_USER_ONLY */ =20 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d631c4683c..ba0741b20e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -440,6 +440,8 @@ static void arm_cpu_reset(DeviceState *dev) arm_rebuild_hflags(env); } =20 +#ifndef CONFIG_USER_ONLY + static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, unsigned int target_el, unsigned int cur_el, bool secure, @@ -556,7 +558,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, return unmasked || pstate_unmasked; } =20 -bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); CPUARMState *env =3D cs->env_ptr; @@ -608,6 +610,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) cc->tcg_ops->do_interrupt(cs); return true; } +#endif /* !CONFIG_USER_ONLY */ =20 void arm_cpu_update_virq(ARMCPU *cpu) { @@ -2010,11 +2013,11 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D= { static const struct TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, =20 #if !defined(CONFIG_USER_ONLY) + .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .do_interrupt =3D arm_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, .do_unaligned_access =3D arm_cpu_do_unaligned_access, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 33cc75af57..0d5adccf1a 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -22,7 +22,7 @@ /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 -#ifdef CONFIG_TCG +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); @@ -46,7 +46,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) } return ret; } -#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 static void arm926_initfn(Object *obj) { @@ -898,11 +898,11 @@ static void pxa270c5_initfn(Object *obj) static const struct TCGCPUOps arm_v7m_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, =20 #if !defined(CONFIG_USER_ONLY) + .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, .do_interrupt =3D arm_v7m_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, .do_unaligned_access =3D arm_cpu_do_unaligned_access, --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631580274146100001 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-9-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/cris/cpu.h | 2 +- target/cris/cpu.c | 4 ++-- target/cris/helper.c | 17 ++--------------- 3 files changed, 5 insertions(+), 18 deletions(-) diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d3b6492909..be021899ae 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -185,11 +185,11 @@ struct CRISCPU { =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_cris_cpu; -#endif =20 void cris_cpu_do_interrupt(CPUState *cpu); void crisv10_cpu_do_interrupt(CPUState *cpu); bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif =20 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); =20 diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 70932b1f8c..c2e7483f5b 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -205,20 +205,20 @@ static const struct SysemuCPUOps cris_sysemu_ops =3D { =20 static const struct TCGCPUOps crisv10_tcg_ops =3D { .initialize =3D cris_initialize_crisv10_tcg, - .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .tlb_fill =3D cris_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .do_interrupt =3D crisv10_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; =20 static const struct TCGCPUOps crisv32_tcg_ops =3D { .initialize =3D cris_initialize_tcg, - .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .tlb_fill =3D cris_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .do_interrupt =3D cris_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/cris/helper.c b/target/cris/helper.c index 911867f3b4..36926faf32 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -41,20 +41,6 @@ =20 #if defined(CONFIG_USER_ONLY) =20 -void cris_cpu_do_interrupt(CPUState *cs) -{ - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; - - cs->exception_index =3D -1; - env->pregs[PR_ERP] =3D env->pc; -} - -void crisv10_cpu_do_interrupt(CPUState *cs) -{ - cris_cpu_do_interrupt(cs); -} - bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -287,7 +273,6 @@ hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy)); return phy; } -#endif =20 bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -319,3 +304,5 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 return ret; } + +#endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631579225; cv=none; d=zohomail.com; s=zohoarc; b=Wn2GnRzNCh2vEi4mB3ThAIhn8mzoseq0pTuqJaPI4cCnFhip1XP/Ua77G6jXcBPF7yqpc8lErI7A9lCpLC+T6d4Dgvo0ks4gYwHd+oiUoA7xA3Yb2pIcOXW2fQ0LSbTRIWVCde6r1chAXOQ7GXRvHvhs2uJbUqGZx2c6eDCv5zo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631579225; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579227511100001 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-10-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 4 ++-- target/hppa/cpu.c | 2 +- target/hppa/int_helper.c | 7 ++----- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 748270bfa3..7854675b90 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -325,13 +325,13 @@ int cpu_hppa_signal_handler(int host_signum, void *pi= nfo, void *puc); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void hppa_cpu_do_interrupt(CPUState *cpu); -bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); #ifndef CONFIG_USER_ONLY +void hppa_cpu_do_interrupt(CPUState *cpu); +bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, int type, hwaddr *pphys, int *pprot); extern const MemoryRegionOps hppa_io_eir_ops; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 2eace4ee12..e8edd189bf 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -144,10 +144,10 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { static const struct TCGCPUOps hppa_tcg_ops =3D { .initialize =3D hppa_translate_init, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, .tlb_fill =3D hppa_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, .do_interrupt =3D hppa_cpu_do_interrupt, .do_unaligned_access =3D hppa_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 349495d361..13073ae2bd 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -88,7 +88,6 @@ void HELPER(write_eiem)(CPUHPPAState *env, target_ureg va= l) eval_interrupt(env_archcpu(env)); qemu_mutex_unlock_iothread(); } -#endif /* !CONFIG_USER_ONLY */ =20 void hppa_cpu_do_interrupt(CPUState *cs) { @@ -100,7 +99,6 @@ void hppa_cpu_do_interrupt(CPUState *cs) uint64_t iasq_f =3D env->iasq_f; uint64_t iasq_b =3D env->iasq_b; =20 -#ifndef CONFIG_USER_ONLY target_ureg old_psw; =20 /* As documented in pa2.0 -- interruption handling. */ @@ -187,7 +185,6 @@ void hppa_cpu_do_interrupt(CPUState *cs) env->iaoq_b =3D env->iaoq_f + 4; env->iasq_f =3D 0; env->iasq_b =3D 0; -#endif =20 if (qemu_loglevel_mask(CPU_LOG_INT)) { static const char * const names[] =3D { @@ -248,7 +245,6 @@ void hppa_cpu_do_interrupt(CPUState *cs) =20 bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { -#ifndef CONFIG_USER_ONLY HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; =20 @@ -258,6 +254,7 @@ bool hppa_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) hppa_cpu_do_interrupt(cs); return true; } -#endif return false; } + +#endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579452768100002 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-11-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 2 ++ target/i386/tcg/seg_helper.c | 10 ++-------- target/i386/tcg/tcg-cpu.c | 2 +- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 2510cc244e..60ca09e95e 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -38,7 +38,9 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_S= PACE_BITS); * @cpu: vCPU the interrupt is to be handled by. */ void x86_cpu_do_interrupt(CPUState *cpu); +#ifndef CONFIG_USER_ONLY bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif =20 /* helper.c */ bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 56263e358d..4e6f26a7b7 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -1110,6 +1110,7 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int i= ntno, int is_hw) do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw); } =20 +#ifndef CONFIG_USER_ONLY bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu =3D X86_CPU(cs); @@ -1125,23 +1126,17 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int inter= rupt_request) * This is required to make icount-driven execution deterministic. */ switch (interrupt_request) { -#if !defined(CONFIG_USER_ONLY) case CPU_INTERRUPT_POLL: cs->interrupt_request &=3D ~CPU_INTERRUPT_POLL; apic_poll_irq(cpu->apic_state); break; -#endif case CPU_INTERRUPT_SIPI: do_cpu_sipi(cpu); break; case CPU_INTERRUPT_SMI: cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); cs->interrupt_request &=3D ~CPU_INTERRUPT_SMI; -#ifdef CONFIG_USER_ONLY - cpu_abort(CPU(cpu), "SMI interrupt: cannot enter SMM in user-mode"= ); -#else do_smm_enter(cpu); -#endif /* CONFIG_USER_ONLY */ break; case CPU_INTERRUPT_NMI: cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); @@ -1162,7 +1157,6 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) "Servicing hardware INT=3D0x%02x\n", intno); do_interrupt_x86_hardirq(env, intno, 1); break; -#if !defined(CONFIG_USER_ONLY) case CPU_INTERRUPT_VIRQ: cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0); intno =3D x86_ldl_phys(cs, env->vm_vmcb @@ -1173,12 +1167,12 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int inter= rupt_request) cs->interrupt_request &=3D ~CPU_INTERRUPT_VIRQ; env->int_ctl &=3D ~V_IRQ_MASK; break; -#endif } =20 /* Ensure that no TB jump will be modified as the program flow was cha= nged. */ return true; } +#endif /* CONFIG_USER_ONLY */ =20 void helper_lldt(CPUX86State *env, int selector) { diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 04c35486a2..3ecfae34cb 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -72,12 +72,12 @@ static const struct TCGCPUOps x86_tcg_ops =3D { .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .cpu_exec_enter =3D x86_cpu_exec_enter, .cpu_exec_exit =3D x86_cpu_exec_exit, - .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, .tlb_fill =3D x86_cpu_tlb_fill, #ifdef CONFIG_USER_ONLY .fake_user_interrupt =3D x86_cpu_do_interrupt, #else .do_interrupt =3D x86_cpu_do_interrupt, + .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, .debug_excp_handler =3D breakpoint_handler, .debug_check_breakpoint =3D x86_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631578883875100001 From: Philippe Mathieu-Daud=C3=A9 Following the logic of commit 30493a030ff ("i386: split seg_helper into user-only and sysemu parts"), move x86_cpu_exec_interrupt() under sysemu/seg_helper.c. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-By: Warner Losh Message-Id: <20210911165434.531552-12-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/i386/tcg/seg_helper.c | 64 ----------------------------- target/i386/tcg/sysemu/seg_helper.c | 62 ++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 64 deletions(-) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 4e6f26a7b7..baa905a0cd 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -1110,70 +1110,6 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int = intno, int is_hw) do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw); } =20 -#ifndef CONFIG_USER_ONLY -bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - int intno; - - interrupt_request =3D x86_cpu_pending_interrupt(cs, interrupt_request); - if (!interrupt_request) { - return false; - } - - /* Don't process multiple interrupt requests in a single call. - * This is required to make icount-driven execution deterministic. - */ - switch (interrupt_request) { - case CPU_INTERRUPT_POLL: - cs->interrupt_request &=3D ~CPU_INTERRUPT_POLL; - apic_poll_irq(cpu->apic_state); - break; - case CPU_INTERRUPT_SIPI: - do_cpu_sipi(cpu); - break; - case CPU_INTERRUPT_SMI: - cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); - cs->interrupt_request &=3D ~CPU_INTERRUPT_SMI; - do_smm_enter(cpu); - break; - case CPU_INTERRUPT_NMI: - cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); - cs->interrupt_request &=3D ~CPU_INTERRUPT_NMI; - env->hflags2 |=3D HF2_NMI_MASK; - do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); - break; - case CPU_INTERRUPT_MCE: - cs->interrupt_request &=3D ~CPU_INTERRUPT_MCE; - do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); - break; - case CPU_INTERRUPT_HARD: - cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0); - cs->interrupt_request &=3D ~(CPU_INTERRUPT_HARD | - CPU_INTERRUPT_VIRQ); - intno =3D cpu_get_pic_interrupt(env); - qemu_log_mask(CPU_LOG_TB_IN_ASM, - "Servicing hardware INT=3D0x%02x\n", intno); - do_interrupt_x86_hardirq(env, intno, 1); - break; - case CPU_INTERRUPT_VIRQ: - cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0); - intno =3D x86_ldl_phys(cs, env->vm_vmcb - + offsetof(struct vmcb, control.int_vector)); - qemu_log_mask(CPU_LOG_TB_IN_ASM, - "Servicing virtual hardware INT=3D0x%02x\n", intno); - do_interrupt_x86_hardirq(env, intno, 1); - cs->interrupt_request &=3D ~CPU_INTERRUPT_VIRQ; - env->int_ctl &=3D ~V_IRQ_MASK; - break; - } - - /* Ensure that no TB jump will be modified as the program flow was cha= nged. */ - return true; -} -#endif /* CONFIG_USER_ONLY */ - void helper_lldt(CPUX86State *env, int selector) { SegmentCache *dt; diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/s= eg_helper.c index 82c0856c41..bf3444c26b 100644 --- a/target/i386/tcg/sysemu/seg_helper.c +++ b/target/i386/tcg/sysemu/seg_helper.c @@ -125,6 +125,68 @@ void x86_cpu_do_interrupt(CPUState *cs) } } =20 +bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + int intno; + + interrupt_request =3D x86_cpu_pending_interrupt(cs, interrupt_request); + if (!interrupt_request) { + return false; + } + + /* Don't process multiple interrupt requests in a single call. + * This is required to make icount-driven execution deterministic. + */ + switch (interrupt_request) { + case CPU_INTERRUPT_POLL: + cs->interrupt_request &=3D ~CPU_INTERRUPT_POLL; + apic_poll_irq(cpu->apic_state); + break; + case CPU_INTERRUPT_SIPI: + do_cpu_sipi(cpu); + break; + case CPU_INTERRUPT_SMI: + cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); + cs->interrupt_request &=3D ~CPU_INTERRUPT_SMI; + do_smm_enter(cpu); + break; + case CPU_INTERRUPT_NMI: + cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); + cs->interrupt_request &=3D ~CPU_INTERRUPT_NMI; + env->hflags2 |=3D HF2_NMI_MASK; + do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); + break; + case CPU_INTERRUPT_MCE: + cs->interrupt_request &=3D ~CPU_INTERRUPT_MCE; + do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); + break; + case CPU_INTERRUPT_HARD: + cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0); + cs->interrupt_request &=3D ~(CPU_INTERRUPT_HARD | + CPU_INTERRUPT_VIRQ); + intno =3D cpu_get_pic_interrupt(env); + qemu_log_mask(CPU_LOG_TB_IN_ASM, + "Servicing hardware INT=3D0x%02x\n", intno); + do_interrupt_x86_hardirq(env, intno, 1); + break; + case CPU_INTERRUPT_VIRQ: + cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0); + intno =3D x86_ldl_phys(cs, env->vm_vmcb + + offsetof(struct vmcb, control.int_vector)); + qemu_log_mask(CPU_LOG_TB_IN_ASM, + "Servicing virtual hardware INT=3D0x%02x\n", intno); + do_interrupt_x86_hardirq(env, intno, 1); + cs->interrupt_request &=3D ~CPU_INTERRUPT_VIRQ; + env->int_ctl &=3D ~V_IRQ_MASK; + break; + } + + /* Ensure that no TB jump will be modified as the program flow was cha= nged. */ + return true; +} + /* check if Port I/O is allowed in TSS */ void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size) { --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579675290100001 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-13-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 2 ++ target/m68k/cpu.c | 2 +- target/m68k/op_helper.c | 16 +++------------- 3 files changed, 6 insertions(+), 14 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 997d588911..550eb028b6 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -166,8 +166,10 @@ struct M68kCPU { }; =20 =20 +#ifndef CONFIG_USER_ONLY void m68k_cpu_do_interrupt(CPUState *cpu); bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif /* !CONFIG_USER_ONLY */ void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 72de6e9726..66d22d1189 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -515,10 +515,10 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { =20 static const struct TCGCPUOps m68k_tcg_ops =3D { .initialize =3D m68k_tcg_init, - .cpu_exec_interrupt =3D m68k_cpu_exec_interrupt, .tlb_fill =3D m68k_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D m68k_cpu_exec_interrupt, .do_interrupt =3D m68k_cpu_do_interrupt, .do_transaction_failed =3D m68k_cpu_transaction_failed, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index d006d1cb3e..5d624838ae 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -24,18 +24,7 @@ #include "semihosting/semihost.h" #include "tcg/tcg.h" =20 -#if defined(CONFIG_USER_ONLY) - -void m68k_cpu_do_interrupt(CPUState *cs) -{ - cs->exception_index =3D -1; -} - -static inline void do_interrupt_m68k_hardirq(CPUM68KState *env) -{ -} - -#else +#if !defined(CONFIG_USER_ONLY) =20 static void cf_rte(CPUM68KState *env) { @@ -516,7 +505,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, cpu_loop_exit(cs); } } -#endif =20 bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -538,6 +526,8 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) return false; } =20 +#endif /* !CONFIG_USER_ONLY */ + static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) { CPUState *cs =3D env_cpu(env); --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631578880; cv=none; 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Mon, 13 Sep 2021 17:15:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 21/44] target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu Date: Mon, 13 Sep 2021 17:14:33 -0700 Message-Id: <20210914001456.793490-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631578881795100004 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-14-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 ++ target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 13 ++----------- 3 files changed, 5 insertions(+), 12 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e4bba8a755..40401c33b7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -355,8 +355,10 @@ struct MicroBlazeCPU { }; =20 =20 +#ifndef CONFIG_USER_ONLY void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); +#endif /* !CONFIG_USER_ONLY */ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 72d8f2a0da..15db277925 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -365,10 +365,10 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { static const struct TCGCPUOps mb_tcg_ops =3D { .initialize =3D mb_tcg_init, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, .tlb_fill =3D mb_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, .do_interrupt =3D mb_cpu_do_interrupt, .do_transaction_failed =3D mb_cpu_transaction_failed, .do_unaligned_access =3D mb_cpu_do_unaligned_access, diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 20dbd67313..dd2aecd1d5 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -26,16 +26,6 @@ =20 #if defined(CONFIG_USER_ONLY) =20 -void mb_cpu_do_interrupt(CPUState *cs) -{ - MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); - CPUMBState *env =3D &cpu->env; - - cs->exception_index =3D -1; - env->res_addr =3D RES_ADDR_NONE; - env->regs[14] =3D env->pc; -} - bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -271,7 +261,6 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, v= addr addr, =20 return paddr; } -#endif =20 bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -289,6 +278,8 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_= request) return false; } =20 +#endif /* !CONFIG_USER_ONLY */ + void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Mon, 13 Sep 2021 17:15:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 22/44] target/mips: Restrict cpu_exec_interrupt() handler to sysemu Date: Mon, 13 Sep 2021 17:14:34 -0700 Message-Id: <20210914001456.793490-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579456858100001 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-15-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/mips/tcg/tcg-internal.h | 5 +++-- target/mips/cpu.c | 2 +- target/mips/tcg/exception.c | 18 ------------------ target/mips/tcg/sysemu/tlb_helper.c | 18 ++++++++++++++++++ target/mips/tcg/user/tlb_helper.c | 5 ----- 5 files changed, 22 insertions(+), 26 deletions(-) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 81b14eb219..c7a77ddccd 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -18,8 +18,6 @@ void mips_tcg_init(void); =20 void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); -void mips_cpu_do_interrupt(CPUState *cpu); -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -41,6 +39,9 @@ static inline void QEMU_NORETURN do_raise_exception(CPUMI= PSState *env, =20 #if !defined(CONFIG_USER_ONLY) =20 +void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); + void mmu_init(CPUMIPSState *env, const mips_def_t *def); =20 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d426918291..00e0c55d0e 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -539,10 +539,10 @@ static const struct SysemuCPUOps mips_sysemu_ops =3D { static const struct TCGCPUOps mips_tcg_ops =3D { .initialize =3D mips_tcg_init, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .tlb_fill =3D mips_cpu_tlb_fill, =20 #if !defined(CONFIG_USER_ONLY) + .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .do_interrupt =3D mips_cpu_do_interrupt, .do_transaction_failed =3D mips_cpu_do_transaction_failed, .do_unaligned_access =3D mips_cpu_do_unaligned_access, diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index 4fb8b00711..7b3026b105 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -86,24 +86,6 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const Tr= anslationBlock *tb) env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; } =20 -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - if (cpu_mips_hw_interrupts_enabled(env) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index =3D EXCP_EXT_INTERRUPT; - env->error_code =3D 0; - mips_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - static const char * const excp_names[EXCP_LAST + 1] =3D { [EXCP_RESET] =3D "reset", [EXCP_SRESET] =3D "soft reset", diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index a150a014ec..73254d1929 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -1339,6 +1339,24 @@ void mips_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D EXCP_NONE; } =20 +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index =3D EXCP_EXT_INTERRUPT; + env->error_code =3D 0; + mips_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { CPUState *cs =3D env_cpu(env); diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c index b835144b82..210c6d529e 100644 --- a/target/mips/tcg/user/tlb_helper.c +++ b/target/mips/tcg/user/tlb_helper.c @@ -57,8 +57,3 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, raise_mmu_exception(env, address, access_type); do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); } - -void mips_cpu_do_interrupt(CPUState *cs) -{ - cs->exception_index =3D EXCP_NONE; -} --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631581191081100001 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-16-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/nios2/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 5e37defef8..947bb09bc1 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -127,6 +127,7 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error= **errp) ncc->parent_realize(dev, errp); } =20 +#ifndef CONFIG_USER_ONLY static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { Nios2CPU *cpu =3D NIOS2_CPU(cs); @@ -140,7 +141,7 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) } return false; } - +#endif /* !CONFIG_USER_ONLY */ =20 static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { @@ -219,10 +220,10 @@ static const struct SysemuCPUOps nios2_sysemu_ops =3D= { =20 static const struct TCGCPUOps nios2_tcg_ops =3D { .initialize =3D nios2_tcg_init, - .cpu_exec_interrupt =3D nios2_cpu_exec_interrupt, .tlb_fill =3D nios2_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D nios2_cpu_exec_interrupt, .do_interrupt =3D nios2_cpu_do_interrupt, .do_unaligned_access =3D nios2_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631581109154100001 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-17-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 5 +++-- target/openrisc/cpu.c | 2 +- target/openrisc/interrupt.c | 2 -- target/openrisc/meson.build | 6 ++++-- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 82cbaeb4f8..be6df81a81 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -312,8 +312,6 @@ struct OpenRISCCPU { =20 =20 void cpu_openrisc_list(void); -void openrisc_cpu_do_interrupt(CPUState *cpu); -bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg= ); @@ -331,6 +329,9 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *inf= o); #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_openrisc_cpu; =20 +void openrisc_cpu_do_interrupt(CPUState *cpu); +bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); + /* hw/openrisc_pic.c */ void cpu_openrisc_pic_init(OpenRISCCPU *cpu); =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index bd34e429ec..27cb04152f 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -186,10 +186,10 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { =20 static const struct TCGCPUOps openrisc_tcg_ops =3D { .initialize =3D openrisc_translate_init, - .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .tlb_fill =3D openrisc_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .do_interrupt =3D openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 3eab771dcd..19223e3f25 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -28,7 +28,6 @@ =20 void openrisc_cpu_do_interrupt(CPUState *cs) { -#ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); CPUOpenRISCState *env =3D &cpu->env; int exception =3D cs->exception_index; @@ -96,7 +95,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) } else { cpu_abort(cs, "Unhandled exception 0x%x\n", exception); } -#endif =20 cs->exception_index =3D -1; } diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build index 9774a58306..e445dec4a0 100644 --- a/target/openrisc/meson.build +++ b/target/openrisc/meson.build @@ -9,7 +9,6 @@ openrisc_ss.add(files( 'exception_helper.c', 'fpu_helper.c', 'gdbstub.c', - 'interrupt.c', 'interrupt_helper.c', 'mmu.c', 'sys_helper.c', @@ -17,7 +16,10 @@ openrisc_ss.add(files( )) =20 openrisc_softmmu_ss =3D ss.source_set() -openrisc_softmmu_ss.add(files('machine.c')) +openrisc_softmmu_ss.add(files( + 'interrupt.c', + 'machine.c', +)) =20 target_arch +=3D {'openrisc': openrisc_ss} target_softmmu_arch +=3D {'openrisc': openrisc_softmmu_ss} --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631580974650100001 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Acked-by: David Gibson Message-Id: <20210911165434.531552-18-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 4 ++-- target/ppc/cpu_init.c | 2 +- target/ppc/excp_helper.c | 21 +++------------------ 3 files changed, 6 insertions(+), 21 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 500205229c..362e7c4c5c 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1254,8 +1254,6 @@ DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtual= HypervisorClass, PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR) #endif /* CONFIG_USER_ONLY */ =20 -void ppc_cpu_do_interrupt(CPUState *cpu); -bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -1271,6 +1269,8 @@ int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction = f, CPUState *cs, int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); #ifndef CONFIG_USER_ONLY +void ppc_cpu_do_interrupt(CPUState *cpu); +bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); void ppc_cpu_do_system_reset(CPUState *cs); void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector); extern const VMStateDescription vmstate_ppc_cpu; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index ad7abc6041..6aad01d1d3 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -9014,10 +9014,10 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D= { =20 static const struct TCGCPUOps ppc_tcg_ops =3D { .initialize =3D ppc_translate_init, - .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .tlb_fill =3D ppc_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .do_interrupt =3D ppc_cpu_do_interrupt, .cpu_exec_enter =3D ppc_cpu_exec_enter, .cpu_exec_exit =3D ppc_cpu_exec_exit, diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 7b6ac16eef..d7e32ee107 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -40,24 +40,8 @@ =20 /*************************************************************************= ****/ /* Exception processing */ -#if defined(CONFIG_USER_ONLY) -void ppc_cpu_do_interrupt(CPUState *cs) -{ - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; +#if !defined(CONFIG_USER_ONLY) =20 - cs->exception_index =3D POWERPC_EXCP_NONE; - env->error_code =3D 0; -} - -static void ppc_hw_interrupt(CPUPPCState *env) -{ - CPUState *cs =3D env_cpu(env); - - cs->exception_index =3D POWERPC_EXCP_NONE; - env->error_code =3D 0; -} -#else /* defined(CONFIG_USER_ONLY) */ static inline void dump_syscall(CPUPPCState *env) { qemu_log_mask(CPU_LOG_INT, "syscall r0=3D%016" PRIx64 @@ -1113,7 +1097,6 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, tar= get_ulong vector) =20 powerpc_set_excp_state(cpu, vector, msr); } -#endif /* !CONFIG_USER_ONLY */ =20 bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -1130,6 +1113,8 @@ bool ppc_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) return false; } =20 +#endif /* !CONFIG_USER_ONLY */ + #if defined(DEBUG_OP) static void cpu_dump_rfi(target_ulong RA, target_ulong msr) { --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631579896270100001 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-Id: <20210911165434.531552-19-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 5 ----- 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..e735e53e26 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -334,7 +334,6 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f,= CPUState *cs, int cpuid, void *opaque); int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); @@ -362,6 +361,7 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY +bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value= ); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1a2b03d579..13575c1408 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -644,10 +644,10 @@ static const struct SysemuCPUOps riscv_sysemu_ops =3D= { static const struct TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .tlb_fill =3D riscv_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, .do_unaligned_access =3D riscv_cpu_do_unaligned_access, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 968cb8046f..701858d670 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -75,11 +75,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *en= v) return RISCV_EXCP_NONE; /* indicates no pending interrupt */ } } -#endif =20 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { -#if !defined(CONFIG_USER_ONLY) if (interrupt_request & CPU_INTERRUPT_HARD) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; @@ -90,12 +88,9 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) return true; } } -#endif return false; } =20 -#if !defined(CONFIG_USER_ONLY) - /* Return true is floating point support is currently enabled */ bool riscv_cpu_fp_enabled(CPURISCVState *env) { --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631580120; cv=none; d=zohomail.com; s=zohoarc; b=mu2o+Zs17A1nX7EuVA5v6oCalEL9+xO8cbxkoHTrWCQqyNApYBdWervY8L0TuALi/Ye95oXw6mI0k/udCcg1LovHBqwUG4GBIjOeOOAJiCWEjuoxX0/hBFdiHOKkqYswhBI0bRoy8t1Yn0FaEJwg7T+7j8fONcD72MPv0e+zdAI= ARC-Message-Signature: i=1; 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Mon, 13 Sep 2021 17:15:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 27/44] target/sh4: Restrict cpu_exec_interrupt() handler to sysemu Date: Mon, 13 Sep 2021 17:14:39 -0700 Message-Id: <20210914001456.793490-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631580122228100001 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-20-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 4 ++-- target/sh4/cpu.c | 2 +- target/sh4/helper.c | 9 ++------- 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 01c4344082..017a770214 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -204,8 +204,6 @@ struct SuperHCPU { }; =20 =20 -void superh_cpu_do_interrupt(CPUState *cpu); -bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -223,6 +221,8 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, =20 void sh4_cpu_list(void); #if !defined(CONFIG_USER_ONLY) +void superh_cpu_do_interrupt(CPUState *cpu); +bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void cpu_sh4_invalidate_tlb(CPUSH4State *s); uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr); diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 8326922942..2047742d03 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -236,10 +236,10 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { static const struct TCGCPUOps superh_tcg_ops =3D { .initialize =3D sh4_translate_init, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, .tlb_fill =3D superh_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, .do_interrupt =3D superh_cpu_do_interrupt, .do_unaligned_access =3D superh_cpu_do_unaligned_access, .io_recompile_replay_branch =3D superh_io_recompile_replay_branch, diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 2d622081e8..53cb9c3b63 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -45,11 +45,6 @@ =20 #if defined(CONFIG_USER_ONLY) =20 -void superh_cpu_do_interrupt(CPUState *cs) -{ - cs->exception_index =3D -1; -} - int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) { /* For user mode, only U0 area is cacheable. */ @@ -784,8 +779,6 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong a= ddr) return 0; } =20 -#endif - bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { @@ -803,6 +796,8 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) return false; } =20 +#endif /* !CONFIG_USER_ONLY */ + bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631579672; 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Mon, 13 Sep 2021 17:15:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 28/44] target/sparc: Restrict cpu_exec_interrupt() handler to sysemu Date: Mon, 13 Sep 2021 17:14:40 -0700 Message-Id: <20210914001456.793490-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579673220100001 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-21-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/sparc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index da6b30ec74..5a8a4ce750 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -77,6 +77,7 @@ static void sparc_cpu_reset(DeviceState *dev) env->cache_control =3D 0; } =20 +#ifndef CONFIG_USER_ONLY static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { @@ -96,6 +97,7 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int in= terrupt_request) } return false; } +#endif /* !CONFIG_USER_ONLY */ =20 static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) { @@ -863,10 +865,10 @@ static const struct SysemuCPUOps sparc_sysemu_ops =3D= { static const struct TCGCPUOps sparc_tcg_ops =3D { .initialize =3D sparc_tcg_init, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, .tlb_fill =3D sparc_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, .do_interrupt =3D sparc_cpu_do_interrupt, .do_transaction_failed =3D sparc_cpu_do_transaction_failed, .do_unaligned_access =3D sparc_cpu_do_unaligned_access, --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631581480987100001 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-22-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/rx/cpu.h | 2 ++ target/rx/cpu.c | 2 +- target/rx/helper.c | 4 ++++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 0b4b998c7b..faa3606f52 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -124,8 +124,10 @@ typedef RXCPU ArchCPU; #define CPU_RESOLVING_TYPE TYPE_RX_CPU =20 const char *rx_crname(uint8_t cr); +#ifndef CONFIG_USER_ONLY void rx_cpu_do_interrupt(CPUState *cpu); bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif /* !CONFIG_USER_ONLY */ void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 96cc96e514..25a4aa2976 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -186,10 +186,10 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { static const struct TCGCPUOps rx_tcg_ops =3D { .initialize =3D rx_translate_init, .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, .tlb_fill =3D rx_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, .do_interrupt =3D rx_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/rx/helper.c b/target/rx/helper.c index db6b07e389..f34945e7e2 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -40,6 +40,8 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int= rte) env->psw_c =3D FIELD_EX32(psw, PSW, C); } =20 +#ifndef CONFIG_USER_ONLY + #define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) void rx_cpu_do_interrupt(CPUState *cs) { @@ -142,6 +144,8 @@ bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_= request) return false; } =20 +#endif /* !CONFIG_USER_ONLY */ + hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { return addr; --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631581297; cv=none; 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Mon, 13 Sep 2021 17:15:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 30/44] target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu Date: Mon, 13 Sep 2021 17:14:42 -0700 Message-Id: <20210914001456.793490-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631581299283100001 From: Philippe Mathieu-Daud=C3=A9 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-23-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 4 ++-- target/xtensa/cpu.c | 2 +- target/xtensa/exc_helper.c | 7 ++----- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 1e0cb1535c..cbb720e7cc 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -566,14 +566,14 @@ struct XtensaCPU { bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); -#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, unsigned size, MMUAccessType access_= type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t reta= ddr); -#endif /* !CONFIG_USER_ONLY */ +#endif void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void xtensa_count_regs(const XtensaConfig *config, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 58ec3a0862..c1cbd03595 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -192,11 +192,11 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = =3D { =20 static const struct TCGCPUOps xtensa_tcg_ops =3D { .initialize =3D xtensa_translate_init, - .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, .tlb_fill =3D xtensa_cpu_tlb_fill, .debug_excp_handler =3D xtensa_breakpoint_handler, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, .do_interrupt =3D xtensa_cpu_do_interrupt, .do_transaction_failed =3D xtensa_cpu_do_transaction_failed, .do_unaligned_access =3D xtensa_cpu_do_unaligned_access, diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index 10e75ab070..9bc7f50d35 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -255,11 +255,6 @@ void xtensa_cpu_do_interrupt(CPUState *cs) } check_interrupts(env); } -#else -void xtensa_cpu_do_interrupt(CPUState *cs) -{ -} -#endif =20 bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -270,3 +265,5 @@ bool xtensa_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) } return false; } + +#endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631578693; cv=none; d=zohomail.com; s=zohoarc; b=HyZ3fIuVj+zKW1zbjBs/FZYPLrHcp+Dc14TpYCoYTBtwLugOVh7DfCoTX/Xw/Fxjdjofq1PL1HLrlbed1eV5CSQXJfrCGP4HWgkqjF9mU1Uw4QngWtnh0PJRJpc39/EkLvYSYQRIqHFZwm6JN6RF5oAIjGA2i+voMLlB8M1weZc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631578693; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631578694973100001 From: Philippe Mathieu-Daud=C3=A9 All targets call TCGCPUOps::cpu_exec_interrupt() from sysemu code. Move its declaration to restrict it to system emulation. Extend the code guarded. Restrict the static inlined need_replay_interrupt() method to avoid a "defined but not used" warning. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-24-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 4 ++-- accel/tcg/cpu-exec.c | 10 +++++++--- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 6c7ab9600b..55123cb4d2 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -35,8 +35,6 @@ struct TCGCPUOps { void (*cpu_exec_enter)(CPUState *cpu); /** @cpu_exec_exit: Callback for cpu_exec cleanup */ void (*cpu_exec_exit)(CPUState *cpu); - /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ - bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); /** * @tlb_fill: Handle a softmmu tlb miss or user-only address fault * @@ -68,6 +66,8 @@ struct TCGCPUOps { void (*do_interrupt)(CPUState *cpu); #endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ #ifdef CONFIG_SOFTMMU + /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ + bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); /** * @do_transaction_failed: Callback for handling failed memory transac= tions * (ie bus faults or external aborts; not MMU faults) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2838177e7f..75dbc1e4e3 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -685,6 +685,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) return false; } =20 +#ifndef CONFIG_USER_ONLY /* * CPU_INTERRUPT_POLL is a virtual event which gets converted into a * "real" interrupt event later. It does not need to be recorded for @@ -698,12 +699,11 @@ static inline bool need_replay_interrupt(int interrup= t_request) return true; #endif } +#endif /* !CONFIG_USER_ONLY */ =20 static inline bool cpu_handle_interrupt(CPUState *cpu, TranslationBlock **last_tb) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); - /* Clear the interrupt flag now since we're processing * cpu->interrupt_request and cpu->exit_request. * Ensure zeroing happens before reading cpu->exit_request or @@ -725,6 +725,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, qemu_mutex_unlock_iothread(); return true; } +#if !defined(CONFIG_USER_ONLY) if (replay_mode =3D=3D REPLAY_MODE_PLAY && !replay_has_interrupt()= ) { /* Do nothing */ } else if (interrupt_request & CPU_INTERRUPT_HALT) { @@ -753,12 +754,14 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, qemu_mutex_unlock_iothread(); return true; } -#endif +#endif /* !TARGET_I386 */ /* The target hook has 3 exit conditions: False when the interrupt isn't processed, True when it is, and we should restart on a new TB, and via longjmp via cpu_loop_exit. */ else { + CPUClass *cc =3D CPU_GET_CLASS(cpu); + if (cc->tcg_ops->cpu_exec_interrupt && cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { if (need_replay_interrupt(interrupt_request)) { @@ -777,6 +780,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * reload the 'interrupt_request' value */ interrupt_request =3D cpu->interrupt_request; } +#endif /* !CONFIG_USER_ONLY */ if (interrupt_request & CPU_INTERRUPT_EXITTB) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_EXITTB; /* ensure that no TB jump will be modified as --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631579892; cv=none; d=zohomail.com; s=zohoarc; b=i3SriFvu4wmWGxqEmR/OT/RCKZ+dQyfTIpi+aS3QbEWzAxZlK4WwTgqoqvX5fuAKMmP3peBG9rW0rLu59BytScwwDuODe0ZZBKay9XBR+NMUW48L0hBWVIBHYTcdBbSj4ZKCPF3EgqNguerF5fqWFaMRSLoZ/aZmOLH428a/MLk= ARC-Message-Signature: i=1; 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Mon, 13 Sep 2021 17:15:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 32/44] user: Remove cpu_get_pic_interrupt() stubs Date: Mon, 13 Sep 2021 17:14:44 -0700 Message-Id: <20210914001456.793490-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579894117100003 From: Philippe Mathieu-Daud=C3=A9 cpu_get_pic_interrupt() is now unreachable from user-mode, delete the unnecessary stubs. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210911165434.531552-25-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/i386/cpu.h | 2 +- bsd-user/i386/target_arch_cpu.c | 5 ----- bsd-user/x86_64/target_arch_cpu.c | 5 ----- linux-user/main.c | 7 ------- 4 files changed, 1 insertion(+), 18 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 1a36c53c18..7dd664791a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1836,9 +1836,9 @@ int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t= *buf, int reg); void x86_cpu_list(void); int cpu_x86_support_mca_broadcast(CPUX86State *env); =20 +#ifndef CONFIG_USER_ONLY int cpu_get_pic_interrupt(CPUX86State *s); =20 -#ifndef CONFIG_USER_ONLY /* MSDOS compatibility mode FPU exception support */ void x86_register_ferr_irq(qemu_irq irq); void fpu_check_raise_ferr_irq(CPUX86State *s); diff --git a/bsd-user/i386/target_arch_cpu.c b/bsd-user/i386/target_arch_cp= u.c index 71998e5ba5..d349e45299 100644 --- a/bsd-user/i386/target_arch_cpu.c +++ b/bsd-user/i386/target_arch_cpu.c @@ -33,11 +33,6 @@ uint64_t cpu_get_tsc(CPUX86State *env) return cpu_get_host_ticks(); } =20 -int cpu_get_pic_interrupt(CPUX86State *env) -{ - return -1; -} - void bsd_i386_write_dt(void *ptr, unsigned long addr, unsigned long limit, int flags) { diff --git a/bsd-user/x86_64/target_arch_cpu.c b/bsd-user/x86_64/target_arc= h_cpu.c index db822e54c6..be7bd10720 100644 --- a/bsd-user/x86_64/target_arch_cpu.c +++ b/bsd-user/x86_64/target_arch_cpu.c @@ -33,11 +33,6 @@ uint64_t cpu_get_tsc(CPUX86State *env) return cpu_get_host_ticks(); } =20 -int cpu_get_pic_interrupt(CPUX86State *env) -{ - return -1; -} - void bsd_x86_64_write_dt(void *ptr, unsigned long addr, unsigned long limit, int flags) { diff --git a/linux-user/main.c b/linux-user/main.c index a6094563b6..45bde4598d 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -120,13 +120,6 @@ const char *qemu_uname_release; by remapping the process stack directly at the right place */ unsigned long guest_stack_size =3D 8 * 1024 * 1024UL; =20 -#if defined(TARGET_I386) -int cpu_get_pic_interrupt(CPUX86State *env) -{ - return -1; -} -#endif - /***********************************************************/ /* Helper routines for implementing atomic operations. */ =20 --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631580289975906.0228410338692; Mon, 13 Sep 2021 17:44:49 -0700 (PDT) Received: from localhost ([::1]:53908 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPwZ7-0002iH-0d for importer@patchew.org; Mon, 13 Sep 2021 20:44:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPw6j-0001oH-2W for qemu-devel@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631580290918100001 From: Philippe Mathieu-Daud=C3=A9 cpu_loop() never exits, so mark it with QEMU_NORETURN. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng Reviewed-By: Warner Losh Reviewed-by: Richard Henderson Message-Id: <20210905000429.1097336-1-f4bug@amsat.org> Signed-off-by: Richard Henderson --- bsd-user/qemu.h | 2 +- linux-user/qemu.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 522d6c4031..1511327d51 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -168,7 +168,7 @@ abi_long do_openbsd_syscall(void *cpu_env, int num, abi= _long arg1, abi_long arg5, abi_long arg6); void gemu_log(const char *fmt, ...) GCC_FMT_ATTR(1, 2); extern __thread CPUState *thread_cpu; -void cpu_loop(CPUArchState *env); +void QEMU_NORETURN cpu_loop(CPUArchState *env); char *target_strerror(int err); int get_osversion(void); void fork_start(void); diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 3b0b6b75fe..5b2c764ae7 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -236,7 +236,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long ar= g1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8); extern __thread CPUState *thread_cpu; -void cpu_loop(CPUArchState *env); +void QEMU_NORETURN cpu_loop(CPUArchState *env); const char *target_strerror(int err); int get_osversion(void); void init_qemu_uname_release(void); --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 13 Sep 2021 17:15:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 34/44] accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts Date: Mon, 13 Sep 2021 17:14:46 -0700 Message-Id: <20210914001456.793490-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ilya Leoshkevich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631580593279100001 Content-Type: text/plain; charset="utf-8" From: Ilya Leoshkevich x86_64 dotnet/runtime uses cmpxchg for code patching. When running it under s390x qemu-linux user, cpu_signal_handler() does not recognize this as a write and does not restore PAGE_WRITE cleared by tb_page_add(), incorrectly forwarding the signal to the guest code. Signed-off-by: Ilya Leoshkevich Reviewed-by: Richard Henderson Message-Id: <20210803221606.150103-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 48 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 41 insertions(+), 7 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 90d1a2d327..8fed542622 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -680,18 +680,26 @@ int cpu_signal_handler(int host_signum, void *pinfo, =20 pc =3D uc->uc_mcontext.psw.addr; =20 - /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead - of the normal 2 arguments. The 3rd argument contains the "int_code" - from the hardware which does in fact contain the is_write value. - The rt signal handler, as far as I can tell, does not give this val= ue - at all. Not that we could get to it from here even if it were. */ - /* ??? This is not even close to complete, since it ignores all - of the read-modify-write instructions. */ + /* + * ??? On linux, the non-rt signal handler has 4 (!) arguments instead + * of the normal 2 arguments. The 4th argument contains the "Translat= ion- + * Exception Identification for DAT Exceptions" from the hardware (aka + * "int_parm_long"), which does in fact contain the is_write value. + * The rt signal handler, as far as I can tell, does not give this val= ue + * at all. Not that we could get to it from here even if it were. + * So fall back to parsing instructions. Treat read-modify-write ones= as + * writes, which is not fully correct, but for tracking self-modifying= code + * this is better than treating them as reads. Checking si_addr page = flags + * might be a viable improvement, albeit a racy one. + */ + /* ??? This is not even close to complete. */ pinsn =3D (uint16_t *)pc; switch (pinsn[0] >> 8) { case 0x50: /* ST */ case 0x42: /* STC */ case 0x40: /* STH */ + case 0xba: /* CS */ + case 0xbb: /* CDS */ is_write =3D 1; break; case 0xc4: /* RIL format insns */ @@ -702,6 +710,12 @@ int cpu_signal_handler(int host_signum, void *pinfo, is_write =3D 1; } break; + case 0xc8: /* SSF format insns */ + switch (pinsn[0] & 0xf) { + case 0x2: /* CSST */ + is_write =3D 1; + } + break; case 0xe3: /* RXY format insns */ switch (pinsn[2] & 0xff) { case 0x50: /* STY */ @@ -715,7 +729,27 @@ int cpu_signal_handler(int host_signum, void *pinfo, is_write =3D 1; } break; + case 0xeb: /* RSY format insns */ + switch (pinsn[2] & 0xff) { + case 0x14: /* CSY */ + case 0x30: /* CSG */ + case 0x31: /* CDSY */ + case 0x3e: /* CDSG */ + case 0xe4: /* LANG */ + case 0xe6: /* LAOG */ + case 0xe7: /* LAXG */ + case 0xe8: /* LAAG */ + case 0xea: /* LAALG */ + case 0xf4: /* LAN */ + case 0xf6: /* LAO */ + case 0xf7: /* LAX */ + case 0xfa: /* LAAL */ + case 0xf8: /* LAA */ + is_write =3D 1; + } + break; } + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } =20 --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631580113; cv=none; d=zohomail.com; s=zohoarc; b=FAA3JpLJ9decxRyUz41NUfuL98XelgRGepSQzJQFew9Zn6bgzal36htayr8i4abXiXuXynjDOA3+i18jjEcVAuTiJeK+g97jIoUVVyTcJNfvPZykrKmfFmW06dHAK54fVVd0ccg2zaRkLVxJxwD6+ojNv7EVSLLZkVYql4joHH4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631580113; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=enaLGbWvNUeIQNl3JSOugT8ZMiXLFPXRZRQVmjGvuVU=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631580116262100002 Content-Type: text/plain; charset="utf-8" GCC since 4.8 provides the definition and we now require 7.5. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index d113b7f8db..18bb16c784 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -26,25 +26,6 @@ #ifndef ARM_TCG_TARGET_H #define ARM_TCG_TARGET_H =20 -/* The __ARM_ARCH define is provided by gcc 4.8. Construct it otherwise. = */ -#ifndef __ARM_ARCH -# if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ - || defined(__ARM_ARCH_7EM__) -# define __ARM_ARCH 7 -# elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ - || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \ - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__) -# define __ARM_ARCH 6 -# elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \ - || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \ - || defined(__ARM_ARCH_5TEJ__) -# define __ARM_ARCH 5 -# else -# define __ARM_ARCH 4 -# endif -#endif - extern int arm_arch; =20 #if defined(__ARM_ARCH_5T__) \ --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 13 Sep 2021 17:15:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 36/44] tcg/arm: Standardize on tcg_out__{reg,imm} Date: Mon, 13 Sep 2021 17:14:48 -0700 Message-Id: <20210914001456.793490-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579050247100001 Some of the functions specified _reg, some _imm, and some left it blank. Make it clearer to which we are referring. Split tcg_out_b_reg from tcg_out_bx_reg, to indicate when we do not actually require BX semantics. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index e5b4f86841..7d15c36f85 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -525,19 +525,19 @@ static bool tcg_target_const_match(int64_t val, TCGTy= pe type, int ct) return 0; } =20 -static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset) +static inline void tcg_out_b_imm(TCGContext *s, int cond, int32_t offset) { tcg_out32(s, (cond << 28) | 0x0a000000 | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset) +static inline void tcg_out_bl_imm(TCGContext *s, int cond, int32_t offset) { tcg_out32(s, (cond << 28) | 0x0b000000 | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static inline void tcg_out_blx(TCGContext *s, int cond, int rn) +static inline void tcg_out_blx_reg(TCGContext *s, int cond, int rn) { tcg_out32(s, (cond << 28) | 0x012fff30 | rn); } @@ -568,13 +568,19 @@ static inline void tcg_out_mov_reg(TCGContext *s, int= cond, int rd, int rm) } } =20 -static inline void tcg_out_bx(TCGContext *s, int cond, TCGReg rn) +static void tcg_out_bx_reg(TCGContext *s, int cond, TCGReg rn) { - /* Unless the C portion of QEMU is compiled as thumb, we don't - actually need true BX semantics; merely a branch to an address - held in a register. */ + tcg_out32(s, (cond << 28) | 0x012fff10 | rn); +} + +static void tcg_out_b_reg(TCGContext *s, int cond, TCGReg rn) +{ + /* + * Unless the C portion of QEMU is compiled as thumb, we don't need + * true BX semantics; merely a branch to an address held in a register. + */ if (use_armv5t_instructions) { - tcg_out32(s, (cond << 28) | 0x012fff10 | rn); + tcg_out_bx_reg(s, cond, rn); } else { tcg_out_mov_reg(s, cond, TCG_REG_PC, rn); } @@ -1215,7 +1221,7 @@ static void tcg_out_goto(TCGContext *s, int cond, con= st tcg_insn_unit *addr) ptrdiff_t disp =3D tcg_pcrel_diff(s, addr); =20 if ((addri & 1) =3D=3D 0 && disp - 8 < 0x01fffffd && disp - 8 > -0x01f= ffffd) { - tcg_out_b(s, cond, disp); + tcg_out_b_imm(s, cond, disp); return; } tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); @@ -1236,11 +1242,11 @@ static void tcg_out_call(TCGContext *s, const tcg_i= nsn_unit *addr) } tcg_out_blx_imm(s, disp); } else { - tcg_out_bl(s, COND_AL, disp); + tcg_out_bl_imm(s, COND_AL, disp); } } else if (use_armv7_instructions) { tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); - tcg_out_blx(s, COND_AL, TCG_REG_TMP); + tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); } else { /* ??? Know that movi_pool emits exactly 1 insn. */ tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0); @@ -1254,7 +1260,7 @@ static inline void tcg_out_goto_label(TCGContext *s, = int cond, TCGLabel *l) tcg_out_goto(s, cond, l->u.value_ptr); } else { tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); - tcg_out_b(s, cond, 0); + tcg_out_b_imm(s, cond, 0); } } =20 @@ -1823,7 +1829,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) /* This a conditional BL only to load a pointer within this opcode int= o LR for the slow path. We will not be using the value for a tail call.= */ label_ptr =3D s->code_ptr; - tcg_out_bl(s, COND_NE, 0); + tcg_out_bl_imm(s, COND_NE, 0); =20 tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend); =20 @@ -1929,7 +1935,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) =20 /* The conditional call must come last, as we're going to return here.= */ label_ptr =3D s->code_ptr; - tcg_out_bl(s, COND_NE, 0); + tcg_out_bl_imm(s, COND_NE, 0); =20 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); @@ -1982,7 +1988,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } break; case INDEX_op_goto_ptr: - tcg_out_bx(s, COND_AL, args[0]); + tcg_out_b_reg(s, COND_AL, args[0]); break; case INDEX_op_br: tcg_out_goto_label(s, COND_AL, arg_label(args[0])); @@ -3066,7 +3072,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); =20 - tcg_out_bx(s, COND_AL, tcg_target_call_iarg_regs[1]); + tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); =20 /* * Return path for goto_ptr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631581574229100001 Content-Type: text/plain; charset="utf-8" According to the Arm ARM DDI 0406C, section A1.3, the valid variants are ARMv5T, ARMv5TE, ARMv5TEJ -- there is no ARMv5 without Thumb. Therefore simplify the test from preprocessor ifdefs to base architecture revision. Retain the "t" in the name to minimize churn. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 18bb16c784..f41b809554 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -28,13 +28,7 @@ =20 extern int arm_arch; =20 -#if defined(__ARM_ARCH_5T__) \ - || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__) -# define use_armv5t_instructions 1 -#else -# define use_armv5t_instructions use_armv6_instructions -#endif - +#define use_armv5t_instructions (__ARM_ARCH >=3D 5 || arm_arch >=3D 5) #define use_armv6_instructions (__ARM_ARCH >=3D 6 || arm_arch >=3D 6) #define use_armv7_instructions (__ARM_ARCH >=3D 7 || arm_arch >=3D 7) =20 --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 13 Sep 2021 17:15:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 38/44] tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call Date: Mon, 13 Sep 2021 17:14:50 -0700 Message-Id: <20210914001456.793490-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631580680591100001 Content-Type: text/plain; charset="utf-8" ARMv4T has BX as its only interworking instruction. In order to support testing of different architecture revisions with a qemu binary that may have been built for, say ARMv6T2, fill in the blank required to make calls to helpers in thumb mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 49 ++++++++++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 15 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 7d15c36f85..852100bb80 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1211,7 +1211,8 @@ static inline void tcg_out_st8(TCGContext *s, int con= d, tcg_out_st8_12(s, cond, rd, rn, offset); } =20 -/* The _goto case is normally between TBs within the same code buffer, and +/* + * The _goto case is normally between TBs within the same code buffer, and * with the code buffer limited to 16MB we wouldn't need the long case. * But we also use it for the tail-call to the qemu_ld/st helpers, which d= oes. */ @@ -1219,38 +1220,56 @@ static void tcg_out_goto(TCGContext *s, int cond, c= onst tcg_insn_unit *addr) { intptr_t addri =3D (intptr_t)addr; ptrdiff_t disp =3D tcg_pcrel_diff(s, addr); + bool arm_mode =3D !(addri & 1); =20 - if ((addri & 1) =3D=3D 0 && disp - 8 < 0x01fffffd && disp - 8 > -0x01f= ffffd) { + if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { tcg_out_b_imm(s, cond, disp); return; } - tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); + + /* LDR is interworking from v5t. */ + if (arm_mode || use_armv5t_instructions) { + tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); + return; + } + + /* else v4t */ + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); + tcg_out_bx_reg(s, COND_AL, TCG_REG_TMP); } =20 -/* The call case is mostly used for helpers - so it's not unreasonable - * for them to be beyond branch range */ +/* + * The call case is mostly used for helpers - so it's not unreasonable + * for them to be beyond branch range. + */ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr) { intptr_t addri =3D (intptr_t)addr; ptrdiff_t disp =3D tcg_pcrel_diff(s, addr); + bool arm_mode =3D !(addri & 1); =20 if (disp - 8 < 0x02000000 && disp - 8 >=3D -0x02000000) { - if (addri & 1) { - /* Use BLX if the target is in Thumb mode */ - if (!use_armv5t_instructions) { - tcg_abort(); - } - tcg_out_blx_imm(s, disp); - } else { + if (arm_mode) { tcg_out_bl_imm(s, COND_AL, disp); + return; } - } else if (use_armv7_instructions) { + if (use_armv5t_instructions) { + tcg_out_blx_imm(s, disp); + return; + } + } + + if (use_armv5t_instructions) { tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); - } else { + } else if (arm_mode) { /* ??? Know that movi_pool emits exactly 1 insn. */ - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0); + tcg_out_mov_reg(s, COND_AL, TCG_REG_R14, TCG_REG_PC); tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri); + } else { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); + tcg_out_mov_reg(s, COND_AL, TCG_REG_R14, TCG_REG_PC); + tcg_out_bx_reg(s, COND_AL, TCG_REG_TMP); } } =20 --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631580269; cv=none; d=zohomail.com; s=zohoarc; b=B08Fn71uuBeSFCv6fJ71fDcWiPs7L6QEo/gTizIe/isFErEQ9bY16Q9oO6+BLYZioR8G0fMv2n87+FNrZuIjEZjF+uyO3CxbcLpo8dA5V7q9lg7NoMOrPImURifjUh2P1XWmZ/eB3t/KU5Bx16LT5apDwZM5Uzi7cL68J4gaBgM= ARC-Message-Signature: i=1; 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Mon, 13 Sep 2021 17:15:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 39/44] tcg/arm: Split out tcg_out_ldstm Date: Mon, 13 Sep 2021 17:14:51 -0700 Message-Id: <20210914001456.793490-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631580271932100001 Content-Type: text/plain; charset="utf-8" Expand these hard-coded instructions symbolically. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 852100bb80..c9e3fcfeac 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -141,6 +141,9 @@ typedef enum { INSN_CLZ =3D 0x016f0f10, INSN_RBIT =3D 0x06ff0f30, =20 + INSN_LDMIA =3D 0x08b00000, + INSN_STMDB =3D 0x09200000, + INSN_LDR_IMM =3D 0x04100000, INSN_LDR_REG =3D 0x06100000, INSN_STR_IMM =3D 0x04000000, @@ -593,6 +596,12 @@ static inline void tcg_out_dat_imm(TCGContext *s, (rn << 16) | (rd << 12) | im); } =20 +static void tcg_out_ldstm(TCGContext *s, int cond, int opc, + TCGReg rn, uint16_t mask) +{ + tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); +} + /* Note that this routine is used for both LDR and LDRH formats, so we do not wish to include an immediate shift at this point. */ static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg r= t, @@ -3081,7 +3090,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) { /* Calling convention requires us to save r4-r11 and lr. */ /* stmdb sp!, { r4 - r11, lr } */ - tcg_out32(s, (COND_AL << 28) | 0x092d4ff0); + tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, + (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6= ) | + (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9= ) | + (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_= R14)); =20 /* Reserve callee argument and tcg temp space. */ tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, @@ -3109,7 +3121,10 @@ static void tcg_out_epilogue(TCGContext *s) TCG_REG_CALL_STACK, STACK_ADDEND, 1); =20 /* ldmia sp!, { r4 - r11, pc } */ - tcg_out32(s, (COND_AL << 28) | 0x08bd8ff0); + tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, + (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6= ) | + (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9= ) | + (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_= PC)); } =20 typedef struct { --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 13 Sep 2021 17:18:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 40/44] tcg/arm: Simplify usage of encode_imm Date: Mon, 13 Sep 2021 17:14:52 -0700 Message-Id: <20210914001456.793490-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631580857045100001 Content-Type: text/plain; charset="utf-8" We have already computed the rotated value of the imm8 portion of the complete imm12 encoding. No sense leaving the combination of rot + rotation to the caller. Create an encode_imm12_nofail helper that performs an assert. This removes the final use of the local "rotl" function, which duplicated our generic "rol32" function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 141 +++++++++++++++++++++------------------ 1 file changed, 77 insertions(+), 64 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index c9e3fcfeac..1931cea1ca 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -312,10 +312,10 @@ static bool reloc_pc8(tcg_insn_unit *src_rw, const tc= g_insn_unit *target) { const tcg_insn_unit *src_rx =3D tcg_splitwx_to_rx(src_rw); ptrdiff_t offset =3D tcg_ptr_byte_diff(target, src_rx) - 8; - int rot =3D encode_imm(offset); + int imm12 =3D encode_imm(offset); =20 - if (rot >=3D 0) { - *src_rw =3D deposit32(*src_rw, 0, 12, rol32(offset, rot) | (rot <<= 7)); + if (imm12 >=3D 0) { + *src_rw =3D deposit32(*src_rw, 0, 12, imm12); return true; } return false; @@ -369,33 +369,52 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1))) #endif =20 -static inline uint32_t rotl(uint32_t val, int n) -{ - return (val << n) | (val >> (32 - n)); -} - -/* ARM immediates for ALU instructions are made of an unsigned 8-bit - right-rotated by an even amount between 0 and 30. */ +/* + * ARM immediates for ALU instructions are made of an unsigned 8-bit + * right-rotated by an even amount between 0 and 30. + * + * Return < 0 if @imm cannot be encoded, else the entire imm12 field. + */ static int encode_imm(uint32_t imm) { - int shift; + uint32_t rot, imm8; =20 - /* simple case, only lower bits */ - if ((imm & ~0xff) =3D=3D 0) - return 0; - /* then try a simple even shift */ - shift =3D ctz32(imm) & ~1; - if (((imm >> shift) & ~0xff) =3D=3D 0) - return 32 - shift; - /* now try harder with rotations */ - if ((rotl(imm, 2) & ~0xff) =3D=3D 0) - return 2; - if ((rotl(imm, 4) & ~0xff) =3D=3D 0) - return 4; - if ((rotl(imm, 6) & ~0xff) =3D=3D 0) - return 6; - /* imm can't be encoded */ + /* Simple case, no rotation required. */ + if ((imm & ~0xff) =3D=3D 0) { + return imm; + } + + /* Next, try a simple even shift. */ + rot =3D ctz32(imm) & ~1; + imm8 =3D imm >> rot; + rot =3D 32 - rot; + if ((imm8 & ~0xff) =3D=3D 0) { + goto found; + } + + /* + * Finally, try harder with rotations. + * The ctz test above will have taken care of rotates >=3D 8. + */ + for (rot =3D 2; rot < 8; rot +=3D 2) { + imm8 =3D rol32(imm, rot); + if ((imm8 & ~0xff) =3D=3D 0) { + goto found; + } + } + /* Fail: imm cannot be encoded. */ return -1; + + found: + /* Note that rot is even, and we discard bit 0 by shifting by 7. */ + return rot << 7 | imm8; +} + +static int encode_imm_nofail(uint32_t imm) +{ + int ret =3D encode_imm(imm); + tcg_debug_assert(ret >=3D 0); + return ret; } =20 static inline int check_fit_imm(uint32_t imm) @@ -782,20 +801,18 @@ static void tcg_out_movi_pool(TCGContext *s, int cond= , int rd, uint32_t arg) =20 static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) { - int rot, diff, opc, sh1, sh2; + int imm12, diff, opc, sh1, sh2; uint32_t tt0, tt1, tt2; =20 /* Check a single MOV/MVN before anything else. */ - rot =3D encode_imm(arg); - if (rot >=3D 0) { - tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, - rotl(arg, rot) | (rot << 7)); + imm12 =3D encode_imm(arg); + if (imm12 >=3D 0) { + tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); return; } - rot =3D encode_imm(~arg); - if (rot >=3D 0) { - tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, - rotl(~arg, rot) | (rot << 7)); + imm12 =3D encode_imm(~arg); + if (imm12 >=3D 0) { + tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); return; } =20 @@ -803,17 +820,15 @@ static void tcg_out_movi32(TCGContext *s, int cond, i= nt rd, uint32_t arg) or within the TB, which is immediately before the code block. */ diff =3D tcg_pcrel_diff(s, (void *)arg) - 8; if (diff >=3D 0) { - rot =3D encode_imm(diff); - if (rot >=3D 0) { - tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, - rotl(diff, rot) | (rot << 7)); + imm12 =3D encode_imm(diff); + if (imm12 >=3D 0) { + tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); return; } } else { - rot =3D encode_imm(-diff); - if (rot >=3D 0) { - tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, - rotl(-diff, rot) | (rot << 7)); + imm12 =3D encode_imm(-diff); + if (imm12 >=3D 0) { + tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); return; } } @@ -845,6 +860,8 @@ static void tcg_out_movi32(TCGContext *s, int cond, int= rd, uint32_t arg) sh2 =3D ctz32(tt1) & ~1; tt2 =3D tt1 & ~(0xff << sh2); if (tt2 =3D=3D 0) { + int rot; + rot =3D ((32 - sh1) << 7) & 0xf00; tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); rot =3D ((32 - sh2) << 7) & 0xf00; @@ -857,37 +874,35 @@ static void tcg_out_movi32(TCGContext *s, int cond, i= nt rd, uint32_t arg) tcg_out_movi_pool(s, cond, rd, arg); } =20 +/* + * Emit either the reg,imm or reg,reg form of a data-processing insn. + * rhs must satisfy the "rI" constraint. + */ static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg= dst, TCGArg lhs, TCGArg rhs, int rhs_is_const) { - /* Emit either the reg,imm or reg,reg form of a data-processing insn. - * rhs must satisfy the "rI" constraint. - */ if (rhs_is_const) { - int rot =3D encode_imm(rhs); - tcg_debug_assert(rot >=3D 0); - tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7= )); + tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); } else { tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); } } =20 +/* + * Emit either the reg,imm or reg,reg form of a data-processing insn. + * rhs must satisfy the "rIK" constraint. + */ static void tcg_out_dat_rIK(TCGContext *s, int cond, int opc, int opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, bool rhs_is_const) { - /* Emit either the reg,imm or reg,reg form of a data-processing insn. - * rhs must satisfy the "rIK" constraint. - */ if (rhs_is_const) { - int rot =3D encode_imm(rhs); - if (rot < 0) { - rhs =3D ~rhs; - rot =3D encode_imm(rhs); - tcg_debug_assert(rot >=3D 0); + int imm12 =3D encode_imm(rhs); + if (imm12 < 0) { + imm12 =3D encode_imm_nofail(~rhs); opc =3D opinv; } - tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7= )); + tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); } else { tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); } @@ -901,14 +916,12 @@ static void tcg_out_dat_rIN(TCGContext *s, int cond, = int opc, int opneg, * rhs must satisfy the "rIN" constraint. */ if (rhs_is_const) { - int rot =3D encode_imm(rhs); - if (rot < 0) { - rhs =3D -rhs; - rot =3D encode_imm(rhs); - tcg_debug_assert(rot >=3D 0); + int imm12 =3D encode_imm(rhs); + if (imm12 < 0) { + imm12 =3D encode_imm_nofail(-rhs); opc =3D opneg; } - tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7= )); + tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); } else { tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); } --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Mon, 13 Sep 2021 17:18:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 41/44] tcg/arm: Drop inline markers Date: Mon, 13 Sep 2021 17:14:53 -0700 Message-Id: <20210914001456.793490-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631579229611100003 Let the compiler decide about inlining. Remove tcg_out_nop as unused. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 234 +++++++++++++++++++-------------------- 1 file changed, 114 insertions(+), 120 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 1931cea1ca..529728fbbe 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -417,7 +417,7 @@ static int encode_imm_nofail(uint32_t imm) return ret; } =20 -static inline int check_fit_imm(uint32_t imm) +static bool check_fit_imm(uint32_t imm) { return encode_imm(imm) >=3D 0; } @@ -547,42 +547,37 @@ static bool tcg_target_const_match(int64_t val, TCGTy= pe type, int ct) return 0; } =20 -static inline void tcg_out_b_imm(TCGContext *s, int cond, int32_t offset) +static void tcg_out_b_imm(TCGContext *s, int cond, int32_t offset) { tcg_out32(s, (cond << 28) | 0x0a000000 | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static inline void tcg_out_bl_imm(TCGContext *s, int cond, int32_t offset) +static void tcg_out_bl_imm(TCGContext *s, int cond, int32_t offset) { tcg_out32(s, (cond << 28) | 0x0b000000 | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static inline void tcg_out_blx_reg(TCGContext *s, int cond, int rn) +static void tcg_out_blx_reg(TCGContext *s, int cond, int rn) { tcg_out32(s, (cond << 28) | 0x012fff30 | rn); } =20 -static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset) +static void tcg_out_blx_imm(TCGContext *s, int32_t offset) { tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static inline void tcg_out_dat_reg(TCGContext *s, +static void tcg_out_dat_reg(TCGContext *s, int cond, int opc, int rd, int rn, int rm, int shift) { tcg_out32(s, (cond << 28) | (0 << 25) | opc | (rn << 16) | (rd << 12) | shift | rm); } =20 -static inline void tcg_out_nop(TCGContext *s) -{ - tcg_out32(s, INSN_NOP); -} - -static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm) +static void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm) { /* Simple reg-reg move, optimising out the 'do nothing' case */ if (rd !=3D rm) { @@ -608,8 +603,8 @@ static void tcg_out_b_reg(TCGContext *s, int cond, TCGR= eg rn) } } =20 -static inline void tcg_out_dat_imm(TCGContext *s, - int cond, int opc, int rd, int rn, int im) +static void tcg_out_dat_imm(TCGContext *s, int cond, int opc, + int rd, int rn, int im) { tcg_out32(s, (cond << 28) | (1 << 25) | opc | (rn << 16) | (rd << 12) | im); @@ -654,141 +649,141 @@ static void tcg_out_memop_12(TCGContext *s, int con= d, ARMInsn opc, TCGReg rt, (rn << 16) | (rt << 12) | imm12); } =20 -static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) +static void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); } =20 -static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) +static void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); } =20 -static inline void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) +static void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_ldrd_rwb(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void __attribute__((unused)) +tcg_out_ldrd_rwb(TCGContext *s, int cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1); } =20 -static inline void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) +static void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); } =20 /* Register pre-increment with base writeback. */ -static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); } =20 -static inline void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); } =20 -static inline void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) +static void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) +static void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) +static void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) +static void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); } =20 -static inline void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) +static void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); } =20 -static inline void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) +static void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); } @@ -878,8 +873,8 @@ static void tcg_out_movi32(TCGContext *s, int cond, int= rd, uint32_t arg) * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rI" constraint. */ -static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg= dst, - TCGArg lhs, TCGArg rhs, int rhs_is_const) +static void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst, + TCGArg lhs, TCGArg rhs, int rhs_is_const) { if (rhs_is_const) { tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); @@ -927,8 +922,8 @@ static void tcg_out_dat_rIN(TCGContext *s, int cond, in= t opc, int opneg, } } =20 -static inline void tcg_out_mul32(TCGContext *s, int cond, TCGReg rd, - TCGReg rn, TCGReg rm) +static void tcg_out_mul32(TCGContext *s, int cond, TCGReg rd, + TCGReg rn, TCGReg rm) { /* if ArchVersion() < 6 && d =3D=3D n then UNPREDICTABLE; */ if (!use_armv6_instructions && rd =3D=3D rn) { @@ -945,8 +940,8 @@ static inline void tcg_out_mul32(TCGContext *s, int con= d, TCGReg rd, tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn); } =20 -static inline void tcg_out_umull32(TCGContext *s, int cond, TCGReg rd0, - TCGReg rd1, TCGReg rn, TCGReg rm) +static void tcg_out_umull32(TCGContext *s, int cond, TCGReg rd0, + TCGReg rd1, TCGReg rn, TCGReg rm) { /* if ArchVersion() < 6 && (dHi =3D=3D n || dLo =3D=3D n) then UNPREDI= CTABLE; */ if (!use_armv6_instructions && (rd0 =3D=3D rn || rd1 =3D=3D rn)) { @@ -964,8 +959,8 @@ static inline void tcg_out_umull32(TCGContext *s, int c= ond, TCGReg rd0, (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); } =20 -static inline void tcg_out_smull32(TCGContext *s, int cond, TCGReg rd0, - TCGReg rd1, TCGReg rn, TCGReg rm) +static void tcg_out_smull32(TCGContext *s, int cond, TCGReg rd0, + TCGReg rd1, TCGReg rn, TCGReg rm) { /* if ArchVersion() < 6 && (dHi =3D=3D n || dLo =3D=3D n) then UNPREDI= CTABLE; */ if (!use_armv6_instructions && (rd0 =3D=3D rn || rd1 =3D=3D rn)) { @@ -983,18 +978,17 @@ static inline void tcg_out_smull32(TCGContext *s, int= cond, TCGReg rd0, (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); } =20 -static inline void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, i= nt rm) +static void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, int rm) { tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); } =20 -static inline void tcg_out_udiv(TCGContext *s, int cond, int rd, int rn, i= nt rm) +static void tcg_out_udiv(TCGContext *s, int cond, int rd, int rn, int rm) { tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); } =20 -static inline void tcg_out_ext8s(TCGContext *s, int cond, - int rd, int rn) +static void tcg_out_ext8s(TCGContext *s, int cond, int rd, int rn) { if (use_armv6_instructions) { /* sxtb */ @@ -1007,14 +1001,13 @@ static inline void tcg_out_ext8s(TCGContext *s, int= cond, } } =20 -static inline void tcg_out_ext8u(TCGContext *s, int cond, - int rd, int rn) +static void __attribute__((unused)) +tcg_out_ext8u(TCGContext *s, int cond, int rd, int rn) { tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); } =20 -static inline void tcg_out_ext16s(TCGContext *s, int cond, - int rd, int rn) +static void tcg_out_ext16s(TCGContext *s, int cond, int rd, int rn) { if (use_armv6_instructions) { /* sxth */ @@ -1027,8 +1020,7 @@ static inline void tcg_out_ext16s(TCGContext *s, int = cond, } } =20 -static inline void tcg_out_ext16u(TCGContext *s, int cond, - int rd, int rn) +static void tcg_out_ext16u(TCGContext *s, int cond, int rd, int rn) { if (use_armv6_instructions) { /* uxth */ @@ -1108,7 +1100,7 @@ static void tcg_out_bswap16(TCGContext *s, int cond, = int rd, int rn, int flags) ? SHIFT_IMM_ASR(8) : SHIFT_IMM_LSR(8))); } =20 -static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) +static void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) { if (use_armv6_instructions) { /* rev */ @@ -1125,8 +1117,8 @@ static inline void tcg_out_bswap32(TCGContext *s, int= cond, int rd, int rn) } } =20 -static inline void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd, - TCGArg a1, int ofs, int len, bool const= _a1) +static void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len, bool const_a1) { if (const_a1) { /* bfi becomes bfc with rn =3D=3D 15. */ @@ -1137,24 +1129,24 @@ static inline void tcg_out_deposit(TCGContext *s, i= nt cond, TCGReg rd, | (ofs << 7) | ((ofs + len - 1) << 16)); } =20 -static inline void tcg_out_extract(TCGContext *s, int cond, TCGReg rd, - TCGArg a1, int ofs, int len) +static void tcg_out_extract(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len) { /* ubfx */ tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | a1 | (ofs << 7) | ((len - 1) << 16)); } =20 -static inline void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd, - TCGArg a1, int ofs, int len) +static void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len) { /* sbfx */ tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | a1 | (ofs << 7) | ((len - 1) << 16)); } =20 -static inline void tcg_out_ld32u(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_ld32u(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1163,8 +1155,8 @@ static inline void tcg_out_ld32u(TCGContext *s, int c= ond, tcg_out_ld32_12(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_st32(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_st32(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1173,8 +1165,8 @@ static inline void tcg_out_st32(TCGContext *s, int co= nd, tcg_out_st32_12(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_ld16u(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_ld16u(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1183,8 +1175,8 @@ static inline void tcg_out_ld16u(TCGContext *s, int c= ond, tcg_out_ld16u_8(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_ld16s(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_ld16s(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1193,8 +1185,8 @@ static inline void tcg_out_ld16s(TCGContext *s, int c= ond, tcg_out_ld16s_8(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_st16(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_st16(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1203,8 +1195,8 @@ static inline void tcg_out_st16(TCGContext *s, int co= nd, tcg_out_st16_8(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_ld8u(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_ld8u(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1213,8 +1205,8 @@ static inline void tcg_out_ld8u(TCGContext *s, int co= nd, tcg_out_ld8_12(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_ld8s(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_ld8s(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1223,8 +1215,8 @@ static inline void tcg_out_ld8s(TCGContext *s, int co= nd, tcg_out_ld8s_8(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_st8(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_st8(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1295,7 +1287,7 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *addr) } } =20 -static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l) +static void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l) { if (l->has_value) { tcg_out_goto(s, cond, l->u.value_ptr); @@ -1305,7 +1297,7 @@ static inline void tcg_out_goto_label(TCGContext *s, = int cond, TCGLabel *l) } } =20 -static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +static void tcg_out_mb(TCGContext *s, TCGArg a0) { if (use_armv7_instructions) { tcg_out32(s, INSN_DMB_ISH); @@ -1761,9 +1753,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) } #endif /* SOFTMMU */ =20 -static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend) +static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addend) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1804,9 +1796,9 @@ static inline void tcg_out_qemu_ld_index(TCGContext *= s, MemOp opc, } } =20 -static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo) +#ifndef CONFIG_SOFTMMU +static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, + TCGReg datahi, TCGReg addrlo) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1844,6 +1836,7 @@ static inline void tcg_out_qemu_ld_direct(TCGContext = *s, MemOp opc, g_assert_not_reached(); } } +#endif =20 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { @@ -1886,9 +1879,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) #endif } =20 -static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp op= c, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend) +static void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addend) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1918,9 +1911,9 @@ static inline void tcg_out_qemu_st_index(TCGContext *= s, int cond, MemOp opc, } } =20 -static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo) +#ifndef CONFIG_SOFTMMU +static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, + TCGReg datahi, TCGReg addrlo) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1949,6 +1942,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext = *s, MemOp opc, g_assert_not_reached(); } } +#endif =20 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { @@ -1993,9 +1987,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) =20 static void tcg_out_epilogue(TCGContext *s); =20 -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0, a1, a2, a3, a4, a5; int c; @@ -2552,8 +2546,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, T= CGReg arg, } } =20 -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) { return false; } --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631580829; cv=none; d=zohomail.com; s=zohoarc; b=J7CrWahdaT0jPhCn+OvHPkBJM9rzjU+dl/sDLPR3K2pYGKe9XCcYzGoTQ8CwE4FIutfNbE8Ns7Bh0C06iR2Z+oHml6ou1LjF/J7d2QGcaT3RxaEQ3/a37nFjRo0AJVR198eCvRnlVbyNLWb/Obzi2cD43ABSKTzVAOf6HqeT9Ow= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Mon, 13 Sep 2021 17:18:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 42/44] tcg/arm: Give enum arm_cond_code_e a typedef and use it Date: Mon, 13 Sep 2021 17:14:54 -0700 Message-Id: <20210914001456.793490-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631580831795100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 136 +++++++++++++++++++-------------------- 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 529728fbbe..c068e707e8 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -92,7 +92,7 @@ static const int tcg_target_call_oarg_regs[2] =3D { #define TCG_REG_TMP TCG_REG_R12 #define TCG_VEC_TMP TCG_REG_Q15 =20 -enum arm_cond_code_e { +typedef enum { COND_EQ =3D 0x0, COND_NE =3D 0x1, COND_CS =3D 0x2, /* Unsigned greater or equal */ @@ -108,7 +108,7 @@ enum arm_cond_code_e { COND_GT =3D 0xc, COND_LE =3D 0xd, COND_AL =3D 0xe, -}; +} ARMCond; =20 #define TO_CPSR (1 << 20) =20 @@ -547,19 +547,19 @@ static bool tcg_target_const_match(int64_t val, TCGTy= pe type, int ct) return 0; } =20 -static void tcg_out_b_imm(TCGContext *s, int cond, int32_t offset) +static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) { tcg_out32(s, (cond << 28) | 0x0a000000 | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static void tcg_out_bl_imm(TCGContext *s, int cond, int32_t offset) +static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) { tcg_out32(s, (cond << 28) | 0x0b000000 | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static void tcg_out_blx_reg(TCGContext *s, int cond, int rn) +static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, int rn) { tcg_out32(s, (cond << 28) | 0x012fff30 | rn); } @@ -570,14 +570,14 @@ static void tcg_out_blx_imm(TCGContext *s, int32_t of= fset) (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static void tcg_out_dat_reg(TCGContext *s, - int cond, int opc, int rd, int rn, int rm, int shift) +static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, int opc, int rd, + int rn, int rm, int shift) { tcg_out32(s, (cond << 28) | (0 << 25) | opc | (rn << 16) | (rd << 12) | shift | rm); } =20 -static void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm) +static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, int rd, int rm) { /* Simple reg-reg move, optimising out the 'do nothing' case */ if (rd !=3D rm) { @@ -585,12 +585,12 @@ static void tcg_out_mov_reg(TCGContext *s, int cond, = int rd, int rm) } } =20 -static void tcg_out_bx_reg(TCGContext *s, int cond, TCGReg rn) +static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) { tcg_out32(s, (cond << 28) | 0x012fff10 | rn); } =20 -static void tcg_out_b_reg(TCGContext *s, int cond, TCGReg rn) +static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) { /* * Unless the C portion of QEMU is compiled as thumb, we don't need @@ -603,14 +603,14 @@ static void tcg_out_b_reg(TCGContext *s, int cond, TC= GReg rn) } } =20 -static void tcg_out_dat_imm(TCGContext *s, int cond, int opc, +static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, int opc, int rd, int rn, int im) { tcg_out32(s, (cond << 28) | (1 << 25) | opc | (rn << 16) | (rd << 12) | im); } =20 -static void tcg_out_ldstm(TCGContext *s, int cond, int opc, +static void tcg_out_ldstm(TCGContext *s, ARMCond cond, int opc, TCGReg rn, uint16_t mask) { tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); @@ -618,14 +618,14 @@ static void tcg_out_ldstm(TCGContext *s, int cond, in= t opc, =20 /* Note that this routine is used for both LDR and LDRH formats, so we do not wish to include an immediate shift at this point. */ -static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg r= t, +static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGR= eg rt, TCGReg rn, TCGReg rm, bool u, bool p, bool w) { tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | (rn << 16) | (rt << 12) | rm); } =20 -static void tcg_out_memop_8(TCGContext *s, int cond, ARMInsn opc, TCGReg r= t, +static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGR= eg rt, TCGReg rn, int imm8, bool p, bool w) { bool u =3D 1; @@ -637,7 +637,7 @@ static void tcg_out_memop_8(TCGContext *s, int cond, AR= MInsn opc, TCGReg rt, (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf= )); } =20 -static void tcg_out_memop_12(TCGContext *s, int cond, ARMInsn opc, TCGReg = rt, +static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, TCG= Reg rt, TCGReg rn, int imm12, bool p, bool w) { bool u =3D 1; @@ -649,152 +649,152 @@ static void tcg_out_memop_12(TCGContext *s, int con= d, ARMInsn opc, TCGReg rt, (rn << 16) | (rt << 12) | imm12); } =20 -static void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); } =20 -static void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); } =20 -static void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); } =20 -static void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); } =20 static void __attribute__((unused)) -tcg_out_ldrd_rwb(TCGContext *s, int cond, TCGReg rt, TCGReg rn, TCGReg rm) +tcg_out_ldrd_rwb(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg= rm) { tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1); } =20 -static void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); } =20 -static void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); } =20 /* Register pre-increment with base writeback. */ -static void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); } =20 -static void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); } =20 -static void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); } =20 -static void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); } =20 -static void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); } =20 -static void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); } =20 -static void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); } =20 -static void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); } =20 -static void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t ar= g) +static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, int rd, uint32_= t arg) { new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); } =20 -static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) +static void tcg_out_movi32(TCGContext *s, ARMCond cond, int rd, uint32_t a= rg) { int imm12, diff, opc, sh1, sh2; uint32_t tt0, tt1, tt2; @@ -873,7 +873,7 @@ static void tcg_out_movi32(TCGContext *s, int cond, int= rd, uint32_t arg) * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rI" constraint. */ -static void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst, +static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, int opc, TCGArg ds= t, TCGArg lhs, TCGArg rhs, int rhs_is_const) { if (rhs_is_const) { @@ -887,7 +887,7 @@ static void tcg_out_dat_rI(TCGContext *s, int cond, int= opc, TCGArg dst, * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rIK" constraint. */ -static void tcg_out_dat_rIK(TCGContext *s, int cond, int opc, int opinv, +static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, int opc, int opin= v, TCGReg dst, TCGReg lhs, TCGArg rhs, bool rhs_is_const) { @@ -903,7 +903,7 @@ static void tcg_out_dat_rIK(TCGContext *s, int cond, in= t opc, int opinv, } } =20 -static void tcg_out_dat_rIN(TCGContext *s, int cond, int opc, int opneg, +static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, int opc, int opne= g, TCGArg dst, TCGArg lhs, TCGArg rhs, bool rhs_is_const) { @@ -922,7 +922,7 @@ static void tcg_out_dat_rIN(TCGContext *s, int cond, in= t opc, int opneg, } } =20 -static void tcg_out_mul32(TCGContext *s, int cond, TCGReg rd, +static void tcg_out_mul32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn, TCGReg rm) { /* if ArchVersion() < 6 && d =3D=3D n then UNPREDICTABLE; */ @@ -940,7 +940,7 @@ static void tcg_out_mul32(TCGContext *s, int cond, TCGR= eg rd, tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn); } =20 -static void tcg_out_umull32(TCGContext *s, int cond, TCGReg rd0, +static void tcg_out_umull32(TCGContext *s, ARMCond cond, TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) { /* if ArchVersion() < 6 && (dHi =3D=3D n || dLo =3D=3D n) then UNPREDI= CTABLE; */ @@ -959,7 +959,7 @@ static void tcg_out_umull32(TCGContext *s, int cond, TC= GReg rd0, (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); } =20 -static void tcg_out_smull32(TCGContext *s, int cond, TCGReg rd0, +static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) { /* if ArchVersion() < 6 && (dHi =3D=3D n || dLo =3D=3D n) then UNPREDI= CTABLE; */ @@ -978,17 +978,17 @@ static void tcg_out_smull32(TCGContext *s, int cond, = TCGReg rd0, (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); } =20 -static void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, int rm) +static void tcg_out_sdiv(TCGContext *s, ARMCond cond, int rd, int rn, int = rm) { tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); } =20 -static void tcg_out_udiv(TCGContext *s, int cond, int rd, int rn, int rm) +static void tcg_out_udiv(TCGContext *s, ARMCond cond, int rd, int rn, int = rm) { tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); } =20 -static void tcg_out_ext8s(TCGContext *s, int cond, int rd, int rn) +static void tcg_out_ext8s(TCGContext *s, ARMCond cond, int rd, int rn) { if (use_armv6_instructions) { /* sxtb */ @@ -1002,12 +1002,12 @@ static void tcg_out_ext8s(TCGContext *s, int cond, = int rd, int rn) } =20 static void __attribute__((unused)) -tcg_out_ext8u(TCGContext *s, int cond, int rd, int rn) +tcg_out_ext8u(TCGContext *s, ARMCond cond, int rd, int rn) { tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); } =20 -static void tcg_out_ext16s(TCGContext *s, int cond, int rd, int rn) +static void tcg_out_ext16s(TCGContext *s, ARMCond cond, int rd, int rn) { if (use_armv6_instructions) { /* sxth */ @@ -1020,7 +1020,7 @@ static void tcg_out_ext16s(TCGContext *s, int cond, i= nt rd, int rn) } } =20 -static void tcg_out_ext16u(TCGContext *s, int cond, int rd, int rn) +static void tcg_out_ext16u(TCGContext *s, ARMCond cond, int rd, int rn) { if (use_armv6_instructions) { /* uxth */ @@ -1033,7 +1033,7 @@ static void tcg_out_ext16u(TCGContext *s, int cond, i= nt rd, int rn) } } =20 -static void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn, int f= lags) +static void tcg_out_bswap16(TCGContext *s, ARMCond cond, int rd, int rn, i= nt flags) { if (use_armv6_instructions) { if (flags & TCG_BSWAP_OS) { @@ -1100,7 +1100,7 @@ static void tcg_out_bswap16(TCGContext *s, int cond, = int rd, int rn, int flags) ? SHIFT_IMM_ASR(8) : SHIFT_IMM_LSR(8))); } =20 -static void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) +static void tcg_out_bswap32(TCGContext *s, ARMCond cond, int rd, int rn) { if (use_armv6_instructions) { /* rev */ @@ -1117,7 +1117,7 @@ static void tcg_out_bswap32(TCGContext *s, int cond, = int rd, int rn) } } =20 -static void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd, +static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, TCGArg a1, int ofs, int len, bool const_a1) { if (const_a1) { @@ -1129,7 +1129,7 @@ static void tcg_out_deposit(TCGContext *s, int cond, = TCGReg rd, | (ofs << 7) | ((ofs + len - 1) << 16)); } =20 -static void tcg_out_extract(TCGContext *s, int cond, TCGReg rd, +static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, TCGArg a1, int ofs, int len) { /* ubfx */ @@ -1137,7 +1137,7 @@ static void tcg_out_extract(TCGContext *s, int cond, = TCGReg rd, | (ofs << 7) | ((len - 1) << 16)); } =20 -static void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd, +static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, TCGArg a1, int ofs, int len) { /* sbfx */ @@ -1145,7 +1145,7 @@ static void tcg_out_sextract(TCGContext *s, int cond,= TCGReg rd, | (ofs << 7) | ((len - 1) << 16)); } =20 -static void tcg_out_ld32u(TCGContext *s, int cond, +static void tcg_out_ld32u(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { @@ -1155,7 +1155,7 @@ static void tcg_out_ld32u(TCGContext *s, int cond, tcg_out_ld32_12(s, cond, rd, rn, offset); } =20 -static void tcg_out_st32(TCGContext *s, int cond, +static void tcg_out_st32(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { @@ -1165,7 +1165,7 @@ static void tcg_out_st32(TCGContext *s, int cond, tcg_out_st32_12(s, cond, rd, rn, offset); } =20 -static void tcg_out_ld16u(TCGContext *s, int cond, +static void tcg_out_ld16u(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { @@ -1175,7 +1175,7 @@ static void tcg_out_ld16u(TCGContext *s, int cond, tcg_out_ld16u_8(s, cond, rd, rn, offset); } =20 -static void tcg_out_ld16s(TCGContext *s, int cond, +static void tcg_out_ld16s(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { @@ -1185,7 +1185,7 @@ static void tcg_out_ld16s(TCGContext *s, int cond, tcg_out_ld16s_8(s, cond, rd, rn, offset); } =20 -static void tcg_out_st16(TCGContext *s, int cond, +static void tcg_out_st16(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { @@ -1195,7 +1195,7 @@ static void tcg_out_st16(TCGContext *s, int cond, tcg_out_st16_8(s, cond, rd, rn, offset); } =20 -static void tcg_out_ld8u(TCGContext *s, int cond, +static void tcg_out_ld8u(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { @@ -1205,7 +1205,7 @@ static void tcg_out_ld8u(TCGContext *s, int cond, tcg_out_ld8_12(s, cond, rd, rn, offset); } =20 -static void tcg_out_ld8s(TCGContext *s, int cond, +static void tcg_out_ld8s(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { @@ -1215,7 +1215,7 @@ static void tcg_out_ld8s(TCGContext *s, int cond, tcg_out_ld8s_8(s, cond, rd, rn, offset); } =20 -static void tcg_out_st8(TCGContext *s, int cond, +static void tcg_out_st8(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { @@ -1230,7 +1230,7 @@ static void tcg_out_st8(TCGContext *s, int cond, * with the code buffer limited to 16MB we wouldn't need the long case. * But we also use it for the tail-call to the qemu_ld/st helpers, which d= oes. */ -static void tcg_out_goto(TCGContext *s, int cond, const tcg_insn_unit *add= r) +static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit = *addr) { intptr_t addri =3D (intptr_t)addr; ptrdiff_t disp =3D tcg_pcrel_diff(s, addr); @@ -1287,7 +1287,7 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *addr) } } =20 -static void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l) +static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) { if (l->has_value) { tcg_out_goto(s, cond, l->u.value_ptr); @@ -1879,7 +1879,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) #endif } =20 -static void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc, +static void tcg_out_qemu_st_index(TCGContext *s, ARMCond cond, MemOp opc, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addend) { --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Mon, 13 Sep 2021 17:18:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 43/44] tcg/arm: More use of the ARMInsn enum Date: Mon, 13 Sep 2021 17:14:55 -0700 Message-Id: <20210914001456.793490-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631581652556100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index c068e707e8..cf0627448b 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -570,7 +570,7 @@ static void tcg_out_blx_imm(TCGContext *s, int32_t offs= et) (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, int opc, int rd, +static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, int = rd, int rn, int rm, int shift) { tcg_out32(s, (cond << 28) | (0 << 25) | opc | @@ -603,14 +603,14 @@ static void tcg_out_b_reg(TCGContext *s, ARMCond cond= , TCGReg rn) } } =20 -static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, int opc, +static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, int rd, int rn, int im) { tcg_out32(s, (cond << 28) | (1 << 25) | opc | (rn << 16) | (rd << 12) | im); } =20 -static void tcg_out_ldstm(TCGContext *s, ARMCond cond, int opc, +static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rn, uint16_t mask) { tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); @@ -637,8 +637,8 @@ static void tcg_out_memop_8(TCGContext *s, ARMCond cond= , ARMInsn opc, TCGReg rt, (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf= )); } =20 -static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, TCG= Reg rt, - TCGReg rn, int imm12, bool p, bool w) +static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, + TCGReg rt, TCGReg rn, int imm12, bool p, bool= w) { bool u =3D 1; if (imm12 < 0) { @@ -873,7 +873,7 @@ static void tcg_out_movi32(TCGContext *s, ARMCond cond,= int rd, uint32_t arg) * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rI" constraint. */ -static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, int opc, TCGArg ds= t, +static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, TCGAr= g dst, TCGArg lhs, TCGArg rhs, int rhs_is_const) { if (rhs_is_const) { @@ -887,8 +887,8 @@ static void tcg_out_dat_rI(TCGContext *s, ARMCond cond,= int opc, TCGArg dst, * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rIK" constraint. */ -static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, int opc, int opin= v, - TCGReg dst, TCGReg lhs, TCGArg rhs, +static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, + ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg = rhs, bool rhs_is_const) { if (rhs_is_const) { @@ -903,8 +903,8 @@ static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond= , int opc, int opinv, } } =20 -static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, int opc, int opne= g, - TCGArg dst, TCGArg lhs, TCGArg rhs, +static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, + ARMInsn opneg, TCGArg dst, TCGArg lhs, TCGArg = rhs, bool rhs_is_const) { /* Emit either the reg,imm or reg,reg form of a data-processing insn. --=20 2.25.1 From nobody Thu Apr 25 07:05:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631581712169100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 65 +++++++++++++++++++++------------------- 1 file changed, 35 insertions(+), 30 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index cf0627448b..d25e68b36b 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -559,7 +559,7 @@ static void tcg_out_bl_imm(TCGContext *s, ARMCond cond,= int32_t offset) (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, int rn) +static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) { tcg_out32(s, (cond << 28) | 0x012fff30 | rn); } @@ -570,14 +570,14 @@ static void tcg_out_blx_imm(TCGContext *s, int32_t of= fset) (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, int = rd, - int rn, int rm, int shift) +static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, + TCGReg rd, TCGReg rn, TCGReg rm, int shift) { tcg_out32(s, (cond << 28) | (0 << 25) | opc | (rn << 16) | (rd << 12) | shift | rm); } =20 -static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, int rd, int rm) +static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg= rm) { /* Simple reg-reg move, optimising out the 'do nothing' case */ if (rd !=3D rm) { @@ -604,7 +604,7 @@ static void tcg_out_b_reg(TCGContext *s, ARMCond cond, = TCGReg rn) } =20 static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, - int rd, int rn, int im) + TCGReg rd, TCGReg rn, int im) { tcg_out32(s, (cond << 28) | (1 << 25) | opc | (rn << 16) | (rd << 12) | im); @@ -788,13 +788,15 @@ static void tcg_out_ld8s_r(TCGContext *s, ARMCond con= d, TCGReg rt, tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, int rd, uint32_= t arg) +static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, + TCGReg rd, uint32_t arg) { new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); } =20 -static void tcg_out_movi32(TCGContext *s, ARMCond cond, int rd, uint32_t a= rg) +static void tcg_out_movi32(TCGContext *s, ARMCond cond, + TCGReg rd, uint32_t arg) { int imm12, diff, opc, sh1, sh2; uint32_t tt0, tt1, tt2; @@ -873,8 +875,8 @@ static void tcg_out_movi32(TCGContext *s, ARMCond cond,= int rd, uint32_t arg) * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rI" constraint. */ -static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, TCGAr= g dst, - TCGArg lhs, TCGArg rhs, int rhs_is_const) +static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, + TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_= const) { if (rhs_is_const) { tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); @@ -904,7 +906,7 @@ static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond= , ARMInsn opc, } =20 static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, - ARMInsn opneg, TCGArg dst, TCGArg lhs, TCGArg = rhs, + ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg = rhs, bool rhs_is_const) { /* Emit either the reg,imm or reg,reg form of a data-processing insn. @@ -978,17 +980,19 @@ static void tcg_out_smull32(TCGContext *s, ARMCond co= nd, TCGReg rd0, (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); } =20 -static void tcg_out_sdiv(TCGContext *s, ARMCond cond, int rd, int rn, int = rm) +static void tcg_out_sdiv(TCGContext *s, ARMCond cond, + TCGReg rd, TCGReg rn, TCGReg rm) { tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); } =20 -static void tcg_out_udiv(TCGContext *s, ARMCond cond, int rd, int rn, int = rm) +static void tcg_out_udiv(TCGContext *s, ARMCond cond, + TCGReg rd, TCGReg rn, TCGReg rm) { tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); } =20 -static void tcg_out_ext8s(TCGContext *s, ARMCond cond, int rd, int rn) +static void tcg_out_ext8s(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg r= n) { if (use_armv6_instructions) { /* sxtb */ @@ -1002,12 +1006,12 @@ static void tcg_out_ext8s(TCGContext *s, ARMCond co= nd, int rd, int rn) } =20 static void __attribute__((unused)) -tcg_out_ext8u(TCGContext *s, ARMCond cond, int rd, int rn) +tcg_out_ext8u(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) { tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); } =20 -static void tcg_out_ext16s(TCGContext *s, ARMCond cond, int rd, int rn) +static void tcg_out_ext16s(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg = rn) { if (use_armv6_instructions) { /* sxth */ @@ -1020,7 +1024,7 @@ static void tcg_out_ext16s(TCGContext *s, ARMCond con= d, int rd, int rn) } } =20 -static void tcg_out_ext16u(TCGContext *s, ARMCond cond, int rd, int rn) +static void tcg_out_ext16u(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg = rn) { if (use_armv6_instructions) { /* uxth */ @@ -1033,7 +1037,8 @@ static void tcg_out_ext16u(TCGContext *s, ARMCond con= d, int rd, int rn) } } =20 -static void tcg_out_bswap16(TCGContext *s, ARMCond cond, int rd, int rn, i= nt flags) +static void tcg_out_bswap16(TCGContext *s, ARMCond cond, + TCGReg rd, TCGReg rn, int flags) { if (use_armv6_instructions) { if (flags & TCG_BSWAP_OS) { @@ -1100,7 +1105,7 @@ static void tcg_out_bswap16(TCGContext *s, ARMCond co= nd, int rd, int rn, int fla ? SHIFT_IMM_ASR(8) : SHIFT_IMM_LSR(8))); } =20 -static void tcg_out_bswap32(TCGContext *s, ARMCond cond, int rd, int rn) +static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg= rn) { if (use_armv6_instructions) { /* rev */ @@ -1130,23 +1135,23 @@ static void tcg_out_deposit(TCGContext *s, ARMCond = cond, TCGReg rd, } =20 static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, - TCGArg a1, int ofs, int len) + TCGReg rn, int ofs, int len) { /* ubfx */ - tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | a1 + tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn | (ofs << 7) | ((len - 1) << 16)); } =20 static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, - TCGArg a1, int ofs, int len) + TCGReg rn, int ofs, int len) { /* sbfx */ - tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | a1 + tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn | (ofs << 7) | ((len - 1) << 16)); } =20 static void tcg_out_ld32u(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1156,7 +1161,7 @@ static void tcg_out_ld32u(TCGContext *s, ARMCond cond, } =20 static void tcg_out_st32(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1166,7 +1171,7 @@ static void tcg_out_st32(TCGContext *s, ARMCond cond, } =20 static void tcg_out_ld16u(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1176,7 +1181,7 @@ static void tcg_out_ld16u(TCGContext *s, ARMCond cond, } =20 static void tcg_out_ld16s(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1186,7 +1191,7 @@ static void tcg_out_ld16s(TCGContext *s, ARMCond cond, } =20 static void tcg_out_st16(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1196,7 +1201,7 @@ static void tcg_out_st16(TCGContext *s, ARMCond cond, } =20 static void tcg_out_ld8u(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1206,7 +1211,7 @@ static void tcg_out_ld8u(TCGContext *s, ARMCond cond, } =20 static void tcg_out_ld8s(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1216,7 +1221,7 @@ static void tcg_out_ld8s(TCGContext *s, ARMCond cond, } =20 static void tcg_out_st8(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); --=20 2.25.1