From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631549715; cv=none; d=zohomail.com; s=zohoarc; b=Bm6hMHP9LkFeqbWz2YT4kXaujOkrQhh+EVQK004QsgDs1uyA9iMPFyDEjbwavJp1GkhS+7f+iP/wU5RjToCFfj7cu5U6e46dh6awggy6q+5BSOSunyfvbRCnrmwTRju6O22CUSSUlkADtA/2W/7SzTupFdryi2oRP7Id1a99EV0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631549715; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4jqRbJzoQ0IV17bkefMOjWjU3QheqryLgpyvHJ/geYw=; b=HYAuYMYuLygRQdsLUG7y5MFcExYxsmi3rlLymo6vKbSobfVSGaWG1VAwWhR/d0Vy2/RbUkpcQUVoEsXp45L2/Zx8ntjw6HbS+xtoVTMt8tJcLSMIWGFEz02U/0Tj0yJq6fY37zRj3HL3x0E15AB6hcBNqTR8VA8MwTzgmoLzf+E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631549715339354.0691245788513; Mon, 13 Sep 2021 09:15:15 -0700 (PDT) Received: from localhost ([::1]:33082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPoby-0005fd-AJ for importer@patchew.org; Mon, 13 Sep 2021 12:15:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYi-0000g1-6b for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:52 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:46971) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYe-00080q-PT for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:51 -0400 Received: by mail-wr1-x42c.google.com with SMTP id x6so15527637wrv.13 for ; Mon, 13 Sep 2021 09:11:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4jqRbJzoQ0IV17bkefMOjWjU3QheqryLgpyvHJ/geYw=; b=NRqtTG1CAJo/taZuCWNCWtHR+5PlbhnzL5ikpWcLc8PgPstC4Bw9FSEL190tznCWVj twzs0czskOvEsdJiiohXJmOPr8qqWntn8Tq50/wVKomT5nXLduBwSRlB0GgaRRbcthr5 2ttzP5/KD0tQyzrSTv9rwT8ccxhcqFVLRukX4lB2nPIEtuYDDgY2lgoszEG+48rqwBx1 GAsyCbdpOjNicRhpzkV3c5ta8B1NfP9DG6tTVo+kfdklGMSfSyfhD85WuSTqySJJmY0Y kA5buCdeIiPct4CjYID3gkIEBySbZKYLZugX6hOwAaefrxCYwpspiKtgNwIoSQLaXBLu 7tfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4jqRbJzoQ0IV17bkefMOjWjU3QheqryLgpyvHJ/geYw=; b=ZN439qQzzuKl/i56NjrUcxGxx2VEV4Bi/tPkVYtMKQvHnP+qFwjcysne6K/Xvmdjkh g93cO4FN3w4baeRwiO5zCBUsbFmbaJiXczBrVGbibQ4+i0PXORS7lU2GWslVrdaDj7ap E4OKPnGC6/2PUcAT3DmTbabQYBY0wcKtqCfVZ6fJTLrTLg5y+vFU4fxukxmLL6leqYLJ p4ekzGimOvmMnpjQgaB8Y2reJ7z7C/YxJUpGWvcJs3XPdSE4rAqvc9jIqv2J1/qLKHkP 0YesiS0yqlFhdSG/csehdmrOXRWi3GtMAFvRKytab6Id3L3fhpYgxwCV+rQrNmgVh12e hO1g== X-Gm-Message-State: AOAM530l6BpIFOQ2sNBkjc+iunwZcwQgTvbwdWc3vXvGRIqZSXxmznDx y8S+qdE3q05hVk3jRsZ3AJM8b+9fkBp7dw== X-Google-Smtp-Source: ABdhPJxbMQN0IRnG+Uqzhbj2iBB3EqSLhtJ3BbLuDlewWGaHLF8v+ZG9mhApyeYoI8uDBfbMWirgwA== X-Received: by 2002:a5d:4d01:: with SMTP id z1mr12482758wrt.209.1631549507387; Mon, 13 Sep 2021 09:11:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/23] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase Date: Mon, 13 Sep 2021 17:11:22 +0100 Message-Id: <20210913161144.12347-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631549715986100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng As of today, when booting upstream U-Boot for Xilinx Zynq, the UART does not receive anything. Debugging shows that the UART input clock frequency is zero which prevents the UART from receiving anything as per the logic in uart_receive(). From zynq_slcr_reset_exit() comment, it intends to compute output clocks according to ps_clk and registers. zynq_slcr_compute_clocks() is called to accomplish the task, inside which device_is_in_reset() is called to actually make the attempt in vain. Rework reset_hold() and reset_exit() so that in the reset exit phase, the logic can really compute output clocks in reset_exit(). With this change, upstream U-Boot boots properly again with: $ qemu-system-arm -M xilinx-zynq-a9 -m 1G -display none -serial null -seria= l stdio \ -device loader,file=3Du-boot-dtb.bin,addr=3D0x4000000,cpu-num=3D0 Fixes: 38867cb7ec90 ("hw/misc/zynq_slcr: add clock generation for uarts") Signed-off-by: Bin Meng Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20210901124521.30599-2-bmeng.cn@gmail.com Signed-off-by: Peter Maydell --- hw/misc/zynq_slcr.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 5086e6b7ed2..8b702859618 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -269,6 +269,21 @@ static uint64_t zynq_slcr_compute_clock(const uint64_t= periods[], zynq_slcr_compute_clock((plls), (state)->regs[reg], \ reg ## _ ## enable_field ## _SHIFT) =20 +static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t p= s_clk) +{ + uint64_t io_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTR= L]); + uint64_t arm_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_C= TRL]); + uint64_t ddr_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_C= TRL]); + + uint64_t uart_mux[4] =3D {io_pll, io_pll, arm_pll, ddr_pll}; + + /* compute uartX reference clocks */ + clock_set(s->uart0_ref_clk, + ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0)); + clock_set(s->uart1_ref_clk, + ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1)); +} + /** * Compute and set the ouputs clocks periods. * But do not propagate them further. Connected clocks @@ -283,17 +298,7 @@ static void zynq_slcr_compute_clocks(ZynqSLCRState *s) ps_clk =3D 0; } =20 - uint64_t io_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTR= L]); - uint64_t arm_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_C= TRL]); - uint64_t ddr_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_C= TRL]); - - uint64_t uart_mux[4] =3D {io_pll, io_pll, arm_pll, ddr_pll}; - - /* compute uartX reference clocks */ - clock_set(s->uart0_ref_clk, - ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0)); - clock_set(s->uart1_ref_clk, - ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1)); + zynq_slcr_compute_clocks_internal(s, ps_clk); } =20 /** @@ -416,7 +421,7 @@ static void zynq_slcr_reset_hold(Object *obj) ZynqSLCRState *s =3D ZYNQ_SLCR(obj); =20 /* will disable all output clocks */ - zynq_slcr_compute_clocks(s); + zynq_slcr_compute_clocks_internal(s, 0); zynq_slcr_propagate_clocks(s); } =20 @@ -425,7 +430,7 @@ static void zynq_slcr_reset_exit(Object *obj) ZynqSLCRState *s =3D ZYNQ_SLCR(obj); =20 /* will compute output clocks according to ps_clk and registers */ - zynq_slcr_compute_clocks(s); + zynq_slcr_compute_clocks_internal(s, clock_get(s->ps_clk)); zynq_slcr_propagate_clocks(s); } =20 --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631549928; cv=none; d=zohomail.com; s=zohoarc; b=Di7Yv6APzIszXWRDQIzaG5QTW1tpHw3I9IkuPdLAdzHGmxqRCCzUyZ7RAccDgUZBV3h0kq27XsZpnFsFdap4ABDpgWGGO3m/EQokbElspG1V14YOhOITKwirae/jVZKZtzqDv8Y1OHuILCBoJ3k/czDRkMd+chKZKUqIPjD1zSw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631549928; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=J7sx/pfcVZeyLsLv5/mylb1QdFq8uLf4QtPs01EY7aA=; b=MCttWLAtBLeY1JjtceFkDjVJL9fy1mVUzyAowWKrrAH7ZumiRUakBe0pAsihUWoR+PinNlo+Dzos5PeH8DFUTe/2ho9O7akWq6WNNj0jHpoDNIzAJTvZ1xxSgFtt07BIsoEQ4tlpokhjsCW5Npdi60TOSmZUJIla6l8nOctjMM0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16315499285933.959562896373882; Mon, 13 Sep 2021 09:18:48 -0700 (PDT) Received: from localhost ([::1]:39200 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPofP-0001fq-CL for importer@patchew.org; Mon, 13 Sep 2021 12:18:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYi-0000gW-Bk for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:52 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:44647) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYf-00081S-9m for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:52 -0400 Received: by mail-wr1-x429.google.com with SMTP id d6so15533926wrc.11 for ; Mon, 13 Sep 2021 09:11:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=J7sx/pfcVZeyLsLv5/mylb1QdFq8uLf4QtPs01EY7aA=; b=YaYXQFrABiy6zeVWo1y+evDuasE+crRswwRUg8e0PnfQYxzImmbCC+YzG4x9WFnTwG rmuYXhulYa5Syo/bMK7anLsJF2Vjf01AU4p4P3gjXg5Jd4RgoSxjQDNAzGcLR1Oo5VvX zFMIVB521TuqIItRUUPjsShFCEhG4M/KA3S8efqVIK1YObCZfHDu+yu/7i+4+x/DHb8/ 2kNHRVRsN02ardVTbe86XhktbVu04Zt5hi+MqFj349U/7OoWa/8Gu+gGwnfSCPiO5p31 CT7uqEZsgE2d5eRcWYYJ1prbtI9iJ7u1mWGgykyASMD4cwx9xpCgcWU2RxFyfnrTdseM 9W0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J7sx/pfcVZeyLsLv5/mylb1QdFq8uLf4QtPs01EY7aA=; b=FCtQ/q5rB3LnH47uft83baDAU8l4/Ta6Twus9mCfiRNX/7LSKEYmYA6cie6LDzSjsq 9EF69rQI5uEPfEjRskn5zRG7frNC+Vt29gNFcFdR5sryFzSPvw9VRAQ8b0KrPz88+u7p PhkQpr7mj8mO5ZVjHoIxT02aFhu/VRqFxpQLFV86K/BC5L+vLvxPpoE4EknOGPnV2Kih 0Es2HKtFzbXFzqkKctwPIN14VQglupdq2pTxj3ro6yzV0jjVmkNRsRK+QGS7erdNbtZx yz2AmtGaEQaBrxc/zgPf2aHNWTEbLTmJj3SWkEH//o/H13I6RSGoE0dmlwWWnP8i4uuT TrrQ== X-Gm-Message-State: AOAM53248W0Nu/S0AImLe6uT1jOoWhOfEPujOZqT8CZOItVcQrCMdTO7 3rnWAlEIX/aWDdq4ns2Mxuef/QdqUhjSlA== X-Google-Smtp-Source: ABdhPJxN14G0ilRsqKpGLdOOrO/w3esfwUwOylU5wJgvwbb3zPcsemhybXf759RB7IpS9qa9Ispqkg== X-Received: by 2002:adf:ed82:: with SMTP id c2mr5798063wro.203.1631549507970; Mon, 13 Sep 2021 09:11:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/23] hw/char: cadence_uart: Disable transmit when input clock is disabled Date: Mon, 13 Sep 2021 17:11:23 +0100 Message-Id: <20210913161144.12347-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631549930405100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng At present when input clock is disabled, any character transmitted to tx fifo can still show on the serial line, which is wrong. Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support") Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20210901124521.30599-3-bmeng.cn@gmail.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index b4b5e8a3ee0..154be34992b 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -327,6 +327,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GI= OCondition cond, static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf, int size) { + /* ignore characters when unclocked or in reset */ + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + return; + } + if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { return; } --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631550028; cv=none; d=zohomail.com; s=zohoarc; b=TeF9FfF2U7JvnSouO/TZGSd9Hr5tPvpHE2Hr73V/NIpXlMwTsMTj9iwHLBbVr8cM1Po4VHNswRWeXocOVqUqBg8GyCZWNvdAEUSFzF68JXq/+J4hpz/P1+VEO4fOQuzu9dELOKvf2gR4i+nM3J+bcBconYu2DzFrueJyZTOcZLU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631550028; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YmREMpGPfp1G5BBnMvJXaL2XEXTZtFxef2p5lhooP3s=; b=O4kGz6hJA1IuJccnEHZqoWgeYiXNknRUPF06cihELgaREaVRBNR2mha52ZByp04CLYX+jeUPtHuyW/G0HBAIXHFWoDG4g4C5MbDFLjy00zASULIC5NqwvnIbUvmuCbtmy0ql1dWVLmwG7QShbU6rGoPBU4I6bYsrMPmp0GsiVrU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163155002835718.41336869681686; Mon, 13 Sep 2021 09:20:28 -0700 (PDT) Received: from localhost ([::1]:41820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPoh1-0003Ud-2E for importer@patchew.org; Mon, 13 Sep 2021 12:20:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYi-0000gx-GS for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:52 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:42682) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYg-00082Z-9T for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:52 -0400 Received: by mail-wr1-x433.google.com with SMTP id q11so15531797wrr.9 for ; Mon, 13 Sep 2021 09:11:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YmREMpGPfp1G5BBnMvJXaL2XEXTZtFxef2p5lhooP3s=; b=HkW0NiF1qFqllRLMTR+h1F7HNIepj3UKAuqt2fi55jPGEt2QLDzBr8oS8JfJfsVAO1 vYIaWT2hrmd0vm58jQGE9LUr6N1aVZgNUGocUunbhtpPAcDl5PWF3YFPOLgcmp68c1K4 NfLbAWLCQmyKEsiXJ0kg/dwBk7c4v7S0KvTE753PCT7OGLHPC8VK4ru3nSLeYSmGfGy1 bzZr5vwi8bH8ZxwzH4K9M7EQV8TwhC/IKFkHc/lg93QJaZ/3/LQpMp/BZvZ/zf0GwPv4 9s1nPhEK8KWp1UqbRf7fu/TZEkfuCyh8T3gILkqhMWyCL4zhftrBH1Z8ZW2Wdau1oCaU vgOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YmREMpGPfp1G5BBnMvJXaL2XEXTZtFxef2p5lhooP3s=; b=NqcMYOLORgwWZ8mvzUO2PVBNc6pV2ttc2TACOAwIz3LNqVJzGzc+dakSTzIiA1sSVh gxsrhtHegDK2JsRyTYaaN/a618B86CkcFGkJHeem23nC0a5FILn7hunFBJHyQ6OYPUEn W/Wqs8G+m7TupSDZ4hWx9uCJrnAVNOTlFH8cekT56XZ0/nKfAiEfBL6dokyXtSLDlWg5 +f1RG+cg7TBo/87R1CAs5ZHiRc4ZnyJJu5QAbaO5SN3OyMkDzy+VLvPCp1SpXc/u90Iy 3/BciducpJKTc3I+Q0f2qn4oXfTHo2iINNdnbc95a+Kd4ohNg3FJzykoGBiCKOz32HYZ 5ReQ== X-Gm-Message-State: AOAM533siC7Y2TRPev+YQn6XhnaflMeOhOJHXFhROtFcGhTStVkAx4Gw YUiM2tLQ1oq0nmYDK8j6TReh18WRHRlphA== X-Google-Smtp-Source: ABdhPJw5dJc8Q4Z1trl9RZh5sbRwcxupQ7u9XNTkViuRbyTKJwTAy2klrGVCuycVLR9pe21Hip+Tyg== X-Received: by 2002:a5d:404b:: with SMTP id w11mr13595704wrp.437.1631549508893; Mon, 13 Sep 2021 09:11:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/23] hw/char: cadence_uart: Move clock/reset check to uart_can_receive() Date: Mon, 13 Sep 2021 17:11:24 +0100 Message-Id: <20210913161144.12347-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550028829100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Currently the clock/reset check is done in uart_receive(), but we can move the check to uart_can_receive() which is earlier. Signed-off-by: Bin Meng Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20210901124521.30599-4-bmeng.cn@gmail.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 154be34992b..fff8be36191 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -235,8 +235,16 @@ static void uart_parameters_setup(CadenceUARTState *s) static int uart_can_receive(void *opaque) { CadenceUARTState *s =3D opaque; - int ret =3D MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); - uint32_t ch_mode =3D s->r[R_MR] & UART_MR_CHMODE; + int ret; + uint32_t ch_mode; + + /* ignore characters when unclocked or in reset */ + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + return 0; + } + + ret =3D MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); + ch_mode =3D s->r[R_MR] & UART_MR_CHMODE; =20 if (ch_mode =3D=3D NORMAL_MODE || ch_mode =3D=3D ECHO_MODE) { ret =3D MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); @@ -358,11 +366,6 @@ static void uart_receive(void *opaque, const uint8_t *= buf, int size) CadenceUARTState *s =3D opaque; uint32_t ch_mode =3D s->r[R_MR] & UART_MR_CHMODE; =20 - /* ignore characters when unclocked or in reset */ - if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { - return; - } - if (ch_mode =3D=3D NORMAL_MODE || ch_mode =3D=3D ECHO_MODE) { uart_write_rx_fifo(opaque, buf, size); } --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631550208; cv=none; d=zohomail.com; s=zohoarc; b=GMRdr2bPqXYW42PBRm0eyj89H43EqEHlM+SReAe+Qv3BDCYSLXdUXEeOqaif8/XIuiev3OtXRoji+ERZPBx/hc38KFYOdsHJ3Qx6ElKLuonLtThPLJEYyBgvMcLO6j9IyDn/v6pFyxplXM5CJnNLtHyUdlmd7APrKsH412FZYbk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631550208; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7onW0Bfb60JGQhCGTb7ec53pyNPLVFuz/cIRlQftZzg=; b=AwMMxX/1FmjC2983izqW7fpg3C1CprNXyw3s32hoPOMkwH/encTo0U567WrlTLMx1/CrzxIz3FVUWgeaV96IoXzwK/sR9Pnk/qPTyfSXwJ9BauKke3AZn5NhPnBayhTEGVJ6nARGed3sEukKbT4Jp4xhV/prSpmyOrC6iRZApPY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631550208685209.12486269457906; Mon, 13 Sep 2021 09:23:28 -0700 (PDT) Received: from localhost ([::1]:50018 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPojv-0000gQ-IT for importer@patchew.org; Mon, 13 Sep 2021 12:23:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60672) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYi-0000i1-Sq for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:52 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:43778) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYg-000838-Ub for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:52 -0400 Received: by mail-wr1-x42c.google.com with SMTP id b6so15529454wrh.10 for ; Mon, 13 Sep 2021 09:11:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7onW0Bfb60JGQhCGTb7ec53pyNPLVFuz/cIRlQftZzg=; b=bonEPv5UO+lQi3NJIolyLoR854mMy6E27dWrbkH7JZSubaWCVxy/mf5LTE0JQByWR8 eBq385KBbd4jRv3MNa/+Zvg63iVeX9ilmPSZr58XFnhTljGwDVutoK8cmatN5HlHCyvi E6bpULHW+jL6hCDZAOjKkjwBQITc0Ugft9A+snqfzIL3Qunznn9/GQ/OFduhwUVBYZ69 S76QIObCNAEGNiApM+e0kEzh5HeI9rrUU0rKBlOpFG1E6HKdFe/qqW9iL4ZI56+YcfP7 yfb6VsUE0LG0Tv0TgHzAw7TmmXJXGCHF94/iR5XiYFTVy6xNh5spe0SGZWI70bZ+tTI9 ac2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7onW0Bfb60JGQhCGTb7ec53pyNPLVFuz/cIRlQftZzg=; b=zgMmJN5QZyr8pGjK7nYAhRaJLiH3IxrCpe/IyWjaEEFoh2JYSy9Bu6GjCuw51CNHEI Lv3DaYywA8wiCQlwyKKsKmnN7VQ7uxhj3KqOIgsYrRGj+kX8nSVN/I2k5x4PytkzZ8sT o+Vfy/9ED8mxoVbHZRVNiI0sEwJnokais1TqFKoXAsvqtQzzOSur9cBFtvcfj5++YoCB O88XbEZkBsS+aK/JoS7h2xcEMHRxBbZiRSMC4uCP2wYQTBJplv1iEHJjXQXHjJA78Uat /fm2tWU4Fxptr4Sz4oOxtw9WjsAELOprq3ozUnJvvbf+XRIcI+Y/tWc0MFc/5At1ce8T JI8g== X-Gm-Message-State: AOAM533gmoQZyW/imIaQBZZB+aPozq3M6MjrW5fsEMNHZreIGXbjuU22 APWhoHo8UHOy+jWwEq1vFnMzVXTnroyN+g== X-Google-Smtp-Source: ABdhPJxH9Dg6dtR85ZWGAiz1jBljyY2gx+VKMj0ygyFO7vyQbGOF4k6KKmVJ3aLcDZ7uW8MVAnzVHw== X-Received: by 2002:a5d:4a46:: with SMTP id v6mr3042864wrs.262.1631549509515; Mon, 13 Sep 2021 09:11:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/23] hw/char: cadence_uart: Convert to memop_with_attrs() ops Date: Mon, 13 Sep 2021 17:11:25 +0100 Message-Id: <20210913161144.12347-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550210824100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng This converts uart_read() and uart_write() to memop_with_attrs() ops. Signed-off-by: Bin Meng Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20210901124521.30599-5-bmeng.cn@gmail.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index fff8be36191..8bcf2b718a0 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -411,15 +411,15 @@ static void uart_read_rx_fifo(CadenceUARTState *s, ui= nt32_t *c) uart_update_status(s); } =20 -static void uart_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) +static MemTxResult uart_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size, MemTxAttrs at= trs) { CadenceUARTState *s =3D opaque; =20 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); offset >>=3D 2; if (offset >=3D CADENCE_UART_R_MAX) { - return; + return MEMTX_DECODE_ERROR; } switch (offset) { case R_IER: /* ier (wts imr) */ @@ -466,30 +466,34 @@ static void uart_write(void *opaque, hwaddr offset, break; } uart_update_status(s); + + return MEMTX_OK; } =20 -static uint64_t uart_read(void *opaque, hwaddr offset, - unsigned size) +static MemTxResult uart_read(void *opaque, hwaddr offset, + uint64_t *value, unsigned size, MemTxAttrs at= trs) { CadenceUARTState *s =3D opaque; uint32_t c =3D 0; =20 offset >>=3D 2; if (offset >=3D CADENCE_UART_R_MAX) { - c =3D 0; - } else if (offset =3D=3D R_TX_RX) { + return MEMTX_DECODE_ERROR; + } + if (offset =3D=3D R_TX_RX) { uart_read_rx_fifo(s, &c); } else { - c =3D s->r[offset]; + c =3D s->r[offset]; } =20 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)= c); - return c; + *value =3D c; + return MEMTX_OK; } =20 static const MemoryRegionOps uart_ops =3D { - .read =3D uart_read, - .write =3D uart_write, + .read_with_attrs =3D uart_read, + .write_with_attrs =3D uart_write, .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631549766; cv=none; d=zohomail.com; s=zohoarc; b=OHHk/gTlt3RljHszf/lWMSJH1Q75H20o27xUyBJWCg0usPhLc6zp4Rir87E1Bal11+4FE0AZNNKwRuUvy4Rx9wHR9VLu8USkPRs6uQ4pqti7aApXDtB3a2rwqtSyaKI9i3pYa58BcgXNYxlaY3wSLQMn0KJREErW7pBdzvIZ538= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631549766; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KUKdUJ0N5EPE3TGaxGcZDbPbShFxk6EWZr/urNOByoM=; b=gZAp7reM3mLrhCpt8fHSZhQ1fYm9H9bIVMbYiwY3fFLJEa/cYObpH+BQB2nSWBJJdaDXFcXSaX9GDaOH8fpS2sBI84Q15it0qarcWtPnSvGnC1THhvWz3lxQiOhqLxXZr8V8WAS+VLm4PYqkDWBKbd1PLu4/n6MWUq/8cUxwdIY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631549766822886.6439683468242; Mon, 13 Sep 2021 09:16:06 -0700 (PDT) Received: from localhost ([::1]:34938 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPocn-0006y6-OS for importer@patchew.org; Mon, 13 Sep 2021 12:16:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60694) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYj-0000kb-Ix for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:53 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:43775) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYh-00083q-G7 for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:53 -0400 Received: by mail-wm1-x336.google.com with SMTP id n7-20020a05600c3b8700b002f8ca941d89so361477wms.2 for ; Mon, 13 Sep 2021 09:11:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KUKdUJ0N5EPE3TGaxGcZDbPbShFxk6EWZr/urNOByoM=; b=rCA9PptDsj6wyPSij58a7/BOf0N5EmfJ9ttee7xMrTrPLMJ4YZiOZ1JNR3WzTqzwq8 8lJDVKOS2CFtCHT8DL7xzbWQ6OiYlUqo0q14qndy9ANHo8TEJRHls2CKMcmUMILlHzCY 3cnmHATePWxnk6TpJqzSftFlZH8m0Ru/FgE2wW5D9ScJTpv8ZOnpoZ4tH2yI5u+2/yh+ +b9avvt5LzrIF/sEYRYabLfxfAmZ8o8v7+mDlvR0aYox8IEcyQfiyBTvxXYtvJpgaIhE 2Nx2fpus8OXDUHdfuEA4OiVMSW09IRSXLhVgD1CbsWVqdHDocnAfJ+JHIClan5eHQnO0 DViQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KUKdUJ0N5EPE3TGaxGcZDbPbShFxk6EWZr/urNOByoM=; b=O8ptEIrAh3U5TFaV2KAf83rTrGL7qVIl93xpkVKqJWqZazcNbQt4HEWLRwSnwP1Nla ociV7VVjttSupd7GYivdK19Xwi9NWkhqOAcr7weR1PcioFpIZ2oI4qUD3GAlsYH4Lqin kKVipn/TEKoVUefr9x/txYMAsFMej9WswV16gJM+pxFAntBVWVsiK+aeXZb8+apucYVc Uc+0PA2/DeDzEzo+xHsq+MrjFWgFwI4ZsmI5Y/bBtwnMUZTHl7v3nZMIKfsmQ1tLqAZl f0hQtWWeFnwi+/3WmA43R4tmoxbqDKkTNrAymFnPFjpvmTBIcjr57SlM9wgiYRuaDfyJ pbRQ== X-Gm-Message-State: AOAM532nJYA6itGHcoCzrwj+kyoQ1Jc5kfxJBb5Tyirvq7rt0tzrpJZJ 6FZRQcmFUWao2qfwE2Qzo0vuPggGtYexDg== X-Google-Smtp-Source: ABdhPJx5JxNeZwpqvG95qHyhKRcyeQ4MY3L6771Q0WH8co1/S5uJJuiXnRcgqF0uJtAaI7IBThb+7Q== X-Received: by 2002:a1c:2943:: with SMTP id p64mr11949971wmp.107.1631549510154; Mon, 13 Sep 2021 09:11:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/23] hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() Date: Mon, 13 Sep 2021 17:11:26 +0100 Message-Id: <20210913161144.12347-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631549768751100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Read or write to uart registers when unclocked or in reset should be ignored. Add the check there, and as a result of this, the check in uart_write_tx_fifo() is now unnecessary. Signed-off-by: Bin Meng Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20210901124521.30599-6-bmeng.cn@gmail.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 8bcf2b718a0..5f5a4645ac0 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -335,11 +335,6 @@ static gboolean cadence_uart_xmit(void *do_not_use, GI= OCondition cond, static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf, int size) { - /* ignore characters when unclocked or in reset */ - if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { - return; - } - if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { return; } @@ -416,6 +411,11 @@ static MemTxResult uart_write(void *opaque, hwaddr off= set, { CadenceUARTState *s =3D opaque; =20 + /* ignore access when unclocked or in reset */ + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + return MEMTX_ERROR; + } + DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); offset >>=3D 2; if (offset >=3D CADENCE_UART_R_MAX) { @@ -476,6 +476,11 @@ static MemTxResult uart_read(void *opaque, hwaddr offs= et, CadenceUARTState *s =3D opaque; uint32_t c =3D 0; =20 + /* ignore access when unclocked or in reset */ + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + return MEMTX_ERROR; + } + offset >>=3D 2; if (offset >=3D CADENCE_UART_R_MAX) { return MEMTX_DECODE_ERROR; --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631550147; cv=none; d=zohomail.com; s=zohoarc; b=kZRWvXW3Tsvq8fvMUy+88TiOeMw4evBLZBQrhAvNSAwdfM1wpQ236kbKf/EpoMBZkB1G5uZlIhz9qmJ08/DTUAChKCsjR9CfUeiajESLk6e/DwqNLT/z6mhxOnNp/Qr1H3aF5wggbkW4MTyw4peQSedlhanMKEteZiWwDZFO8SI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631550147; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8Qm2M6BsrBGMW4YGB9hfcLdqesFtIB+T41YhjY71TkM=; b=KeIjl2WeL/utmhJPBKti2u2yant4RKh+87SSeqZ7M/Vu1k7HzuayyMP8ZPci55hrA44MY6/81qf5TKONFjKnFtUbyfvobgpB/jwYky4li+wr/QcZ4p46c+P70uJ8rVPnI5iOXLxK2yTEBvmMVhernVbjHCTuPv+HDraGxGUkMRg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631550147505572.3813007294749; Mon, 13 Sep 2021 09:22:27 -0700 (PDT) Received: from localhost ([::1]:47678 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPoiw-0007YV-Dw for importer@patchew.org; Mon, 13 Sep 2021 12:22:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYj-0000l5-SO for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:53 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:41962) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYi-00084d-5m for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:53 -0400 Received: by mail-wr1-x42a.google.com with SMTP id w29so14783089wra.8 for ; Mon, 13 Sep 2021 09:11:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8Qm2M6BsrBGMW4YGB9hfcLdqesFtIB+T41YhjY71TkM=; b=CUR3D0GGzatDLAWTLVswUS7Q7Gy7SYfAeyCdSLwYUNFaR0fggQOv/jlO9FI+gzoZ38 w6h3qRdoAXM540eSLqqMB03g/qUwh/+jyYelHWozkt02DgWRjHxqIq7U8wKNQZn+huXb +ckaNQneUNWxjV/vSPNxJrarBqKxW0dk9uLBm9e7nGReAPIMT2xKSXFzi/1hSgJ3uONm xw3HYa8v0UYHaYlWSzyaD50PJvncP86OXvqKFR4N2kqFI7Qz41UUauJzsF3uEe2rs/Us c8K4zRLLTn//Nf1CISd1K35UW/SDJDOxCeyJbQ2ksNL3wiE0OsZXAnL/2WPVMdV8Efzh 5YHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8Qm2M6BsrBGMW4YGB9hfcLdqesFtIB+T41YhjY71TkM=; b=0sAY2sg1Twy29DKc0r9K5MA4XV/WcpgV9TIRyFVcgjZfzsO0XdZLhAJA92GPspeRrp YRFM2knArJAvI3PfnRcI/qRDqUMFdVlGxOzpHvWXZHGsTDEGqYJl0jqB3wcbTvByTyMP HBtajPzDNIN4WjxD19I3RAQ4AhUVCyQ4wMn8L0pLa0gqZiVr1OnLqHk5INaZiXSW4o+R e7Gou5+rSQuQhPSG6VbiHMMu9sXl5tzC9Bl2wp1aTnUtvSF7dLQaBTYC5+OA1WyYpmp8 zQbETmvJrg8btwVrtbCGAxYPW1v8lUoKfQiHN2vEswLswXzn1otGEWfh3kvAt6YrK1nm fELQ== X-Gm-Message-State: AOAM532eiRI3SVdPIn22U9PmSXeV6paZNbnI+SxIF5oSpDXJlf357pxX F2K8giAj3B54LRrLG8CNG5pBRCu6LA//Pw== X-Google-Smtp-Source: ABdhPJw0sjiNK7Z/Lr4sZ3//UJt5urOvceQNVHXD8Z0FQOQ7ChpP3dgmYV4HxJw+dtK37EJ1yvWH7g== X-Received: by 2002:adf:ce85:: with SMTP id r5mr13560399wrn.323.1631549510737; Mon, 13 Sep 2021 09:11:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/23] hw/char: cadence_uart: Log a guest error when device is unclocked or in reset Date: Mon, 13 Sep 2021 17:11:27 +0100 Message-Id: <20210913161144.12347-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550149034100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng We've got SW that expects FSBL (Bootlooader) to setup clocks and resets. It's quite common that users run that SW on QEMU without FSBL (FSBL typically requires the Xilinx tools installed). That's fine, since users can stil use -device loader to enable clocks etc. To help folks understand what's going, a log (guest-error) message would be helpful here. In particular with the serial port since things will go very quiet if they get things wrong. Suggested-by: Edgar E. Iglesias Signed-off-by: Bin Meng Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20210901124521.30599-7-bmeng.cn@gmail.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 5f5a4645ac0..c069a30842e 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -240,6 +240,8 @@ static int uart_can_receive(void *opaque) =20 /* ignore characters when unclocked or in reset */ if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: uart is unclocked or in reset\= n", + __func__); return 0; } =20 @@ -376,6 +378,8 @@ static void uart_event(void *opaque, QEMUChrEvent event) =20 /* ignore characters when unclocked or in reset */ if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: uart is unclocked or in reset\= n", + __func__); return; } =20 @@ -413,6 +417,8 @@ static MemTxResult uart_write(void *opaque, hwaddr offs= et, =20 /* ignore access when unclocked or in reset */ if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: uart is unclocked or in reset\= n", + __func__); return MEMTX_ERROR; } =20 @@ -478,6 +484,8 @@ static MemTxResult uart_read(void *opaque, hwaddr offse= t, =20 /* ignore access when unclocked or in reset */ if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: uart is unclocked or in reset\= n", + __func__); return MEMTX_ERROR; } =20 --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631549675; cv=none; d=zohomail.com; s=zohoarc; b=ZFnfVAI9Zlm+M9O3kJfmPP27DwLuZNaW4pxa6Qgom0AupqqUR/zxvJKbBke0UQXJ3pp5hMnZH8jUS+uOIie4+MRkB3IVeG3+kn6YfKS9hGC5i99jiZ9yUTt8D1aCa1WCeAKPDwfWbiTlXy8Rg2WO6LG9PVqnRXfF1sxd9hHN16o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631549675; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yR6/d1fmgWVmWz0dJq82TlR2uLKkG1hd+bNE4R+MmmQ=; b=MMAqYtM6Qxtkh9K+gsiVWiilRG4WRaFH/VQ4AkfC0TnjXgl7gWRPtDWFAfFmSHbakMOgm3rqrmJVyO3mGZ+RojwgFpsH13d7YVxVq93TT4Gmgbawa+ihNCK75c5lGhCFMlPI6bbkBme736QzeMDksFuOoS/OM6qcz9cEmvcHebE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631549675810371.8027651275221; Mon, 13 Sep 2021 09:14:35 -0700 (PDT) Received: from localhost ([::1]:59984 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPobK-0004e2-N4 for importer@patchew.org; Mon, 13 Sep 2021 12:14:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60722) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYl-0000oU-JN for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:55 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:36787) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYi-00085W-Ru for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:54 -0400 Received: by mail-wm1-x331.google.com with SMTP id l18-20020a05600c4f1200b002f8cf606262so7432931wmq.1 for ; Mon, 13 Sep 2021 09:11:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=yR6/d1fmgWVmWz0dJq82TlR2uLKkG1hd+bNE4R+MmmQ=; b=oI5PrN3uWUJVlANxGXDWpTr4352CauISQNkMA2HHMzr/FlV3ggnTHmvNrmKu59zNfp VYv6NpV2S5QQgDDcRhdEGiaRXCkqbTCLvMMIBaD7LcyYnP8Z93URUayEv7DyP44SsKO1 3gZjAp8DU9FkF6U1mEfvHbTXAIhmn6I/uvaLR6JkOm4vFfukN5+PTvKkl/+6svX80ckz sCro+Gnfq9JfPf0F+O/I8PQbqEPZim4eRJmYeTsZBWnlHssT0wXXih0IkKw1giUShLWx vxw5W/SgbRGCZXaWx3I/9UGj9ZzORADt4Cp2qNXe29EjqWXLu6vw7+GvwrW3Zl2a65LA 4LYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yR6/d1fmgWVmWz0dJq82TlR2uLKkG1hd+bNE4R+MmmQ=; b=7apYANrNSSmec+LmbDM8ZZ3iZM58bA5cUyHh5ebhgNyQEwLAhj1Tw5JCyhSAUxZAKg sxcJUUTgHGaxJvCyL2H7ib4penUd6+KMlijQ6EqAhIToCHuSGfH3wGkwAwXQAtxho1Wo YgbCU1uuBa6N1cwxstKj0uSavSwg/hbHlTNTA4ozypuwZ4CZ4EhcRhQ3ES2VOjHVoUM1 4cmy1MOVGZv7vlUN4HkpMVg8CJoWGSUeO4m3aEVtHzzr1mpJ29TKVLWISE8r3PZVmz8L pdw3RmupABRnwVtBvDtEjAs8Bfpnzlr0/dU88k9kCBmEIG1gQ8KKS3oy+sKGO8K3i/Io SJ3w== X-Gm-Message-State: AOAM531X+bm5i9fIibslrEt2AvbBTNn1KactqmNYAQjCK9kUb/jN1p/X 2MoCslfayUjuZLhSLrWf7AjLbk9Sm5Y7Bg== X-Google-Smtp-Source: ABdhPJz46CLbd8cNYejElKD6wQwNukeOWYiY2Lg9ddU6Q6voZNaYXffTBrFmraUbhM8pOuRGZ7+djg== X-Received: by 2002:a7b:c405:: with SMTP id k5mr10822954wmi.24.1631549511444; Mon, 13 Sep 2021 09:11:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/23] hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM Date: Mon, 13 Sep 2021 17:11:28 +0100 Message-Id: <20210913161144.12347-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631549677146100003 Content-Type: text/plain; charset="utf-8" From: Marc Zyngier Although we probe for the IPA limits imposed by KVM (and the hardware) when computing the memory map, we still use the old style '0' when creating a scratch VM in kvm_arm_create_scratch_host_vcpu(). On systems that are severely IPA challenged (such as the Apple M1), this results in a failure as KVM cannot use the default 40bit that '0' represents. Instead, probe for the extension and use the reported IPA limit if available. Cc: Andrew Jones Cc: Eric Auger Cc: Peter Maydell Signed-off-by: Marc Zyngier Reviewed-by: Andrew Jones Message-id: 20210822144441.1290891-2-maz@kernel.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5d55de1a493..94b970bbf9b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -70,12 +70,17 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *c= pus_to_try, struct kvm_vcpu_init *init) { int ret =3D 0, kvmfd =3D -1, vmfd =3D -1, cpufd =3D -1; + int max_vm_pa_size; =20 kvmfd =3D qemu_open_old("/dev/kvm", O_RDWR); if (kvmfd < 0) { goto err; } - vmfd =3D ioctl(kvmfd, KVM_CREATE_VM, 0); + max_vm_pa_size =3D ioctl(kvmfd, KVM_CHECK_EXTENSION, KVM_CAP_ARM_VM_IP= A_SIZE); + if (max_vm_pa_size < 0) { + max_vm_pa_size =3D 0; + } + vmfd =3D ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size); if (vmfd < 0) { goto err; } --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631550372; cv=none; d=zohomail.com; s=zohoarc; b=huxzEM2lxGYsu+npf9j60nRvdPqKrBr4GNcHW76FK9zUdlZOqXwF1BrNdHRTNNSRT1uSIGpqwQA2CWUOGRdq4MouDZ3/1QeXFDCITjJWZguGgsbBYx0WxHQo12omRvvqRXejz78IJ39fpeHJGArSTsbowdr1Lxaq4mNF0HrXDa4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631550372; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=W1m+efY/6GMnWBMpz/5KqQHrR+9ltxKm9JEf0bLzWQw=; b=fQMDriO+xwGyX+bsgi3MZu2GKUMQvEOr5zgMGQ6dUbaZ9p/qMP0LXdWK7KxTTxnZ5TDheCNliWSq85UPW5zQfXT6I05wVoDUUQ3Jwj6DXwtPHskriFjq2ZZameyECJ/28fCR2o4PBnt5jTopXeehS2tq9ygOhCwdnuajAF08YVQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631550372613109.78737851390099; Mon, 13 Sep 2021 09:26:12 -0700 (PDT) Received: from localhost ([::1]:58694 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPomZ-0006UL-Ez for importer@patchew.org; Mon, 13 Sep 2021 12:26:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60732) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYm-0000qa-5w for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:56 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:46078) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYj-000866-B2 for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:55 -0400 Received: by mail-wr1-x436.google.com with SMTP id d21so7850662wra.12 for ; Mon, 13 Sep 2021 09:11:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=W1m+efY/6GMnWBMpz/5KqQHrR+9ltxKm9JEf0bLzWQw=; b=u89gkGbgKzotz3NkexmuJAuazz386yB5aD0/trTLs4tKJnrVFO8DkDDtugAk3p6Ast WYCz+rlEbssLvt0dLbNA8IS0FcQbUvY6t7PJEdtFkLPZK5fWYeYjRBP5ZCQLOiELjBDT D1KNg6dQO6Mr0nR9meRhcWlcTnS1mzdOI9pjtPJRWyyNFFkSNPlRuJwAVmFmTfotm9WR tytUKCwTz31UMsYfwZGt+rZXGW6Y+OAbTLB4bgyJ00gh2zTAtmuB0pUIJGrVNhwWdSWK tNIyGceKl/QAO4zb9SGEorvEsERy8pUMWcFpgNhGbYrtKEqnzqdsuXaiYsjRDStJ11Ro PZ2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W1m+efY/6GMnWBMpz/5KqQHrR+9ltxKm9JEf0bLzWQw=; b=5lYuoSnlb94L0yh6qhJdp6ZMnjxNS/5fspKgSYe3FJ56um6Hqun2rqZoZtOmIpaiiI nZcqxNpyrySmVCDiBf5QctCcKh1lZl4BD7+3r/BPeu2vqHmJPaK1vmeqE/uKxWG49GKr 8bR941p5A2MyfmV50/vj+Hkw5qOWZq7BlXdv0c48OAS+OivrrYS9dpXnSVoVxbJgF8oP Utt+VM+/lWBVA6xJnJ+s6mTynufk6XKqPi9QhJk5O+g+UgWrnye5AUCnQxHOgxT4p+Om 6t1C0f+eWV3v2iEVtUCQ7Kro41RpaQ1wnmXx5u7fxH05whC9OBPjyGIVtfaldrgRRoXT vsWg== X-Gm-Message-State: AOAM531tgbR/UagZ3p+Vm4k98mQVUwbZqSaNhKMyenh4cjQg+HhB2bEJ S10iqjm7x7A4JBPdyL1gyofVn8r/G5UbBQ== X-Google-Smtp-Source: ABdhPJzUDCsxWvw46LynKK1ZjXXJEUXrm+hcL7gPENMA5QwxzMk328RkpmkzhWAp5C4WgCW7nKzWnw== X-Received: by 2002:adf:e643:: with SMTP id b3mr13837198wrn.67.1631549512041; Mon, 13 Sep 2021 09:11:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/23] hw/arm: Add support for kudo-bmc board. Date: Mon, 13 Sep 2021 17:11:29 +0100 Message-Id: <20210913161144.12347-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550373915100003 Content-Type: text/plain; charset="utf-8" From: Chris Rauer kudo-bmc is a board supported by OpenBMC. https://github.com/openbmc/openbmc/tree/master/meta-fii/meta-kudo Since v1: - hyphenated Cortex-A9 Tested: Booted kudo firmware. Signed-off-by: Chris Rauer Reviewed-by: Patrick Venture Message-id: 20210907223234.1165705-1-crauer@google.com Signed-off-by: Peter Maydell --- docs/system/arm/nuvoton.rst | 1 + hw/arm/npcm7xx_boards.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index 69f57c2886f..adf497e6791 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -20,6 +20,7 @@ Hyperscale applications. The following machines are based= on this chip : =20 - ``quanta-gbs-bmc`` Quanta GBS server BMC - ``quanta-gsj`` Quanta GSJ server BMC +- ``kudo-bmc`` Fii USA Kudo server BMC =20 There are also two more SoCs, NPCM710 and NPCM705, which are single-core variants of NPCM750 and NPCM730, respectively. These are currently not diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index e5a32439954..a656169f61e 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -31,6 +31,7 @@ #define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 #define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff #define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff +#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff =20 static const char npcm7xx_default_bootrom[] =3D "npcm7xx_bootrom.bin"; =20 @@ -357,6 +358,23 @@ static void quanta_gbs_init(MachineState *machine) npcm7xx_load_kernel(machine, soc); } =20 +static void kudo_bmc_init(MachineState *machine) +{ + NPCM7xxState *soc; + + soc =3D npcm7xx_create_soc(machine, KUDO_BMC_POWER_ON_STRAPS); + npcm7xx_connect_dram(soc, machine->ram); + qdev_realize(DEVICE(soc), NULL, &error_fatal); + + npcm7xx_load_bootrom(machine, soc); + npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f", + drive_get(IF_MTD, 0, 0)); + npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f", + drive_get(IF_MTD, 3, 0)); + + npcm7xx_load_kernel(machine, soc); +} + static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *typ= e) { NPCM7xxClass *sc =3D NPCM7XX_CLASS(object_class_by_name(type)); @@ -417,6 +435,18 @@ static void gbs_bmc_machine_class_init(ObjectClass *oc= , void *data) mc->default_ram_size =3D 1 * GiB; } =20 +static void kudo_bmc_machine_class_init(ObjectClass *oc, void *data) +{ + NPCM7xxMachineClass *nmc =3D NPCM7XX_MACHINE_CLASS(oc); + MachineClass *mc =3D MACHINE_CLASS(oc); + + npcm7xx_set_soc_type(nmc, TYPE_NPCM730); + + mc->desc =3D "Kudo BMC (Cortex-A9)"; + mc->init =3D kudo_bmc_init; + mc->default_ram_size =3D 1 * GiB; +}; + static const TypeInfo npcm7xx_machine_types[] =3D { { .name =3D TYPE_NPCM7XX_MACHINE, @@ -437,6 +467,10 @@ static const TypeInfo npcm7xx_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("quanta-gbs-bmc"), .parent =3D TYPE_NPCM7XX_MACHINE, .class_init =3D gbs_bmc_machine_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("kudo-bmc"), + .parent =3D TYPE_NPCM7XX_MACHINE, + .class_init =3D kudo_bmc_machine_class_init, }, }; =20 --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631550095; cv=none; d=zohomail.com; s=zohoarc; b=Rm+Hu+aTRB6gb7XAqRxetPlxTL7vDNBfMco4jtOmtt+1u/9wBaurY+nBSFtF5YZAfvhKmMbGRXVNgEff9OIeIEyQNwSZ4q4WxQNKq/KirGA6FURD1VOppC8NJbTkqfYWkCes7gbMD1lbf0wq32piAOjNSzxHIZKYcGqBNlPQl7g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631550095; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=y3z6gDR9t+IjPFmqO3ziA38lEGKhcQKQuIXfcFZjAgg=; b=T2fAya6nRUHJdn3KfpsaXNC4TA5TyKMAkHBJL3gqmQ8P/5yFMILq8zTlrtauIUbgRu1oLoxe7UPDf5oQegee7dMKvR5/wUsyqEDrMRcKUbt63NuAhoXli9saPPraSOVIXcCjLljK47bz9pEuVlH/8hnkw89BXpLqPW0a0deszdM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16315500958651010.0782703232231; Mon, 13 Sep 2021 09:21:35 -0700 (PDT) Received: from localhost ([::1]:43484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPoi6-0004he-Fl for importer@patchew.org; Mon, 13 Sep 2021 12:21:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYo-0000v0-19 for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:58 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:41972) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYl-00086r-GL for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:57 -0400 Received: by mail-wr1-x434.google.com with SMTP id w29so14783325wra.8 for ; Mon, 13 Sep 2021 09:11:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=y3z6gDR9t+IjPFmqO3ziA38lEGKhcQKQuIXfcFZjAgg=; b=xhsoNB4Q8VIlx3TJRFSQEhL0sv5qZqzIWirPFhfLdFWvZ2EtCgOObvktmXCWz3ubCX RzSETZxO4Td4mzhJvvsVG3UQOu+yEZ/fNAEX54zBgjZTgLrjouH4nhCBz7ARcA5v3FYY ikg/cDbvjZA1gCFGJ4Pvox1zQTi10jqyl3wvRlaWrLdXMl+9H8UCBiAbHOYoUqbsm4df sw+sZZvPJm45ElAVxJy4YA0gVNKIs/frw59yHxbtX/2u5abWDEzfsJJ9PgImwqvgwTQk f+8OitYlyHNJoj3zAKB6wBhtODoo5MZsYpuX3vTQGosLnk8gIpmOMlKF8mhCVpmaJP+J vzbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y3z6gDR9t+IjPFmqO3ziA38lEGKhcQKQuIXfcFZjAgg=; b=d6GFPk64/1Zb10AaV1Pcg2lQJgE92j2puKuJ/c4asG7JhfW0Cz8gVJX1nqntI8r5jj rXqZ16bzfXB1Cr9pRSoO4j4VBnsk2ZAu8lvCqLO6I9kSJXChX2dh8Wg61FfW+MlkmbYX FDq2QteE43ZSOYwccfAHgI6yKfkZud1apjwGkZunYV3k6MQBwEqjenbHPKaJItX236OY 60YCtmU7YOoXxksIkuBG+eZoEdREsulrlbyKOI32lQi+qlqlHbUENgRW3ztTDSBaFUsy gAmE3EQLX/VEwnT8dDH1tob7wvARlCHT43r2pdGG/0rkTjSbCOnjDdYYyJ1Lh2ROfnxt +qIQ== X-Gm-Message-State: AOAM5323xn6xZ0UKKZNOOm1n8hWL1JgOf3n2dnBeLCP8Qa2jLXNuBcRT Jj5QjLEvDgBiwCkr2EDHlZmOZteDq5bjtw== X-Google-Smtp-Source: ABdhPJz3t7xr/z06RKlyYY26S/V2ak27efl8U5MljnCR+wCBz509wpit2RqapoaP8dqHImIz9P66ng== X-Received: by 2002:a5d:5408:: with SMTP id g8mr13701039wrv.34.1631549512957; Mon, 13 Sep 2021 09:11:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/23] hw/intc: GICv3 ITS initial framework Date: Mon, 13 Sep 2021 17:11:30 +0100 Message-Id: <20210913161144.12347-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550097943100001 Content-Type: text/plain; charset="utf-8" From: Shashi Mallela Added register definitions relevant to ITS,implemented overall ITS device framework with stubs for ITS control and translater regions read/write,extended ITS common to handle mmio init between existing kvm device and newer qemu device. Signed-off-by: Shashi Mallela Reviewed-by: Peter Maydell Reviewed-by: Eric Auger Tested-by: Neil Armstrong Message-id: 20210910143951.92242-2-shashi.mallela@linaro.org Signed-off-by: Peter Maydell --- hw/intc/gicv3_internal.h | 96 +++++++++- include/hw/intc/arm_gicv3_its_common.h | 9 +- hw/intc/arm_gicv3_its.c | 241 +++++++++++++++++++++++++ hw/intc/arm_gicv3_its_common.c | 7 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/meson.build | 1 + 6 files changed, 342 insertions(+), 14 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 05303a55c88..b99bf9db465 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -24,6 +24,7 @@ #ifndef QEMU_ARM_GICV3_INTERNAL_H #define QEMU_ARM_GICV3_INTERNAL_H =20 +#include "hw/registerfields.h" #include "hw/intc/arm_gicv3_common.h" =20 /* Distributor registers, as offsets from the distributor base address */ @@ -67,6 +68,9 @@ #define GICD_CTLR_E1NWF (1U << 7) #define GICD_CTLR_RWP (1U << 31) =20 +/* 16 bits EventId */ +#define GICD_TYPER_IDBITS 0xf + /* * Redistributor frame offsets from RD_base */ @@ -122,17 +126,17 @@ #define GICR_WAKER_ProcessorSleep (1U << 1) #define GICR_WAKER_ChildrenAsleep (1U << 2) =20 -#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK (7ULL << 56) -#define GICR_PROPBASER_ADDR_MASK (0xfffffffffULL << 12) -#define GICR_PROPBASER_SHAREABILITY_MASK (3U << 10) -#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7) -#define GICR_PROPBASER_IDBITS_MASK (0x1f) +FIELD(GICR_PROPBASER, IDBITS, 0, 5) +FIELD(GICR_PROPBASER, INNERCACHE, 7, 3) +FIELD(GICR_PROPBASER, SHAREABILITY, 10, 2) +FIELD(GICR_PROPBASER, PHYADDR, 12, 40) +FIELD(GICR_PROPBASER, OUTERCACHE, 56, 3) =20 -#define GICR_PENDBASER_PTZ (1ULL << 62) -#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK (7ULL << 56) -#define GICR_PENDBASER_ADDR_MASK (0xffffffffULL << 16) -#define GICR_PENDBASER_SHAREABILITY_MASK (3U << 10) -#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7) +FIELD(GICR_PENDBASER, INNERCACHE, 7, 3) +FIELD(GICR_PENDBASER, SHAREABILITY, 10, 2) +FIELD(GICR_PENDBASER, PHYADDR, 16, 36) +FIELD(GICR_PENDBASER, OUTERCACHE, 56, 3) +FIELD(GICR_PENDBASER, PTZ, 62, 1) =20 #define ICC_CTLR_EL1_CBPR (1U << 0) #define ICC_CTLR_EL1_EOIMODE (1U << 1) @@ -239,6 +243,78 @@ #define ICH_VTR_EL2_PREBITS_SHIFT 26 #define ICH_VTR_EL2_PRIBITS_SHIFT 29 =20 +/* ITS Registers */ + +FIELD(GITS_BASER, SIZE, 0, 8) +FIELD(GITS_BASER, PAGESIZE, 8, 2) +FIELD(GITS_BASER, SHAREABILITY, 10, 2) +FIELD(GITS_BASER, PHYADDR, 12, 36) +FIELD(GITS_BASER, PHYADDRL_64K, 16, 32) +FIELD(GITS_BASER, PHYADDRH_64K, 12, 4) +FIELD(GITS_BASER, ENTRYSIZE, 48, 5) +FIELD(GITS_BASER, OUTERCACHE, 53, 3) +FIELD(GITS_BASER, TYPE, 56, 3) +FIELD(GITS_BASER, INNERCACHE, 59, 3) +FIELD(GITS_BASER, INDIRECT, 62, 1) +FIELD(GITS_BASER, VALID, 63, 1) + +FIELD(GITS_CTLR, QUIESCENT, 31, 1) + +FIELD(GITS_TYPER, PHYSICAL, 0, 1) +FIELD(GITS_TYPER, ITT_ENTRY_SIZE, 4, 4) +FIELD(GITS_TYPER, IDBITS, 8, 5) +FIELD(GITS_TYPER, DEVBITS, 13, 5) +FIELD(GITS_TYPER, SEIS, 18, 1) +FIELD(GITS_TYPER, PTA, 19, 1) +FIELD(GITS_TYPER, CIDBITS, 32, 4) +FIELD(GITS_TYPER, CIL, 36, 1) + +#define GITS_BASER_PAGESIZE_4K 0 +#define GITS_BASER_PAGESIZE_16K 1 +#define GITS_BASER_PAGESIZE_64K 2 + +#define GITS_BASER_TYPE_DEVICE 1ULL +#define GITS_BASER_TYPE_COLLECTION 4ULL + +/** + * Default features advertised by this version of ITS + */ +/* Physical LPIs supported */ +#define GITS_TYPE_PHYSICAL (1U << 0) + +/* + * 12 bytes Interrupt translation Table Entry size + * as per Table 5.3 in GICv3 spec + * ITE Lower 8 Bytes + * Bits: | 49 ... 26 | 25 ... 2 | 1 | 0 | + * Values: | 1023 | IntNum | IntType | Valid | + * ITE Higher 4 Bytes + * Bits: | 31 ... 16 | 15 ...0 | + * Values: | vPEID | ICID | + */ +#define ITS_ITT_ENTRY_SIZE 0xC + +/* 16 bits EventId */ +#define ITS_IDBITS GICD_TYPER_IDBITS + +/* 16 bits DeviceId */ +#define ITS_DEVBITS 0xF + +/* 16 bits CollectionId */ +#define ITS_CIDBITS 0xF + +/* + * 8 bytes Device Table Entry size + * Valid =3D 1 bit,ITTAddr =3D 44 bits,Size =3D 5 bits + */ +#define GITS_DTE_SIZE (0x8ULL) + +/* + * 8 bytes Collection Table Entry size + * Valid =3D 1 bit,RDBase =3D 36 bits(considering max RDBASE) + */ +#define GITS_CTE_SIZE (0x8ULL) + /* Special interrupt IDs */ #define INTID_SECURE 1020 #define INTID_NONSECURE 1021 diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_g= icv3_its_common.h index 5a0952b4049..65d1191db17 100644 --- a/include/hw/intc/arm_gicv3_its_common.h +++ b/include/hw/intc/arm_gicv3_its_common.h @@ -25,17 +25,22 @@ #include "hw/intc/arm_gicv3_common.h" #include "qom/object.h" =20 +#define TYPE_ARM_GICV3_ITS "arm-gicv3-its" + #define ITS_CONTROL_SIZE 0x10000 #define ITS_TRANS_SIZE 0x10000 #define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE) =20 #define GITS_CTLR 0x0 #define GITS_IIDR 0x4 +#define GITS_TYPER 0x8 #define GITS_CBASER 0x80 #define GITS_CWRITER 0x88 #define GITS_CREADR 0x90 #define GITS_BASER 0x100 =20 +#define GITS_TRANSLATER 0x0040 + struct GICv3ITSState { SysBusDevice parent_obj; =20 @@ -52,6 +57,7 @@ struct GICv3ITSState { /* Registers */ uint32_t ctlr; uint32_t iidr; + uint64_t typer; uint64_t cbaser; uint64_t cwriter; uint64_t creadr; @@ -62,7 +68,8 @@ struct GICv3ITSState { =20 typedef struct GICv3ITSState GICv3ITSState; =20 -void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops); +void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops, + const MemoryRegionOps *tops); =20 #define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common" typedef struct GICv3ITSCommonClass GICv3ITSCommonClass; diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c new file mode 100644 index 00000000000..83ece7c4c1d --- /dev/null +++ b/hw/intc/arm_gicv3_its.c @@ -0,0 +1,241 @@ +/* + * ITS emulation for a GICv3-based system + * + * Copyright Linaro.org 2021 + * + * Authors: + * Shashi Mallela + * + * This work is licensed under the terms of the GNU GPL, version 2 or (at = your + * option) any later version. See the COPYING file in the top-level direc= tory. + * + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/qdev-properties.h" +#include "hw/intc/arm_gicv3_its_common.h" +#include "gicv3_internal.h" +#include "qom/object.h" +#include "qapi/error.h" + +typedef struct GICv3ITSClass GICv3ITSClass; +/* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */ +DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass, + ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS) + +struct GICv3ITSClass { + GICv3ITSCommonClass parent_class; + void (*parent_reset)(DeviceState *dev); +}; + +static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset, + uint64_t data, unsigned siz= e, + MemTxAttrs attrs) +{ + return MEMTX_OK; +} + +static bool its_writel(GICv3ITSState *s, hwaddr offset, + uint64_t value, MemTxAttrs attrs) +{ + bool result =3D true; + + return result; +} + +static bool its_readl(GICv3ITSState *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) +{ + bool result =3D true; + + return result; +} + +static bool its_writell(GICv3ITSState *s, hwaddr offset, + uint64_t value, MemTxAttrs attrs) +{ + bool result =3D true; + + return result; +} + +static bool its_readll(GICv3ITSState *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) +{ + bool result =3D true; + + return result; +} + +static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *d= ata, + unsigned size, MemTxAttrs attrs) +{ + GICv3ITSState *s =3D (GICv3ITSState *)opaque; + bool result; + + switch (size) { + case 4: + result =3D its_readl(s, offset, data, attrs); + break; + case 8: + result =3D its_readll(s, offset, data, attrs); + break; + default: + result =3D false; + break; + } + + if (!result) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid guest read at offset " TARGET_FMT_plx + "size %u\n", __func__, offset, size); + /* + * The spec requires that reserved registers are RAZ/WI; + * so use false returns from leaf functions as a way to + * trigger the guest-error logging but don't return it to + * the caller, or we'll cause a spurious guest data abort. + */ + *data =3D 0; + } + return MEMTX_OK; +} + +static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t d= ata, + unsigned size, MemTxAttrs attrs) +{ + GICv3ITSState *s =3D (GICv3ITSState *)opaque; + bool result; + + switch (size) { + case 4: + result =3D its_writel(s, offset, data, attrs); + break; + case 8: + result =3D its_writell(s, offset, data, attrs); + break; + default: + result =3D false; + break; + } + + if (!result) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid guest write at offset " TARGET_FMT_plx + "size %u\n", __func__, offset, size); + /* + * The spec requires that reserved registers are RAZ/WI; + * so use false returns from leaf functions as a way to + * trigger the guest-error logging but don't return it to + * the caller, or we'll cause a spurious guest data abort. + */ + } + return MEMTX_OK; +} + +static const MemoryRegionOps gicv3_its_control_ops =3D { + .read_with_attrs =3D gicv3_its_read, + .write_with_attrs =3D gicv3_its_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 8, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static const MemoryRegionOps gicv3_its_translation_ops =3D { + .write_with_attrs =3D gicv3_its_translation_write, + .valid.min_access_size =3D 2, + .valid.max_access_size =3D 4, + .impl.min_access_size =3D 2, + .impl.max_access_size =3D 4, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void gicv3_arm_its_realize(DeviceState *dev, Error **errp) +{ + GICv3ITSState *s =3D ARM_GICV3_ITS_COMMON(dev); + int i; + + for (i =3D 0; i < s->gicv3->num_cpu; i++) { + if (!(s->gicv3->cpu[i].gicr_typer & GICR_TYPER_PLPIS)) { + error_setg(errp, "Physical LPI not supported by CPU %d", i); + return; + } + } + + gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_= ops); + + /* set the ITS default features supported */ + s->typer =3D FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL, + GITS_TYPE_PHYSICAL); + s->typer =3D FIELD_DP64(s->typer, GITS_TYPER, ITT_ENTRY_SIZE, + ITS_ITT_ENTRY_SIZE - 1); + s->typer =3D FIELD_DP64(s->typer, GITS_TYPER, IDBITS, ITS_IDBITS); + s->typer =3D FIELD_DP64(s->typer, GITS_TYPER, DEVBITS, ITS_DEVBITS); + s->typer =3D FIELD_DP64(s->typer, GITS_TYPER, CIL, 1); + s->typer =3D FIELD_DP64(s->typer, GITS_TYPER, CIDBITS, ITS_CIDBITS); +} + +static void gicv3_its_reset(DeviceState *dev) +{ + GICv3ITSState *s =3D ARM_GICV3_ITS_COMMON(dev); + GICv3ITSClass *c =3D ARM_GICV3_ITS_GET_CLASS(s); + + c->parent_reset(dev); + + /* Quiescent bit reset to 1 */ + s->ctlr =3D FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1); + + /* + * setting GITS_BASER0.Type =3D 0b001 (Device) + * GITS_BASER1.Type =3D 0b100 (Collection Table) + * GITS_BASER.Type,where n =3D 3 to 7 are 0b00 (Unimplement= ed) + * GITS_BASER<0,1>.Page_Size =3D 64KB + * and default translation table entry size to 16 bytes + */ + s->baser[0] =3D FIELD_DP64(s->baser[0], GITS_BASER, TYPE, + GITS_BASER_TYPE_DEVICE); + s->baser[0] =3D FIELD_DP64(s->baser[0], GITS_BASER, PAGESIZE, + GITS_BASER_PAGESIZE_64K); + s->baser[0] =3D FIELD_DP64(s->baser[0], GITS_BASER, ENTRYSIZE, + GITS_DTE_SIZE - 1); + + s->baser[1] =3D FIELD_DP64(s->baser[1], GITS_BASER, TYPE, + GITS_BASER_TYPE_COLLECTION); + s->baser[1] =3D FIELD_DP64(s->baser[1], GITS_BASER, PAGESIZE, + GITS_BASER_PAGESIZE_64K); + s->baser[1] =3D FIELD_DP64(s->baser[1], GITS_BASER, ENTRYSIZE, + GITS_CTE_SIZE - 1); +} + +static Property gicv3_its_props[] =3D { + DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-gicv3", + GICv3State *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void gicv3_its_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + GICv3ITSClass *ic =3D ARM_GICV3_ITS_CLASS(klass); + + dc->realize =3D gicv3_arm_its_realize; + device_class_set_props(dc, gicv3_its_props); + device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset); +} + +static const TypeInfo gicv3_its_info =3D { + .name =3D TYPE_ARM_GICV3_ITS, + .parent =3D TYPE_ARM_GICV3_ITS_COMMON, + .instance_size =3D sizeof(GICv3ITSState), + .class_init =3D gicv3_its_class_init, + .class_size =3D sizeof(GICv3ITSClass), +}; + +static void gicv3_its_register_types(void) +{ + type_register_static(&gicv3_its_info); +} + +type_init(gicv3_its_register_types) diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c index 66c4c6a1888..7d7f3882e76 100644 --- a/hw/intc/arm_gicv3_its_common.c +++ b/hw/intc/arm_gicv3_its_common.c @@ -50,6 +50,8 @@ static int gicv3_its_post_load(void *opaque, int version_= id) =20 static const VMStateDescription vmstate_its =3D { .name =3D "arm_gicv3_its", + .version_id =3D 1, + .minimum_version_id =3D 1, .pre_save =3D gicv3_its_pre_save, .post_load =3D gicv3_its_post_load, .priority =3D MIG_PRI_GICV3_ITS, @@ -99,14 +101,15 @@ static const MemoryRegionOps gicv3_its_trans_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops) +void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops, + const MemoryRegionOps *tops) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(s); =20 memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s, "control", ITS_CONTROL_SIZE); memory_region_init_io(&s->iomem_its_translation, OBJECT(s), - &gicv3_its_trans_ops, s, + tops ? tops : &gicv3_its_trans_ops, s, "translation", ITS_TRANS_SIZE); =20 /* Our two regions are always adjacent, therefore we now combine them diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index b554d2ede0a..0b4cbed28b3 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -106,7 +106,7 @@ static void kvm_arm_its_realize(DeviceState *dev, Error= **errp) kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_= ADDR, KVM_VGIC_ITS_ADDR_TYPE, s->dev_fd, 0); =20 - gicv3_its_init_mmio(s, NULL); + gicv3_its_init_mmio(s, NULL, NULL); =20 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, GITS_CTLR)) { diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 6e52a166e38..4dcfea6aa8b 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -8,6 +8,7 @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files( 'arm_gicv3_dist.c', 'arm_gicv3_its_common.c', 'arm_gicv3_redist.c', + 'arm_gicv3_its.c', )) softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c')) softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c= ')) --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xajZ0y4QY6OQ4aBMWPIwcMXOhdqzQ0wfm30OrVEe0Aw=; b=m27zrVC/hPlea3c/bQzmLu+6lwqRbwPpYfKChm2nkQPnhK6gfVf4QsX/yEVjRv793n DN+RIukEVDS7/2zMsLlc0YIJWd10fA84uU/mqrpwbUW0v6l/iPYZEq//nLbnnvmKuxvp ResB6rVcWQgq7LwHJzJrnIfRNY/xzhUAjl3xa4Qtdr20QLJ6RsEjUYnNQ06mbpDogsRG TTotw1V0onYDTzTcZ2RF758k7hZzH6gKizGuIPsLMLojgvmyS+5MTzoshrLNX6Pgy4V+ qVxLxwesJtBsX/8upe+Us9FpAIJ2vwgdPvLq4JxzFszXFi23kWj1q8GQE0TRT/YToxK4 Rqwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xajZ0y4QY6OQ4aBMWPIwcMXOhdqzQ0wfm30OrVEe0Aw=; b=S/k8MjBPPhtJ6fIJZIp92I7DOShVfsVWxvcBxKvoPGowwD+Xe/XkjPr8hJ2ueeD5cY thm52omuamNRgwBJqNz4A4jt5LbEfXvkhL3ZLlhQMjJgwjfQqoHh2cI34oFXaZtQhWBf WUwwwjSRy7U707/VDytdA2Vuz6LMhrZ/BUJjKd24MBRt3IUn4sbUzpuOzVlrQU2o/K5F G9YIKamtyrEu1TvcG3cJpFkre9IpBc1B2qG5XgdRoYj5sogplieIcEFlU79PCj3LxsiW hGE2PpdUOxBK5hCLtps+2d/kpiHr232/0z2dCDtnwkNQKHEfwAkYFr4WaAkvYFWn1QIT uuuQ== X-Gm-Message-State: AOAM530mzhdKYzJzYjWI3PdOB55F8GKsBTWZV+tXFl1wiIXBp7kWbl9K yDk2J9tC/A1TdHvIY+FnUfYXM/EmAl4Haw== X-Google-Smtp-Source: ABdhPJzqdqGb4fRbTKFBeDR3ZHb5lmTMu3QwMLtDIMu1G+x3Ldqio2MbVOdrInUOKNbFUGuEciWLPQ== X-Received: by 2002:adf:fc0e:: with SMTP id i14mr13383960wrr.173.1631549513942; Mon, 13 Sep 2021 09:11:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/23] hw/intc: GICv3 ITS register definitions added Date: Mon, 13 Sep 2021 17:11:31 +0100 Message-Id: <20210913161144.12347-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550749864100001 Content-Type: text/plain; charset="utf-8" From: Shashi Mallela Defined descriptors for ITS device table,collection table and ITS command queue entities.Implemented register read/write functions, extract ITS table parameters and command queue parameters,extended gicv3 common to capture qemu address space(which host the ITS table platform memories required for subsequent ITS processing) and initialize the same in ITS device. Signed-off-by: Shashi Mallela Reviewed-by: Peter Maydell Reviewed-by: Eric Auger Tested-by: Neil Armstrong Message-id: 20210910143951.92242-3-shashi.mallela@linaro.org Signed-off-by: Peter Maydell --- hw/intc/gicv3_internal.h | 29 ++ include/hw/intc/arm_gicv3_common.h | 3 + include/hw/intc/arm_gicv3_its_common.h | 23 ++ hw/intc/arm_gicv3_its.c | 376 +++++++++++++++++++++++++ 4 files changed, 431 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index b99bf9db465..92e0a4fa686 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -258,6 +258,20 @@ FIELD(GITS_BASER, INNERCACHE, 59, 3) FIELD(GITS_BASER, INDIRECT, 62, 1) FIELD(GITS_BASER, VALID, 63, 1) =20 +FIELD(GITS_CBASER, SIZE, 0, 8) +FIELD(GITS_CBASER, SHAREABILITY, 10, 2) +FIELD(GITS_CBASER, PHYADDR, 12, 40) +FIELD(GITS_CBASER, OUTERCACHE, 53, 3) +FIELD(GITS_CBASER, INNERCACHE, 59, 3) +FIELD(GITS_CBASER, VALID, 63, 1) + +FIELD(GITS_CREADR, STALLED, 0, 1) +FIELD(GITS_CREADR, OFFSET, 5, 15) + +FIELD(GITS_CWRITER, RETRY, 0, 1) +FIELD(GITS_CWRITER, OFFSET, 5, 15) + +FIELD(GITS_CTLR, ENABLED, 0, 1) FIELD(GITS_CTLR, QUIESCENT, 31, 1) =20 FIELD(GITS_TYPER, PHYSICAL, 0, 1) @@ -269,6 +283,13 @@ FIELD(GITS_TYPER, PTA, 19, 1) FIELD(GITS_TYPER, CIDBITS, 32, 4) FIELD(GITS_TYPER, CIL, 36, 1) =20 +#define GITS_IDREGS 0xFFD0 + +#define ITS_CTLR_ENABLED (1U) /* ITS Enabled */ + +#define GITS_BASER_RO_MASK (R_GITS_BASER_ENTRYSIZE_MASK |= \ + R_GITS_BASER_TYPE_MASK) + #define GITS_BASER_PAGESIZE_4K 0 #define GITS_BASER_PAGESIZE_16K 1 #define GITS_BASER_PAGESIZE_64K 2 @@ -276,6 +297,14 @@ FIELD(GITS_TYPER, CIL, 36, 1) #define GITS_BASER_TYPE_DEVICE 1ULL #define GITS_BASER_TYPE_COLLECTION 4ULL =20 +#define GITS_PAGE_SIZE_4K 0x1000 +#define GITS_PAGE_SIZE_16K 0x4000 +#define GITS_PAGE_SIZE_64K 0x10000 + +#define L1TABLE_ENTRY_SIZE 8 + +#define GITS_CMDQ_ENTRY_SIZE 32 + /** * Default features advertised by this version of ITS */ diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 91491a2f664..1fd5cedbbdb 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -226,6 +226,9 @@ struct GICv3State { int dev_fd; /* kvm device fd if backed by kvm vgic support */ Error *migration_blocker; =20 + MemoryRegion *dma; + AddressSpace dma_as; + /* Distributor */ =20 /* for a GIC with the security extensions the NS banked version of this diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_g= icv3_its_common.h index 65d1191db17..4e79145dde3 100644 --- a/include/hw/intc/arm_gicv3_its_common.h +++ b/include/hw/intc/arm_gicv3_its_common.h @@ -41,6 +41,25 @@ =20 #define GITS_TRANSLATER 0x0040 =20 +typedef struct { + bool valid; + bool indirect; + uint16_t entry_sz; + uint32_t page_sz; + uint32_t max_entries; + union { + uint32_t max_devids; + uint32_t max_collids; + } maxids; + uint64_t base_addr; +} TableDesc; + +typedef struct { + bool valid; + uint32_t max_entries; + uint64_t base_addr; +} CmdQDesc; + struct GICv3ITSState { SysBusDevice parent_obj; =20 @@ -63,6 +82,10 @@ struct GICv3ITSState { uint64_t creadr; uint64_t baser[8]; =20 + TableDesc dt; + TableDesc ct; + CmdQDesc cq; + Error *migration_blocker; }; =20 diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 83ece7c4c1d..8234939ccc1 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -29,6 +29,160 @@ struct GICv3ITSClass { void (*parent_reset)(DeviceState *dev); }; =20 +static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz) +{ + uint64_t result =3D 0; + + switch (page_sz) { + case GITS_PAGE_SIZE_4K: + case GITS_PAGE_SIZE_16K: + result =3D FIELD_EX64(value, GITS_BASER, PHYADDR) << 12; + break; + + case GITS_PAGE_SIZE_64K: + result =3D FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) << 16; + result |=3D FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) << 48; + break; + + default: + break; + } + return result; +} + +/* + * This function extracts the ITS Device and Collection table specific + * parameters (like base_addr, size etc) from GITS_BASER register. + * It is called during ITS enable and also during post_load migration + */ +static void extract_table_params(GICv3ITSState *s) +{ + uint16_t num_pages =3D 0; + uint8_t page_sz_type; + uint8_t type; + uint32_t page_sz =3D 0; + uint64_t value; + + for (int i =3D 0; i < 8; i++) { + value =3D s->baser[i]; + + if (!value) { + continue; + } + + page_sz_type =3D FIELD_EX64(value, GITS_BASER, PAGESIZE); + + switch (page_sz_type) { + case 0: + page_sz =3D GITS_PAGE_SIZE_4K; + break; + + case 1: + page_sz =3D GITS_PAGE_SIZE_16K; + break; + + case 2: + case 3: + page_sz =3D GITS_PAGE_SIZE_64K; + break; + + default: + g_assert_not_reached(); + } + + num_pages =3D FIELD_EX64(value, GITS_BASER, SIZE) + 1; + + type =3D FIELD_EX64(value, GITS_BASER, TYPE); + + switch (type) { + + case GITS_BASER_TYPE_DEVICE: + memset(&s->dt, 0 , sizeof(s->dt)); + s->dt.valid =3D FIELD_EX64(value, GITS_BASER, VALID); + + if (!s->dt.valid) { + return; + } + + s->dt.page_sz =3D page_sz; + s->dt.indirect =3D FIELD_EX64(value, GITS_BASER, INDIRECT); + s->dt.entry_sz =3D FIELD_EX64(value, GITS_BASER, ENTRYSIZE); + + if (!s->dt.indirect) { + s->dt.max_entries =3D (num_pages * page_sz) / s->dt.entry_= sz; + } else { + s->dt.max_entries =3D (((num_pages * page_sz) / + L1TABLE_ENTRY_SIZE) * + (page_sz / s->dt.entry_sz)); + } + + s->dt.maxids.max_devids =3D (1UL << (FIELD_EX64(s->typer, GITS= _TYPER, + DEVBITS) + 1)); + + s->dt.base_addr =3D baser_base_addr(value, page_sz); + + break; + + case GITS_BASER_TYPE_COLLECTION: + memset(&s->ct, 0 , sizeof(s->ct)); + s->ct.valid =3D FIELD_EX64(value, GITS_BASER, VALID); + + /* + * GITS_TYPER.HCC is 0 for this implementation + * hence writes are discarded if ct.valid is 0 + */ + if (!s->ct.valid) { + return; + } + + s->ct.page_sz =3D page_sz; + s->ct.indirect =3D FIELD_EX64(value, GITS_BASER, INDIRECT); + s->ct.entry_sz =3D FIELD_EX64(value, GITS_BASER, ENTRYSIZE); + + if (!s->ct.indirect) { + s->ct.max_entries =3D (num_pages * page_sz) / s->ct.entry_= sz; + } else { + s->ct.max_entries =3D (((num_pages * page_sz) / + L1TABLE_ENTRY_SIZE) * + (page_sz / s->ct.entry_sz)); + } + + if (FIELD_EX64(s->typer, GITS_TYPER, CIL)) { + s->ct.maxids.max_collids =3D (1UL << (FIELD_EX64(s->typer, + GITS_TYPER, CIDBITS) + 1)); + } else { + /* 16-bit CollectionId supported when CIL =3D=3D 0 */ + s->ct.maxids.max_collids =3D (1UL << 16); + } + + s->ct.base_addr =3D baser_base_addr(value, page_sz); + + break; + + default: + break; + } + } +} + +static void extract_cmdq_params(GICv3ITSState *s) +{ + uint16_t num_pages =3D 0; + uint64_t value =3D s->cbaser; + + num_pages =3D FIELD_EX64(value, GITS_CBASER, SIZE) + 1; + + memset(&s->cq, 0 , sizeof(s->cq)); + s->cq.valid =3D FIELD_EX64(value, GITS_CBASER, VALID); + + if (s->cq.valid) { + s->cq.max_entries =3D (num_pages * GITS_PAGE_SIZE_4K) / + GITS_CMDQ_ENTRY_SIZE; + s->cq.base_addr =3D FIELD_EX64(value, GITS_CBASER, PHYADDR); + s->cq.base_addr <<=3D R_GITS_CBASER_PHYADDR_SHIFT; + } +} + static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset, uint64_t data, unsigned siz= e, MemTxAttrs attrs) @@ -40,7 +194,99 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, uint64_t value, MemTxAttrs attrs) { bool result =3D true; + int index; =20 + switch (offset) { + case GITS_CTLR: + s->ctlr |=3D (value & ~(s->ctlr)); + + if (s->ctlr & ITS_CTLR_ENABLED) { + extract_table_params(s); + extract_cmdq_params(s); + s->creadr =3D 0; + } + break; + case GITS_CBASER: + /* + * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is + * already enabled + */ + if (!(s->ctlr & ITS_CTLR_ENABLED)) { + s->cbaser =3D deposit64(s->cbaser, 0, 32, value); + s->creadr =3D 0; + s->cwriter =3D s->creadr; + } + break; + case GITS_CBASER + 4: + /* + * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is + * already enabled + */ + if (!(s->ctlr & ITS_CTLR_ENABLED)) { + s->cbaser =3D deposit64(s->cbaser, 32, 32, value); + s->creadr =3D 0; + s->cwriter =3D s->creadr; + } + break; + case GITS_CWRITER: + s->cwriter =3D deposit64(s->cwriter, 0, 32, + (value & ~R_GITS_CWRITER_RETRY_MASK)); + break; + case GITS_CWRITER + 4: + s->cwriter =3D deposit64(s->cwriter, 32, 32, value); + break; + case GITS_CREADR: + if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) { + s->creadr =3D deposit64(s->creadr, 0, 32, + (value & ~R_GITS_CREADR_STALLED_MASK)); + } else { + /* RO register, ignore the write */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid guest write to RO register at offse= t " + TARGET_FMT_plx "\n", __func__, offset); + } + break; + case GITS_CREADR + 4: + if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) { + s->creadr =3D deposit64(s->creadr, 32, 32, value); + } else { + /* RO register, ignore the write */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid guest write to RO register at offse= t " + TARGET_FMT_plx "\n", __func__, offset); + } + break; + case GITS_BASER ... GITS_BASER + 0x3f: + /* + * IMPDEF choice:- GITS_BASERn register becomes RO if ITS is + * already enabled + */ + if (!(s->ctlr & ITS_CTLR_ENABLED)) { + index =3D (offset - GITS_BASER) / 8; + + if (offset & 7) { + value <<=3D 32; + value &=3D ~GITS_BASER_RO_MASK; + s->baser[index] &=3D GITS_BASER_RO_MASK | MAKE_64BIT_MASK(= 0, 32); + s->baser[index] |=3D value; + } else { + value &=3D ~GITS_BASER_RO_MASK; + s->baser[index] &=3D GITS_BASER_RO_MASK | MAKE_64BIT_MASK(= 32, 32); + s->baser[index] |=3D value; + } + } + break; + case GITS_IIDR: + case GITS_IDREGS ... GITS_IDREGS + 0x2f: + /* RO registers, ignore the write */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid guest write to RO register at offset " + TARGET_FMT_plx "\n", __func__, offset); + break; + default: + result =3D false; + break; + } return result; } =20 @@ -48,7 +294,55 @@ static bool its_readl(GICv3ITSState *s, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { bool result =3D true; + int index; =20 + switch (offset) { + case GITS_CTLR: + *data =3D s->ctlr; + break; + case GITS_IIDR: + *data =3D gicv3_iidr(); + break; + case GITS_IDREGS ... GITS_IDREGS + 0x2f: + /* ID registers */ + *data =3D gicv3_idreg(offset - GITS_IDREGS); + break; + case GITS_TYPER: + *data =3D extract64(s->typer, 0, 32); + break; + case GITS_TYPER + 4: + *data =3D extract64(s->typer, 32, 32); + break; + case GITS_CBASER: + *data =3D extract64(s->cbaser, 0, 32); + break; + case GITS_CBASER + 4: + *data =3D extract64(s->cbaser, 32, 32); + break; + case GITS_CREADR: + *data =3D extract64(s->creadr, 0, 32); + break; + case GITS_CREADR + 4: + *data =3D extract64(s->creadr, 32, 32); + break; + case GITS_CWRITER: + *data =3D extract64(s->cwriter, 0, 32); + break; + case GITS_CWRITER + 4: + *data =3D extract64(s->cwriter, 32, 32); + break; + case GITS_BASER ... GITS_BASER + 0x3f: + index =3D (offset - GITS_BASER) / 8; + if (offset & 7) { + *data =3D extract64(s->baser[index], 32, 32); + } else { + *data =3D extract64(s->baser[index], 0, 32); + } + break; + default: + result =3D false; + break; + } return result; } =20 @@ -56,7 +350,54 @@ static bool its_writell(GICv3ITSState *s, hwaddr offset, uint64_t value, MemTxAttrs attrs) { bool result =3D true; + int index; =20 + switch (offset) { + case GITS_BASER ... GITS_BASER + 0x3f: + /* + * IMPDEF choice:- GITS_BASERn register becomes RO if ITS is + * already enabled + */ + if (!(s->ctlr & ITS_CTLR_ENABLED)) { + index =3D (offset - GITS_BASER) / 8; + s->baser[index] &=3D GITS_BASER_RO_MASK; + s->baser[index] |=3D (value & ~GITS_BASER_RO_MASK); + } + break; + case GITS_CBASER: + /* + * IMPDEF choice:- GITS_CBASER register becomes RO if ITS is + * already enabled + */ + if (!(s->ctlr & ITS_CTLR_ENABLED)) { + s->cbaser =3D value; + s->creadr =3D 0; + s->cwriter =3D s->creadr; + } + break; + case GITS_CWRITER: + s->cwriter =3D value & ~R_GITS_CWRITER_RETRY_MASK; + break; + case GITS_CREADR: + if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) { + s->creadr =3D value & ~R_GITS_CREADR_STALLED_MASK; + } else { + /* RO register, ignore the write */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid guest write to RO register at offse= t " + TARGET_FMT_plx "\n", __func__, offset); + } + break; + case GITS_TYPER: + /* RO registers, ignore the write */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid guest write to RO register at offset " + TARGET_FMT_plx "\n", __func__, offset); + break; + default: + result =3D false; + break; + } return result; } =20 @@ -64,7 +405,29 @@ static bool its_readll(GICv3ITSState *s, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { bool result =3D true; + int index; =20 + switch (offset) { + case GITS_TYPER: + *data =3D s->typer; + break; + case GITS_BASER ... GITS_BASER + 0x3f: + index =3D (offset - GITS_BASER) / 8; + *data =3D s->baser[index]; + break; + case GITS_CBASER: + *data =3D s->cbaser; + break; + case GITS_CREADR: + *data =3D s->creadr; + break; + case GITS_CWRITER: + *data =3D s->cwriter; + break; + default: + result =3D false; + break; + } return result; } =20 @@ -166,6 +529,9 @@ static void gicv3_arm_its_realize(DeviceState *dev, Err= or **errp) =20 gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_= ops); =20 + address_space_init(&s->gicv3->dma_as, s->gicv3->dma, + "gicv3-its-sysmem"); + /* set the ITS default features supported */ s->typer =3D FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL, GITS_TYPE_PHYSICAL); @@ -209,6 +575,14 @@ static void gicv3_its_reset(DeviceState *dev) GITS_CTE_SIZE - 1); } =20 +static void gicv3_its_post_load(GICv3ITSState *s) +{ + if (s->ctlr & ITS_CTLR_ENABLED) { + extract_table_params(s); + extract_cmdq_params(s); + } +} + static Property gicv3_its_props[] =3D { DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-gicv3", GICv3State *), @@ -219,10 +593,12 @@ static void gicv3_its_class_init(ObjectClass *klass, = void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); GICv3ITSClass *ic =3D ARM_GICV3_ITS_CLASS(klass); + GICv3ITSCommonClass *icc =3D ARM_GICV3_ITS_COMMON_CLASS(klass); =20 dc->realize =3D gicv3_arm_its_realize; device_class_set_props(dc, gicv3_its_props); device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset); + icc->post_load =3D gicv3_its_post_load; } =20 static const TypeInfo gicv3_its_info =3D { --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631550345; cv=none; d=zohomail.com; s=zohoarc; b=DfEkcY1RUrdqrX3VtkX2fA+OWvF1NTjFc8sF4HSuNGhCQqna9SLsZAj0uFTQAJGnF1tX7SbMBrG3rwdOod2br8/6IT+T9Neq6/wss8tUtaX16N0dZgjCUmgITXapzPO7aCJrrAcboOqes3z1C8eTqD4PqYJ0n/QqRkmnoxiaoVU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631550345; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GJlp/P7OhsPJD6qDW238HHIaWRncW9StTyBdqOo0xTo=; b=GMQ00JV4fV/vXZKbogKLzFLX0e4kGX7hGpg40LfbB4lWAqadcnN1MBeA8mrg7BY9rrBJuycJhTaEiTNM96TeTtXYQtasYpXmmBcN9uA2MdhaLn4Q9PE5ofcFxUUf2Pdul9yhG0aJR4U7r1B5m1ZKW3EO8CLbIikeaxeH7C7T9fw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631550345658871.0387011686349; Mon, 13 Sep 2021 09:25:45 -0700 (PDT) Received: from localhost ([::1]:56494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPom8-0004y1-Ha for importer@patchew.org; Mon, 13 Sep 2021 12:25:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60794) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYo-0000x7-J2 for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:58 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:41885) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYm-00089M-Dk for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:11:58 -0400 Received: by mail-wm1-x32d.google.com with SMTP id g19-20020a1c9d13000000b003075062d4daso393713wme.0 for ; Mon, 13 Sep 2021 09:11:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=GJlp/P7OhsPJD6qDW238HHIaWRncW9StTyBdqOo0xTo=; b=VUozuQqmH2HgZvZcxgrTMJkaVEFmhSEUHt7DmSSwQo6UmNZPRnQiw5GAzuAH18+EEP xn6Um9UhhbCPF/lYfQSAWW8jNzRRnXK6P8hN/o1Y7NZLZAcT7qWm0IyO6W9zrhyD+zAW ZMovct5678mCYfhRspJh8390t//87PhAsq/oT99IuKhRrFHklT8EARHLvFhMdnkjnQ4Q BkcBEy8Avn7BSmCjcZZjpnTKmPAdME6N6TBKMffJxY+5uA66tevuhRfhrrEiCF2VfLDc 1XuB3cFk+R+ApBTDlGuUJ6P13OfFaqlefzRWKxotAE2y62tiKwx7vqwRv8ok8lS+X9Ei TAFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GJlp/P7OhsPJD6qDW238HHIaWRncW9StTyBdqOo0xTo=; b=UpKsT94gx8SGlh2NAN9OMZErtGctbAMDK6H4Za7XzZ4PDv/zWtmqrz4dEv8EW05Pd+ TB5VN4UykKCUWfWBFjrjQRWEYLY0NcYbwDrL1z5ZC/rbuvehWO/bP1RqoEdu/SiAK0RW zif6Ra1WKZ3FxpQWjiutLTP4MsCYzO6OlyeOrPzKBkRBgPonSNwxireAQ+nAPTMC2Rvx qR5tx3MFSOM78dDq2JpeTRsXk32bsqsTmxNtNtb2N61ZGxDN3sq2lsXFuCRpRA+CWMlJ pp2tx9dn37zu32sXE+ZuContJBNXYNb3svR9Js/bhxpXCTxtlKiCOvq8/fgbRxmSStCu v6UQ== X-Gm-Message-State: AOAM530FwhpCXWxgHzmCssjlDw/jlNgA+ZNFZrJxVd6JnzrKssRe/KCI qq1OA8VQsfODpzPfJvgcHrk2u8Zl1eqLvQ== X-Google-Smtp-Source: ABdhPJyvzjkyk3cSXDjXN40ZbQZrjYhXr59GohK6/yJ5j33xL7617EyNimIj0JehuyyLdmf5KUSMlw== X-Received: by 2002:a1c:3b41:: with SMTP id i62mr12132743wma.38.1631549515003; Mon, 13 Sep 2021 09:11:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/23] hw/intc: GICv3 ITS command queue framework Date: Mon, 13 Sep 2021 17:11:32 +0100 Message-Id: <20210913161144.12347-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550347140100001 Content-Type: text/plain; charset="utf-8" From: Shashi Mallela Added functionality to trigger ITS command queue processing on write to CWRITE register and process each command queue entry to identify the command type and handle commands like MAPD,MAPC,SYNC. Signed-off-by: Shashi Mallela Reviewed-by: Peter Maydell Reviewed-by: Eric Auger Tested-by: Neil Armstrong Message-id: 20210910143951.92242-4-shashi.mallela@linaro.org Signed-off-by: Peter Maydell --- hw/intc/gicv3_internal.h | 40 +++++ hw/intc/arm_gicv3_its.c | 319 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 359 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 92e0a4fa686..034fadfebeb 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -304,6 +304,43 @@ FIELD(GITS_TYPER, CIL, 36, 1) #define L1TABLE_ENTRY_SIZE 8 =20 #define GITS_CMDQ_ENTRY_SIZE 32 +#define NUM_BYTES_IN_DW 8 + +#define CMD_MASK 0xff + +/* ITS Commands */ +#define GITS_CMD_CLEAR 0x04 +#define GITS_CMD_DISCARD 0x0F +#define GITS_CMD_INT 0x03 +#define GITS_CMD_MAPC 0x09 +#define GITS_CMD_MAPD 0x08 +#define GITS_CMD_MAPI 0x0B +#define GITS_CMD_MAPTI 0x0A +#define GITS_CMD_INV 0x0C +#define GITS_CMD_INVALL 0x0D +#define GITS_CMD_SYNC 0x05 + +/* MAPC command fields */ +#define ICID_LENGTH 16 +#define ICID_MASK ((1U << ICID_LENGTH) - 1) +FIELD(MAPC, RDBASE, 16, 32) + +#define RDBASE_PROCNUM_LENGTH 16 +#define RDBASE_PROCNUM_MASK ((1ULL << RDBASE_PROCNUM_LENGTH) - 1) + +/* MAPD command fields */ +#define ITTADDR_LENGTH 44 +#define ITTADDR_SHIFT 8 +#define ITTADDR_MASK MAKE_64BIT_MASK(ITTADDR_SHIFT, ITTADDR_LE= NGTH) +#define SIZE_MASK 0x1f + +#define DEVID_SHIFT 32 +#define DEVID_MASK MAKE_64BIT_MASK(32, 32) + +#define VALID_SHIFT 63 +#define CMD_FIELD_VALID_MASK (1ULL << VALID_SHIFT) +#define L2_TABLE_VALID_MASK CMD_FIELD_VALID_MASK +#define TABLE_ENTRY_VALID_MASK (1ULL << 0) =20 /** * Default features advertised by this version of ITS @@ -337,6 +374,9 @@ FIELD(GITS_TYPER, CIL, 36, 1) * Valid =3D 1 bit,ITTAddr =3D 44 bits,Size =3D 5 bits */ #define GITS_DTE_SIZE (0x8ULL) +#define GITS_DTE_ITTADDR_SHIFT 6 +#define GITS_DTE_ITTADDR_MASK MAKE_64BIT_MASK(GITS_DTE_ITTADDR_SHI= FT, \ + ITTADDR_LENGTH) =20 /* * 8 bytes Collection Table Entry size diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 8234939ccc1..fcd152271a6 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -50,6 +50,318 @@ static uint64_t baser_base_addr(uint64_t value, uint32_= t page_sz) return result; } =20 +static bool update_cte(GICv3ITSState *s, uint16_t icid, bool valid, + uint64_t rdbase) +{ + AddressSpace *as =3D &s->gicv3->dma_as; + uint64_t value; + uint64_t l2t_addr; + bool valid_l2t; + uint32_t l2t_id; + uint32_t max_l2_entries; + uint64_t cte =3D 0; + MemTxResult res =3D MEMTX_OK; + + if (!s->ct.valid) { + return true; + } + + if (valid) { + /* add mapping entry to collection table */ + cte =3D (valid & TABLE_ENTRY_VALID_MASK) | (rdbase << 1ULL); + } + + /* + * The specification defines the format of level 1 entries of a + * 2-level table, but the format of level 2 entries and the format + * of flat-mapped tables is IMPDEF. + */ + if (s->ct.indirect) { + l2t_id =3D icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE); + + value =3D address_space_ldq_le(as, + s->ct.base_addr + + (l2t_id * L1TABLE_ENTRY_SIZE), + MEMTXATTRS_UNSPECIFIED, &res); + + if (res !=3D MEMTX_OK) { + return false; + } + + valid_l2t =3D (value & L2_TABLE_VALID_MASK) !=3D 0; + + if (valid_l2t) { + max_l2_entries =3D s->ct.page_sz / s->ct.entry_sz; + + l2t_addr =3D value & ((1ULL << 51) - 1); + + address_space_stq_le(as, l2t_addr + + ((icid % max_l2_entries) * GITS_CTE_SIZE), + cte, MEMTXATTRS_UNSPECIFIED, &res); + } + } else { + /* Flat level table */ + address_space_stq_le(as, s->ct.base_addr + (icid * GITS_CTE_SIZE), + cte, MEMTXATTRS_UNSPECIFIED, &res); + } + if (res !=3D MEMTX_OK) { + return false; + } else { + return true; + } +} + +static bool process_mapc(GICv3ITSState *s, uint32_t offset) +{ + AddressSpace *as =3D &s->gicv3->dma_as; + uint16_t icid; + uint64_t rdbase; + bool valid; + MemTxResult res =3D MEMTX_OK; + bool result =3D false; + uint64_t value; + + offset +=3D NUM_BYTES_IN_DW; + offset +=3D NUM_BYTES_IN_DW; + + value =3D address_space_ldq_le(as, s->cq.base_addr + offset, + MEMTXATTRS_UNSPECIFIED, &res); + + if (res !=3D MEMTX_OK) { + return result; + } + + icid =3D value & ICID_MASK; + + rdbase =3D (value & R_MAPC_RDBASE_MASK) >> R_MAPC_RDBASE_SHIFT; + rdbase &=3D RDBASE_PROCNUM_MASK; + + valid =3D (value & CMD_FIELD_VALID_MASK); + + if ((icid > s->ct.maxids.max_collids) || (rdbase > s->gicv3->num_cpu))= { + qemu_log_mask(LOG_GUEST_ERROR, + "ITS MAPC: invalid collection table attributes " + "icid %d rdbase %lu\n", icid, rdbase); + /* + * in this implementation, in case of error + * we ignore this command and move onto the next + * command in the queue + */ + } else { + result =3D update_cte(s, icid, valid, rdbase); + } + + return result; +} + +static bool update_dte(GICv3ITSState *s, uint32_t devid, bool valid, + uint8_t size, uint64_t itt_addr) +{ + AddressSpace *as =3D &s->gicv3->dma_as; + uint64_t value; + uint64_t l2t_addr; + bool valid_l2t; + uint32_t l2t_id; + uint32_t max_l2_entries; + uint64_t dte =3D 0; + MemTxResult res =3D MEMTX_OK; + + if (s->dt.valid) { + if (valid) { + /* add mapping entry to device table */ + dte =3D (valid & TABLE_ENTRY_VALID_MASK) | + ((size & SIZE_MASK) << 1U) | + (itt_addr << GITS_DTE_ITTADDR_SHIFT); + } + } else { + return true; + } + + /* + * The specification defines the format of level 1 entries of a + * 2-level table, but the format of level 2 entries and the format + * of flat-mapped tables is IMPDEF. + */ + if (s->dt.indirect) { + l2t_id =3D devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE); + + value =3D address_space_ldq_le(as, + s->dt.base_addr + + (l2t_id * L1TABLE_ENTRY_SIZE), + MEMTXATTRS_UNSPECIFIED, &res); + + if (res !=3D MEMTX_OK) { + return false; + } + + valid_l2t =3D (value & L2_TABLE_VALID_MASK) !=3D 0; + + if (valid_l2t) { + max_l2_entries =3D s->dt.page_sz / s->dt.entry_sz; + + l2t_addr =3D value & ((1ULL << 51) - 1); + + address_space_stq_le(as, l2t_addr + + ((devid % max_l2_entries) * GITS_DTE_SIZE= ), + dte, MEMTXATTRS_UNSPECIFIED, &res); + } + } else { + /* Flat level table */ + address_space_stq_le(as, s->dt.base_addr + (devid * GITS_DTE_SIZE), + dte, MEMTXATTRS_UNSPECIFIED, &res); + } + if (res !=3D MEMTX_OK) { + return false; + } else { + return true; + } +} + +static bool process_mapd(GICv3ITSState *s, uint64_t value, uint32_t offset) +{ + AddressSpace *as =3D &s->gicv3->dma_as; + uint32_t devid; + uint8_t size; + uint64_t itt_addr; + bool valid; + MemTxResult res =3D MEMTX_OK; + bool result =3D false; + + devid =3D ((value & DEVID_MASK) >> DEVID_SHIFT); + + offset +=3D NUM_BYTES_IN_DW; + value =3D address_space_ldq_le(as, s->cq.base_addr + offset, + MEMTXATTRS_UNSPECIFIED, &res); + + if (res !=3D MEMTX_OK) { + return result; + } + + size =3D (value & SIZE_MASK); + + offset +=3D NUM_BYTES_IN_DW; + value =3D address_space_ldq_le(as, s->cq.base_addr + offset, + MEMTXATTRS_UNSPECIFIED, &res); + + if (res !=3D MEMTX_OK) { + return result; + } + + itt_addr =3D (value & ITTADDR_MASK) >> ITTADDR_SHIFT; + + valid =3D (value & CMD_FIELD_VALID_MASK); + + if ((devid > s->dt.maxids.max_devids) || + (size > FIELD_EX64(s->typer, GITS_TYPER, IDBITS))) { + qemu_log_mask(LOG_GUEST_ERROR, + "ITS MAPD: invalid device table attributes " + "devid %d or size %d\n", devid, size); + /* + * in this implementation, in case of error + * we ignore this command and move onto the next + * command in the queue + */ + } else { + result =3D update_dte(s, devid, valid, size, itt_addr); + } + + return result; +} + +/* + * Current implementation blocks until all + * commands are processed + */ +static void process_cmdq(GICv3ITSState *s) +{ + uint32_t wr_offset =3D 0; + uint32_t rd_offset =3D 0; + uint32_t cq_offset =3D 0; + uint64_t data; + AddressSpace *as =3D &s->gicv3->dma_as; + MemTxResult res =3D MEMTX_OK; + bool result =3D true; + uint8_t cmd; + + if (!(s->ctlr & ITS_CTLR_ENABLED)) { + return; + } + + wr_offset =3D FIELD_EX64(s->cwriter, GITS_CWRITER, OFFSET); + + if (wr_offset > s->cq.max_entries) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid write offset " + "%d\n", __func__, wr_offset); + return; + } + + rd_offset =3D FIELD_EX64(s->creadr, GITS_CREADR, OFFSET); + + if (rd_offset > s->cq.max_entries) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid read offset " + "%d\n", __func__, rd_offset); + return; + } + + while (wr_offset !=3D rd_offset) { + cq_offset =3D (rd_offset * GITS_CMDQ_ENTRY_SIZE); + data =3D address_space_ldq_le(as, s->cq.base_addr + cq_offset, + MEMTXATTRS_UNSPECIFIED, &res); + if (res !=3D MEMTX_OK) { + result =3D false; + } + cmd =3D (data & CMD_MASK); + + switch (cmd) { + case GITS_CMD_INT: + break; + case GITS_CMD_CLEAR: + break; + case GITS_CMD_SYNC: + /* + * Current implementation makes a blocking synchronous call + * for every command issued earlier, hence the internal state + * is already consistent by the time SYNC command is executed. + * Hence no further processing is required for SYNC command. + */ + break; + case GITS_CMD_MAPD: + result =3D process_mapd(s, data, cq_offset); + break; + case GITS_CMD_MAPC: + result =3D process_mapc(s, cq_offset); + break; + case GITS_CMD_MAPTI: + break; + case GITS_CMD_MAPI: + break; + case GITS_CMD_DISCARD: + break; + case GITS_CMD_INV: + case GITS_CMD_INVALL: + break; + default: + break; + } + if (result) { + rd_offset++; + rd_offset %=3D s->cq.max_entries; + s->creadr =3D FIELD_DP64(s->creadr, GITS_CREADR, OFFSET, rd_of= fset); + } else { + /* + * in this implementation, in case of dma read/write error + * we stall the command processing + */ + s->creadr =3D FIELD_DP64(s->creadr, GITS_CREADR, STALLED, 1); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %x cmd processing failed\n", __func__, cmd); + break; + } + } +} + /* * This function extracts the ITS Device and Collection table specific * parameters (like base_addr, size etc) from GITS_BASER register. @@ -204,6 +516,7 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, extract_table_params(s); extract_cmdq_params(s); s->creadr =3D 0; + process_cmdq(s); } break; case GITS_CBASER: @@ -231,6 +544,9 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, case GITS_CWRITER: s->cwriter =3D deposit64(s->cwriter, 0, 32, (value & ~R_GITS_CWRITER_RETRY_MASK)); + if (s->cwriter !=3D s->creadr) { + process_cmdq(s); + } break; case GITS_CWRITER + 4: s->cwriter =3D deposit64(s->cwriter, 32, 32, value); @@ -377,6 +693,9 @@ static bool its_writell(GICv3ITSState *s, hwaddr offset, break; case GITS_CWRITER: s->cwriter =3D value & ~R_GITS_CWRITER_RETRY_MASK; + if (s->cwriter !=3D s->creadr) { + process_cmdq(s); + } break; case GITS_CREADR: if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) { --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eUo7QUT/xI3d/p0AcuiFOVXMAjTUS3es5nCrI/CrjcY=; b=FnJXyz1iOvT1IRieNFihO6fgkjTnnB1MUxFM6h324YUDTHWngBhyyhXnLf5iRZldpI 9Ndh8iP3nC01l/Tj3zNRDCq8wwvayRA5LrBW8EYdEK9vsTtn4u+Qe9L0xLwVYCmM0rSG LYcJ69F4rzlUeI8+ZBLRVfwmqOFxUKXuljgviKkb18BTJxoWQLEUt6AHFycPvpfL/yBA XNaiMhJ4P91ho7ll+9ZRdCm4amTKxWQU891b3z/RVTCvTWeiak4476TPLkcxFDuAqNID 1T7yL4UesEYX1m8cFbaHwtVt9tvpwJaPDO8wP5RWGi5wa/QguwQma061i8CrKSNAQeEr e0MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eUo7QUT/xI3d/p0AcuiFOVXMAjTUS3es5nCrI/CrjcY=; b=O6rXtXPemqx7oyVa3yhIcZ/4BjL+wBXg37LOr7w1ibKrC+BKTSPvi4uhTfWjfDJ7BR ivWjuxHztGdlDStn7/8+9btX+F/5FtGEf9322/GU6dkOLtToU0gZQW0ZyKy9rGIS0LxW Ejeiwu+AS9u4DeCQ7keJJ73ypvhlGkz7WVo+bMbUWLfktmwrxEwU85Yd7ZzPGZ/FikgZ W2/7w8EAqEaUsUCs5V7lTrZOc80ZjVCBRNsyLsZKDcMc0Qv7xauj12EwP/3pDsgGhPah lGNkQqMr+VjZqL3bG8Yr4Ri41czk5z+bgHOyH0FLg9PR+DcVjCCgjAj4HgjKTJP3+Cbt AKyA== X-Gm-Message-State: AOAM53100ndM9BlbwdbMh9HVILuMebRRCD8Im0RZeGAC0zt6u6LSwPUc SwM3WLeVpf/zyGY1u5YyvJ0dLhiHGv+YBg== X-Google-Smtp-Source: ABdhPJy31+wM3oW9dtvbCNMhbDmYQa4VAtwB/ae/m/tuj6n1QANU53puwJOxLL7UgYqtgAmrsKXe/g== X-Received: by 2002:adf:fd92:: with SMTP id d18mr13648083wrr.28.1631549516164; Mon, 13 Sep 2021 09:11:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/23] hw/intc: GICv3 ITS Command processing Date: Mon, 13 Sep 2021 17:11:33 +0100 Message-Id: <20210913161144.12347-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550977836100001 Content-Type: text/plain; charset="utf-8" From: Shashi Mallela Added ITS command queue handling for MAPTI,MAPI commands,handled ITS translation which triggers an LPI via INT command as well as write to GITS_TRANSLATER register,defined enum to differentiate between ITS command interrupt trigger and GITS_TRANSLATER based interrupt trigger. Each of these commands make use of other functionalities implemented to get device table entry,collection table entry or interrupt translation table entry required for their processing. Signed-off-by: Shashi Mallela Reviewed-by: Peter Maydell Message-id: 20210910143951.92242-5-shashi.mallela@linaro.org Signed-off-by: Peter Maydell --- hw/intc/gicv3_internal.h | 12 + include/hw/intc/arm_gicv3_common.h | 2 + hw/intc/arm_gicv3_its.c | 365 ++++++++++++++++++++++++++++- 3 files changed, 378 insertions(+), 1 deletion(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 034fadfebeb..19664447902 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -334,6 +334,13 @@ FIELD(MAPC, RDBASE, 16, 32) #define ITTADDR_MASK MAKE_64BIT_MASK(ITTADDR_SHIFT, ITTADDR_LE= NGTH) #define SIZE_MASK 0x1f =20 +/* MAPI command fields */ +#define EVENTID_MASK ((1ULL << 32) - 1) + +/* MAPTI command fields */ +#define pINTID_SHIFT 32 +#define pINTID_MASK MAKE_64BIT_MASK(32, 32) + #define DEVID_SHIFT 32 #define DEVID_MASK MAKE_64BIT_MASK(32, 32) =20 @@ -359,6 +366,11 @@ FIELD(MAPC, RDBASE, 16, 32) * Values: | vPEID | ICID | */ #define ITS_ITT_ENTRY_SIZE 0xC +#define ITE_ENTRY_INTTYPE_SHIFT 1 +#define ITE_ENTRY_INTID_SHIFT 2 +#define ITE_ENTRY_INTID_MASK MAKE_64BIT_MASK(2, 24) +#define ITE_ENTRY_INTSP_SHIFT 26 +#define ITE_ENTRY_ICID_MASK MAKE_64BIT_MASK(0, 16) =20 /* 16 bits EventId */ #define ITS_IDBITS GICD_TYPER_IDBITS diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 1fd5cedbbdb..0715b0bc2a7 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -36,6 +36,8 @@ #define GICV3_MAXIRQ 1020 #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL) =20 +#define GICV3_LPI_INTID_START 8192 + #define GICV3_REDIST_SIZE 0x20000 =20 /* Number of SGI target-list bits */ diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index fcd152271a6..03c68009978 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -29,6 +29,22 @@ struct GICv3ITSClass { void (*parent_reset)(DeviceState *dev); }; =20 +/* + * This is an internal enum used to distinguish between LPI triggered + * via command queue and LPI triggered via gits_translater write. + */ +typedef enum ItsCmdType { + NONE =3D 0, /* internal indication for GITS_TRANSLATER write */ + CLEAR =3D 1, + DISCARD =3D 2, + INT =3D 3, +} ItsCmdType; + +typedef struct { + uint32_t iteh; + uint64_t itel; +} IteEntry; + static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz) { uint64_t result =3D 0; @@ -50,6 +66,329 @@ static uint64_t baser_base_addr(uint64_t value, uint32_= t page_sz) return result; } =20 +static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t *cte, + MemTxResult *res) +{ + AddressSpace *as =3D &s->gicv3->dma_as; + uint64_t l2t_addr; + uint64_t value; + bool valid_l2t; + uint32_t l2t_id; + uint32_t max_l2_entries; + + if (s->ct.indirect) { + l2t_id =3D icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE); + + value =3D address_space_ldq_le(as, + s->ct.base_addr + + (l2t_id * L1TABLE_ENTRY_SIZE), + MEMTXATTRS_UNSPECIFIED, res); + + if (*res =3D=3D MEMTX_OK) { + valid_l2t =3D (value & L2_TABLE_VALID_MASK) !=3D 0; + + if (valid_l2t) { + max_l2_entries =3D s->ct.page_sz / s->ct.entry_sz; + + l2t_addr =3D value & ((1ULL << 51) - 1); + + *cte =3D address_space_ldq_le(as, l2t_addr + + ((icid % max_l2_entries) * GITS_CTE_SI= ZE), + MEMTXATTRS_UNSPECIFIED, res); + } + } + } else { + /* Flat level table */ + *cte =3D address_space_ldq_le(as, s->ct.base_addr + + (icid * GITS_CTE_SIZE), + MEMTXATTRS_UNSPECIFIED, res); + } + + return (*cte & TABLE_ENTRY_VALID_MASK) !=3D 0; +} + +static bool update_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte, + IteEntry ite) +{ + AddressSpace *as =3D &s->gicv3->dma_as; + uint64_t itt_addr; + MemTxResult res =3D MEMTX_OK; + + itt_addr =3D (dte & GITS_DTE_ITTADDR_MASK) >> GITS_DTE_ITTADDR_SHIFT; + itt_addr <<=3D ITTADDR_SHIFT; /* 256 byte aligned */ + + address_space_stq_le(as, itt_addr + (eventid * (sizeof(uint64_t) + + sizeof(uint32_t))), ite.itel, MEMTXATTRS_UNSPECIF= IED, + &res); + + if (res =3D=3D MEMTX_OK) { + address_space_stl_le(as, itt_addr + (eventid * (sizeof(uint64_t) + + sizeof(uint32_t))) + sizeof(uint32_t), ite.it= eh, + MEMTXATTRS_UNSPECIFIED, &res); + } + if (res !=3D MEMTX_OK) { + return false; + } else { + return true; + } +} + +static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte, + uint16_t *icid, uint32_t *pIntid, MemTxResult *res) +{ + AddressSpace *as =3D &s->gicv3->dma_as; + uint64_t itt_addr; + bool status =3D false; + IteEntry ite =3D {}; + + itt_addr =3D (dte & GITS_DTE_ITTADDR_MASK) >> GITS_DTE_ITTADDR_SHIFT; + itt_addr <<=3D ITTADDR_SHIFT; /* 256 byte aligned */ + + ite.itel =3D address_space_ldq_le(as, itt_addr + + (eventid * (sizeof(uint64_t) + + sizeof(uint32_t))), MEMTXATTRS_UNSPECI= FIED, + res); + + if (*res =3D=3D MEMTX_OK) { + ite.iteh =3D address_space_ldl_le(as, itt_addr + + (eventid * (sizeof(uint64_t) + + sizeof(uint32_t))) + sizeof(uint32= _t), + MEMTXATTRS_UNSPECIFIED, res); + + if (*res =3D=3D MEMTX_OK) { + if (ite.itel & TABLE_ENTRY_VALID_MASK) { + if ((ite.itel >> ITE_ENTRY_INTTYPE_SHIFT) & + GITS_TYPE_PHYSICAL) { + *pIntid =3D (ite.itel & ITE_ENTRY_INTID_MASK) >> + ITE_ENTRY_INTID_SHIFT; + *icid =3D ite.iteh & ITE_ENTRY_ICID_MASK; + status =3D true; + } + } + } + } + return status; +} + +static uint64_t get_dte(GICv3ITSState *s, uint32_t devid, MemTxResult *res) +{ + AddressSpace *as =3D &s->gicv3->dma_as; + uint64_t l2t_addr; + uint64_t value; + bool valid_l2t; + uint32_t l2t_id; + uint32_t max_l2_entries; + + if (s->dt.indirect) { + l2t_id =3D devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE); + + value =3D address_space_ldq_le(as, + s->dt.base_addr + + (l2t_id * L1TABLE_ENTRY_SIZE), + MEMTXATTRS_UNSPECIFIED, res); + + if (*res =3D=3D MEMTX_OK) { + valid_l2t =3D (value & L2_TABLE_VALID_MASK) !=3D 0; + + if (valid_l2t) { + max_l2_entries =3D s->dt.page_sz / s->dt.entry_sz; + + l2t_addr =3D value & ((1ULL << 51) - 1); + + value =3D address_space_ldq_le(as, l2t_addr + + ((devid % max_l2_entries) * GITS_DTE_SI= ZE), + MEMTXATTRS_UNSPECIFIED, res); + } + } + } else { + /* Flat level table */ + value =3D address_space_ldq_le(as, s->dt.base_addr + + (devid * GITS_DTE_SIZE), + MEMTXATTRS_UNSPECIFIED, res); + } + + return value; +} + +/* + * This function handles the processing of following commands based on + * the ItsCmdType parameter passed:- + * 1. triggering of lpi interrupt translation via ITS INT command + * 2. triggering of lpi interrupt translation via gits_translater register + * 3. handling of ITS CLEAR command + * 4. handling of ITS DISCARD command + */ +static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t off= set, + ItsCmdType cmd) +{ + AddressSpace *as =3D &s->gicv3->dma_as; + uint32_t devid, eventid; + MemTxResult res =3D MEMTX_OK; + bool dte_valid; + uint64_t dte =3D 0; + uint32_t max_eventid; + uint16_t icid =3D 0; + uint32_t pIntid =3D 0; + bool ite_valid =3D false; + uint64_t cte =3D 0; + bool cte_valid =3D false; + bool result =3D false; + + if (cmd =3D=3D NONE) { + devid =3D offset; + } else { + devid =3D ((value & DEVID_MASK) >> DEVID_SHIFT); + + offset +=3D NUM_BYTES_IN_DW; + value =3D address_space_ldq_le(as, s->cq.base_addr + offset, + MEMTXATTRS_UNSPECIFIED, &res); + } + + if (res !=3D MEMTX_OK) { + return result; + } + + eventid =3D (value & EVENTID_MASK); + + dte =3D get_dte(s, devid, &res); + + if (res !=3D MEMTX_OK) { + return result; + } + dte_valid =3D dte & TABLE_ENTRY_VALID_MASK; + + if (dte_valid) { + max_eventid =3D (1UL << (((dte >> 1U) & SIZE_MASK) + 1)); + + ite_valid =3D get_ite(s, eventid, dte, &icid, &pIntid, &res); + + if (res !=3D MEMTX_OK) { + return result; + } + + if (ite_valid) { + cte_valid =3D get_cte(s, icid, &cte, &res); + } + + if (res !=3D MEMTX_OK) { + return result; + } + } + + if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid || + !cte_valid || (eventid > max_eventid)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes " + "devid %d or eventid %d or invalid dte %d or" + "invalid cte %d or invalid ite %d\n", + __func__, devid, eventid, dte_valid, cte_valid, + ite_valid); + /* + * in this implementation, in case of error + * we ignore this command and move onto the next + * command in the queue + */ + } else { + /* + * Current implementation only supports rdbase =3D=3D procnum + * Hence rdbase physical address is ignored + */ + if (cmd =3D=3D DISCARD) { + IteEntry ite =3D {}; + /* remove mapping from interrupt translation table */ + result =3D update_ite(s, eventid, dte, ite); + } + } + + return result; +} + +static bool process_mapti(GICv3ITSState *s, uint64_t value, uint32_t offse= t, + bool ignore_pInt) +{ + AddressSpace *as =3D &s->gicv3->dma_as; + uint32_t devid, eventid; + uint32_t pIntid =3D 0; + uint32_t max_eventid, max_Intid; + bool dte_valid; + MemTxResult res =3D MEMTX_OK; + uint16_t icid =3D 0; + uint64_t dte =3D 0; + IteEntry ite; + uint32_t int_spurious =3D INTID_SPURIOUS; + bool result =3D false; + + devid =3D ((value & DEVID_MASK) >> DEVID_SHIFT); + offset +=3D NUM_BYTES_IN_DW; + value =3D address_space_ldq_le(as, s->cq.base_addr + offset, + MEMTXATTRS_UNSPECIFIED, &res); + + if (res !=3D MEMTX_OK) { + return result; + } + + eventid =3D (value & EVENTID_MASK); + + if (!ignore_pInt) { + pIntid =3D ((value & pINTID_MASK) >> pINTID_SHIFT); + } + + offset +=3D NUM_BYTES_IN_DW; + value =3D address_space_ldq_le(as, s->cq.base_addr + offset, + MEMTXATTRS_UNSPECIFIED, &res); + + if (res !=3D MEMTX_OK) { + return result; + } + + icid =3D value & ICID_MASK; + + dte =3D get_dte(s, devid, &res); + + if (res !=3D MEMTX_OK) { + return result; + } + dte_valid =3D dte & TABLE_ENTRY_VALID_MASK; + + max_eventid =3D (1UL << (((dte >> 1U) & SIZE_MASK) + 1)); + + if (!ignore_pInt) { + max_Intid =3D (1ULL << (GICD_TYPER_IDBITS + 1)) - 1; + } + + if ((devid > s->dt.maxids.max_devids) || (icid > s->ct.maxids.max_coll= ids) + || !dte_valid || (eventid > max_eventid) || + (!ignore_pInt && (((pIntid < GICV3_LPI_INTID_START) || + (pIntid > max_Intid)) && (pIntid !=3D INTID_SPURIOUS)))) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes " + "devid %d or icid %d or eventid %d or pIntid %d or" + "unmapped dte %d\n", __func__, devid, icid, eventid, + pIntid, dte_valid); + /* + * in this implementation, in case of error + * we ignore this command and move onto the next + * command in the queue + */ + } else { + /* add ite entry to interrupt translation table */ + ite.itel =3D (dte_valid & TABLE_ENTRY_VALID_MASK) | + (GITS_TYPE_PHYSICAL << ITE_ENTRY_INTTYPE_SHIFT); + + if (ignore_pInt) { + ite.itel |=3D (eventid << ITE_ENTRY_INTID_SHIFT); + } else { + ite.itel |=3D (pIntid << ITE_ENTRY_INTID_SHIFT); + } + ite.itel |=3D (int_spurious << ITE_ENTRY_INTSP_SHIFT); + ite.iteh =3D icid; + + result =3D update_ite(s, eventid, dte, ite); + } + + return result; +} + static bool update_cte(GICv3ITSState *s, uint16_t icid, bool valid, uint64_t rdbase) { @@ -316,8 +655,10 @@ static void process_cmdq(GICv3ITSState *s) =20 switch (cmd) { case GITS_CMD_INT: + res =3D process_its_cmd(s, data, cq_offset, INT); break; case GITS_CMD_CLEAR: + res =3D process_its_cmd(s, data, cq_offset, CLEAR); break; case GITS_CMD_SYNC: /* @@ -334,10 +675,13 @@ static void process_cmdq(GICv3ITSState *s) result =3D process_mapc(s, cq_offset); break; case GITS_CMD_MAPTI: + result =3D process_mapti(s, data, cq_offset, false); break; case GITS_CMD_MAPI: + result =3D process_mapti(s, data, cq_offset, true); break; case GITS_CMD_DISCARD: + result =3D process_its_cmd(s, data, cq_offset, DISCARD); break; case GITS_CMD_INV: case GITS_CMD_INVALL: @@ -499,7 +843,26 @@ static MemTxResult gicv3_its_translation_write(void *o= paque, hwaddr offset, uint64_t data, unsigned siz= e, MemTxAttrs attrs) { - return MEMTX_OK; + GICv3ITSState *s =3D (GICv3ITSState *)opaque; + bool result =3D true; + uint32_t devid =3D 0; + + switch (offset) { + case GITS_TRANSLATER: + if (s->ctlr & ITS_CTLR_ENABLED) { + devid =3D attrs.requester_id; + result =3D process_its_cmd(s, data, devid, NONE); + } + break; + default: + break; + } + + if (result) { + return MEMTX_OK; + } else { + return MEMTX_ERROR; + } } =20 static bool its_writel(GICv3ITSState *s, hwaddr offset, --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sfxsKCUZyyxMMR541WiYb6hWKyYJy4Gknw3RAa8OGtg=; b=NXrH3u4u5u+SIX2aflYi4BhXskv+q6M3GT76dLCm0ZYxbbtq4PqDBlkLaDA+DvHB/q 1M78FQnlhNjEgpNO6hKmYEXLZ01m1e+sHdGLAh/aRLU53AgKVhOe+/KrzfsdRAMzl7Hf 409c3pe8aofKTfrhl67s85B7QKxpqqzk0K+8NCamk4DoYSit+dWUfBn7x+yJa19W0x0D XN1HaQq/xkP7urK51xEuYdii4tpqhcLWqCdTnPcu9uNfJmAHrt8L4ysFnyvPDnDp4kfo TJGiaE0NtcwkvIs595UM45cxqs2bYKw7LLyckx3ReeV+VcX9Mi3RIxdlCpSPwMJ+47Nq w0Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sfxsKCUZyyxMMR541WiYb6hWKyYJy4Gknw3RAa8OGtg=; b=TX3y6pw1HjVyyfmRUdQyqNRIIOwfnguQoa0UcxtzES92S+lH/AC+3sTOdnYcSKFGDu txUXonKzgfA5Nk8hmUudbVfT/jrv5AOq0qYJhXkCxOYpv36yrnuewFC7FN7XXvf7AD+j f+fzNZO9TShKdCu5+tvqy5jTDSLMNLIRXZ+qZ0TYmZSPTWb4Z0kzz/eYumn7e/EyIgM3 KeQxf64M4/eGVD5yErPOaqgP+VIGOcV5yhjfqxV4iHef8kz//2SU+eTniM3rMEJIXSv2 cag4tmVpADc/bQexn7XBF0borI9fMHmoqTY1MU7zyIAXYz1rIOzXTgp3ZBzYe79EUUco Y/Pw== X-Gm-Message-State: AOAM5339Aufn8Y+WduCecQ+Alu2W1biulrbyMdX/4LrjzJCEd1CX/APi sEqLcQhUs9Z9S0nONQ9a+SZ5gEtRAImDjQ== X-Google-Smtp-Source: ABdhPJw1AAVShCmLgcPZ4raf+hoVdBBrKmwuedMYa9z/j3zwc9Gg/j4/w8LN/zo/BrvYl0gOHVAPKA== X-Received: by 2002:a05:6000:374:: with SMTP id f20mr13590993wrf.129.1631549517141; Mon, 13 Sep 2021 09:11:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/23] hw/intc: GICv3 ITS Feature enablement Date: Mon, 13 Sep 2021 17:11:34 +0100 Message-Id: <20210913161144.12347-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550542311100001 Content-Type: text/plain; charset="utf-8" From: Shashi Mallela Added properties to enable ITS feature and define qemu system address space memory in gicv3 common,setup distributor and redistributor registers to indicate LPI support. Signed-off-by: Shashi Mallela Reviewed-by: Peter Maydell Tested-by: Neil Armstrong Message-id: 20210910143951.92242-6-shashi.mallela@linaro.org Signed-off-by: Peter Maydell --- hw/intc/gicv3_internal.h | 2 ++ include/hw/intc/arm_gicv3_common.h | 1 + hw/intc/arm_gicv3_common.c | 12 ++++++++++++ hw/intc/arm_gicv3_dist.c | 5 ++++- hw/intc/arm_gicv3_redist.c | 12 +++++++++--- 5 files changed, 28 insertions(+), 4 deletions(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 19664447902..530d1c17897 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -68,6 +68,8 @@ #define GICD_CTLR_E1NWF (1U << 7) #define GICD_CTLR_RWP (1U << 31) =20 +#define GICD_TYPER_LPIS_SHIFT 17 + /* 16 bits EventId */ #define GICD_TYPER_IDBITS 0xf =20 diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 0715b0bc2a7..c1348cc60a1 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -221,6 +221,7 @@ struct GICv3State { uint32_t num_cpu; uint32_t num_irq; uint32_t revision; + bool lpi_enable; bool security_extn; bool irq_reset_nonsecure; bool gicd_no_migration_shift_bug; diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 58ef65f589e..53dea2a7756 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -345,6 +345,11 @@ static void arm_gicv3_common_realize(DeviceState *dev,= Error **errp) return; } =20 + if (s->lpi_enable && !s->dma) { + error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not se= t"); + return; + } + s->cpu =3D g_new0(GICv3CPUState, s->num_cpu); =20 for (i =3D 0; i < s->num_cpu; i++) { @@ -381,6 +386,10 @@ static void arm_gicv3_common_realize(DeviceState *dev,= Error **errp) (1 << 24) | (i << 8) | (last << 4); + + if (s->lpi_enable) { + s->cpu[i].gicr_typer |=3D GICR_TYPER_PLPIS; + } } } =20 @@ -494,9 +503,12 @@ static Property arm_gicv3_common_properties[] =3D { DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1), DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), + DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0), DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn,= 0), DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions, redist_region_count, qdev_prop_uint32, uint32_t), + DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION, + MemoryRegion *), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 5beb7c4235a..4164500ea96 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -384,7 +384,9 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, * A3V =3D=3D 1 (non-zero values of Affinity level 3 supported) * IDbits =3D=3D 0xf (we support 16-bit interrupt identifiers) * DVIS =3D=3D 0 (Direct virtual LPI injection not supported) - * LPIS =3D=3D 0 (LPIs not supported) + * LPIS =3D=3D 1 (LPIs are supported if affinity routing is enable= d) + * num_LPIs =3D=3D 0b00000 (bits [15:11],Number of LPIs as indicat= ed + * by GICD_TYPER.IDbits) * MBIS =3D=3D 0 (message-based SPIs not supported) * SecurityExtn =3D=3D 1 if security extns supported * CPUNumber =3D=3D 0 since for us ARE is always 1 @@ -399,6 +401,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, bool sec_extn =3D !(s->gicd_ctlr & GICD_CTLR_DS); =20 *data =3D (1 << 25) | (1 << 24) | (sec_extn << 10) | + (s->lpi_enable << GICD_TYPER_LPIS_SHIFT) | (0xf << 19) | itlinesnumber; return true; } diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 53da703ed84..2108abfe9c3 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -248,10 +248,16 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwa= ddr offset, case GICR_CTLR: /* For our implementation, GICR_TYPER.DPGS is 0 and so all * the DPG bits are RAZ/WI. We don't do anything asynchronously, - * so UWP and RWP are RAZ/WI. And GICR_TYPER.LPIS is 0 (we don't - * implement LPIs) so Enable_LPIs is RES0. So there are no writable - * bits for us. + * so UWP and RWP are RAZ/WI. GICR_TYPER.LPIS is 1 (we + * implement LPIs) so Enable_LPIs is programmable. */ + if (cs->gicr_typer & GICR_TYPER_PLPIS) { + if (value & GICR_CTLR_ENABLE_LPIS) { + cs->gicr_ctlr |=3D GICR_CTLR_ENABLE_LPIS; + } else { + cs->gicr_ctlr &=3D ~GICR_CTLR_ENABLE_LPIS; + } + } return MEMTX_OK; case GICR_STATUSR: /* RAZ/WI for our implementation */ --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631549984; cv=none; d=zohomail.com; s=zohoarc; b=RLDwyVScRLZDF5MGYy4A+iFkE4T4G3qSscWgQUTMnsp/miTcy78XlAFwmTf1vrZFsDtmoyEzbO2IDr94M0aIb1ImKak+2q2O4foV+G2fZRgEQkmGdtgSXMgCQjjiEedDskKPVDjWsfL1FCufJgl84O491dCPcZFtEEtsFDKylGo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631549984; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GCsDRJBpMn1VTHJToXsg549TDTPGFlHhcVmAwYBrH+Y=; b=Y1bL7fv/1zDUeytHQDPwOWXvQrjXR/O9AUqrNtjVMS0WdZc1Qjr0bUlpXsJm3OACeXy1m/iNC9UaLlPLjncIThrlEg4z1oqGG3rSc6xcapLmrWEFlGz77V47cWE3GqQIuP1MuqwpkMA00cLqT9Wy50TyIXzQMapnFVU5hCIkFrc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631549984315867.0664797204897; Mon, 13 Sep 2021 09:19:44 -0700 (PDT) Received: from localhost ([::1]:40288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPogJ-0002Rn-3l for importer@patchew.org; Mon, 13 Sep 2021 12:19:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60914) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYu-00017i-Bk for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:04 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:38638) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYq-0008DG-H0 for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:03 -0400 Received: by mail-wr1-x42f.google.com with SMTP id u16so15554274wrn.5 for ; Mon, 13 Sep 2021 09:11:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=GCsDRJBpMn1VTHJToXsg549TDTPGFlHhcVmAwYBrH+Y=; b=GODltXlRFejsf7EFM/UR2LzhYd+7EAV6+wsYSynyrsK42xZVJWUp/vgTcJQGb/Svmi h0Y3Q9eXu+z7+9v7089hwdL+NSh1Nv850HcKTZE0JLFpOYyyPPQB/Ne97UeACCm+uccR FYzqPzxk4SqgL6gg1n3+YJaskQS/V8I6Br+kJo7q6imHRFej6RmDis3XSzhZIRBZjt3q NNRBeJPn71hlvhYX38pR5nEtaPujB4EduKOgBqi8h4ZtIVG55bCz6JnE/SkdKDWx3DZC YR7OS/Lm8DdCLPrkl+qcizZ445m2gp9SOL0ST14lgRvWcaN4JwGqqvLo77qB5HmK+AuR jE+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GCsDRJBpMn1VTHJToXsg549TDTPGFlHhcVmAwYBrH+Y=; b=PNF+X7J8/yOyZXOD6MGM+Eyeba3lA/ixv9fG9+WN3aPy4WJg3dZAskqISrLYA8VA3a caJXv2iz90KaQfsbe58CiXfw5Hh4P7OxiMqY0h/yeEnasiGgeAj1NS7b1Q0KN53S6tKG RSl9t7iHl+LJPAwe4Huu1Pf3mA7vNbq16lf/BW1yOB2veIf9cQ5qdLWGfblZYIDSsuEl CQfqXgBOG6M3uOhZhtKRzlA7cS5wt4I9trRPnoB0Rq+7paiCTZeNx2e6Cd8Utm3EPbY2 2jZb+Va2w6Zuido1KLjzDqimOTQ7h9glUvMvTfEcV3jSSU7E3OhjQOjWmamGtvlk2Wi1 bfOA== X-Gm-Message-State: AOAM533I4HFhaCIZOeCD8wOz1qe/0Ajb96Zwsxss/Tdo+OnjurQucZSZ Wwl7dk529OcGBUU0leaKHajCR0KQ+n+lNw== X-Google-Smtp-Source: ABdhPJw1+KqNp5mg9+cZcmMRO96bKneoDHG+4UrnXCsNcVUh0frO+O5DIRuNB0qCTUO4NIRoyKAu4g== X-Received: by 2002:adf:f683:: with SMTP id v3mr9442373wrp.423.1631549518020; Mon, 13 Sep 2021 09:11:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/23] hw/intc: GICv3 redistributor ITS processing Date: Mon, 13 Sep 2021 17:11:35 +0100 Message-Id: <20210913161144.12347-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631549984832100001 Content-Type: text/plain; charset="utf-8" From: Shashi Mallela Implemented lpi processing at redistributor to get lpi config info from lpi configuration table,determine priority,set pending state in lpi pending table and forward the lpi to cpuif.Added logic to invoke redistributor lpi processing with translated LPI which set/clear LPI from ITS device as part of ITS INT,CLEAR,DISCARD command and GITS_TRANSLATER processing. Signed-off-by: Shashi Mallela Tested-by: Neil Armstrong Reviewed-by: Peter Maydell Message-id: 20210910143951.92242-7-shashi.mallela@linaro.org Signed-off-by: Peter Maydell --- hw/intc/gicv3_internal.h | 9 ++ include/hw/intc/arm_gicv3_common.h | 7 ++ hw/intc/arm_gicv3.c | 14 +++ hw/intc/arm_gicv3_common.c | 1 + hw/intc/arm_gicv3_cpuif.c | 7 +- hw/intc/arm_gicv3_its.c | 23 +++++ hw/intc/arm_gicv3_redist.c | 141 +++++++++++++++++++++++++++++ 7 files changed, 200 insertions(+), 2 deletions(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 530d1c17897..a0369dace7b 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -140,6 +140,8 @@ FIELD(GICR_PENDBASER, PHYADDR, 16, 36) FIELD(GICR_PENDBASER, OUTERCACHE, 56, 3) FIELD(GICR_PENDBASER, PTZ, 62, 1) =20 +#define GICR_PROPBASER_IDBITS_THRESHOLD 0xd + #define ICC_CTLR_EL1_CBPR (1U << 0) #define ICC_CTLR_EL1_EOIMODE (1U << 1) #define ICC_CTLR_EL1_PMHE (1U << 6) @@ -305,6 +307,9 @@ FIELD(GITS_TYPER, CIL, 36, 1) =20 #define L1TABLE_ENTRY_SIZE 8 =20 +#define LPI_CTE_ENABLED TABLE_ENTRY_VALID_MASK +#define LPI_PRIORITY_MASK 0xfc + #define GITS_CMDQ_ENTRY_SIZE 32 #define NUM_BYTES_IN_DW 8 =20 @@ -397,6 +402,7 @@ FIELD(MAPC, RDBASE, 16, 32) * Valid =3D 1 bit,RDBase =3D 36 bits(considering max RDBASE) */ #define GITS_CTE_SIZE (0x8ULL) +#define GITS_CTE_RDBASE_PROCNUM_MASK MAKE_64BIT_MASK(1, RDBASE_PROCNUM_LE= NGTH) =20 /* Special interrupt IDs */ #define INTID_SECURE 1020 @@ -455,6 +461,9 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr off= set, uint64_t data, unsigned size, MemTxAttrs attrs); void gicv3_dist_set_irq(GICv3State *s, int irq, int level); void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level); +void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level); +void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level); +void gicv3_redist_update_lpi(GICv3CPUState *cs); void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns); void gicv3_init_cpuif(GICv3State *s); =20 diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index c1348cc60a1..aa4f0d67703 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -204,6 +204,13 @@ struct GICv3CPUState { * real state above; it doesn't need to be migrated. */ PendingIrq hppi; + + /* + * Cached information recalculated from LPI tables + * in guest memory + */ + PendingIrq hpplpi; + /* This is temporary working state, to avoid a malloc in gicv3_update(= ) */ bool seenbetter; }; diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index d63f8af604d..3f24707838c 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -165,6 +165,16 @@ static void gicv3_redist_update_noirqset(GICv3CPUState= *cs) cs->hppi.grp =3D gicv3_irq_group(cs->gic, cs, cs->hppi.irq); } =20 + if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable && + (cs->hpplpi.prio !=3D 0xff)) { + if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) { + cs->hppi.irq =3D cs->hpplpi.irq; + cs->hppi.prio =3D cs->hpplpi.prio; + cs->hppi.grp =3D cs->hpplpi.grp; + seenbetter =3D true; + } + } + /* If the best interrupt we just found would preempt whatever * was the previous best interrupt before this update, then * we know it's definitely the best one now. @@ -339,9 +349,13 @@ static void gicv3_set_irq(void *opaque, int irq, int l= evel) =20 static void arm_gicv3_post_load(GICv3State *s) { + int i; /* Recalculate our cached idea of the current highest priority * pending interrupt, but don't set IRQ or FIQ lines. */ + for (i =3D 0; i < s->num_cpu; i++) { + gicv3_redist_update_lpi(&s->cpu[i]); + } gicv3_full_update_noirqset(s); /* Repopulate the cache of GICv3CPUState pointers for target CPUs */ gicv3_cache_all_target_cpustates(s); diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 53dea2a7756..223db16feca 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -435,6 +435,7 @@ static void arm_gicv3_common_reset(DeviceState *dev) memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr)); =20 cs->hppi.prio =3D 0xff; + cs->hpplpi.prio =3D 0xff; =20 /* State in the CPU interface must *not* be reset here, because it * is part of the CPU's reset domain, not the GIC device's. diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index a032d505f53..462a35f66eb 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -899,10 +899,12 @@ static void icc_activate_irq(GICv3CPUState *cs, int i= rq) cs->gicr_iactiver0 =3D deposit32(cs->gicr_iactiver0, irq, 1, 1); cs->gicr_ipendr0 =3D deposit32(cs->gicr_ipendr0, irq, 1, 0); gicv3_redist_update(cs); - } else { + } else if (irq < GICV3_LPI_INTID_START) { gicv3_gicd_active_set(cs->gic, irq); gicv3_gicd_pending_clear(cs->gic, irq); gicv3_update(cs->gic, irq, 1); + } else { + gicv3_redist_lpi_pending(cs, irq, 0); } } =20 @@ -1318,7 +1320,8 @@ static void icc_eoir_write(CPUARMState *env, const AR= MCPRegInfo *ri, trace_gicv3_icc_eoir_write(is_eoir0 ? 0 : 1, gicv3_redist_affid(cs), value); =20 - if (irq >=3D cs->gic->num_irq) { + if ((irq >=3D cs->gic->num_irq) && + !(cs->gic->lpi_enable && (irq >=3D GICV3_LPI_INTID_START))) { /* This handles two cases: * 1. If software writes the ID of a spurious interrupt [ie 1020-1= 023] * to the GICC_EOIR, the GIC ignores that write. diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 03c68009978..efb1b5ecab8 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -233,6 +233,7 @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t = value, uint32_t offset, uint64_t cte =3D 0; bool cte_valid =3D false; bool result =3D false; + uint64_t rdbase; =20 if (cmd =3D=3D NONE) { devid =3D offset; @@ -293,6 +294,18 @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t= value, uint32_t offset, * Current implementation only supports rdbase =3D=3D procnum * Hence rdbase physical address is ignored */ + rdbase =3D (cte & GITS_CTE_RDBASE_PROCNUM_MASK) >> 1U; + + if (rdbase > s->gicv3->num_cpu) { + return result; + } + + if ((cmd =3D=3D CLEAR) || (cmd =3D=3D DISCARD)) { + gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 0); + } else { + gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 1); + } + if (cmd =3D=3D DISCARD) { IteEntry ite =3D {}; /* remove mapping from interrupt translation table */ @@ -621,6 +634,7 @@ static void process_cmdq(GICv3ITSState *s) MemTxResult res =3D MEMTX_OK; bool result =3D true; uint8_t cmd; + int i; =20 if (!(s->ctlr & ITS_CTLR_ENABLED)) { return; @@ -685,6 +699,15 @@ static void process_cmdq(GICv3ITSState *s) break; case GITS_CMD_INV: case GITS_CMD_INVALL: + /* + * Current implementation doesn't cache any ITS tables, + * but the calculated lpi priority information. We only + * need to trigger lpi priority re-calculation to be in + * sync with LPI config table or pending table changes. + */ + for (i =3D 0; i < s->gicv3->num_cpu; i++) { + gicv3_redist_update_lpi(&s->gicv3->cpu[i]); + } break; default: break; diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 2108abfe9c3..7072bfcbb1d 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -254,6 +254,9 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwadd= r offset, if (cs->gicr_typer & GICR_TYPER_PLPIS) { if (value & GICR_CTLR_ENABLE_LPIS) { cs->gicr_ctlr |=3D GICR_CTLR_ENABLE_LPIS; + /* Check for any pending interr in pending table */ + gicv3_redist_update_lpi(cs); + gicv3_redist_update(cs); } else { cs->gicr_ctlr &=3D ~GICR_CTLR_ENABLE_LPIS; } @@ -532,6 +535,144 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr o= ffset, uint64_t data, return r; } =20 +static void gicv3_redist_check_lpi_priority(GICv3CPUState *cs, int irq) +{ + AddressSpace *as =3D &cs->gic->dma_as; + uint64_t lpict_baddr; + uint8_t lpite; + uint8_t prio; + + lpict_baddr =3D cs->gicr_propbaser & R_GICR_PROPBASER_PHYADDR_MASK; + + address_space_read(as, lpict_baddr + ((irq - GICV3_LPI_INTID_START) * + sizeof(lpite)), MEMTXATTRS_UNSPECIFIED, &lpite, + sizeof(lpite)); + + if (!(lpite & LPI_CTE_ENABLED)) { + return; + } + + if (cs->gic->gicd_ctlr & GICD_CTLR_DS) { + prio =3D lpite & LPI_PRIORITY_MASK; + } else { + prio =3D ((lpite & LPI_PRIORITY_MASK) >> 1) | 0x80; + } + + if ((prio < cs->hpplpi.prio) || + ((prio =3D=3D cs->hpplpi.prio) && (irq <=3D cs->hpplpi.irq))) { + cs->hpplpi.irq =3D irq; + cs->hpplpi.prio =3D prio; + /* LPIs are always non-secure Grp1 interrupts */ + cs->hpplpi.grp =3D GICV3_G1NS; + } +} + +void gicv3_redist_update_lpi(GICv3CPUState *cs) +{ + /* + * This function scans the LPI pending table and for each pending + * LPI, reads the corresponding entry from LPI configuration table + * to extract the priority info and determine if the current LPI + * priority is lower than the last computed high priority lpi interrup= t. + * If yes, replace current LPI as the new high priority lpi interrupt. + */ + AddressSpace *as =3D &cs->gic->dma_as; + uint64_t lpipt_baddr; + uint32_t pendt_size =3D 0; + uint8_t pend; + int i, bit; + uint64_t idbits; + + idbits =3D MIN(FIELD_EX64(cs->gicr_propbaser, GICR_PROPBASER, IDBITS), + GICD_TYPER_IDBITS); + + if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || !cs->gicr_propbaser || + !cs->gicr_pendbaser) { + return; + } + + cs->hpplpi.prio =3D 0xff; + + lpipt_baddr =3D cs->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK; + + /* Determine the highest priority pending interrupt among LPIs */ + pendt_size =3D (1ULL << (idbits + 1)); + + for (i =3D GICV3_LPI_INTID_START / 8; i < pendt_size / 8; i++) { + address_space_read(as, lpipt_baddr + i, MEMTXATTRS_UNSPECIFIED, &p= end, + sizeof(pend)); + + while (pend) { + bit =3D ctz32(pend); + gicv3_redist_check_lpi_priority(cs, i * 8 + bit); + pend &=3D ~(1 << bit); + } + } +} + +void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level) +{ + /* + * This function updates the pending bit in lpi pending table for + * the irq being activated or deactivated. + */ + AddressSpace *as =3D &cs->gic->dma_as; + uint64_t lpipt_baddr; + bool ispend =3D false; + uint8_t pend; + + /* + * get the bit value corresponding to this irq in the + * lpi pending table + */ + lpipt_baddr =3D cs->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK; + + address_space_read(as, lpipt_baddr + ((irq / 8) * sizeof(pend)), + MEMTXATTRS_UNSPECIFIED, &pend, sizeof(pend)); + + ispend =3D extract32(pend, irq % 8, 1); + + /* no change in the value of pending bit, return */ + if (ispend =3D=3D level) { + return; + } + pend =3D deposit32(pend, irq % 8, 1, level ? 1 : 0); + + address_space_write(as, lpipt_baddr + ((irq / 8) * sizeof(pend)), + MEMTXATTRS_UNSPECIFIED, &pend, sizeof(pend)); + + /* + * check if this LPI is better than the current hpplpi, if yes + * just set hpplpi.prio and .irq without doing a full rescan + */ + if (level) { + gicv3_redist_check_lpi_priority(cs, irq); + } else { + if (irq =3D=3D cs->hpplpi.irq) { + gicv3_redist_update_lpi(cs); + } + } +} + +void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level) +{ + uint64_t idbits; + + idbits =3D MIN(FIELD_EX64(cs->gicr_propbaser, GICR_PROPBASER, IDBITS), + GICD_TYPER_IDBITS); + + if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || !cs->gicr_propbaser || + !cs->gicr_pendbaser || (irq > (1ULL << (idbits + 1)) - 1) || + irq < GICV3_LPI_INTID_START) { + return; + } + + /* set/clear the pending bit for this irq */ + gicv3_redist_lpi_pending(cs, irq, level); + + gicv3_redist_update(cs); +} + void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level) { /* Update redistributor state for a change in an external PPI input li= ne */ --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631551167; cv=none; d=zohomail.com; s=zohoarc; b=B6Z9Dd0JYxb99ExBeMhlz9fjU9tc75EzNAHNrTiFIfScPR0vkF2yIqbNxO6iq0DWhj1qXp8lUWzAOvjoGuKVz4YrPAv5WfRH3UwmPgiJXx2yyPkjNYM0KNA0Me7ZzA1r9o/oeAnx9J5hjDAgLxrPxB7dPDQxM84Xc7grN8KlhFI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631551167; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DnHcKYAUuBwzxze38c9ICqdqdR0A+i5ARIkB9vVjhDI=; b=Z8YRH927YYWxkHyPqhwUH9M/cD5GF2EUnqljblXvnQYl4nucTFo8g8j++8hOYXjvb4MtQvbMeY9utzyDgFoP10nBMWKCmWCBXGVhuFTyGswxHVJxOBKmac0QQ/Xw0D/8qe4fvIM28j7nqo2wlJyHEGkQNrQeT6Hb3mNiEhn00KQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631551167673707.2450501331326; Mon, 13 Sep 2021 09:39:27 -0700 (PDT) Received: from localhost ([::1]:34552 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPozO-0003KJ-Lo for importer@patchew.org; Mon, 13 Sep 2021 12:39:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYt-00015V-FN for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:03 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:38412) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYr-0008DK-5O for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:03 -0400 Received: by mail-wm1-x32f.google.com with SMTP id k5-20020a05600c1c8500b002f76c42214bso7411818wms.3 for ; Mon, 13 Sep 2021 09:12:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DnHcKYAUuBwzxze38c9ICqdqdR0A+i5ARIkB9vVjhDI=; b=YR+sTuyQeKW/OQMKiky9/j6OVTOzhVfVUe7RUTGexFfcyt8SV5VPlLitiLvYVcdoM/ inqYpOqbEYE9PuQn+9Er2EDAOOqKRMZgVDADFoIUVV2eWKxdpnFPMjRmRLv4iHYeEbdR 5kvC/rlvgG57ViC0YKopm4HrFUfTZBYY5WQSdS2t2XsIXXdIf5/VwcJcDKraGeKGa69J d9NJfgG81QZuHCGGN6REEvJZhCtvEDMx88QfOj9YLqyrBuso8iXVr8USk+YyMKm88tl9 eIby0l+JdUF4XEWsXKMxGRth5xOngZOu3Gfzd/2IREJw+VLf1BvfCvgjAxnN//JqEX6t k3pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DnHcKYAUuBwzxze38c9ICqdqdR0A+i5ARIkB9vVjhDI=; b=L08BT8D3b43F+81g8r9N+DYoeLTGMFpWcETzfuN9tje/BefPCEC8CIWD+/EDbQkPkx nm28B1WRk9B3K4Dllw+4w8oLKmQJsECpkv0ifoRJH8gV0FaC4J6DjW7jQ6otaAm4oQBH h7pkVV+kG6b0EyBAqN8VT4gP0ZI/9D09JsiwnZyrhn16SBvhzLyu1In1ptqQqHWOT7kN PPcC3NL3+Wb0mNctotz+/mHXjX54j7g5LHPYg/0v2Ba3z6ZgEtGhPT0e8MVM0CPYvRN+ 5IzpPqF0xPWbJr63vpKBP3sbqrqL691OCueXkjFfDQAv3XcIqpmu/O+nNwKm/vTFwEiF cumQ== X-Gm-Message-State: AOAM531rZkfiwRnbDV5JWcfUSedWoLeMhddJbL32QsnXevt2MlNMKbh9 GtSBbhmZuT7QU906xZd1K5CeD0q0hWbs5g== X-Google-Smtp-Source: ABdhPJxyK/Bj+5FNobF96sjTICO8+kIzHA1uxSQpnk+2CZ5VkF1ixMzq6XXBpXlVwdUdA0oBQTIFBw== X-Received: by 2002:a7b:cc14:: with SMTP id f20mr11960574wmh.137.1631549518789; Mon, 13 Sep 2021 09:11:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/23] tests/data/acpi/virt: Add IORT files for ITS Date: Mon, 13 Sep 2021 17:11:36 +0100 Message-Id: <20210913161144.12347-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631551169182100001 Content-Type: text/plain; charset="utf-8" From: Shashi Mallela Added expected IORT files applicable with latest GICv3 ITS changes.Temporarily differences in these files are okay. Signed-off-by: Shashi Mallela Acked-by: Igor Mammedov Reviewed-by: Peter Maydell Message-id: 20210910143951.92242-8-shashi.mallela@linaro.org Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++ tests/data/acpi/virt/IORT | 0 tests/data/acpi/virt/IORT.memhp | 0 tests/data/acpi/virt/IORT.numamem | 0 tests/data/acpi/virt/IORT.pxb | 0 5 files changed, 4 insertions(+) create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8bf..2ef211df597 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/IORT", +"tests/data/acpi/virt/IORT.memhp", +"tests/data/acpi/virt/IORT.numamem", +"tests/data/acpi/virt/IORT.pxb", diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT new file mode 100644 index 00000000000..e69de29bb2d diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.me= mhp new file mode 100644 index 00000000000..e69de29bb2d diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.= numamem new file mode 100644 index 00000000000..e69de29bb2d diff --git a/tests/data/acpi/virt/IORT.pxb b/tests/data/acpi/virt/IORT.pxb new file mode 100644 index 00000000000..e69de29bb2d --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631550599; cv=none; d=zohomail.com; s=zohoarc; b=RAkDL+MXvlKT101jvWGeABKBWUym/WlisFyK4cqvkNN6iUtEQVh8aSOYRzpbUNed/F2fdveFW6HEPUoCZEj+iXUOO2UUUUZ8OQde5D9+Dum/WdGLAN6XpIn8q0zkDpNL7Pc4ZAqUR59z3n0kgjkrNdKxbp1DN67GCvNsKR24w/U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631550599; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=V9AmhBm8UfemdEFlMs0B1qq9zHvprzdkVNNmj5F+H8g=; b=Ih5cDFqQC63nRp8oMUO2oIyIEVupvpGuymOPU/pKBWRYBbo5o5r3fmjh4ZU+MgY/nGUj8fBJVG0gzcpt8CYhfa3U8TcYOonb8VYG6aRFKS887Z1+AUfRrnVqeRiC6EYfdNlrD8CPm4FCR6s8x6UZg/R7ABpAH7mthufUInnVuoQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631550599132259.3492064939312; Mon, 13 Sep 2021 09:29:59 -0700 (PDT) Received: from localhost ([::1]:39036 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPoqD-0003tR-VO for importer@patchew.org; Mon, 13 Sep 2021 12:29:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYt-00015S-D2 for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:03 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:44656) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYr-0008Dw-0V for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:03 -0400 Received: by mail-wr1-x430.google.com with SMTP id d6so15534852wrc.11 for ; Mon, 13 Sep 2021 09:12:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:11:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=V9AmhBm8UfemdEFlMs0B1qq9zHvprzdkVNNmj5F+H8g=; b=RFvBPTt6PTMm7A1SeBXxYdVVAq/9moZeO0F4jQYQklYHHIxIjlekXgYCpBlPb0Tuxw nhntjgB6EPzQTALo2sHeD65uhEgVJPFawwu3F1JH1YFXhYkKokgocMkGROkdnYFkurMe fIxeuknqhMXiF8kGKO9ZDQEJyB3J5Zoj0FJQOrcbR7uV+QJ4YWXoLqfcHs+VW5zAUrHP MmEbIxa5uAEJUblfHUgsPg7sBtgFEvVW6OjxmUw8zDO4/uCa8m7eKp1KcEO1Yyk4zjM+ ZsY18dKrIc7q2gI8JhBEqAwbVXgU68KhtHJ7EEEcIFKw+w5LgQmtzn3Uh72Neth04p3N No4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V9AmhBm8UfemdEFlMs0B1qq9zHvprzdkVNNmj5F+H8g=; b=WsYyYOaemO5OZ0HfwQLGKziFEjlh9hWOKQRdj+SVE6TrBkaAOU3bftRqTzu0OZ/A4P HLayFMr1jOVDk1szqsRA1Pq6IFWlAgKqWqQK8MpTWI+Z8nD+M1KtmyJqUoFu3OcfckUG p72sl9j6tmFh7y+yhDnI6+M/DgGWjV6VEwPLzTb3VeARXsr0Bw700mAwgzcRtVvf36KX Nsy3m5yAWvBFIdO51kaZbR1e6p4UQTqUJdqukF3pluLnApLRRrNkrV2YQga6D6sLGiN0 jjRDh9X1rdEYf7SjomCYihLOibU6ECp9qqFficM8aWzXM4L4i6hlo6+rbe342YN5aWYw DgDw== X-Gm-Message-State: AOAM530xoeOPvO3Gg4/DypADIEpD3yfJzCmfTIXUDre+i8lTngGn7mOG hSWaDctYtpt0Bx96mr0O5lITdJTtTrgU1w== X-Google-Smtp-Source: ABdhPJxPxWyrtOSgJqYg7QoG5alpvMr844UVJKIGtKoRd3Nmd7QpSotb7MwvCJoJqt8dKxXz/3qwVA== X-Received: by 2002:adf:ed82:: with SMTP id c2mr5799163wro.203.1631549519558; Mon, 13 Sep 2021 09:11:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/23] hw/arm/virt: add ITS support in virt GIC Date: Mon, 13 Sep 2021 17:11:37 +0100 Message-Id: <20210913161144.12347-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550601081100001 Content-Type: text/plain; charset="utf-8" From: Shashi Mallela Included creation of ITS as part of virt platform GIC initialization. This Emulated ITS model now co-exists with kvm ITS and is enabled in absence of kvm irq kernel support in a platform. Signed-off-by: Shashi Mallela Reviewed-by: Peter Maydell Message-id: 20210910143951.92242-9-shashi.mallela@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 2 ++ target/arm/kvm_arm.h | 4 ++-- hw/arm/virt.c | 29 +++++++++++++++++++++++++++-- 3 files changed, 31 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 9661c466996..b461b8d261d 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -120,6 +120,7 @@ struct VirtMachineClass { MachineClass parent; bool disallow_affinity_adjustment; bool no_its; + bool no_tcg_its; bool no_pmu; bool claim_edge_triggered_timers; bool smbios_old_sys_ver; @@ -141,6 +142,7 @@ struct VirtMachineState { bool highmem; bool highmem_ecam; bool its; + bool tcg_its; bool virt; bool ras; bool mte; diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 34f8daa3775..06134549759 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -525,8 +525,8 @@ static inline const char *its_class_name(void) /* KVM implementation requires this capability */ return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL; } else { - /* Software emulation is not implemented yet */ - return NULL; + /* Software emulation based model */ + return "arm-gicv3-its"; } } =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 73e9c6bb7cb..1d59f0e59f7 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -584,6 +584,12 @@ static void create_its(VirtMachineState *vms) const char *itsclass =3D its_class_name(); DeviceState *dev; =20 + if (!strcmp(itsclass, "arm-gicv3-its")) { + if (!vms->tcg_its) { + itsclass =3D NULL; + } + } + if (!itsclass) { /* Do nothing if not supported */ return; @@ -621,7 +627,7 @@ static void create_v2m(VirtMachineState *vms) vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; } =20 -static void create_gic(VirtMachineState *vms) +static void create_gic(VirtMachineState *vms, MemoryRegion *mem) { MachineState *ms =3D MACHINE(vms); /* We create a standalone GIC */ @@ -655,6 +661,14 @@ static void create_gic(VirtMachineState *vms) nb_redist_regions); qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_c= ount); =20 + if (!kvm_irqchip_in_kernel()) { + if (vms->tcg_its) { + object_property_set_link(OBJECT(vms->gic), "sysmem", + OBJECT(mem), &error_fatal); + qdev_prop_set_bit(vms->gic, "has-lpi", true); + } + } + if (nb_redist_regions =3D=3D 2) { uint32_t redist1_capacity =3D vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST= _SIZE; @@ -2039,7 +2053,7 @@ static void machvirt_init(MachineState *machine) =20 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); =20 - create_gic(vms); + create_gic(vms, sysmem); =20 virt_cpu_post_init(vms, sysmem); =20 @@ -2742,6 +2756,12 @@ static void virt_instance_init(Object *obj) } else { /* Default allows ITS instantiation */ vms->its =3D true; + + if (vmc->no_tcg_its) { + vms->tcg_its =3D false; + } else { + vms->tcg_its =3D true; + } } =20 /* Default disallows iommu instantiation */ @@ -2791,8 +2811,13 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 2) =20 static void virt_machine_6_1_options(MachineClass *mc) { + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_6_2_options(mc); compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); + + /* qemu ITS was introduced with 6.2 */ + vmc->no_tcg_its =3D true; } DEFINE_VIRT_MACHINE(6, 1) =20 --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631550162; cv=none; d=zohomail.com; s=zohoarc; b=hDbguuID396p5Lka4+7QcXFCmTQiI1Q5IjdCA902RjT38sbvZJPEa+DkLpWWZOBYwQZZ/q67K0ua2zUd5AwNzjNYaAHvMnDYlDG0Cu5lgGKCaLZ04krP0+3VAc1/B5YsDYwx0bHjvqy8oSvVpF+3mQuSnRysVdhXfYBFTG/XB84= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631550162; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z+DQga4OxwpG9/mEVso6ZacpZ5heGCrmNENm1NfaNLY=; b=ARhQim0LmlIpQBq9rFvZK9a+iGZe9W/LF00jLs1HhC0B8ANnG0DoV/i4yy1y41hzcQ+NpOue8sA9u/a5ZVQMxLkPgKNpHBqFNDNDUXLlS1jp9lJwLd5ggkXWYzHGxJ5RCs82k2O3Xvcyd1MQz2z3XU6nq3u0qbkII1w8slg+j04= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631550162350139.7506011507054; Mon, 13 Sep 2021 09:22:42 -0700 (PDT) Received: from localhost ([::1]:48922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPojB-0008MQ-Bo for importer@patchew.org; Mon, 13 Sep 2021 12:22:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYw-00018R-1N for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:06 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:36700) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYr-0008FA-Og for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:05 -0400 Received: by mail-wr1-x42b.google.com with SMTP id g16so15581577wrb.3 for ; Mon, 13 Sep 2021 09:12:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.11.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:12:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=z+DQga4OxwpG9/mEVso6ZacpZ5heGCrmNENm1NfaNLY=; b=nFmS9GmT35wJVhZpaTjg4HI8rb4pZRHD7Hs9XQSQG3DhJNhZahkqrz5xNhrKAuwRee vnxHQIE/D2asZK1AiGESLm5JOPFesM8ZZfQsDs9Jo1YKjVw2i3hquEtsHSbaV0/j7csD tQdoX4dwnYZPhDd0ffUmytRXzYwNvlf1awKhe/DfsyX8UX2y8fBELvGGfw8XvYPXDYJo HrkOWtuj/OG2bc7PL/eluOe5xGEFTzA2qnerGHaPaeewnaTo7GXzV9yqdAAc1QDuUfSt Jfh+TA+UpYixp08RidqJz5njf73XbgkU9746tsvA0tvzJ9DDzT2CgP0Aqay/YZJr4KyT XtaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z+DQga4OxwpG9/mEVso6ZacpZ5heGCrmNENm1NfaNLY=; b=V5tVq+SilpiQCHTsyDDYQdC68LOCnnQgGTz/Pj+Yl3Q/3F1BryZiYgmRLPd956/IzC epUuocU1/vckPmsjmdrIb8LPS0vpUAsGnN8AYIFqTQ8jPVEFHMcr7iYTvEeMR1MN4mBj cvtWZBwoBeFdFE0+90JHqm9oYxqX4+hs4U+5wBGPSMpl4Ai0Zj57qXwKR4R/QnXs7uTF qRGJTa3LoremD+9GoEYQeIedObjA2RRzFMBgp85AVLBoXyeANSspzt0RovOSkQIpppoM Bch1r5JjMad+4ZLRcYh8W88VBqlcVI1p0580LUo4bDOpKn65tcHSCLNnICLec9OCwo6i RbDw== X-Gm-Message-State: AOAM533E8vNqb4Iup+ItRZ7yyAVin2MeGuV7qzBw9hrTmJtbXFDejWex Yy6bhSRHb4MAWzSm8oSkB6zIyeIPSY+MZg== X-Google-Smtp-Source: ABdhPJx3edlUWHAVtkoLtE9v0Jwk5h0XttZCpqpyVUvThDuIghFAK+7qU7VS8ec4zc3LnsoIFG//yg== X-Received: by 2002:adf:c550:: with SMTP id s16mr13596119wrf.25.1631549520350; Mon, 13 Sep 2021 09:12:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/23] tests/data/acpi/virt: Update IORT files for ITS Date: Mon, 13 Sep 2021 17:11:38 +0100 Message-Id: <20210913161144.12347-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550163459100001 Content-Type: text/plain; charset="utf-8" From: Shashi Mallela Updated expected IORT files applicable with latest GICv3 ITS changes. Full diff of new file disassembly: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180629 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * * Disassembly of tests/data/acpi/virt/IORT.pxb, Tue Jun 29 17:35:38 2021 * * ACPI Data Table [IORT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "IORT" [IO Remapping Tabl= e] [004h 0004 4] Table Length : 0000007C [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 07 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Node Count : 00000002 [028h 0040 4] Node Offset : 00000030 [02Ch 0044 4] Reserved : 00000000 [030h 0048 1] Type : 00 [031h 0049 2] Length : 0018 [033h 0051 1] Revision : 00 [034h 0052 4] Reserved : 00000000 [038h 0056 4] Mapping Count : 00000000 [03Ch 0060 4] Mapping Offset : 00000000 [040h 0064 4] ItsCount : 00000001 [044h 0068 4] Identifiers : 00000000 [048h 0072 1] Type : 02 [049h 0073 2] Length : 0034 [04Bh 0075 1] Revision : 00 [04Ch 0076 4] Reserved : 00000000 [050h 0080 4] Mapping Count : 00000001 [054h 0084 4] Mapping Offset : 00000020 [058h 0088 8] Memory Properties : [IORT Memory Access Properti= es] [058h 0088 4] Cache Coherency : 00000001 [05Ch 0092 1] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [05Dh 0093 2] Reserved : 0000 [05Fh 0095 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 [060h 0096 4] ATS Attribute : 00000000 [064h 0100 4] PCI Segment Number : 00000000 [068h 0104 1] Memory Size Limit : 00 [069h 0105 3] Reserved : 000000 [068h 0104 4] Input base : 00000000 [06Ch 0108 4] ID Count : 0000FFFF [070h 0112 4] Output Base : 00000000 [074h 0116 4] Output Reference : 00000030 [078h 0120 4] Flags (decoded below) : 00000000 Single Mapping : 0 Raw Table Data: Length 124 (0x7C) 0000: 49 4F 52 54 7C 00 00 00 00 07 42 4F 43 48 53 20 // IORT|.....BOC= HS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....B= XPC 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // ........0....= ... 0030: 00 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0040: 01 00 00 00 00 00 00 00 02 34 00 00 00 00 00 00 // .........4...= ... 0050: 01 00 00 00 20 00 00 00 01 00 00 00 00 00 00 03 // .... ........= ... 0060: 00 00 00 00 00 00 00 00 00 00 00 00 FF FF 00 00 // .............= ... 0070: 00 00 00 00 30 00 00 00 00 00 00 00 // ....0....... Signed-off-by: Shashi Mallela Acked-by: Igor Mammedov Reviewed-by: Peter Maydell Message-id: 20210910143951.92242-10-shashi.mallela@linaro.org Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ---- tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 5 files changed, 4 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 2ef211df597..dfb8523c8bf 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,5 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/virt/IORT", -"tests/data/acpi/virt/IORT.memhp", -"tests/data/acpi/virt/IORT.numamem", -"tests/data/acpi/virt/IORT.pxb", diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82= d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=3De`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=3Dp0RR91 literal 0 HcmV?d00001 diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.me= mhp index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82= d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=3De`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=3Dp0RR91 literal 0 HcmV?d00001 diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.= numamem index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82= d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=3De`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=3Dp0RR91 literal 0 HcmV?d00001 diff --git a/tests/data/acpi/virt/IORT.pxb b/tests/data/acpi/virt/IORT.pxb index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82= d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=3De`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=3Dp0RR91 literal 0 HcmV?d00001 --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631551359; cv=none; d=zohomail.com; s=zohoarc; b=AA5BmvmqsEXJsxBdJEpqUJiAKO5uNH9pmQGjoihBzB6Dq7mtrkYZnvFN5nb0myk3lV0rpLS7qNTkrFfekQ+guB2MyugmBosEmnmNI9QvkvFygnVTQeXytyk3zWV6kuXDijZfaysFD2PodTaKpyxfbuRSr5YQpl7VYSbhipx37VQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631551359; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Zz+XXnR82d1+nOU34apWR43o+z8/4Rka6z5QRXYMUMw=; b=JzdYFd3YjyOCDzVP3oeFnduERHTIOQgxWARD4T0Q2gknDaPlfrbqosIkXh0nqtgPiTGT87CxG/1UTJrnWy+yAD/L8x1ugL9iPofHSlnrwYYA3Ps06EjQr4bAkspnSJA5cvXriYWbDcoyZ8wA6J5MqKc47K3argQmfIrX1qP8RvQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631551359237150.25451602690464; Mon, 13 Sep 2021 09:42:39 -0700 (PDT) Received: from localhost ([::1]:41662 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPp2U-0008RJ-6t for importer@patchew.org; Mon, 13 Sep 2021 12:42:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60954) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYv-00018Q-PF for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:06 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:36788) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYs-0008Fb-Gu for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:05 -0400 Received: by mail-wm1-x331.google.com with SMTP id l18-20020a05600c4f1200b002f8cf606262so7433320wmq.1 for ; Mon, 13 Sep 2021 09:12:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.12.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:12:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Zz+XXnR82d1+nOU34apWR43o+z8/4Rka6z5QRXYMUMw=; b=io7zhc0GpMlxRX6kKQBoywkJqsUdLY6zaM9R5PMQVzE0V9u+VHAa16HPKMZg64datY 1OhOJedclpUnfkzmi+OW5sPRdNO+bcAnFX5uSkL+j8IRfx36YAtQfTe7NvHwp0mNKpjM /iHk+/ClRy8KQuOc5tjiMUFoNN85BuqIPh6rcGsgBteWwjvuT886XwMQlOU4Xqfpkf7G 7rc7r1PUgMe3VRB0i4MUgM6iFGQ1CWx0TNpcT7AsXo02DjCAj9emL1MN6DLuBapDtyHo muvzUy9Ay9yDflW5NBqg2pCKnFo1Kj5DUuV848ELt0R93hTkmVL+xmgNhN1/dnMmOTqC k0Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Zz+XXnR82d1+nOU34apWR43o+z8/4Rka6z5QRXYMUMw=; b=qIqXJuD//CkSgIbLfVVeMUUzTktJycZ/4y+R+LevChiwcvyjk9AI8/Kyd/xJQJq7Yy AaI0ASKMfScqW84UHW7nt8aDXwDDp8PLue1ISSJcG2gjQ1+KKcMaubYswwH+jhrPOILs AG++MQXwhqvLm/0tyF+uFf2DVD4ozoH8OU44pAaYNEnFhRiJYp4AqX4dYCunUCiYfsAT P740T43tcmrFqg1XW7iD2+80EYxjrU94jMUA1Fx6WGoGnRqnshFuOJQQ+pIF4QF2bXiX yA5Jd2JAwwOv7YndzNj9+JPBsgakn9GgvfwfDXWcV6p8cvusYyKFrkMxmQzMne1yjRfJ XTOw== X-Gm-Message-State: AOAM5314QNUb6q2v0wwyh/IA/wCCKY89qX4dtFJ7NpQDypeX94oSdAgt Q4aNRS8gCMCBkglOW1R99ZkAtHmHkLYqSg== X-Google-Smtp-Source: ABdhPJw6gZTJHjWPDCVigV5WoDssNH7f+LYuDCo7np0x6eHY+c1PPafLwSnK/ZqsTXwP7gK0gHuuEg== X-Received: by 2002:a1c:e915:: with SMTP id q21mr12393266wmc.180.1631549521199; Mon, 13 Sep 2021 09:12:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/23] target/arm: Take an exception if PSTATE.IL is set Date: Mon, 13 Sep 2021 17:11:39 +0100 Message-Id: <20210913161144.12347-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631551361109100001 Content-Type: text/plain; charset="utf-8" In v8A, the PSTATE.IL bit is set for various kinds of illegal exception return or mode-change attempts. We already set PSTATE.IL (or its AArch32 equivalent CPSR.IL) in all those cases, but we weren't implementing the part of the behaviour where attempting to execute an instruction with PSTATE.IL takes an immediate exception with an appropriate syndrome value. Add a new TB flags bit tracking PSTATE.IL/CPSR.IL, and generate code to take an exception instead of whatever the instruction would have been. PSTATE.IL and CPSR.IL change only on exception entry, attempted exception exit, and various AArch32 mode changes via cpsr_write(). These places generally already rebuild the hflags, so the only place we need an extra rebuild_hflags call is in the illegal-return codepath of the AArch64 exception_return helper. Signed-off-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Richard Henderson Message-id: 20210821195958.41312-2-richard.henderson@linaro.org Message-Id: <20210817162118.24319-1-peter.maydell@linaro.org> Reviewed-by: Richard Henderson [rth: Added missing returns; set IL bit in syndrome] Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/syndrome.h | 5 +++++ target/arm/translate.h | 2 ++ target/arm/helper-a64.c | 1 + target/arm/helper.c | 8 ++++++++ target/arm/translate-a64.c | 11 +++++++++++ target/arm/translate.c | 21 +++++++++++++++++++++ 7 files changed, 49 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6a987f65e41..fb0ef1ee2c9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3455,6 +3455,7 @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) +FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1) =20 /* * Bit usage when in AArch32 state, both A- and M-profile. diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 8dd88a0cb17..f30f4130a27 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -277,4 +277,9 @@ static inline uint32_t syn_wfx(int cv, int cond, int ti= , bool is_16bit) (cv << 24) | (cond << 20) | ti; } =20 +static inline uint32_t syn_illegalstate(void) +{ + return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/target/arm/translate.h b/target/arm/translate.h index 8636c20c3b4..605d1f2e33d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -98,6 +98,8 @@ typedef struct DisasContext { bool hstr_active; /* True if memory operations require alignment */ bool align_mem; + /* True if PSTATE.IL is set */ + bool pstate_il; /* * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 26f79f9141a..19445b3c947 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1071,6 +1071,7 @@ illegal_return: if (!arm_singlestep_active(env)) { env->pstate &=3D ~PSTATE_SS; } + helper_rebuild_hflags_a64(env, cur_el); qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: " "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc= ); } diff --git a/target/arm/helper.c b/target/arm/helper.c index a7ae78146d4..b210da2bc26 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13462,6 +13462,10 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMStat= e *env, int fp_el, DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); } =20 + if (env->uncached_cpsr & CPSR_IL) { + DP_TBFLAG_ANY(flags, PSTATE__IL, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 @@ -13556,6 +13560,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMStat= e *env, int el, int fp_el, } } =20 + if (env->pstate & PSTATE_IL) { + DP_TBFLAG_ANY(flags, PSTATE__IL, 1); + } + if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { /* * Set MTE_ACTIVE if any access may be Checked, and leave clear diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 422e2ac0c96..230cc8d83bf 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14662,6 +14662,16 @@ static void disas_a64_insn(CPUARMState *env, Disas= Context *s) s->fp_access_checked =3D false; s->sve_access_checked =3D false; =20 + if (s->pstate_il) { + /* + * Illegal execution state. This has priority over BTI + * exceptions, but comes after instruction abort exceptions. + */ + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(s)); + return; + } + if (dc_isar_feature(aa64_bti, s)) { if (s->base.num_insns =3D=3D 1) { /* @@ -14780,6 +14790,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, #endif dc->fp_excp_el =3D EX_TBFLAG_ANY(tb_flags, FPEXC_EL); dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); + dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->sve_excp_el =3D EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sve_len =3D (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16; dc->pauth_active =3D EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); diff --git a/target/arm/translate.c b/target/arm/translate.c index 24b7f49d767..435c6597239 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9090,6 +9090,16 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) return; } =20 + if (s->pstate_il) { + /* + * Illegal execution state. This has priority over BTI + * exceptions, but comes after instruction abort exceptions. + */ + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(s)); + return; + } + if (cond =3D=3D 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we * choose to UNDEF. In ARMv5 and above the space is used @@ -9358,6 +9368,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) #endif dc->fp_excp_el =3D EX_TBFLAG_ANY(tb_flags, FPEXC_EL); dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); + dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); =20 if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled =3D 1; @@ -9621,6 +9632,16 @@ static void thumb_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) } dc->insn =3D insn; =20 + if (dc->pstate_il) { + /* + * Illegal execution state. This has priority over BTI + * exceptions, but comes after instruction abort exceptions. + */ + gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(dc)); + return; + } + if (dc->eci) { /* * For M-profile continuable instructions, ECI/ICI handling --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631551488; cv=none; d=zohomail.com; s=zohoarc; b=lTvha/3zsgUyS61eP7HzkiqJfBqeR+M69tHN8p0n64Rjfnhje08fPOVro+1Oc80EnsT5T5l3nQWKQPXa5xqKz377Nzu6DnLkJ5BZTeggwMmZkN8hb14wu18urfuHMmfBXG8PQLTsZF2ZnYP2cdSVttXGaAwGJoO+25EB9btWWAw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631551488; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=k5Qpc8QmGY44GxBrZeg5/5PM08qjaMO2Ak5NUV/HCVI=; b=WCK1Mn6li4DCU28PDT4stNp9/3Nind/BfsAzExIIqhStqmIk8LBfACAMlcFrxv9Op57HuJU0ZVI04bXAyxMS6GXHwwBJVIRIsb9WryYtFOkWGGaQw9ZMNcdxJv2Yj9uRSbg96P978QIl6hTGmJTBkkq4SR4PVNRgLCyFHeXYhrs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631551488515440.9022667110311; Mon, 13 Sep 2021 09:44:48 -0700 (PDT) Received: from localhost ([::1]:47018 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPp4Z-0003vX-Ey for importer@patchew.org; Mon, 13 Sep 2021 12:44:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYw-00018V-IN for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:06 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:46981) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYt-0008Fs-E7 for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:06 -0400 Received: by mail-wr1-x434.google.com with SMTP id x6so15528758wrv.13 for ; Mon, 13 Sep 2021 09:12:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.12.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:12:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=k5Qpc8QmGY44GxBrZeg5/5PM08qjaMO2Ak5NUV/HCVI=; b=hu6/E3hwSTLaHdfOCPKZ5wDO7aDHIpMMQJlYau0q8mm0EK+OmXUgXd3hTWd/TvrVqb gUWKy78u1MQflytcEOEFudoGskFz2ds2uukYfgIy0NCK/DEaqmu0KSS0algIi/V9GwQ+ FmEFhoSQbpsNQlzZ/uYv2mK3S5c2ez+W6aed7NuH0apyJYGNIT6bCwVnEhrCS9zKXNtm dsiytOlU4y3MFOJ7RibxQpZysMoJAFIOpcZK2qJO0Hr8vaCKhBRAiTVcUSp4aVpwj5hP nXz0u8w6ticw91GqXd5pdCmpg+SHXFZavhWtr3/Px3xk8HpBT/CT0luP83vw27tN2wWK JPOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k5Qpc8QmGY44GxBrZeg5/5PM08qjaMO2Ak5NUV/HCVI=; b=bwfMv/A4swFdy0kyrn5pCNxODePLJm8JZh3R3fWGWta8v3OhHt+FF+aIHrXssHoA4u BuIP7dS1MIrW6/Fr00G+utBve5bMaXT2cSUfEGpyY+CbkZeznDHqZN97aYuPd94DTadi YQyR59+LW5J9bpZRLDMkxKyLgmHd80VFmNK+FcnZdMX2mEnWd1SyvBEArFqysfYnR6Ra JkeUQynyooCfO6qvCyPmyCzsaPERNOktX7MmAflbojrY/DeB9BCLmKMw+OGOPRaF8qOH vhKuVsWHFTrHpNHR31Jb6BKBz6KmM7Ud9y1dqHuslUzgVtUwRB9Ob/xFCoOrULpTSxAn ZHtQ== X-Gm-Message-State: AOAM533v0Xv5bfNkPBx7dJFENQMM506eiJshkOh8DTBU/QgMtC3IXeE3 nDbMgHRf/vTM7zGg2ovwCAvD8FQ3/oziKQ== X-Google-Smtp-Source: ABdhPJxbWIQg5rZqFHfz0tSrS+KDULqcl9mXEQih3F/G8YdEsRS52cFtLxqk/UwPhLrMZkfQcU6ePg== X-Received: by 2002:a5d:4a46:: with SMTP id v6mr3044046wrs.262.1631549522092; Mon, 13 Sep 2021 09:12:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/23] target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn Date: Mon, 13 Sep 2021 17:11:40 +0100 Message-Id: <20210913161144.12347-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631551489170100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson It is confusing to have different exits from translation for various conditions in separate functions. Merge disas_a64_insn into its only caller. Standardize on the "s" name for the DisasContext, as the code from disas_a64_insn had more instances. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210821195958.41312-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 224 ++++++++++++++++++------------------- 1 file changed, 109 insertions(+), 115 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 230cc8d83bf..333bc836b27 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14649,113 +14649,6 @@ static bool btype_destination_ok(uint32_t insn, b= ool bt, int btype) return false; } =20 -/* C3.1 A64 instruction index by encoding */ -static void disas_a64_insn(CPUARMState *env, DisasContext *s) -{ - uint32_t insn; - - s->pc_curr =3D s->base.pc_next; - insn =3D arm_ldl_code(env, s->base.pc_next, s->sctlr_b); - s->insn =3D insn; - s->base.pc_next +=3D 4; - - s->fp_access_checked =3D false; - s->sve_access_checked =3D false; - - if (s->pstate_il) { - /* - * Illegal execution state. This has priority over BTI - * exceptions, but comes after instruction abort exceptions. - */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(s)); - return; - } - - if (dc_isar_feature(aa64_bti, s)) { - if (s->base.num_insns =3D=3D 1) { - /* - * At the first insn of the TB, compute s->guarded_page. - * We delayed computing this until successfully reading - * the first insn of the TB, above. This (mostly) ensures - * that the softmmu tlb entry has been populated, and the - * page table GP bit is available. - * - * Note that we need to compute this even if btype =3D=3D 0, - * because this value is used for BR instructions later - * where ENV is not available. - */ - s->guarded_page =3D is_guarded_page(env, s); - - /* First insn can have btype set to non-zero. */ - tcg_debug_assert(s->btype >=3D 0); - - /* - * Note that the Branch Target Exception has fairly high - * priority -- below debugging exceptions but above most - * everything else. This allows us to handle this now - * instead of waiting until the insn is otherwise decoded. - */ - if (s->btype !=3D 0 - && s->guarded_page - && !btype_destination_ok(insn, s->bt, s->btype)) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_btitrap(s->btype), - default_exception_el(s)); - return; - } - } else { - /* Not the first insn: btype must be 0. */ - tcg_debug_assert(s->btype =3D=3D 0); - } - } - - switch (extract32(insn, 25, 4)) { - case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ - unallocated_encoding(s); - break; - case 0x2: - if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) { - unallocated_encoding(s); - } - break; - case 0x8: case 0x9: /* Data processing - immediate */ - disas_data_proc_imm(s, insn); - break; - case 0xa: case 0xb: /* Branch, exception generation and system insns */ - disas_b_exc_sys(s, insn); - break; - case 0x4: - case 0x6: - case 0xc: - case 0xe: /* Loads and stores */ - disas_ldst(s, insn); - break; - case 0x5: - case 0xd: /* Data processing - register */ - disas_data_proc_reg(s, insn); - break; - case 0x7: - case 0xf: /* Data processing - SIMD and floating point */ - disas_data_proc_simd_fp(s, insn); - break; - default: - assert(FALSE); /* all 15 cases should be handled above */ - break; - } - - /* if we allocated any temporaries, free them here */ - free_tmp_a64(s); - - /* - * After execution of most insns, btype is reset to 0. - * Note that we set btype =3D=3D -1 when the insn sets btype. - */ - if (s->btype > 0 && s->base.is_jmp !=3D DISAS_NORETURN) { - reset_btype(s); - } -} - static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) { @@ -14857,10 +14750,11 @@ static void aarch64_tr_insn_start(DisasContextBas= e *dcbase, CPUState *cpu) =20 static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) { - DisasContext *dc =3D container_of(dcbase, DisasContext, base); + DisasContext *s =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; + uint32_t insn; =20 - if (dc->ss_active && !dc->pstate_ss) { + if (s->ss_active && !s->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either * a) we just took an exception to an EL which is being debugged @@ -14871,14 +14765,114 @@ static void aarch64_tr_translate_insn(DisasConte= xtBase *dcbase, CPUState *cpu) * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(dc->base.num_insns =3D=3D 1); - gen_swstep_exception(dc, 0, 0); - dc->base.is_jmp =3D DISAS_NORETURN; - } else { - disas_a64_insn(env, dc); + assert(s->base.num_insns =3D=3D 1); + gen_swstep_exception(s, 0, 0); + s->base.is_jmp =3D DISAS_NORETURN; + return; } =20 - translator_loop_temp_check(&dc->base); + s->pc_curr =3D s->base.pc_next; + insn =3D arm_ldl_code(env, s->base.pc_next, s->sctlr_b); + s->insn =3D insn; + s->base.pc_next +=3D 4; + + s->fp_access_checked =3D false; + s->sve_access_checked =3D false; + + if (s->pstate_il) { + /* + * Illegal execution state. This has priority over BTI + * exceptions, but comes after instruction abort exceptions. + */ + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(s)); + return; + } + + if (dc_isar_feature(aa64_bti, s)) { + if (s->base.num_insns =3D=3D 1) { + /* + * At the first insn of the TB, compute s->guarded_page. + * We delayed computing this until successfully reading + * the first insn of the TB, above. This (mostly) ensures + * that the softmmu tlb entry has been populated, and the + * page table GP bit is available. + * + * Note that we need to compute this even if btype =3D=3D 0, + * because this value is used for BR instructions later + * where ENV is not available. + */ + s->guarded_page =3D is_guarded_page(env, s); + + /* First insn can have btype set to non-zero. */ + tcg_debug_assert(s->btype >=3D 0); + + /* + * Note that the Branch Target Exception has fairly high + * priority -- below debugging exceptions but above most + * everything else. This allows us to handle this now + * instead of waiting until the insn is otherwise decoded. + */ + if (s->btype !=3D 0 + && s->guarded_page + && !btype_destination_ok(insn, s->bt, s->btype)) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_btitrap(s->btype), + default_exception_el(s)); + return; + } + } else { + /* Not the first insn: btype must be 0. */ + tcg_debug_assert(s->btype =3D=3D 0); + } + } + + switch (extract32(insn, 25, 4)) { + case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ + unallocated_encoding(s); + break; + case 0x2: + if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) { + unallocated_encoding(s); + } + break; + case 0x8: case 0x9: /* Data processing - immediate */ + disas_data_proc_imm(s, insn); + break; + case 0xa: case 0xb: /* Branch, exception generation and system insns */ + disas_b_exc_sys(s, insn); + break; + case 0x4: + case 0x6: + case 0xc: + case 0xe: /* Loads and stores */ + disas_ldst(s, insn); + break; + case 0x5: + case 0xd: /* Data processing - register */ + disas_data_proc_reg(s, insn); + break; + case 0x7: + case 0xf: /* Data processing - SIMD and floating point */ + disas_data_proc_simd_fp(s, insn); + break; + default: + assert(FALSE); /* all 15 cases should be handled above */ + break; + } + + /* if we allocated any temporaries, free them here */ + free_tmp_a64(s); + + /* + * After execution of most insns, btype is reset to 0. + * Note that we set btype =3D=3D -1 when the insn sets btype. + */ + if (s->btype > 0 && s->base.is_jmp !=3D DISAS_NORETURN) { + reset_btype(s); + } + + translator_loop_temp_check(&s->base); } =20 static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631550359; cv=none; d=zohomail.com; s=zohoarc; b=NTOP0GreGuQiuo6SFS2IU6nqHDH/3hlKyx/zITv1nstkEIALAj12sWxxy2N6hSFv0ouHAjoTC+RROagtfOg0x6IS9ii+itjvj0cweREXiG3ECDfKrZKJwLtKWH1TM/Izwj2RgFui3PUq19j4qEl/YolNPrerbe3snhCPp/hSUPw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631550359; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oZqbaO7c6QCloZzkB19gQ8ommdJiJOBGAsKV4oV9j4I=; b=U3orJqwYhfULgTXD8tlzPHEBeJjUuLM733xr6tWF45HyYbP+IqQ+g3U3qyU9c2btyQr9NuCvO+XkbUX6QyCzl02koKOyBDUKS5d3IzltWy5rMTkugbN8tUj84yheJyzQJPuW1i2xOlWtIXBlNQsP20o5oqqlj9tGLsxyPsORspI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631550359213878.3029191070203; Mon, 13 Sep 2021 09:25:59 -0700 (PDT) Received: from localhost ([::1]:57458 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPomM-0005ca-0p for importer@patchew.org; Mon, 13 Sep 2021 12:25:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYw-00018U-Hq for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:06 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:46982) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYu-0008GQ-5X for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:06 -0400 Received: by mail-wr1-x435.google.com with SMTP id x6so15528784wrv.13 for ; Mon, 13 Sep 2021 09:12:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.12.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:12:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oZqbaO7c6QCloZzkB19gQ8ommdJiJOBGAsKV4oV9j4I=; b=CMLN2hJ+SjF3NGGpwqXhStsEXAd4XrsOEmdlbPO5tEycEXFyfwd/4436DzrVMTwKh9 V63OGlm6+Q3HxFKjd32D2ndl6fxD7uZmjmwnLAp5U+DIOBq+QL5YnxVrWAfh3PJajYa3 0OLDvCdXs+mffWe0bbBN7uJwy0mBtyUirDK84KJ5+fBKwIB5dYcqWpcOKsFY0e5iTrzx FIQ5ukA2wX8ZB7JRnA11NZlZZtek9YLUzk+wYuKt/cywXyS2p8Kd2rycg564YgvlTjTP vlpCLGxvEA7WaIbhBSLx70IkaFUkFbrlNxBqmhMuAvoo1966PTqQFvtcL3sg7UwUHU+A 2J1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oZqbaO7c6QCloZzkB19gQ8ommdJiJOBGAsKV4oV9j4I=; b=iSaQ6p/7rW8ryrxUT2WZd8TQ5rmKgMq1CRg5m4uB3PvjIcv5Tf6UuyLz80algGVnhN XKk/HQxb9BQU/HquRfx9sMnOFxW+R99hhzEDZd8hTHcJdHzJS3b0pC5bapKVBKVC9uC1 MrLkgFz1VtwDuKey+rlQXziVfkY1kG9LOAkRX8nvCeGmiiUJFKl/uDMHkLofZhxR3SVI 6Oi75fdimd+86EPJ0zWyt/6/jZ2h3zZQSPvV/dM7XEEsKlTAADFeEKEpAj2Zms7glKjd QXfzYOm1Vt8LNkHynOlRW8b/JPnOyp+txVEtJ6Wh2NIATcPf9jmJowpeg7FtQTnHGTXs q4EA== X-Gm-Message-State: AOAM532nDzZDOxhN1T2vc6FulO5KivrVhMl/ki3qqqKevmMPGZTr2/OK rBGxE13u95M8dKACknRqPDIAm2G6YrSBWg== X-Google-Smtp-Source: ABdhPJxRMiOHXVjduOTp9iS5TAYnIJwy+c7IPWxktzEFnhgZjd2soJo7YA5dqltlM6foXxBtPoXqUw== X-Received: by 2002:a5d:6902:: with SMTP id t2mr13005949wru.23.1631549522691; Mon, 13 Sep 2021 09:12:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/23] qdev: Support marking individual buses as 'full' Date: Mon, 13 Sep 2021 17:11:41 +0100 Message-Id: <20210913161144.12347-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550361054100003 Content-Type: text/plain; charset="utf-8" By default, QEMU will allow devices to be plugged into a bus up to the bus class's device count limit. If the user creates a device on the command line or via the monitor and doesn't explicitly specify the bus to plug it in, QEMU will plug it into the first non-full bus that it finds. This is fine in most cases, but some machines have multiple buses of a given type, some of which are dedicated to on-board devices and some of which have an externally exposed connector for user-pluggable devices. One example is I2C buses. Provide a new function qbus_mark_full() so that a machine model can mark this kind of "internal only" bus as 'full' after it has created all the devices that should be plugged into that bus. The "find a non-full bus" algorithm will then skip the internal-only bus when looking for a place to plug in user-created devices. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210903151435.22379-2-peter.maydell@linaro.org --- include/hw/qdev-core.h | 24 ++++++++++++++++++++++++ softmmu/qdev-monitor.c | 7 ++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index bafc311bfa1..762f9584dde 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -264,6 +264,7 @@ struct BusState { HotplugHandler *hotplug_handler; int max_index; bool realized; + bool full; int num_children; =20 /* @@ -798,6 +799,29 @@ static inline bool qbus_is_hotpluggable(BusState *bus) return bus->hotplug_handler; } =20 +/** + * qbus_mark_full: Mark this bus as full, so no more devices can be attach= ed + * @bus: Bus to mark as full + * + * By default, QEMU will allow devices to be plugged into a bus up + * to the bus class's device count limit. Calling this function + * marks a particular bus as full, so that no more devices can be + * plugged into it. In particular this means that the bus will not + * be considered as a candidate for plugging in devices created by + * the user on the commandline or via the monitor. + * If a machine has multiple buses of a given type, such as I2C, + * where some of those buses in the real hardware are used only for + * internal devices and some are exposed via expansion ports, you + * can use this function to mark the internal-only buses as full + * after you have created all their internal devices. Then user + * created devices will appear on the expansion-port bus where + * guest software expects them. + */ +static inline void qbus_mark_full(BusState *bus) +{ + bus->full =3D true; +} + void device_listener_register(DeviceListener *listener); void device_listener_unregister(DeviceListener *listener); =20 diff --git a/softmmu/qdev-monitor.c b/softmmu/qdev-monitor.c index a304754ab91..0705f008466 100644 --- a/softmmu/qdev-monitor.c +++ b/softmmu/qdev-monitor.c @@ -435,7 +435,12 @@ static DeviceState *qbus_find_dev(BusState *bus, char = *elem) =20 static inline bool qbus_is_full(BusState *bus) { - BusClass *bus_class =3D BUS_GET_CLASS(bus); + BusClass *bus_class; + + if (bus->full) { + return true; + } + bus_class =3D BUS_GET_CLASS(bus); return bus_class->max_dev && bus->num_children >=3D bus_class->max_dev; } =20 --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1631551685; cv=none; d=zohomail.com; s=zohoarc; b=hHho7ij1WJ7AzQokRCGuwhH7o5KbRs7YOPdi0EYgbYO2fb07miblgSP34EkO8jRkix6phkEypYkWOEA91Qfp+MEbIRxanoBHNY/gMAG/PWCaiPEOBp4RcrdBk4RXh9GwGWTeag6Xg7kjAcyCeWGCvwz4IbpIALHzsLvwZqNZ6fA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631551685; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=K6n3SsAGE/Xg6IHlS+ExdQzk++OHTVIMQJzivKpwBXE=; b=TX8qFGgBP6BnL6cPGd/Uvda3gGFNk0xDZ6Tg6/P62cT0kqo1KOZbUNlInnSIAVEd+kZmCzfcNSq1G4WO/qLH1Ota4TuvsLE3mPlMAVZ85v0mEbIpv2nQv17Ow50CZncLIdichRJv3JPOpS91JDH2A/e53NqJ1ypibd1jpPNjj5g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631551685942669.8770688836253; Mon, 13 Sep 2021 09:48:05 -0700 (PDT) Received: from localhost ([::1]:51428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPp7k-0007I6-Pu for importer@patchew.org; Mon, 13 Sep 2021 12:48:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPoYz-0001C9-Qr for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:10 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:41972) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPoYv-0008HO-Hq for qemu-devel@nongnu.org; Mon, 13 Sep 2021 12:12:08 -0400 Received: by mail-wr1-x432.google.com with SMTP id w29so14784125wra.8 for ; Mon, 13 Sep 2021 09:12:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.12.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:12:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=K6n3SsAGE/Xg6IHlS+ExdQzk++OHTVIMQJzivKpwBXE=; b=IwLPJQW4xaiXNBPM9+ZeOxSkmfk9W3fZK2s6Q0wfDfsXdAANJD9OorMchQJeAJphf5 VA5c9/Bz15t8RHCrLMDgd0447oSWpySdjdq79tABiFNkoMWAzkHHePu3PVXoUhjolZtC 0y1oVFiSmd7Wl/SwcoRRiZj9fqBlqYTVe0otxdZJEGm0S5Uof+/CSKNgrOVh1pDkWnDP tSmdKAk8rcmdratvpVP5x4dd4XxchTn1alC4aXE1JbRKGnH8g78NvXEZeJ9YghyZEJtw hOSU9XXdTz5RyD0Lhsm7BjTM9IKyO+WMleQOyIgJJHYduIRQKZ5OcCmCLveT1hX5g6zq XmmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K6n3SsAGE/Xg6IHlS+ExdQzk++OHTVIMQJzivKpwBXE=; b=zmQBhGt8pZu3OJRCnDJlTZLcrkoypdIpQDveSEKKA4xV2RQdTSJpIoWcQWkrppJ5i2 G1zfshuMmMroNrqeUMWYGtYbgRyobomC2TPQHLOX1z52QB6wFcF038RrXl9PnLlqbLIv vuBEZiqn/NStdHufDBowTOTrdb0lZ7QOScYp15ZNKrIaiXYbbKFGbspuE4XaKpmxlACF g8td4B1FCKxB9vsRHlVxTMd72VtQdMypIcjUcjOrdY2hXYEAxov+i40KaMcLkGU7MI6X YZhfTl0as+i8ROaUMyGL8wDat5F4Aai+jx4v4eoz3Z5s6eKW3YQZ5fZ54QECItDI4XrC XBmg== X-Gm-Message-State: AOAM531/Ga2KTRGFiRsY8ppk5Xsr8yF5c901oucjj01wXK7bkYF4Xuy+ M3vi5vX+M+98S8ca6se0goSWZ+DIyeJAnQ== X-Google-Smtp-Source: ABdhPJxkkJ5BQm6RIKFiIZCvf8a/Qp5vN4h9B0pDBoT7xTJeKaC02up2K0ySISzjUh0hjWINwjdnEA== X-Received: by 2002:a5d:6dd0:: with SMTP id d16mr13242136wrz.177.1631549523533; Mon, 13 Sep 2021 09:12:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/23] hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn Date: Mon, 13 Sep 2021 17:11:42 +0100 Message-Id: <20210913161144.12347-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631551687620100001 Content-Type: text/plain; charset="utf-8" The mps2-tz boards use a data-driven structure to create the devices that sit behind peripheral protection controllers. Currently the functions which create these devices are passed an 'opaque' pointer which is always the address within the machine struct of the device to create, and some "all devices need this" information like irqs and addresses. If a specific device needs more information than this, it is currently not possible to pass that through from the PPCInfo data structure. Add support for passing an extra data parameter, so that we can more flexibly handle the needs of specific device types. To provide some type-safety we make this extra parameter a pointer to a union (which initially has no members). In particular, we would like to be able to indicate which of the i2c controllers are for on-board devices only and which are connected to the external 'shield' expansion port; a subsequent patch will use this mechanism for that purpose. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210903151435.22379-3-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index e23830f4b7d..746ba3cc59e 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -373,6 +373,10 @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms= , int irqno) } } =20 +/* Union describing the device-specific extra data we pass to the devfn. */ +typedef union PPCExtraData { +} PPCExtraData; + /* Most of the devices in the AN505 FPGA image sit behind * Peripheral Protection Controllers. These data structures * define the layout of which devices sit behind which PPCs. @@ -382,7 +386,8 @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms,= int irqno) */ typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs); + const int *irqs, + const PPCExtraData *extradata); =20 typedef struct PPCPortInfo { const char *name; @@ -391,6 +396,7 @@ typedef struct PPCPortInfo { hwaddr addr; hwaddr size; int irqs[3]; /* currently no device needs more IRQ lines than this */ + PPCExtraData extradata; /* to pass device-specific info to the devfn */ } PPCPortInfo; =20 typedef struct PPCInfo { @@ -401,7 +407,8 @@ typedef struct PPCInfo { static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, + const PPCExtraData *extradata) { /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, * and return a pointer to its MemoryRegion. @@ -417,7 +424,7 @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState = *mms, =20 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrad= ata) { /* The irq[] array is tx, rx, combined, in that order */ MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); @@ -441,7 +448,7 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms,= void *opaque, =20 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrada= ta) { MPS2SCC *scc =3D opaque; DeviceState *sccdev; @@ -465,7 +472,7 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, = void *opaque, =20 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extr= adata) { MPS2FPGAIO *fpgaio =3D opaque; MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); @@ -480,7 +487,8 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mm= s, void *opaque, =20 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, + const PPCExtraData *extradata) { SysBusDevice *s; NICInfo *nd =3D &nd_table[0]; @@ -500,7 +508,8 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *m= ms, void *opaque, =20 static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, + const PPCExtraData *extradata) { /* * The AN524 makes the ethernet and USB share a PPC port. @@ -543,7 +552,7 @@ static MemoryRegion *make_eth_usb(MPS2TZMachineState *m= ms, void *opaque, =20 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrada= ta) { TZMPC *mpc =3D opaque; int i =3D mpc - &mms->mpc[0]; @@ -615,7 +624,7 @@ static void remap_irq_fn(void *opaque, int n, int level) =20 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrada= ta) { /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ PL080State *dma =3D opaque; @@ -672,7 +681,7 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, = void *opaque, =20 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrada= ta) { /* * The AN505 has five PL022 SPI controllers. @@ -694,7 +703,7 @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, = void *opaque, =20 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrada= ta) { ArmSbconI2CState *i2c =3D opaque; SysBusDevice *s; @@ -707,7 +716,7 @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms, = void *opaque, =20 static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrada= ta) { PL031State *pl031 =3D opaque; SysBusDevice *s; @@ -1084,7 +1093,7 @@ static void mps2tz_common_init(MachineState *machine) } =20 mr =3D pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->si= ze, - pinfo->irqs); + pinfo->irqs, &pinfo->extradata); portname =3D g_strdup_printf("port[%d]", port); object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), &error_fatal); --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.12.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:12:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eNgBTqHB+fi0Y+oESbrufAW/CqyPi3d87ouK5WTfuQs=; b=O1Py2peuEhWUQ3h2WTGKkH6HNDF2BAMAOnkm7QFF2sZwsbJXcQMvihdKY8mAWiLLIQ IkzuKBxecGRRbCSX0ebw9CtBe4HrGzfXeMMtmavpQFu46sQMbwPrwu6Lg2UuOZvuVzve RIm0rEh2s5dMSP465AuP4Ak3VRdAfzKdpoZblIS4mDK/WAgWZ+F/sdmsWdkeQ2UKBiCo eaUsbrgdMFIm26HWRLfJKclt53pyDdRnzoDhV3fRpIuZiIEP0Ul+uEA5GRK+VuwhyE1j uhkLsjzBtPkJA/f4dcQ3dQ09hw9ipvntl2pEn6+DgYnqs7YJERePDn1v5hRLoezS9Hsx L0AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eNgBTqHB+fi0Y+oESbrufAW/CqyPi3d87ouK5WTfuQs=; b=Ptg4XYVbya54hPlNWZSJ6g3DTvP1Bomqy11A+6jFsSlu5RN4Bval0m9p70uRUFMq1o NkAjux1efqpVEpQiYnrNbSIfiQ4IjHmpCwSe+dtBTkt+CuxffFk4TC2M9VNhyBbCbooD 6PO8/ClKuouy/9FXMkU9975u4iwyBPMaaPNwOGE6YVV8r+1ExKVlf3A6Lhw7i2kl1giW gAz3RfNrGHgkkRH+k981lGfSLZCrGDFlZBHp28hAtaD8mEY9ei1vtH2ZF/8B/2uWQygT Oeq2xn97/ZYmjzT8iZk+gPf1KEoKV5jzlZfRPIjm4bIxoTUL8AThNr1qU+s07mx/UaLI Th5g== X-Gm-Message-State: AOAM532V79iEW9VxsrdvS5pwg7cJ448IpmwVIseAqG1yt48qPXuScP1a PJGhOMF16xTlt+fHmY2jJ0GUGaWVB3u/iA== X-Google-Smtp-Source: ABdhPJyrhkJn/hVd8yW2TPXWV1v15gvjYbWOkrW3oFRlxSOtymQ/VJIrQjnfiKCewEBL2dLVVKnZXQ== X-Received: by 2002:a5d:4eca:: with SMTP id s10mr1064346wrv.116.1631549524245; Mon, 13 Sep 2021 09:12:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/23] hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' Date: Mon, 13 Sep 2021 17:11:43 +0100 Message-Id: <20210913161144.12347-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550802730100001 Content-Type: text/plain; charset="utf-8" The various MPS2 boards have multiple I2C buses: typically a bus dedicated to the audio configuration, one for the LCD touchscreen controller, one for a DDR4 EEPROM, and two which are connected to the external Shield expansion connector. Mark the buses which are used only for board-internal devices as 'full' so that if the user creates i2c devices on the commandline without specifying a bus name then they will be connected to the I2C controller used for the Shield connector, where guest software will expect them. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210903151435.22379-4-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 57 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 43 insertions(+), 14 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 746ba3cc59e..f40e854dec7 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -375,6 +375,7 @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms,= int irqno) =20 /* Union describing the device-specific extra data we pass to the devfn. */ typedef union PPCExtraData { + bool i2c_internal; } PPCExtraData; =20 /* Most of the devices in the AN505 FPGA image sit behind @@ -711,6 +712,20 @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms,= void *opaque, object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C); s =3D SYS_BUS_DEVICE(i2c); sysbus_realize(s, &error_fatal); + + /* + * If this is an internal-use-only i2c bus, mark it full + * so that user-created i2c devices are not plugged into it. + * If we implement models of any on-board i2c devices that + * plug in to one of the internal-use-only buses, then we will + * need to create and plugging those in here before we mark the + * bus as full. + */ + if (extradata->i2c_internal) { + BusState *qbus =3D qdev_get_child_bus(DEVICE(i2c), "i2c"); + qbus_mark_full(qbus); + } + return sysbus_mmio_get_region(s, 0); } =20 @@ -921,10 +936,14 @@ static void mps2tz_common_init(MachineState *machine) { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, {= 36, 37, 44 } }, { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, {= 38, 39, 45 } }, { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, {= 40, 41, 46 } }, - { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, - { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, - { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, - { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 }, + { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000, {}, + { .i2c_internal =3D true /* touchscreen */ } }, + { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000, {}, + { .i2c_internal =3D true /* audio conf */ } }, + { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000, {}, + { .i2c_internal =3D false /* shield 0 */ } }, + { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000, {}, + { .i2c_internal =3D false /* shield 1 */ } }, }, }, { .name =3D "apb_ppcexp2", @@ -965,15 +984,20 @@ static void mps2tz_common_init(MachineState *machine) }, { .name =3D "apb_ppcexp1", .ports =3D { - { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 }, - { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 }, + { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000, {}, + { .i2c_internal =3D true /* touchscreen */ } }, + { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000, {}, + { .i2c_internal =3D true /* audio conf */ } }, { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52= } }, { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53= } }, { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54= } }, - { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 }, - { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 }, + { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000, {}, + { .i2c_internal =3D false /* shield 0 */ } }, + { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000, {}, + { .i2c_internal =3D false /* shield 1 */ } }, { /* port 7 reserved */ }, - { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 }, + { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000, {}, + { .i2c_internal =3D true /* DDR4 EEPROM */ } }, }, }, { .name =3D "apb_ppcexp2", @@ -1015,15 +1039,20 @@ static void mps2tz_common_init(MachineState *machin= e) }, { .name =3D "apb_ppcexp1", .ports =3D { - { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000 }, - { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000 }, + { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000, {}, + { .i2c_internal =3D true /* touchscreen */ } }, + { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000, {}, + { .i2c_internal =3D true /* audio conf */ } }, { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53= } }, { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54= } }, { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55= } }, - { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000 }, - { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000 }, + { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000, {}, + { .i2c_internal =3D false /* shield 0 */ } }, + { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000, {}, + { .i2c_internal =3D false /* shield 1 */ } }, { /* port 7 reserved */ }, - { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000 }, + { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000, {}, + { .i2c_internal =3D true /* DDR4 EEPROM */ } }, }, }, { .name =3D "apb_ppcexp2", --=20 2.20.1 From nobody Sat May 11 02:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm7629265wmq.43.2021.09.13.09.12.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 09:12:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Bw7COqvNSGbBSupnPfzjqa5dbyyy8rYOvFDBxednX+Y=; b=Ya8XIwim4NTvdPBa0WO5OWAWRiOWa7W2rDIhTIYfPfl6j5dEc3pjy+l9idbhtmVLH9 AoV4CupILeYFqezOGl5FG3ZkV4dtEtpN2iirZedq1DgJ8QdF2LnlePcnzjynwwel35zW sW09gbgEErCYiXKR6A+JurFuU/tH67bimmvDcYiFM4kj5J+QznxrOPLf9f52GX7a1KwV Rt5H/+NfLPwWvXilgwKqnTYwa7P00Z6Hq+x3ZImtgL5HovvjxQNizdQUN0U3mX+TtdzH Yl7xymOFk+R4PiwZI1Sghe7p+twg7wSi4Biy57XGCcpU3DT5F9oHPCz9ddeLY2QOdbxy QGpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bw7COqvNSGbBSupnPfzjqa5dbyyy8rYOvFDBxednX+Y=; b=klWlvyig1psw037IiUv3UVRTQ0TAGonpH1/ZF+Aa8czq3plG75/RjCTu3b0wCge3Gz +N+X05vG5a247Vyi88QuN/Jzj3knDAVfb3ehamrFUlsYUvN05siClxpjWNMmEwdEx+GX KdrRNW97gSlmKC0+57mEh+22GOWYbeRN2fqijD2MOmvbjX9b+v4y+2bCL8DCWmMTe90A 48l8lP6M22BE/IXOFUS2EzYQWGOyGNIrDm64NNYLUNICDrswPgoAbW2wlOwwoPghfhjZ Yo/Ts7MCaszCb5HbqRf0ZHGYg2CJ99QkkuFJuBNlSYuOGRsYL7YP/c75FpTSffZUh7AF K49Q== X-Gm-Message-State: AOAM531BY0XngLu32lMm+5gEiu4eJQpU1qGjPYTh0G7EVq07RCSzY6pX DNvPNdbSCmr4cdUSbZURMNCUetmSLCXFmw== X-Google-Smtp-Source: ABdhPJzldh+/sRGKXp/M6PrkO+2sXL5RUQJhEGA5G5knSOaN7H4C4gKYlVrcoQdOQJk1j0WgnY/o6w== X-Received: by 2002:adf:e643:: with SMTP id b3mr13838460wrn.67.1631549524858; Mon, 13 Sep 2021 09:12:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/23] hw/arm/mps2.c: Mark internal-only I2C buses as 'full' Date: Mon, 13 Sep 2021 17:11:44 +0100 Message-Id: <20210913161144.12347-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org> References: <20210913161144.12347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631550638653100001 Content-Type: text/plain; charset="utf-8" The various MPS2 boards implemented in mps2.c have multiple I2C buses: a bus dedicated to the audio configuration, one for the LCD touchscreen controller, and two which are connected to the external Shield expansion connector. Mark the buses which are used only for board-internal devices as 'full' so that if the user creates i2c devices on the commandline without specifying a bus name then they will be connected to the I2C controller used for the Shield connector, where guest software will expect them. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210903151435.22379-5-peter.maydell@linaro.org --- hw/arm/mps2.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 4634aa1a1ca..bb76fa68890 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -428,7 +428,17 @@ static void mps2_common_init(MachineState *machine) 0x40023000, /* Audio */ 0x40029000, /* Shield0 */ 0x4002a000}; /* Shield1 */ - sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL); + DeviceState *dev; + + dev =3D sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL); + if (i < 2) { + /* + * internal-only bus: mark it full to avoid user-created + * i2c devices being plugged into it. + */ + BusState *qbus =3D qdev_get_child_bus(dev, "i2c"); + qbus_mark_full(qbus); + } } create_unimplemented_device("i2s", 0x40024000, 0x400); =20 --=20 2.20.1