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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Richard W . M . Jones" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1631469083654100001 Content-Type: text/plain; charset="utf-8" With arm32, the ABI gives us 8-byte alignment for the stack. While it's possible to realign the stack to provide 16-byte alignment, it's far easier to simply not encode 16-byte alignment in the VLD1 and VST1 instructions that we emit. Remove the assertion in temp_allocate_frame, limit natural alignment to the provided stack alignment, and add a comment. Reported-by: Richard W.M. Jones Signed-off-by: Richard Henderson --- I haven't seen the assertion with the various arm kernels that I happen to have laying about. I have not taken the time to build the combo from the bug report: [ 0.000000] Linux version 5.14.0-60.fc36.armv7hl (mockbuild@buildvm-a32-= 12.iad2.fedoraproject.org) (gcc (GCC) 11.2.1 20210728 (Red Hat 11.2.1-1), G= NU ld version 2.37-9.fc36) #1 SMP Mon Aug 30 14:08:34 UTC 2021 I thought about parameterizing this patch further, but I can't think of another ISA that would be affected. (i686 clumsily changed its abi 20 years ago to avoid faulting on vector spills; other isas so far have allowed vectors to be unaligned.) r~ --- tcg/tcg.c | 8 +++++++- tcg/arm/tcg-target.c.inc | 13 +++++++++---- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 4142d42d77..ca5bcc4635 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3060,7 +3060,13 @@ static void temp_allocate_frame(TCGContext *s, TCGTe= mp *ts) g_assert_not_reached(); } =20 - assert(align <=3D TCG_TARGET_STACK_ALIGN); + /* + * Assume the stack is sufficiently aligned. + * This affects e.g. ARM NEON, where we have 8 byte stack alignment + * and do not require 16 byte vector alignment. This seems slightly + * easier than fully parameterizing the above switch statement. + */ + align =3D MIN(TCG_TARGET_STACK_ALIGN, align); off =3D ROUND_UP(s->current_frame_offset, align); =20 /* If we've exhausted the stack frame, restart with a smaller TB. */ diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index e5b4f86841..8515717435 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2477,8 +2477,13 @@ static void tcg_out_ld(TCGContext *s, TCGType type, = TCGReg arg, tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); return; case TCG_TYPE_V128: - /* regs 2; size 8; align 16 */ - tcg_out_vldst(s, INSN_VLD1 | 0xae0, arg, arg1, arg2); + /* + * We have only 8-byte alignment for the stack per the ABI. + * Rather than dynamically re-align the stack, it's easier + * to simply not request alignment beyond that. So: + * regs 2; size 8; align 8 + */ + tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); return; default: g_assert_not_reached(); @@ -2497,8 +2502,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, T= CGReg arg, tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); return; case TCG_TYPE_V128: - /* regs 2; size 8; align 16 */ - tcg_out_vldst(s, INSN_VST1 | 0xae0, arg, arg1, arg2); + /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ + tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); return; default: g_assert_not_reached(); --=20 2.25.1