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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id u13sm4905814wrt.41.2021.09.12.10.29.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Sep 2021 10:29:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f3Od9c5FomPD/l72K+Rq1wthBnusWV2dJ1FXDZtawPg=; b=elQ1/G1ehtI76j0ZyXX9EGE+QQpd9gNvhE82pMGe9gPyS038VPssOM/9zuxWo5JyE1 hnmi45UdQh63b+BQY3mO+0rIQAmtXZLEfmOHkJ9xqavBLwM/EE+5p9xF5wr2Gh7wUBv4 5d0jzSDy82yygVi2x8+qdI4gqLEuU4tj6q/UYcFl2lNsLQI+1XReyIvIGu7MNSlAV6FR l6HJuJGJBTUstk3nLFwsskobAr29fMAByYSZL96cQuuc2cE/Q15yOdEYyQhrbVx+r2Qn LuY5qB2pX/NXzUKgkXlf1C7EVOl8nzaQg8B5SmQ4AP7R6fAYVeTLDQVUDaw9tR8hNGUT nujg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=f3Od9c5FomPD/l72K+Rq1wthBnusWV2dJ1FXDZtawPg=; b=6OQP60tWDtF4zqK9zH77qU9UdHoNnCYNlzaIPAsuJQDaei0K+/uRFwYpL3rm7+bI+h b3MR4PEr61jFjaIWwnhI1IA66mlVw0F3i8K1HHQk7bTJEJAeKYdvQwD0WD2pboc966Mb Ouvv89T0pi7CN9Ym41QXCq8Bko4lKEc9UwjJbEAclP8dq2PbDu987A38jqc/7kAlKf5V Eyxu4OexleFS4bpzcE5+rR5qc9AYTQE21Cbi+/2FcFH82h88u8Q1dLq1vraE2NaUMpdG U1fG7gxLhmdpUC9Ib9vs50e9cBQcxSVXN7RDdzWWHsgF1cRQdHrdXusWK71olibtrxE+ UrrA== X-Gm-Message-State: AOAM532vaalKdyM0bUPq5nNwUeyDYf3EeQl6fK5JTOdLdyGTAeMCqwD9 D+kzd1u7Gb0oRrDzM8+UemU= X-Google-Smtp-Source: ABdhPJxTFvQxxtCDO0Jny4zT6V2tv/cdbt+uC53R2jrTVSRPJ2zgYfcEv/iNnu8VToS4UmbvT00sLA== X-Received: by 2002:a1c:25c7:: with SMTP id l190mr7441870wml.118.1631467750508; Sun, 12 Sep 2021 10:29:10 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Gibson , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 20/30] target/ppc: Introduce PowerPCCPUClass::has_work() Date: Sun, 12 Sep 2021 19:27:21 +0200 Message-Id: <20210912172731.789788-21-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210912172731.789788-1-f4bug@amsat.org> References: <20210912172731.789788-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1631467753366100001 We're moving the hook from CPUState to TCGCPUOps. TCGCPUOps is a const structure, so to avoid creating multiple versions of the same structure, simply changing the has_work() handler, introduce yet another indirection with a has_work() handler in PowerPCCPUClass, and ppc_cpu_has_work() method which dispatch to it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/ppc/cpu-qom.h | 1 + target/ppc/cpu_init.c | 23 ++++++++++++++--------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 5800fa324e8..36110112506 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -188,6 +188,7 @@ struct PowerPCCPUClass { uint32_t flags; int bfd_mach; uint32_t l1_dcache_size, l1_icache_size; + bool (*has_work)(CPUState *cpu); #ifndef CONFIG_USER_ONLY unsigned int gdb_num_sprs; const char *gdb_spr_xml; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6aad01d1d3a..2f7d262b176 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7621,7 +7621,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); =20 dc->fw_name =3D "PowerPC,POWER7"; dc->desc =3D "POWER7"; @@ -7630,7 +7629,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->pcr_supported =3D PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER7; pcc->check_pow =3D check_pow_nocheck; - cc->has_work =3D cpu_has_work_POWER7; + pcc->has_work =3D cpu_has_work_POWER7; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -7789,7 +7788,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); =20 dc->fw_name =3D "PowerPC,POWER8"; dc->desc =3D "POWER8"; @@ -7798,7 +7796,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->pcr_supported =3D PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_= 2_05; pcc->init_proc =3D init_proc_POWER8; pcc->check_pow =3D check_pow_nocheck; - cc->has_work =3D cpu_has_work_POWER8; + pcc->has_work =3D cpu_has_work_POWER8; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -8003,7 +8001,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); =20 dc->fw_name =3D "PowerPC,POWER9"; dc->desc =3D "POWER9"; @@ -8013,7 +8010,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER9; pcc->check_pow =3D check_pow_nocheck; - cc->has_work =3D cpu_has_work_POWER9; + pcc->has_work =3D cpu_has_work_POWER9; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -8212,7 +8209,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); =20 dc->fw_name =3D "PowerPC,POWER10"; dc->desc =3D "POWER10"; @@ -8223,7 +8219,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER10; pcc->check_pow =3D check_pow_nocheck; - cc->has_work =3D cpu_has_work_POWER10; + pcc->has_work =3D cpu_has_work_POWER10; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -8790,7 +8786,7 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.nip =3D value; } =20 -static bool ppc_cpu_has_work(CPUState *cs) +static bool cpu_has_work_default(CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; @@ -8798,6 +8794,14 @@ static bool ppc_cpu_has_work(CPUState *cs) return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); } =20 +static bool ppc_cpu_has_work(CPUState *cs) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + + return pcc->has_work(cs); +} + static void ppc_cpu_reset(DeviceState *dev) { CPUState *s =3D CPU(dev); @@ -9037,6 +9041,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void = *data) device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, &pcc->parent_unrealize); pcc->pvr_match =3D ppc_pvr_match_default; + pcc->has_work =3D cpu_has_work_default; device_class_set_props(dc, ppc_cpu_properties); =20 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); --=20 2.31.1