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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id u13sm2185968wrg.68.2021.09.11.09.55.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V7zq9ygHOST6Surc7M7Rd7Muo9vEZYb0xO5KQYL2Z9g=; b=XzyRMGklhJv/3jO2rzP+eHd7rg/GI3/pbHRLE+S+PseXqg5y00obXvD/QPi4ENd+s6 Le2N8XGN/D14V92gY9UiYmS2cOghgkOke+o44m/TMNSkOQ6WuzhGdj2xVb8CaJbrvbR9 9JkALCvyv0HpnXrNVZ0olnyQsvrh9t9LW32uWkQ/S9JjGh7zSER99mkpnthRQsrPhPJU fCwrOS8ndhAkIeXJDxDTCc81PvFEDTsotXY7F00T6ou153C/PHOharqlBF3i/c4FCC1X bYu0/dSlisP/pmT13gPglbSZap70cn13vdfI6UMdW5qboGuAXFp7uoTDoBhzTvogYVfh PV0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=V7zq9ygHOST6Surc7M7Rd7Muo9vEZYb0xO5KQYL2Z9g=; b=dqfEBZ1Zpi0bNO+m2JH+hTCPdPH5TZ1VdbapCNAzH9bG7sYLENqBBmWyOOCZ2Q80fD LYH1EimNOCTqWG3nWvCgId545qnUzMT3WpOkEPHm6sYfVG22wVl7f2pZCMgoa7DkgJSr zFRKYFwmoFlvrVDgU3wnYChjCAUQdTysfO3J9V8dPmRcP+n1ByCGWTQtlbOGkPGOUZgu Q87TCrOY5LXd+k/FltEnED33jNc3yqwD5GOcgUl4bvk4rPlmoqP2Hoj3XigsTSGlWrLn vRNKp4ob15/NVHpfRJa09v6Hui9RugoWABlCfNU2m33agzRXUwcqvcZpiRrhjMm3G6Fq nriA== X-Gm-Message-State: AOAM5319N5XfAVZ1iR+63Jg2oy7rS1E3b8AVsM8mE4w6hMcu2XI63gZ5 SPFHUiyrnOZcwqm77FVReRY= X-Google-Smtp-Source: ABdhPJxqMlQ9bijBVciVwcZ6hXF4FqTXXJwnpstopv8oQqaisHACNDccDRg+tvRDSW9i631NpbeHiQ== X-Received: by 2002:a5d:65d0:: with SMTP id e16mr3930572wrw.182.1631379311159; Sat, 11 Sep 2021 09:55:11 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Subject: [PATCH v3 07/24] target/arm: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:17 +0200 Message-Id: <20210911165434.531552-8-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1631379314330100001 Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 3 +-- target/arm/cpu.c | 7 +++++-- target/arm/cpu_tcg.c | 6 +++--- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6a987f65e41..cfd755cff99 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1040,11 +1040,10 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clust= ersz); =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; -#endif =20 void arm_cpu_do_interrupt(CPUState *cpu); void arm_v7m_cpu_do_interrupt(CPUState *cpu); -bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif /* !CONFIG_USER_ONLY */ =20 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d631c4683c4..ba0741b20e4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -440,6 +440,8 @@ static void arm_cpu_reset(DeviceState *dev) arm_rebuild_hflags(env); } =20 +#ifndef CONFIG_USER_ONLY + static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, unsigned int target_el, unsigned int cur_el, bool secure, @@ -556,7 +558,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, return unmasked || pstate_unmasked; } =20 -bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); CPUARMState *env =3D cs->env_ptr; @@ -608,6 +610,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) cc->tcg_ops->do_interrupt(cs); return true; } +#endif /* !CONFIG_USER_ONLY */ =20 void arm_cpu_update_virq(ARMCPU *cpu) { @@ -2010,11 +2013,11 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D= { static const struct TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, =20 #if !defined(CONFIG_USER_ONLY) + .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .do_interrupt =3D arm_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, .do_unaligned_access =3D arm_cpu_do_unaligned_access, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 33cc75af57d..0d5adccf1a7 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -22,7 +22,7 @@ /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 -#ifdef CONFIG_TCG +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); @@ -46,7 +46,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) } return ret; } -#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 static void arm926_initfn(Object *obj) { @@ -898,11 +898,11 @@ static void pxa270c5_initfn(Object *obj) static const struct TCGCPUOps arm_v7m_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, =20 #if !defined(CONFIG_USER_ONLY) + .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, .do_interrupt =3D arm_v7m_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, .do_unaligned_access =3D arm_cpu_do_unaligned_access, --=20 2.31.1