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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id k22sm2161065wrd.59.2021.09.11.09.54.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=82KmkOHInD6T32/MBrAXuGha1mEQ9aTunJA89epWqX8=; b=Wvx18w7OXDMt3qrFbOeAJi01TZPxs6nfyKUuc1WoZpxPbN0luw8v90VdrQP8WpXxvz 6D5Z9YN06NEuWYNUOWpOFtgRuqDO1ofR+8c8+Adrr6+lH7VpSjAm0RD4DBbToIWBKr4O EpcSnGgKKnBjDnbMAyv+l4tj6NyBAwt7kZEQqHtpu+mrJBg9lIUOHURWt8YNbjcNNekI PsSNkyj7HWyZhh+oo7qQKlSqTJicoQ4/diXt6kWUbicyX6LOYgdiLJtYaLWAv6sesqFI fyA3QIMa0d5w9reWvrevYuOFDJO4lqOdvEGSV6x/w/kKpfrEYL+7I47qZw+23ogphZX4 G4ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=82KmkOHInD6T32/MBrAXuGha1mEQ9aTunJA89epWqX8=; b=FQu5EoDB3QejBfc3ZNvD97MQDgvEBagZqSUscXveyr07vQmStIwoBFVnIBfHxPGbp8 CATwilepD0goZxNWBllCLjT2+M0xB2UkofPxUvPgvY4DltrfEPhjfWgBVKvJHvr4/AzK B38l9cXEZ+JFXOd9T51LgWXdLTQy/OQs9N7czGublR/bVLJ87kthr+ac86eDq48mOat6 Zp82tbpPNkaCoQNufWLZZmskOMJ7eM9BPxNehhw/LCYQEDTAdvgekzJCQRtRP2xQXRAu /lFszt0mf110qoFgwkHlwIFvtDF+YOkvUx8QQeyYKHSeoYEsfqyhobqEcRigLOYzPk5b ot9w== X-Gm-Message-State: AOAM5309fUzfEvm1XCBpHpamIhaGh11Aacm31XDF9dhKBR+pCcN7T7Xv nJs/DRntzNALXrykimzQqJM= X-Google-Smtp-Source: ABdhPJyZOkeQqeD9Cha1QZ+au7oTLStFUBD5ohQ53fqgRfqQc/XFPWDiauSpdQuOdbGBK+hI2RSlpQ== X-Received: by 2002:a05:6000:7:: with SMTP id h7mr3871888wrx.134.1631379300719; Sat, 11 Sep 2021 09:55:00 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Subject: [PATCH v3 05/24] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt Date: Sat, 11 Sep 2021 18:54:15 +0200 Message-Id: <20210911165434.531552-6-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1631379303893100001 do_interrupt() is sysemu specific. However due to some X86 specific hack, it is also used in user-mode emulation, which is why it couldn't be restricted to CONFIG_SOFTMMU (see the comment around added in commit 78271684719: "cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"). Keep the hack but rename the handler as fake_user_interrupt() and restrict do_interrupt() to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/tcg-cpu-ops.h | 22 ++++++++++++++-------- accel/tcg/cpu-exec.c | 4 ++-- target/i386/tcg/tcg-cpu.c | 6 ++++-- 3 files changed, 20 insertions(+), 12 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index eab27d0c030..6c7ab9600ba 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -37,14 +37,6 @@ struct TCGCPUOps { void (*cpu_exec_exit)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); - /** - * @do_interrupt: Callback for interrupt handling. - * - * note that this is in general SOFTMMU only, but it actually isn't - * because of an x86 hack (accel/tcg/cpu-exec.c), so we cannot put it - * in the SOFTMMU section in general. - */ - void (*do_interrupt)(CPUState *cpu); /** * @tlb_fill: Handle a softmmu tlb miss or user-only address fault * @@ -61,6 +53,20 @@ struct TCGCPUOps { void (*debug_excp_handler)(CPUState *cpu); =20 #ifdef NEED_CPU_H +#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386) + /** + * @fake_user_interrupt: Callback for 'fake exception' handling. + * + * Simulate 'fake exception' which will be handled outside the + * cpu execution loop (hack for x86 user mode). + */ + void (*fake_user_interrupt)(CPUState *cpu); +#else + /** + * @do_interrupt: Callback for interrupt handling. + */ + void (*do_interrupt)(CPUState *cpu); +#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ #ifdef CONFIG_SOFTMMU /** * @do_transaction_failed: Callback for handling failed memory transac= tions diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index e5c0ccd1a2a..2838177e7f0 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -651,8 +651,8 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) loop */ #if defined(TARGET_I386) CPUClass *cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops->do_interrupt(cpu); -#endif + cc->tcg_ops->fake_user_interrupt(cpu); +#endif /* TARGET_I386 */ *ret =3D cpu->exception_index; cpu->exception_index =3D -1; return true; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 93a79a57415..04c35486a2f 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -73,9 +73,11 @@ static const struct TCGCPUOps x86_tcg_ops =3D { .cpu_exec_enter =3D x86_cpu_exec_enter, .cpu_exec_exit =3D x86_cpu_exec_exit, .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, - .do_interrupt =3D x86_cpu_do_interrupt, .tlb_fill =3D x86_cpu_tlb_fill, -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .fake_user_interrupt =3D x86_cpu_do_interrupt, +#else + .do_interrupt =3D x86_cpu_do_interrupt, .debug_excp_handler =3D breakpoint_handler, .debug_check_breakpoint =3D x86_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ --=20 2.31.1