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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id g9sm2082333wmg.21.2021.09.11.09.56.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:56:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JWKBtEMqz5hUsAPJr5foR0KE5eQgXFRtLCwxDOixiMc=; b=e+qje1cuNCCYtVs3KdwRTIkK5ZSjpTp6BMpUs7GfwGUUqy9HrXZS9daBZrcx5mI4ok OENU+npl3zj6/dVuVcRYhUhAqDhVjmXp38eSUE86vftr3VWxgvw7Q94BDdlUMdjz/T30 sk6eAXeNxKSC3DpwPB9v00vTQM5zhDHwUwtkhnEsxaVdZYFZaLiAWVDAiKpjK3NHzcNK 5VUdN4o84R9/XMFwwevHfp65f/Qj4JGPgiCKMnhlEzBWD6sTGjLfVBwUbLbuuA7HtwGe 7Q4eJhIaNer4ZGDHhqI9N5OoxAwx/cAPC3daT2WQddta09UaQuuE83Y6iGvX66IPSIxZ dE6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=JWKBtEMqz5hUsAPJr5foR0KE5eQgXFRtLCwxDOixiMc=; b=yewJEffk9plAzfifmtXB0rhRblbL/cJEAVo6YpXFNx+Bf9vwwvp7j8EB17+EqysBfU 5gfRVZZxfystSPTza7lUqRMj5vApGzc9XZ/WFdURAuzgJ2kB4iZGq8XdMBwDCrhJc8BX mglpae1XkncjwjbjLSo0RjhZXiP2IQ6GwPzuUD9TueNphNFAx7oqJLLfPdSkcob2AHBR 1VoXs0ImpSxJygPX8WcL3IWoffrUpKtahMwdNC9UNHOPTVXpCLDIYFSntGLz1sZbLPko PnPmNqTB7sw10RcTuD9JEQ4l3aW7eBxUKa/LQsOlrjEdk2Dpb9zFltJudRYRdtdaNiid uhFw== X-Gm-Message-State: AOAM530rOxVWRfzhaNQeRM5Lz9lzePW9o1eKEsJTsmUs16pJGeTkVJoP qEvz7azkwF3IwxSBrQBxVG4= X-Google-Smtp-Source: ABdhPJy+XHF69mbQsLLAtV7bZsAkSniKDt5sTjSzxp9SGCwJ2i2TA2ouRs1eUod+YbkkquNP91rP9g== X-Received: by 2002:adf:fd03:: with SMTP id e3mr3900306wrr.46.1631379391724; Sat, 11 Sep 2021 09:56:31 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 23/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Date: Sat, 11 Sep 2021 18:54:33 +0200 Message-Id: <20210911165434.531552-24-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1631379393845100001 All targets call TCGCPUOps::cpu_exec_interrupt() from sysemu code. Move its declaration to restrict it to system emulation. Extend the code guarded. Restrict the static inlined need_replay_interrupt() method to avoid a "defined but not used" warning. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/tcg-cpu-ops.h | 4 ++-- accel/tcg/cpu-exec.c | 10 +++++++--- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 6c7ab9600ba..55123cb4d22 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -35,8 +35,6 @@ struct TCGCPUOps { void (*cpu_exec_enter)(CPUState *cpu); /** @cpu_exec_exit: Callback for cpu_exec cleanup */ void (*cpu_exec_exit)(CPUState *cpu); - /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ - bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); /** * @tlb_fill: Handle a softmmu tlb miss or user-only address fault * @@ -68,6 +66,8 @@ struct TCGCPUOps { void (*do_interrupt)(CPUState *cpu); #endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ #ifdef CONFIG_SOFTMMU + /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ + bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); /** * @do_transaction_failed: Callback for handling failed memory transac= tions * (ie bus faults or external aborts; not MMU faults) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2838177e7f0..75dbc1e4e33 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -685,6 +685,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) return false; } =20 +#ifndef CONFIG_USER_ONLY /* * CPU_INTERRUPT_POLL is a virtual event which gets converted into a * "real" interrupt event later. It does not need to be recorded for @@ -698,12 +699,11 @@ static inline bool need_replay_interrupt(int interrup= t_request) return true; #endif } +#endif /* !CONFIG_USER_ONLY */ =20 static inline bool cpu_handle_interrupt(CPUState *cpu, TranslationBlock **last_tb) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); - /* Clear the interrupt flag now since we're processing * cpu->interrupt_request and cpu->exit_request. * Ensure zeroing happens before reading cpu->exit_request or @@ -725,6 +725,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, qemu_mutex_unlock_iothread(); return true; } +#if !defined(CONFIG_USER_ONLY) if (replay_mode =3D=3D REPLAY_MODE_PLAY && !replay_has_interrupt()= ) { /* Do nothing */ } else if (interrupt_request & CPU_INTERRUPT_HALT) { @@ -753,12 +754,14 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, qemu_mutex_unlock_iothread(); return true; } -#endif +#endif /* !TARGET_I386 */ /* The target hook has 3 exit conditions: False when the interrupt isn't processed, True when it is, and we should restart on a new TB, and via longjmp via cpu_loop_exit. */ else { + CPUClass *cc =3D CPU_GET_CLASS(cpu); + if (cc->tcg_ops->cpu_exec_interrupt && cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { if (need_replay_interrupt(interrupt_request)) { @@ -777,6 +780,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * reload the 'interrupt_request' value */ interrupt_request =3D cpu->interrupt_request; } +#endif /* !CONFIG_USER_ONLY */ if (interrupt_request & CPU_INTERRUPT_EXITTB) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_EXITTB; /* ensure that no TB jump will be modified as --=20 2.31.1