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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id j17sm2113722wrh.67.2021.09.11.09.56.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:56:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j9PM97jpqrx9RzHI+KsmBSg+6+9rj2SJK4q8cO/CNpE=; b=bsQeH4AcGspn+4Meelms8C/sAQhY5D9MfKC3AvHUjmsvnPf+FJSxiq9OT4AKKuALTA qldb4kjBMwDE4031OgdlS6diX56tzjjlqFQV9MvI8UxRhGLX9TO4ixtYHXtMR5i0xTyF 2YmWFmveNvDR9qD4Lz37Pu6hD8V701HhdLNdZYZEZjnHK5EehwpSPd4+PeB2Fv5tvVqR tKVYom984eQbzf0a2I0sUgAV0NUNrkov94a53PFq6hAWGtNwbhT1omSl49YiN8D7c/8n 9LxwEBY+7zmfDJRoIvPKcWjfDfgI+4V1TtcW6KaoMGUEi1j9gI3OtMPyb05Mx2D9oZ8F eV7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=j9PM97jpqrx9RzHI+KsmBSg+6+9rj2SJK4q8cO/CNpE=; b=NLwHXkK0tI0WBh0+uXNVn/HSQRyPkut2KQeQ1kJ1D9/htuAONA0CGPyfjjmcYlSDpJ J2XulbfdVDzuvFjJRmKfrBXYR6Zqp9mQaFfFZyJ/8+oX/IcfTyCoFAUV42mn+rBRxNvB /4ezv3eOk4FIzs6i+D9FUw75eM0lUDR9es86C7Yhj3Ec2WEYCiBNC8gdp9CvGf+6PPE/ CFjaT9jd5ynp7wob0GFusuxe5BL9+ewKjRBGSLXk6iUKDyqp9VUjI+nLk+hx/wI56Wbp VfbsNrqd6fAPniqHzt8OJlV/igtUMx5Z+DBb5e2HzUwdKmqFIXiWdO7B5FRGTY82AYrg gxnA== X-Gm-Message-State: AOAM532NNt+NxX4VawarpBgp+KLs0ZisgWPthNMzkYiRSwd3XUnvQK9w AX2FjaexTGgv2Cnl+sjZY2s= X-Google-Smtp-Source: ABdhPJyvFhFhGZFAm/dT6+mJaPZZyfUo5jImbnNC/uz/Ca//l3gV+dl9T1FN9XkwEqdZ6Fc21ZfBbA== X-Received: by 2002:adf:b78d:: with SMTP id s13mr3934379wre.344.1631379365845; Sat, 11 Sep 2021 09:56:05 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh , Bin Meng Subject: [PATCH v3 18/24] target/riscv: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:28 +0200 Message-Id: <20210911165434.531552-19-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1631379368798100001 Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 5 ----- 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00b..e735e53e26c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -334,7 +334,6 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f,= CPUState *cs, int cpuid, void *opaque); int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); @@ -362,6 +361,7 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY +bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value= ); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1a2b03d579c..13575c14085 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -644,10 +644,10 @@ static const struct SysemuCPUOps riscv_sysemu_ops =3D= { static const struct TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .tlb_fill =3D riscv_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, .do_unaligned_access =3D riscv_cpu_do_unaligned_access, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 968cb8046f4..701858d670c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -75,11 +75,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *en= v) return RISCV_EXCP_NONE; /* indicates no pending interrupt */ } } -#endif =20 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { -#if !defined(CONFIG_USER_ONLY) if (interrupt_request & CPU_INTERRUPT_HARD) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; @@ -90,12 +88,9 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) return true; } } -#endif return false; } =20 -#if !defined(CONFIG_USER_ONLY) - /* Return true is floating point support is currently enabled */ bool riscv_cpu_fp_enabled(CPURISCVState *env) { --=20 2.31.1